A system for dual-thread parallel read-write shared space

Abstract

The application belongs to the technical field of data communication and specifically relates to a system for parallel reading and writing of a shared space by double threads, which comprises an application software module, a PCIE double address mapping module and a shared space module. The system breaks the traditional point-to-point data communication mode, realizes independent reading and writing of an external shared space when a processor runs a double thread application component through software-defined PCIE double address mapping and SRIO arbitration mechanism, ensures that double threads do not interfere with each other when communicating between heterogeneous platforms, and the access time is controllable.

Description

Technical Field

[0001] This invention belongs to the field of data communication technology, specifically relating to a system for dual-threaded parallel reading and writing of a shared space. Background Technology

[0002] As chip processing power continues to improve, in order to reduce R&D costs and increase product integration, multiple threads are typically built on a single main processor, integrating multiple functional software or application components. However, there is usually only one physical interface for external access. To avoid mutual interference and uncertain timing of multiple threads reading and writing data between heterogeneous platforms, it is necessary to build a multi-threaded parallel communication architecture through software to achieve parallel reading and writing of external shared space by multiple threads, with no crosstalk between them and a certain access time. Summary of the Invention

[0003] (a) Technical problems to be solved

[0004] The technical problem to be solved by this invention is: how to provide a system for parallel reading and writing of shared space using two threads.

[0005] (II) Technical Solution

[0006] To solve the above technical problems, the present invention provides a system for dual-thread parallel reading and writing of shared space, the system comprising: an application software module, a PCIe dual address mapping module, and a shared space module;

[0007] The application software module includes: application thread 1, application thread 2, and PCIE driver. Application thread 1 and application thread 2 can independently call the PCIE driver.

[0008] The PCIe dual-address mapping module includes: a PCIe IP core, an SRIO access arbitration mechanism, and an SRIO IP core. The PCIe IP core internally instantiates two completely independent PCIe decoders, address FIFOs, command FIFOs, write data FIFOs, and read data FIFOs, forming two independent PCIe address spaces. The SRIO access arbitration mechanism determines the access order based on the address, data, and command information of the two independent PCIe address spaces, realizing the mapping relationship between the dual PCIe address spaces and the single SRIO address space. The SRIO IP core is used to access the shared space module. The two completely independent PCIe decoders are PCIe decoder 1 and PCIe decoder 2.

[0009] The shared space module includes two independent spaces created through underlying hardware logic, which are respectively used by application thread 1 and application thread 2 of the application software module to read and write data.

[0010] There is only one PCIe physical link between the application software module and the PCIe dual address mapping module. By instantiating two completely independent PCIe address spaces inside the PCIe IP core, the two application threads can read and write to the two completely independent PCIe address spaces in parallel through virtualized dual PCIe without interfering with each other.

[0011] There is only one SRIO physical path between the PCIe dual address mapping module and the shared space module. Through the SRIO access arbitration mechanism, the two PCIe address spaces can alternately access SRIO, so that the virtualized dual PCIe address spaces can read and write the two shared spaces without cross-referencing after passing through SRIO, thus ensuring the access time of the two application threads.

[0012] The system can be quickly expanded and used, allowing multiple application software modules to access a shared space module simultaneously through a PCIe dual address mapping module, thus enabling real-time data sharing between multiple application threads of different application software modules.

[0013] The application software module can run on a CPU platform.

[0014] The PCIe dual address mapping module can run on an FPGA platform.

[0015] The shared space module can run on a DSP platform.

[0016] The communication interface between the CPU platform and the FPGA platform is one 4x PCIe interface, and the communication interface between the FPGA platform and the DSP platform is one 4x SRIO interface.

[0017] The specific steps of the system operation for dual-threaded parallel reading and writing of the shared space are as follows:

[0018] Step 1: Application thread 1 on the CPU platform accesses PCIe decoder 1 on the FPGA platform by calling the PCIe driver; Application thread 2 accesses PCIe decoder 2 on the FPGA platform by calling the PCIe driver.

[0019] Step 2: SRIO access arbitration mechanism: interpret the bus data of PCIe decoder 1 and PCIe decoder 2, and then alternately access the SRIO IP core to perform read and write operations on the SRIO node on the DSP platform.

[0020] Step 3: The space is divided on the DSP platform. Application thread 1 can only write to the first address space of 0xD..., and application thread 2 can only write to the first address space of 0x8.... Application thread 1 and application thread 2 can read data in any space to ensure that the data will not be tampered with and that reading and writing do not interfere with each other.

[0021] (III) Beneficial Effects

[0022] Compared with existing technologies, this invention breaks the traditional point-to-point data communication mode. Through software-defined PCIe dual address mapping and SRIO arbitration mechanism, it enables a processor to independently read and write external shared space when running dual-thread application components. This solves the problem of data overlap and access contention between two threads when communicating between heterogeneous platforms, ensuring that the two threads do not overlap when communicating between heterogeneous platforms and that access time is controllable. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of a system for parallel reading and writing of shared space using two threads. Detailed Implementation

[0024] To make the objectives, contents, and advantages of the present invention clearer, the specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples.

[0025] To solve the above technical problems, the present invention provides a system for dual-thread parallel reading and writing of shared space, the system comprising: an application software module, a PCIe dual address mapping module, and a shared space module;

[0026] The application software module includes: application thread 1, application thread 2, and PCIE driver. Application thread 1 and application thread 2 can independently call the PCIE driver.

[0027] The PCIe dual-address mapping module includes: a PCIe IP core, an SRIO access arbitration mechanism, and an SRIO IP core. The PCIe IP core internally instantiates two completely independent PCIe decoders, address FIFOs, command FIFOs, write data FIFOs, and read data FIFOs, forming two independent PCIe address spaces. The SRIO access arbitration mechanism determines the access order based on the address, data, and command information of the two independent PCIe address spaces, realizing the mapping relationship between the dual PCIe address spaces and the single SRIO address space. The SRIO IP core is used to access the shared space module. The two completely independent PCIe decoders are PCIe decoder 1 and PCIe decoder 2.

[0028] The shared space module includes two independent spaces created through underlying hardware logic, which are respectively used by application thread 1 and application thread 2 of the application software module to read and write data.

[0029] There is only one PCIe physical link between the application software module and the PCIe dual address mapping module. By instantiating two completely independent PCIe address spaces inside the PCIe IP core, the two application threads can read and write to the two completely independent PCIe address spaces in parallel through virtualized dual PCIe without interfering with each other.

[0030] There is only one SRIO physical path between the PCIe dual address mapping module and the shared space module. Through the SRIO access arbitration mechanism, the two PCIe address spaces can alternately access SRIO, so that the virtualized dual PCIe address spaces can read and write the two shared spaces without cross-referencing after passing through SRIO, thus ensuring the access time of the two application threads.

[0031] The system can be quickly expanded and used, allowing multiple application software modules to access a shared space module simultaneously through a PCIe dual address mapping module, thus enabling real-time data sharing between multiple application threads of different application software modules.

[0032] The application software module can run on a CPU platform.

[0033] The PCIe dual address mapping module can run on an FPGA platform.

[0034] The shared space module can run on a DSP platform.

[0035] The communication interface between the CPU platform and the FPGA platform is one 4x PCIe interface, and the communication interface between the FPGA platform and the DSP platform is one 4x SRIO interface.

[0036] The specific steps of the system operation for dual-threaded parallel reading and writing of the shared space are as follows:

[0037] Step 1: Application thread 1 on the CPU platform accesses PCIe decoder 1 on the FPGA platform by calling the PCIe driver; Application thread 2 accesses PCIe decoder 2 on the FPGA platform by calling the PCIe driver.

[0038] Step 2: SRIO access arbitration mechanism: interpret the bus data of PCIe decoder 1 and PCIe decoder 2, and then alternately access the SRIO IP core to perform read and write operations on the SRIO node on the DSP platform.

[0039] Step 3: The space is divided on the DSP platform. Application thread 1 can only write to the first address space of 0xD..., and application thread 2 can only write to the first address space of 0x8.... Application thread 1 and application thread 2 can read data in any space to ensure that the data will not be tampered with and that reading and writing do not interfere with each other.

[0040] Example 1

[0041] In this embodiment, the application software module can run on a CPU platform, the PCIe dual-address mapping module can run on an FPGA platform, and the shared space module can run on a DSP platform. The communication interface between the CPU and the FPGA is one 4x PCIe interface, and the communication interface between the FPGA and the DSP is one 4x SRIO interface. Specific steps: Application thread 1 on the CPU platform accesses PCIe decoder 1 on the FPGA platform by calling the PCIe driver; application thread 2 accesses PCIe decoder 2 on the FPGA platform by calling the PCIe driver; the SRIO access arbitration mechanism interprets the bus data of PCIe decoder 1 and PCIe decoder 2, and then alternately accesses the SRIO IP core to perform read and write operations on the SRIO node on the DSP platform; the space on the DSP platform is divided, application thread 1 can only write to the 0xD… address space, application thread 2 can only write to the 0x8… address space, and application threads 1 and 2 can read data in any space, ensuring that the data is not tampered with and that read and write operations do not interfere with each other.

[0042] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A system for dual-threaded parallel reading and writing of a shared space, characterized in that, The system includes: an application software module, a PCIe dual address mapping module, and a shared space module; The application software module includes: application thread 1, application thread 2, and PCIE driver. Application thread 1 and application thread 2 can independently call the PCIE driver. The PCIe dual address mapping module includes: a PCIe IP core, an SRIO access arbitration mechanism, and an SRIO IP core. The PCIe IP core internally instantiates two completely independent PCIe decoders, address FIFO, command FIFO, write data FIFO, and read data FIFO, forming two independent PCIe address spaces. The SRIO access arbitration mechanism determines the access order based on the address, data, and command information of the two independent PCIe address spaces, realizing the mapping relationship between the dual PCIe address spaces and the single SRIO address space. The SRIO IP core is used to access the shared space module. The two completely independent PCIe decoders are PCIe decoder 1 and PCIe decoder 2. The shared space module includes two independent spaces opened up by the underlying hardware logic, which are respectively used by application thread 1 and application thread 2 of the application software module to read and write data. There is only one PCIE physical link between the application software module and the PCIE dual address mapping module. By instantiating two completely independent PCIE address spaces inside the PCIE IP core, the two application threads can read and write the two completely independent PCIE address spaces in parallel through virtualized dual PCIE without interfering with each other. There is only one SRIO physical path between the PCIe dual address mapping module and the shared space module. Through the SRIO access arbitration mechanism, the two PCIe address spaces can alternately access SRIO, so that the virtualized dual PCIe address spaces can read and write the two shared spaces without cross-referencing after passing through SRIO, thus ensuring the access time of the two application threads.

2. The system for dual-threaded parallel read / write of shared space as described in claim 1, characterized in that, The system can be quickly expanded and used. Multiple application software modules, combined with the PCIe dual address mapping module, can simultaneously access a shared space module, enabling real-time data sharing between multiple application threads of different application software modules.

3. The system for dual-threaded parallel reading and writing of shared space as described in claim 2, characterized in that, The application software module can run on a CPU platform.

4. The system for dual-threaded parallel read / write of shared space as described in claim 3, characterized in that, The PCIe dual address mapping module can run on an FPGA platform.

5. The system for dual-threaded parallel read / write of shared space as described in claim 4, characterized in that, The shared space module can run on a DSP platform.

6. The system for dual-threaded parallel read / write of shared space as described in claim 5, characterized in that, The communication interface between the CPU platform and the FPGA platform is a 4x PCIe interface, and the communication interface between the FPGA platform and the DSP platform is a 4x SRIO interface.

7. The system for dual-threaded parallel read / write of shared space as described in claim 6, characterized in that, The specific steps of the system operation for dual-threaded parallel read / write of the shared space are as follows: Step 1: Application thread 1 on the CPU platform accesses PCIe decoder 1 on the FPGA platform by calling the PCIe driver; Application thread 2 accesses PCIe decoder 2 on the FPGA platform by calling the PCIe driver; Step 2: SRIO access arbitration mechanism: interpret the bus data of PCIe decoder 1 and PCIe decoder 2, and then alternately access the SRIO IP core to perform read and write operations on the SRIO node on the DSP platform. Step 3: The space is divided on the DSP platform. Application thread 1 can only write to the first address space of 0xD..., and application thread 2 can only write to the first address space of 0x8.... Application thread 1 and application thread 2 can read data in any space to ensure that the data will not be tampered with and that reading and writing do not interfere with each other.

8. The system for dual-threaded parallel read / write of shared space as described in claim 7, characterized in that, The system breaks away from the traditional point-to-point data communication mode. Through software-defined PCIe dual address mapping and SRIO arbitration mechanism, it enables a processor to independently read and write external shared space when running dual-threaded application components, thus solving the problem of data exchange and access contention between two threads when communicating between heterogeneous platforms.

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