Method and device for automatically examining correctness of schematic circuit diagram differential network

Abstract

The invention discloses a method and a device for automatically examining correctness of a circuit schematic diagram differential network. According to the scheme, the method comprises the following steps: inputting a circuit schematic diagram in an EDIF200 standard format, analyzing a schematic diagram file, obtaining chip pins, resistance-capacitance-inductance and related electrical network data, and storing the data to a chip device information matrix PartU and a non-chip device information matrix Partmer. Thirdly, screening differential pins according to a set standard, and storing the differential pins into a matrix Difpin; then, splitting the matrix Difpin into a matrix Difpin1 and a matrix Difpin2, traversing to obtain a differential path, and storing the differential path into a matrix DiffNet1 and a matrix DiffNet2; afterwards, based on the matrix DiffNet1 and the matrix DiffNet2, the correctness and naming normalization of the differential network are examined, incorrect paths are stored in a Diffnocor matrix, and non-standard named paths are stored in the Diffnocor matrix. Finally, the paths in the two matrixes are converted into character strings, text description is added, and an inspection result is output.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic design automation, and in particular to a method and device for automatically reviewing the correctness of a differential network of a circuit schematic. Background Art

[0002] A differential signal consists of a pair of signals with equal voltage magnitudes and opposite polarities. During transmission, the receiver detects the difference between these two signals to obtain information, effectively minimizing the impact of external interference on the signal. Because external interference typically affects both transmission lines simultaneously, differential signaling uses the difference to transmit information. The interference affects both lines equally, and the interference signal is canceled out when the difference is calculated. In modern electronic systems, differential signaling plays a vital role in high-reliability and high-speed electronic systems due to its many advantages, such as strong interference immunity, high signal transmission quality, and effective suppression of common-mode noise. During circuit schematic design, improperly handling differential networks can lead to circuit malfunction or undesirable consequences such as signal reflections, crosstalk, delay mismatch, radiation, received electromagnetic interference, common-mode noise, ringing, and overshoot. Checking the correctness of differential networks is crucial for ensuring schematic design quality and reliable operation of differential networks within the circuit.

[0003] In the existing technology, during schematic design work, the inspection of differential networks mainly relies on manual work. The manual inspection process is relatively cumbersome. The staff must first manually extract the differential pins of the relevant devices from the complex circuit schematic according to the predetermined function of the circuit. Then, carefully check whether the network name connected to the differential pin conforms to the naming rules of the differential network, and ensure that the positive and negative markings are completely consistent with the positive and negative markings of the pins. The manual review method has many shortcomings. For example, manual review is easily affected by subjective factors such as fatigue and negligence, which makes it difficult to guarantee the accuracy of the review results. At the same time, manual review is inefficient. When faced with large-scale design solutions, the review time increases significantly, seriously affecting the progress of project development.

[0004] Therefore, it is necessary to provide a method that can conveniently, efficiently and accurately check the differential network. Summary of the Invention

[0005] This specification provides a method and device for automatically reviewing the correctness of a schematic diagram differential network, which is used to overcome at least one technical problem existing in the related art.

[0006] According to a first aspect of an embodiment of this specification, a method for automatically reviewing the correctness of a differential network in a circuit schematic diagram is provided. The method is executed by a script program written in a scripting language, and the method includes:

[0007] Parse the target EDIF200 format circuit schematic file, store the parsed attribute information of chip devices in the chip device information matrix Part_U, and store the parsed attribute information of non-chip devices in the non-chip device information matrix Part_other; wherein the chip device information matrix Part_U and the non-chip device information matrix Part_other have the same column index;

[0008] Obtaining the differential pair pins that meet a preset differential pair pin screening condition set in the chip device information matrix Part_U, and sequentially storing the attribute information of all the screened differential pair pins into the differential pair pin information matrix Dif_pin; wherein the differential pair pin screening condition set is used to screen pins belonging to the same pair of differential pins;

[0009] Based on the differential pair pin information matrix Dif_pin and the non-chip device information matrix Part_other, a first differential signal transmission path set is obtained, which includes differential signal transmission paths of all pins in the differential pair pin information matrix Dif_pin; wherein any differential signal transmission path in the first differential signal transmission path set is composed of a plurality of path nodes in sequence, a first path node among the plurality of path nodes represents a pin of a source device that generates a corresponding differential signal, and a last path node represents a pin of a destination device that generates and processes the corresponding differential signal;

[0010] Eliminating the differential signal transmission paths that do not meet a predetermined rule from the first differential signal transmission path set to obtain a second differential signal transmission path set; the predetermined rule being that the types and quantities of resistor and capacitor components on the differential signal transmission paths corresponding to the two pins in a pair of differential pair pins are completely consistent in order;

[0011] Based on a predetermined differential network naming specification, it is examined whether the differential network naming of the differential signal transmission paths of the two pins constituting a pair of differential pair pins in the second differential signal transmission path set meets predetermined requirements.

[0012] In some optional implementations, parsing the target EDIF200 format circuit schematic file, storing the parsed chip device information into the chip device information matrix Part_U, and storing the parsed non-chip device attribute information into the non-chip device information matrix Part_other, specifically includes:

[0013] Traversing the project matrix structure of the target EDIF200 format circuit schematic file layer by layer, and identifying the version declaration segment, design hierarchy segment, and library definition segment in the header of the file;

[0014] Recursively parse the hierarchical data blocks formed by bracket syntax in the file based on a predefined keyword processing priority order, wherein the connection topology relationship between network nodes is synchronously recorded when extracting electrical network information;

[0015] During the component instantiation processing stage, the device bit number identifier is matched by regular expression, and the chip device classification containing the U character prefix is stored in the chip device information matrix Part_U, and the device classification containing the character prefix of the non-chip device is stored in the non-chip device information matrix Part_other.

[0016] In some optional implementations, the preset differential pair pin screening condition set is:

[0017] (1) The two pins that constitute a differential pair of pins are adjacent pins on the same chip;

[0018] (2) Both pins in a differential pair are passive pins;

[0019] (3) The pin names of the two pins that form a differential pair of pins have the same character length;

[0020] (4) The pin names of the two pins that form a differential pair of pins are identical except for a single character, and the identical and different characters are in the same position in the pin names;

[0021] (5) The different characters in the names of the two pins constituting a differential pair of pins are selected from one of the three combinations of [+, -], [N, P], and [n, p];

[0022] The process of storing the attribute information of all the screened differential pair pins in the differential pair pin information matrix Dif_pin in order specifically includes:

[0023] Performing a nested loop traversal on the chip device information matrix Part_U, wherein an outer loop in the nested loop scans the pin data in the chip device information matrix Part_U row by row, and an inner loop in the nested loop performs pairing analysis on the pin data of the current row with the pin data of each row after the current row according to the preset differential pair pin screening condition set, and writes the complete attribute information of the two pins in a pair of successfully paired differential pair pins into two consecutive rows in the differential pair pin information matrix Dif_pin in the traversal order, thereby forming a paired storage structure;

[0024] The above operation is executed in a loop until all the data in the chip device information matrix Part_U is traversed, and until the pin attribute information of all differential pair pins in the chip device information matrix Part_U is filled into the differential pair pin information matrix Dif_pin.

[0025] In some optional implementations, obtaining, based on the differential pair pin information matrix Dif_pin and the non-chip device information matrix Part_other, a first differential signal transmission path set including differential signal transmission paths of all pins in the differential pair pin information matrix Dif_pin specifically includes:

[0026] The pin information of the two pins belonging to the same pair of differential pins in the differential pair pin information matrix Dif_pin is split into the first differential pin matrix Dif_pin1 and the second differential pin matrix Dif_pin2 in sequence; based on the non-chip device information matrix Part_other, the first differential pin matrix Dif_pin1 and the second differential pin matrix Dif_pin2, a first differential signal transmission path set of the differential signal transmission paths of all pins in the differential pair pin information matrix Dif_pin is obtained.

[0027] According to a second aspect of an embodiment of this specification, there is provided an automatic review device for the correctness of a differential network of a circuit schematic diagram, comprising:

[0028] A circuit schematic parsing module, configured to parse a target EDIF200 format circuit schematic file, store the parsed attribute information of chip components in a chip component information matrix Part_U, and store the parsed attribute information of non-chip components in a non-chip component information matrix Part_other; wherein the chip component information matrix Part_U and the non-chip component information matrix Part_other have the same column index;

[0029] A differential pair pin screening module is configured to obtain differential pair pins that meet a preset differential pair pin screening condition set in the chip device information matrix Part_U, and sequentially store attribute information of all screened differential pair pins into the differential pair pin information matrix Dif_pin; wherein the differential pair pin screening condition set is used to screen pins belonging to the same pair of differential pins;

[0030] a differential signal transmission path set acquisition module, configured to obtain, based on the differential pair pin information matrix Dif_pin and the non-chip device information matrix Part_other, a first differential signal transmission path set including differential signal transmission paths for all pins in the differential pair pin information matrix Dif_pin; wherein any differential signal transmission path in the first differential signal transmission path set is sequentially composed of a plurality of path nodes, wherein the first path node of the plurality of path nodes represents the pin of a source device that generates a corresponding differential signal, and the last path node represents the pin of a destination device that generates and processes the corresponding differential signal;

[0031] a differential path screening module, configured to remove differential signal transmission paths from the first differential signal transmission path set that do not meet a predetermined rule, thereby obtaining a second differential signal transmission path set; the predetermined rule being that the types and quantities of resistor and capacitor components on the differential signal transmission paths corresponding to the two pins of a differential pair of pins are completely consistent in order;

[0032] The differential network naming review module is used to review whether the differential network naming of the differential signal transmission paths of the two pins constituting a pair of differential pair pins in the second differential signal transmission path set meets the predetermined requirements based on the predetermined differential network naming specification.

[0033] The beneficial effects of the embodiments of this specification are as follows:

[0034] 1. The technical solution of this application can automatically obtain chip pins, electrical network and other data by traversing the circuit schematic file in EDIF200 format, screen differential pins according to set rules, obtain differential paths, review correctness and naming standards, and organize and output the results. This automated process can improve review efficiency, avoid errors caused by human negligence, and improve review accuracy.

[0035] 2. The technical solution of this application is reviewed based on predetermined rules and is not affected by design revisions. Therefore, no matter how the design is changed, as long as it complies with the EDIF200 standard format, it can be automatically reviewed according to established rules, and has strong adaptability.

[0036] 3. This technical solution places no restrictions on the scale or complexity of circuit design projects. It can accurately review differential networks, whether for simple, small circuits or large circuits containing numerous chips and complex topologies. Furthermore, it offers cross-platform compatibility, running stably in various operating systems, EDA tools, and other design environments. It is also robust, capable of handling special situations such as missing data and formatting anomalies, ensuring the stability and reliability of review work. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of this specification or related technologies, the following briefly introduces the drawings required for use in the embodiments or related technical descriptions. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0038] Figure 1 A method flow chart of an automatic review method for the correctness of a differential network of a circuit schematic provided in an embodiment of this specification;

[0039] Figure 2 A partial differential circuit schematic diagram in one embodiment of a method for automatically reviewing the correctness of a differential network in a circuit schematic provided in an embodiment of this specification;

[0040] Figure 3 for Figure 2 Schematic diagram of part of the chip device information matrix Part_U and the non-chip device information matrix Part_other in the embodiment;

[0041] Figure 4 Schematic diagram of part of the differential pair pin information matrix Dif_pin in an embodiment;

[0042] Figure 5 Schematic diagram of a first differential path matrix DiffNet1 and a second differential path matrix DiffNet2 in an embodiment;

[0043] Figure 6 This is a schematic diagram of an output report in the embodiment;

[0044] Figure 7 This is a schematic diagram of the structure of an automatic review device for the correctness of a differential network of a circuit schematic diagram provided in an embodiment of this specification. DETAILED DESCRIPTION

[0045] The following will be combined with the drawings in the embodiments of this specification to clearly and completely describe the technical solutions in the embodiments of this specification. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0046] It should be noted that the terms "including" and "having" and any variations thereof in the embodiments of this specification and the accompanying drawings are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units that are not listed, or may optionally include other steps or units that are inherent to the process, method, product, or apparatus.

[0047] Before introducing the technical solution of the present application, the terms "differential signal" and "differential network" are explained first. Among them, the differential signal consists of a pair of signals, the voltage of which is equal in magnitude and opposite in polarity. It is realized by transmitting a pair of voltage signals with opposite polarity through two signal lines, and the receiving end restores the original information by detecting the difference between the two. The differential network refers to the complete path that the differential signal passes through from the transmitting end to the receiving end. It is the physical carrier of the differential signal and must meet the path symmetry and naming specifications, including the differential pins of the source device, the intermediate series resistor / capacitor / inductor components, the differential pins of the target device, and the network name. The device types and quantities of the two paths for transmitting differential signals must be exactly the same in order, and the network name must clearly indicate the polarity.

[0048] The current method for checking differential networks in schematic design involves manually extracting the differential pins of relevant components based on the intended circuit function. The method then checks whether the net names connected to the differential pins comply with the naming rules for differential networks and that the positive and negative symbols are consistent with the pins. Furthermore, the method checks whether the nets connected to the differential pins contain components such as ferrite beads, zero-resistance resistors, and common-mode inductors. The circuit topology connections in schematic designs are often complex, and manual network traversal and screening can, to a certain extent, affect the efficiency and accuracy of differential network correctness checks. This impact is particularly pronounced when the design is large.

[0049] In order to solve the above technical problems, the technical solution of the present application provides a convenient, efficient and accurate differential network automatic inspection method, which can realize efficient review of differential networks while ensuring accuracy, thereby improving the efficiency and quality of hardware design work. The technical solution of the present application is introduced below in conjunction with the accompanying drawings.

[0050] Figure 1 This is a flow chart of a method for automatically checking the correctness of a circuit schematic differential network provided by an embodiment of this specification. From a program perspective, the execution body of the flow can be a script program written in a scripting language.

[0051] like Figure 1 As shown, the process may include the following steps.

[0052] The embodiments of this specification provide a method for automatically reviewing the correctness of a differential network in a circuit schematic diagram. The method can be executed by a script program and can include the following steps:

[0053] Step 102: Parse the target EDIF200 format circuit schematic file, store the attribute information of the chip devices obtained by the analysis into the chip device information matrix Part_U, and store the attribute information of the non-chip devices obtained by the analysis into the non-chip device information matrix Part_other; wherein the chip device information matrix Part_U and the non-chip device information matrix Part_other have the same column index.

[0054] First, let's explain the term "EDIF200" in this step. EDIF200 (Electronic Design Interchange Format) is a specific version of the Electronic Design Interchange Format (EDIF), specifically used to describe and exchange circuit design information between Electronic Design Automation (EDA) tools. EDIF files store data in plain text and use a hierarchical bracket structure to express design data, which can accurately express the hierarchical relationship and logical structure of the circuit design. The components of the EDIF200 file structure include version status information and component elements. The EDIF200 file structure includes version status information such as EDIF (root element, indicating the beginning of the file), edifVersion (EDIF version number), edifLevel (EDIF file level), keywordMap (keyword mapping), status (design file status information), as well as Library (a library containing a group of related units), Cell (circuit unit), Interface (input and output ports of the circuit unit), Port (a port of the unit, defining the name, direction and other parameters of the port), Contents (the specific content of each circuit unit, which describes the internal structure and connections of the circuit unit in detail). Connection relationship, including information such as the sub-units, components and connections between them), Instance (an instance of a unit, which can be a reference to another unit. Through instantiation, the same unit can be used multiple times in different locations without repeating its internal structure. Each instance has its own name and location information, which is convenient for management and identification in circuit design), Net (network connection, used to represent the connection between different instance ports), Property (related ancillary information in the design element, including additional information of the design element (such as units, ports, networks, etc.), such as component parameter values, layout constraints, design annotations, etc.) and other hierarchically divided components. Therefore, since the target EDIF200 format circuit schematic file is the processing object of the automatic review method for the correctness of the differential network of the entire circuit schematic, EDIF (Electronic Design Interchange Format) is a standard format for electronic design data exchange, and EDIF200 is a specific version of the standard. This format uses text form to describe circuit design information in a structured manner. It has good versatility and portability and can exchange data between different electronic design automation (EDA) tools. The file contains a hierarchical project matrix structure, which involves information such as chip devices, non-chip devices and the electrical connection relationship between them.By parsing it, chip device information and non-chip device attribute information can be obtained, and this information will be stored in corresponding matrices (such as chip device information matrix Part_U and non-chip device information matrix Part_other).

[0055] Non-chip components refer to basic components in electronic circuits other than integrated circuit chips (such as microcontrollers and amplifiers). Non-chip components can include resistors, capacitors, inductors, and other passive components (such as diodes and fuses). Chip components are integrated circuits that integrate a large number of transistors, resistors, capacitors, and other components on a single silicon wafer using semiconductor technology.

[0056] Step 104: Obtain the differential pair pins that meet the preset differential pair pin screening condition set in the chip device information matrix Part_U, and store the attribute information of all the screened differential pair pins in order into the differential pair pin information matrix Dif_pin; wherein, the differential pair pin screening condition set is used to screen pins belonging to the same pair of differential pins.

[0057] In this step, the term "differential pin pair" refers to a pair of pins on the same chip used to transmit differential signals. The "differential pin pair screening condition set" refers to the rules used to identify chip differential pin pairs. This is used to accurately identify pin pairs that meet differential signal transmission requirements from the chip device information matrix Part_U. In this step, the attribute information of all differential pin pairs screened from the chip device information matrix Part_U is sequentially stored in the differential pin pair information matrix Dif_pin.

[0058] Step 106: Based on the differential pair pin information matrix Dif_pin and the non-chip device information matrix Part_other, a first differential signal transmission path set including the differential signal transmission paths of all pins in the differential pair pin information matrix Dif_pin is obtained; wherein, any differential signal transmission path in the first differential signal transmission path set is composed of multiple path nodes in sequence, the first path node among the multiple path nodes represents the pin of the source device that generates the corresponding differential signal, and the last path node represents the pin of the destination device that generates and processes the corresponding differential signal.

[0059] In this step, since the transmission path of the differential signal is constructed with the help of the connection relationship of the electrical network, the connection information between the pins of non-chip devices such as resistors, capacitors, and inductors and the network is stored in the non-chip device information matrix Part_other, and the differential pins and the network to which they are connected are recorded in the differential pair pin information matrix Dif_pin. By matching the network names, the differential pins and the pins of the non-chip device can be associated to form a continuous signal transmission path, thereby obtaining the differential signal transmission path of each pin in the differential pair pin information matrix Dif_pin, forming a first differential signal transmission path set.

[0060] Step 108: Eliminate the differential signal transmission paths that do not meet a predetermined rule in the first differential signal transmission path set to obtain a second differential signal transmission path set; the predetermined rule is that the types and quantities of resistor and capacitor components on the differential signal transmission paths corresponding to the two pins in a pair of differential pair pins are completely consistent in order.

[0061] The purpose of this step is to review the correctness of the differential network. Its goal is to verify the symmetry of the differential pair paths and eliminate the paths that do not meet the predetermined rules to ensure the integrity and anti-interference ability of the differential signal transmission. As mentioned above, the device types and quantities of the two paths that transmit differential signals must be exactly the same in order.

[0062] Step 110: Checking whether the differential network naming of the differential signal transmission paths of the two pins constituting a differential pair of pins in the second differential signal transmission path set meets predetermined requirements based on a predetermined differential network naming specification.

[0063] The differential network naming convention in this step is a set of naming rules developed to ensure the correctness of differential signal transmission. It is used to standardize the name format of differential networks. Its goal can be to distinguish the positive and negative polarity of differential pairs through names to avoid signal confusion caused by naming ambiguity. It can also provide a structured basis for subsequent path tracing and correctness verification.

[0064] based on Figure 1 The present specification also provides some specific implementation plans of the method, which are described below.

[0065] In an optional embodiment, the target EDIF200 format circuit schematic file is parsed, and the chip device information obtained by parsing is stored in the chip device information matrix Part_U, and the non-chip device attribute information obtained by parsing is stored in the non-chip device information matrix Part_other. Specifically, the following steps may be performed:

[0066] Traversing the project matrix structure of the target EDIF200 format circuit schematic file layer by layer, and identifying the version declaration segment, design hierarchy segment, and library definition segment in the header of the file;

[0067] Recursively parse the hierarchical data blocks formed by bracket syntax in the file based on a predefined keyword processing priority order, wherein the connection topology relationship between network nodes is synchronously recorded when extracting electrical network information;

[0068] During the component instantiation processing stage, the device bit number identifier is matched by regular expression, and the chip device classification containing the U character prefix is stored in the chip device information matrix Part_U, and the device classification containing the character prefix of the non-chip device is stored in the non-chip device information matrix Part_other.

[0069] The goal of this step is to extract the attribute information of chip devices (such as U401, U1400) and non-chip devices (such as R414, C481) from the EDIF file, and store them by type in the chip device information matrix Part_U and the non-chip device information matrix Part_other. The specific process can be to first traverse the file structure, that is, identify the header information and hierarchical data blocks of the EDIF file layer by layer. Then perform data extraction and recursive parsing, that is, recursively parse the electrical network and device information based on keyword priority. Finally, the device information is classified and stored. The device prefix can be matched by regular expression, and the chip and non-chip devices can be stored in the corresponding matrix respectively. The EDIF file uses a nested bracket structure (similar to Lisp syntax). The parser traverses each project matrix layer by layer, starting from the top-level design and recursively processing the sub-modules. At the same time, the keyword processing priority can be pre-defined to ensure that key information is extracted first when resolving conflicts (such as processing the design hierarchy first, then processing the device instance). When parsing pins and networks, the connection relationship between the device pins and the network is recorded synchronously. In this step, during the component instantiation stage, the device number prefix can be matched through regular expressions. For example, chip devices (such as U401 and U1400) can be matched through "^U\d+" and stored in the chip device information matrix Part_U; non-chip devices (such as R414, C481, and L1513) can be matched through "^(R|C|L)\d+" and stored in the non-chip device information matrix Part_other.

[0070] In an optional embodiment technical solution, the column indexes of the chip device information matrix Part_U and the non-chip device information matrix Part_other include, in sequence, the bit number, pin number, pin name, pin type, the network to which the pin is connected, the pin starting point coordinates, the pin ending point coordinates and the total number of pins.

[0071] In the technical solution of this embodiment, both the chip device information matrix Part_U and the non-chip device information matrix Part_other contain 8 columns of the same index (bit number, pin number, pin name, etc.) in sequence, which can ensure that the attribute information of the chip and non-chip devices are fully compatible in data structure. In scenarios such as differential path tracing (i.e., step 106 above), the network connection relationship between the chip pins (relevant information is stored in the chip device information matrix Part_U) and the directly connected devices (relevant information is stored in the non-chip device information matrix Part_other) can be quickly associated through the same column index, for example, electrical connection matching can be achieved through the network columns connected to the pins.

[0072] The following is an explanation of the preset differential pair pin screening condition set mentioned in step 104 above. The screening condition is used to screen out all pairs of differential pair pins from the chip device information matrix Part_U. Each pair of differential pair pins should simultaneously meet all the screening conditions in the differential pair pin screening condition set, that is, all differential pair pins that constitute a pair are screened out from the chip device information matrix Part_U to obtain multiple pairs of differential pair pins.

[0073] In an optional embodiment and technical solution, the preset differential pair pin screening condition set may be:

[0074] (1) The two pins that constitute a differential pair of pins are adjacent pins on the same chip;

[0075] (2) Both pins in a differential pair are passive pins;

[0076] (3) The pin names of the two pins that form a differential pair of pins have the same character length;

[0077] (4) The pin names of the two pins that form a differential pair of pins are identical except for a single character, and the identical and different characters are in the same position in the pin names;

[0078] (5) The different characters in the names of the two pins constituting a differential pair of pins are selected from one of the three combinations of [+, -], [N, P], and [n, p].

[0079] The following explains the above conditions: adjacent pins can refer to two pins on the same chip package that are physically close together or serially adjacent. Since differential signals transmit signals of opposite polarity via two signal lines, the receiver recovers the information through the difference. Having the two pins that make up a differential pair of pins adjacent to each other on the same chip ensures the physical lengths of the two transmission paths are consistent, reducing signal delay differences and improving signal integrity. The passive pins mentioned in the second condition refer to chip pins whose electrical properties are signal transmission-type and lack active drive capabilities (such as output voltage / current). They are typically used to receive or transmit differential signals. The fourth condition is used to restrict the names of two pins belonging to the same differential pair to be identical except for one character, and the positions of the different characters are consistent. Examples include TX_P and TX_N (different characters are P and N), CLK+ and CLK- (different characters are + and -), and data_n and data_p (different characters are n and p). This rule ensures that differential pairs can be accurately identified and processed by automated tools during the design and review process by limiting the set of different characters and enforcing naming symmetry. The fifth condition is used to restrict the different characters to two characters from the same group selected from the following three groups: [+, -]: Indicates the positive and negative polarity of the signal; [N, P]: Identified by letters (N = Negative, P = Positive); [n, p]: Lowercase version, used for the same purpose as above.

[0080] The step of sequentially storing the attribute information of all the screened differential pair pins into the differential pair pin information matrix Dif_pin may specifically include:

[0081] Performing a nested loop traversal on the chip device information matrix Part_U, wherein an outer loop in the nested loop scans the pin data in the chip device information matrix Part_U row by row, and an inner loop in the nested loop performs pairing analysis on the pin data of the current row with the pin data of each row after the current row according to the preset differential pair pin screening condition set, and writes the complete attribute information of the two pins in a pair of successfully paired differential pair pins into two consecutive rows in the differential pair pin information matrix Dif_pin in the traversal order, thereby forming a paired storage structure;

[0082] The above operation is executed in a loop until all the data in the chip device information matrix Part_U is traversed, and until the pin attribute information of all differential pair pins in the chip device information matrix Part_U is filled into the differential pair pin information matrix Dif_pin.

[0083] In the technical solution of this embodiment, a nested loop is used to filter the pin attribute information of all paired differential pins from the chip device information matrix Part_U. The outer loop is used to scan the chip device information matrix Part_U row by row, starting from row 0, until it reaches the second-to-last row. During each iteration of the outer loop, a row is selected as the reference pin for pairing with subsequent rows. The inner loop starts from the row below the current outer row and traverses to the end of the chip device information matrix Part_U, comparing the reference pins one by one with each row of the inner loop according to the screening criteria.

[0084] In an optional embodiment technical solution, obtaining a first differential signal transmission path set including differential signal transmission paths of all pins in the differential pair pin information matrix Dif_pin based on the differential pair pin information matrix Dif_pin and the non-chip device information matrix Part_other may specifically include:

[0085] The pin information of the two pins belonging to the same pair of differential pins in the differential pair pin information matrix Dif_pin is split into the first differential pin matrix Dif_pin1 and the second differential pin matrix Dif_pin2 in sequence; based on the non-chip device information matrix Part_other, the first differential pin matrix Dif_pin1 and the second differential pin matrix Dif_pin2, a first differential signal transmission path set of the differential signal transmission paths of all pins in the differential pair pin information matrix Dif_pin is obtained.

[0086] In step 104, the differential pair pin information matrix Dif_pin, which stores all filtered differential pair pin information, has been obtained. Two adjacent rows in the differential pair pin information matrix Dif_pin represent a pair of differential pins. To facilitate subsequent processing of the two pins of a differential pair, the matrix can be split into two matrices: a first differential pin matrix Dif_pin1 and a second differential pin matrix Dif_pin2. The splitting rule is to place two differential pins in adjacent rows of the Dif_pin matrix that form a differential pair of pins, one into the first differential pin matrix Dif_pin1 and the other into the second differential pin matrix Dif_pin2, ensuring that two pins with the same sequence number in the first differential pin matrix Dif_pin1 and the second differential pin matrix Dif_pin2 form a differential pair.

[0087] For example, assume that the differential pair pin information matrix Dif_pin is as follows:

[0088]

[0089]

[0090] After splitting, the first differential pin matrix Dif_pin1 matrix is:

[0091] Line number Chip bit number Pin number Pin Name The network to which the pin is connected 1 U1 P1 Pin1+ Net1+ 2 U2 P3 Pin2+ Net2+

[0092] The second differential pin matrix Dif_pin2 is

[0093] Line number Chip bit number Pin number Pin Name The network to which the pin is connected 1 U1 P2 Pin1- Net1- 2 U2 P4 Pin2- Net2-

[0094] Because the transmission path of differential signals is constructed using the connection relationship of electrical networks, the non-chip device information matrix Part_other stores the connection information between the pins of non-chip devices such as resistors, capacitors, and inductors and the network. The first differential pin matrix Dif_pin1 and the second differential pin matrix Dif_pin2 record the differential pins and the networks they are connected to. By matching the network names, the differential pins can be associated with the pins of the non-chip devices, thereby forming a continuous signal transmission path. At the same time, in this step, the Dif_pin matrix is split into the first differential pin matrix Dif_pin1 and the second differential pin matrix Dif_pin2 to track the positive and negative paths of the differential pair separately. The positive pin (such as SENSE+) and the negative pin (such as SENSE-) are each connected to different networks, such as N19697327 and N19697329. By matching the pin networks of the devices in the non-chip device information matrix Part_other, independent paths can be constructed for the positive and negative pins.

[0095] In an optional embodiment technical solution, obtaining a first differential signal transmission path set of differential signal transmission paths of all pins in the differential pair pin information matrix Dif_pin based on the non-chip device information matrix Part_other, the first differential pin matrix Dif_pin1, and the second differential pin matrix Dif_pin2 may specifically include:

[0096] S1. Obtaining the differential signal transmission paths corresponding to a pair of differential pair pins located at the starting position in the differential pair pin information matrix Dif_pin, specifically comprising:

[0097] S11, starting from a first initial differential pin in the first differential pin matrix Dif_pin1 and a second initial differential pin in the second differential pin matrix Dif_pin2, respectively, initiating a recursive traversal operation, wherein the first initial differential pin and the second initial differential pin belong to a pair of differential pair pins located at a starting position in the differential pair pin information matrix Dif_pin;

[0098] S12. In the recursive process, according to the non-chip device information matrix Part_other, the resistor and capacitor devices that are directly electrically connected to the current traversal node are searched level by level, and the following two recursive paths are generated:

[0099] The first recursive path: starting from the initial node of the first differential pin matrix Dif_pin1, and extending along the connection relationship between the resistor and capacitor components;

[0100] The second recursive path: starting from the initial node of the second differential pin matrix Dif_pin2, and extending along the connection relationship between the resistor and capacitor components;

[0101] S13. Stop the recursion when any of the following termination conditions is met:

[0102] (1) There is no associated resistor / capacitor device at the end of the current path;

[0103] (2) The first recursive path and the second recursive path intersect at the same resistor-capacitor device node;

[0104] S14. Encode each node in the first recursive path according to a coding format of "device bit number_pin number_net name" to obtain a first differential signal transmission path of the first initial differential pin; and encode each node in the second recursive path according to a coding format of "device bit number_pin number_net name" to obtain a second differential signal transmission path of the second initial differential pin.

[0105] The first differential signal transmission path is stored in a first differential path matrix DiffNet1, and the second differential signal transmission path is stored in a second differential path matrix DiffNet2, and the network name at the end of the path is bound to the differential network identifier of the corresponding differential pin;

[0106] S2. Obtain the differential signal transmission paths corresponding to the first pair of differential pair pins in the differential pair pin information matrix Dif_pin in the same manner as the differential signal transmission paths corresponding to the first pair of differential pair pins in the differential pair pin information matrix Dif_pin. The differential signal transmission paths corresponding to the remaining differential pair pins in the differential pair pin information matrix Dif_pin are stored in sequence in the first differential path matrix DiffNet1 and the second differential path matrix DiffNet2.

[0107] The identically numbered rows in the first differential pin matrix Dif_pin1 and the second differential pin matrix Dif_pin2 store attribute information for the two differential pins that comprise a differential pair. Specifically, identically numbered rows in the first differential pin matrix Dif_pin1 and the second differential pin matrix Dif_pin2 store the starting points for the positive and negative signal transmissions for the same differential pin pair. In this embodiment, step S1 initiates a recursive traversal using the first initial differential pin in the first row of the first differential pin matrix Dif_pin1 and the second initial differential pin in the first row of the second differential pin matrix Dif_pin2 as starting points, independently tracing the transmission paths of the positive and negative signals. This allows for understanding the resistors, capacitors, and networks that each signal path passes through, thereby accurately analyzing the transmission of the differential signals. The following uses the first differential pair of pins in the Dif_pin matrix (i.e., the differential pins in the first row of the first differential pin matrix Dif_pin1 and the differential pins in the first row of the second differential pin matrix Dif_pin2) as an example to illustrate how the recursive traversal operation is performed. Since the two recursive traversal operations are performed independently, the following analysis uses the first differential pin matrix Dif_pin1 as the analysis object and the first initial differential pin in the first row of the matrix as an example to explain in detail how the recursive traversal is performed.

[0108] First, an initialization operation is performed. The first initial differential pin in the first row is selected from the first differential pin matrix Dif_pin1. For example, the first differential pin matrix Dif_pin1 in the previous embodiment has the following information: chip bit number U1, pin number P1, and connection network Net1+. This differential pin is used as the current node. An empty list path is created to store the traversal path. The current node is added to the path list in the format of "device bit number_pin number_network name" (i.e., U1_P1_Net1+). A recursive traversal operation then begins. Starting from the connection network Net1+ of the current node, the non-chip device information matrix Part_other is searched for all non-chip device pins connected to this network. Assume that two non-chip device pins connected to Net1+ are found in the non-chip device information matrix Part_other: pin R1_P1 of resistor R1 and pin C1_P1 of capacitor C1. Then, the path is expanded recursively. For each connected pin found, the following operations are performed: (1) For pin R1_P1, the network corresponding to R1_P1 (assuming it is Net2) is used as the new current network, and R1_P1 is added to the path list in the format of "device number_pin number_network name" (i.e., R1_P1_Net2). With R1_P1 as the new current node, the traversal function is recursively called, and the non-chip device pins connected to it are searched in the non-chip device information matrix Part_other starting from the Net2 network. That is, since the non-chip device information matrix Part_other stores information about other devices besides chips (such as capacitors, resistors, inductors, etc.), by comparing the names of the electrical connection networks, the capacitors, resistors, and inductors directly connected to the current traversal node can be found. After finding the directly connected devices, the pins of these directly connected devices are used as new starting points, and the above search process is repeated to continue searching for other devices with the same electrical connection network as these new starting points, gradually expanding the differential path. (2) For pin C1_P1, set the network corresponding to C1_P1 (assuming it is Net3) as the new current network and add C1_P1 to the path list in the format of "device number_pin number_net name" (i.e., C1_P1_Net3). Then, with C1_P1 as the new current node, recursively call the traversal function, continuing from Net3 and searching for the non-chip device pins connected to it in the non-chip device information matrix Part_other.

[0109] During the recursive process, it is necessary to determine whether the termination condition is met. The recursion stops when any of the following conditions are met: (1) There is no associated resistor and capacitor device at the end of the current path. That is, if no non-chip device pin connected to the current network is found in the non-chip device information matrix Part_other, it means that the path has reached the end and the recursion stops. For example, when recursively expanding from R1_P1, it is found that the Net2 network is not connected to any non-chip device pin. At this time, the recursion starting from R1_P1 is stopped.

[0110] (2) The recursive path of the second differential pin matrix Dif_pin2 intersects at the same resistor and capacitor device node, that is, during the traversal process, the recursive traversal of the corresponding initial differential pin in the second differential pin matrix Dif_pin2 needs to be performed simultaneously. If the recursive path of the first differential pin matrix Dif_pin1 and the recursive path of the second differential pin matrix Dif_pin2 intersect at the same non-chip device node, it means that the positive and negative paths of the differential signal converge here, and the recursion stops. For example, if the path of the first differential pin matrix Dif_pin1 extends to R2_P2, and the path of the second differential pin matrix Dif_pin2 also extends to R2_P2, the recursion stops at this time.

[0111] When the recursion is completed, the path information in the path list is stored in the first differential path matrix DiffNet1, and the network name at the end of the path is bound to the differential network identifier of the corresponding differential pin.

[0112] After traversing a differential path, the path information needs to be stored. The storage format uses "device number_pin number_net name" as a node, and records all devices and electrical networks passed through in the path. For example, if the path passes through pin 1 of chip U1, connects to pin 2 of capacitor C1, and then connects to pin 3 of resistor R2, the corresponding networks are Net1, Net2, and Net3 respectively. The stored node information is "U1_1_Net1", "C1_2_Net2", and "R2_3_Net3".

[0113] All devices and electrical networks in the current differential path are stored as a complete differential path in the first differential path matrix DiffNet1 or the second differential path matrix DiffNet2 in node format. That is, the differential path obtained from the pins in the first differential pin matrix Dif_pin1 is stored in the first differential path matrix DiffNet1, and the differential path obtained from the pins in the second differential pin matrix Dif_pin2 is stored in the second differential path matrix DiffNet2.

[0114] For example, assuming that the complete path starting from Pin1+ of the first differential pin matrix Dif_pin1 passes through capacitor C1, resistor R2, and inductor L3 in sequence, the corresponding networks are Net1+, Net2, and Net3, and assuming that the serial numbers of the connection pins of each device are 2, 3, and 4, then the information of each path node in the differential signal transmission path (differential signal transmission path refers to the physical route that the differential signal passes from the transmitting end to the receiving end in the circuit) stored in the first row of the first differential path matrix DiffNet1 can be specifically shown in the following table:

[0115] Node number Node Information 1 U1_1_Net1+ 2 C1_2_Net2 3 R2_3_Net3 4 L3_4_Net3

[0116] The DiffNet1 matrix displays information of each transmission node on the complete differential signal transmission path of a single pin "Pin1+" of the first differential pin matrix Dif_pin1 row by row according to the "node number". In practice, the number of pins corresponding to the complete differential path information stored in the DiffNet1 matrix depends on the number of differential pins in the first differential pin matrix Dif_pin1. That is, the matrix DiffNet1 stores all complete differential path information obtained from each differential pin in the first differential pin matrix Dif_pin1. This information records the nodes through which the differential signal is transmitted in the circuit in a specific format. That is, each row in the matrix DiffNet1 represents the differential signal transmission path information of a differential pin. For example, the first row can store the differential signal transmission path of the 'Pin1+' pin in the first differential pin matrix Dif_pin1, namely "'U1_1_Net1+', 'C1_2_Net2', 'R2_3_Net3', and 'L3_4_Net3'".

[0117] Starting from Pin1- of the second differential pin matrix Dif_pin2, assuming that it passes through capacitor C3, resistor R4, and inductor L4, the corresponding networks are Net4-, Net5, and Net6, and the serial numbers of the connection pins of each device are 5, 6, and 7 respectively. Then the information of each path node in the differential signal transmission path stored in the first row of the DiffNet2 matrix can be shown in the following table:

[0118] Node number Node Information 1 U1_2_Net1- 2 C3_5_Net4- 3 R4_6_Net5 4 L4_7_Net6

[0119] A differential signal originates from a differential pin, passes through a series of devices, and finally reaches the connected electrical network. This final electrical network is the target network for the differential signal, that is, the differential network corresponding to the differential pin. In other words, the electrical network at the end of the stored differential path is the differential network corresponding to the currently traversed node. For example, in the example above, the differential network corresponding to Pin 1+ is Net 3, and the differential network corresponding to Pin 1- is Net 6. After completing the above steps, the differential path and differential network corresponding to the differential pin can be obtained.

[0120] For the remaining pairs of differential pair pins in the differential pair pin information matrix Dif_pin, the differential signal transmission paths corresponding to the pair of differential pair pins located at the starting position in the differential pair pin information matrix Dif_pin can be obtained, and the differential signal transmission paths corresponding to the remaining differential pair pins in the differential pair pin information matrix Dif_pin can be obtained, and can be stored in the matrix DiffNet1 and the matrix DiffNet2 in sequence.

[0121] In an optional embodiment and technical solution, removing the differential signal transmission paths that do not meet a predetermined rule from the first differential signal transmission path set may specifically include:

[0122] Simultaneously traversing the first differential path matrix DiffNet1 and the second differential path matrix DiffNet2, screening out all differential signal transmission paths belonging to the same pair of differential pins that do not satisfy the predetermined rule, then removing the screened differential signal transmission paths that do not satisfy the predetermined rule from the corresponding first differential path matrix DiffNet1 or the first differential path matrix DiffNet2, to obtain an updated first differential path matrix DiffNet1 and an updated second differential path matrix DiffNet2;

[0123] The step of removing the screened differential signal transmission paths that do not meet the symmetry condition from the corresponding first differential path matrix DiffNet1 or the first differential path matrix DiffNet2 may include:

[0124] The filtered differential signal transmission paths that do not meet the predetermined rule are stored in the Diff_no_cor matrix in order.

[0125] For a standard differential pair in a circuit, its core characteristic is complete symmetry. This symmetry is reflected in the fact that the types and quantities of resistors and capacitors on the differential signal transmission paths corresponding to the two pins in a pair of differential pair pins are completely consistent in order (i.e., the "predetermined rules"). Only in this way can the signal attenuation, delay and other characteristics on the two paths be kept consistent when the differential signal is transmitted, effectively suppressing common-mode interference and ensuring signal integrity and accuracy. Once the differential path is asymmetric, it may cause signal distortion, making it difficult for the receiving end to accurately restore the transmitted signal, thereby affecting the performance of the entire circuit system. Therefore, the correctness of the differential network is also reviewed in the technical solution of this application. The content of this review process is analyzed in detail below.

[0126] The first differential path matrix DiffNet1 and the second differential path matrix DiffNet2 respectively store the differential path information obtained from the two pins of the same differential pair, and the elements in the same position (i.e., the same row number) in the matrix DiffNet1 and the matrix DiffNet2 correspond exactly to the two differential paths in a differential pair. During the review, the DiffNet1 matrix and the DiffNet2 matrix are operated in a synchronous traversal manner. Starting from the first row of the matrix, using the row number as a clue, the elements with the same row number in the DiffNet1 and DiffNet2 matrices are processed simultaneously. For example, when processing the third row of the DiffNet1 matrix, the third row of the DiffNet2 matrix must be processed at the same time, because the elements in these two rows represent the two paths of the same differential pair, which can achieve accurate comparison. For each pair of paths that need to be compared, the specific comparison method is to deeply analyze the node information in the path. As mentioned earlier, node information is stored in the format of "device number_pin number_net name." The present invention uses this format to extract the device type at each node and then count the number of each type of device in each path. For example, for node "R3_1_Net1" in the path, the present invention determines that its device type is a resistor; for node "C5_2_Net2," its device type is a capacitor. In this way, the number of various devices, such as resistors, capacitors, and inductors, in the two paths is carefully counted to determine whether they are consistent. If the comparison reveals that two differential paths in the same differential pair are asymmetrical—that is, the types or numbers of serially connected devices differ—these two paths are immediately filtered out. For example, if a path in a row of the DiffNet1 matrix contains three resistors and one capacitor, while the path in the corresponding row of DiffNet2 contains two resistors and two capacitors, the two paths are clearly asymmetrical and need to be filtered out. The filtered paths are removed from both the DiffNet1 and DiffNet2 matrices to ensure that only the correct differential path information is subsequently retained in these two matrices. At the same time, these filtered paths are stored in a dedicated matrix, Diff_no_cor. This storage method is to store the filtered paths in the DiffNet1 matrix in a row of DiffNet_no_cor, followed by the corresponding paths in the DiffNet2 matrix in the next row. This way, the Diff_no_cor matrix fully stores all incorrect differential paths, facilitating subsequent centralized analysis and processing.

[0127] For example, assume that parts of the first differential path matrix DiffNet1 and the second differential path matrix DiffNet2 are as follows:

[0128] DiffNet1:

[0129] Line number Node Information 1 U1_1_Net1,R1_2_Net2,C1_3_Net3,R2_4_Net4 2 U2_1_Net5,L1_2_Net6,R3_3_Net7

[0130] DiffNet2:

[0131] Line number Node Information 1 U1_2_Net1,R1_2_Net2,L1_3_Net3,R2_4_Net4 2 U2_1_Net5,R4_2_Net6,R3_3_Net7

[0132] When comparing the first row, it is found that the third node of the path in the first differential path matrix DiffNet1 is capacitor C1, while the third node of the corresponding path in the second differential path matrix DiffNet2 is inductor L1. The device types are different and the paths are asymmetric. Therefore, these two rows of paths are filtered out, removed from the DiffNet1 matrix and the DiffNet2 matrix, and stored in the Diff_no_cor matrix:

[0133] Diff_no_cor matrix:

[0134] Line number Node Information 1 U1_1_Net1,R1_2_Net2,C1_3_Net3,R2_4_Net4 2 U1_2_Net1,R1_2_Net2,L1_3_Net3,R2_4_Net4

[0135] When comparing the second row, there is an inductor L1 in the first differential path matrix DiffNet1, and the corresponding position in the second differential path matrix DiffNet2 is a resistor R4. Since the device types are different, these two rows of paths are also filtered out and stored in the Diff_no_cor matrix:

[0136] Diff_no_cor matrix (after update):

[0137] Line number Node Information 1 U1_1_Net1,R1_2_Net2,C1_3_Net3,R2_4_Net4 2 U1_2_Net1,R1_2_Net2,L1_3_Net3,R2_4_Net4 3 U2_1_Net5,L1_2_Net6,R3_3_Net7 4 U2_1_Net5,R4_2_Net6,R3_3_Net7

[0138] Through such detailed review, screening and storage operations, incorrect differential paths in circuit design can be found efficiently and accurately.

[0139] Based on the above solution, the standardization of differential network naming may also be reviewed. In this solution, reviewing whether the differential network naming of the differential signal transmission paths of the two pins constituting a differential pair of pins in the second differential signal transmission path set meets predetermined requirements based on predetermined differential network naming standards may include:

[0140] Review the naming standardization of the differential networks in the updated first differential path matrix DiffNet1 and the updated second differential path matrix DiffNet2, which may include:

[0141] According to the differential network naming specification, after filtering out incorrect differential paths, the first differential path matrix DiffNet1 and the second differential path matrix DiffNet2 are formed, and the differential pins are obtained from the beginning of the differential path and the differential network names are obtained from the end. The differential network naming specification is reviewed. If the specification is not met, the differential path corresponding to the differential pair is stored in the matrix Diff_name_no_cor. The differential network naming specification is as follows: (1) The differential network name should correspond to the current differential pair pin, that is, in the combination of [+, -], [N, P], [n, p], "-", "N", "n" correspond to each other, and "+", "P", "p" correspond to each other; (2) The character length of the differential network name in the same differential pair is the same; (3) The characters other than a single character in the names of the two differential networks in the differential pair should be the same, and the different single characters should be one of the combinations of [+, -], [N, P], [n, p]; (4) The positions of the same characters and different characters in the differential network name are consistent.

[0142] In the technical solution of this embodiment, the polarity characters of the differential network name must be consistent with the polarity identifiers of the differential pins. The allowed combinations are [+, -] (such as SENSE+ and SENSE-), [N, P] (such as MDIP and MDIN), and [n, p] (such as data_p and data_n). In the [+, -], [N, P], and [n, p] combinations, "-", "N", and "n" correspond to each other, and "+", "P", and "p" correspond to each other. That is, if a differential pin name contains "+", then the polarity-related characters in the corresponding differential network name should be "+" or the corresponding "P" or "p". Similarly, if the differential pin name contains "-", the polarity-related characters in the corresponding differential network name should be "-" or "N" or "n". For example, if the differential pin is "Pin1+", then the corresponding differential network name should contain "+", "P", or "p", such as "Net1+", "Net1P", or "Net1p". For example, ETH_TRD0+ (positive) and ETH_TRD0- (negative) are a correct combination, while ETH_TRD0_P (positive) and ETH_TRD0_N (negative) are incorrect because they mix + / - and P / N. Furthermore, the character length of two net names for the same differential pair must be the same. For example, USB_DP (4 characters) and USB_DM (4 characters) are correct; USB_DP (4 characters) and USB_DM_1 (6 characters) are incorrect because they have different character counts. All characters except a single character must be identical, and the differing character is the polarity identifier. For example, CLK_P and CLK_N (the differing characters are P / N) are a correct combination; CLK_PP and CLK_N are incorrect because they differ by more than one character. The differing characters must be in the same position in the name. For example, TX1_P (the difference is in the 4th position) and TX1_N (the difference is in the 4th position) are a correct combination; TX1_P (the difference is in the 4th position) and TX_P1 (the difference is in the 3rd position) are an incorrect combination.

[0143] Based on the first differential path matrix DiffNet1 and the second differential path matrix DiffNet2 obtained in the previous embodiment, which filter out incorrect differential paths, this method obtains differential pins from the beginning of the differential path and obtains differential network names from the end of the differential path. Combined with the differential network naming specifications set above, the method reviews the standardization of the differential network naming. If the network name does not fully meet the above four specifications, it is considered an incorrectly named differential network, and the differential paths corresponding to the differential pair are stored in adjacent rows of the matrix Diff_name_no_cor.

[0144] Based on the above embodiment, a visualization operation can also be performed, that is, the incorrect differential pairs and differential paths and the differential paths with irregular names in the Diff_no_cor matrix and the Diff_name_no_cor matrix can be converted into strings row by row, and then output as inspection results after adding relevant text descriptions; the inspection results include the following: (1) incorrect differential paths and their asymmetry reasons; (2) differential networks with irregular names and the specific rules they violate.

[0145] This embodiment converts incorrect differential pairs, differential paths, and differential paths with irregular names in the Diff_no_cor matrix and the Diff_name_no_cor matrix into character strings row by row. In the subsequent output process, the character string format can be easily integrated and displayed with relevant text descriptions.

[0146] For incorrect differential paths from the Diff_no_cor matrix, the text description can highlight the specific cause of the incorrect path, such as "The number of resistors in the two paths in the differential pair is inconsistent, affecting the symmetrical transmission of the differential signal." This facilitates quick understanding of the nature of the problem and allows for targeted corrections. For example, in the Diff_no_cor matrix, assume that one row stores the differential path node information "U1_1_Net1, R1_2_Net2, C1_3_Net3" (indicating a differential path starting from pin 1 of chip U1, passing through pin 2 of resistor R1, and pin 3 of capacitor C1). Converting this to a string format would result in a string such as "Differential path: Starting from pin 1 of chip U1, passing through pin 2 of resistor R1, and then connecting to pin 3 of capacitor C1. This path is an incorrect differential path (path components in the differential pair are asymmetric)."

[0147] For differential paths with non-standard naming from the Diff_name_no_cor matrix, the text description can detail which naming specification is not met, such as "In the naming of this differential network, the position of different characters in the name is inconsistent with another differential network, which does not meet the character position consistency requirement in the naming specification." This helps relevant personnel accurately grasp the naming problem and make standardized naming adjustments. For example, for the Diff_name_no_cor matrix, assuming that the differential path node information stored in one row is "U2_1_Net1, R2_2_Net2, Net2_P" (indicating a differential path starting from pin 1 of chip U2, passing through pin 2 of resistor R2, and finally connecting to the differential network named Net2_P), the string may be "Differential path: Starting from pin 1 of chip U2, passing through pin 2 of resistor R2, and connecting to the differential network Net2_P. The differential network corresponding to this path is not named in a standard way (does not meet the character position consistency requirement in the naming specification)."

[0148] In this solution, after converting the path information into a string, adding relevant text descriptions can more clearly convey the problem. The inspection results are then output as strings with text descriptions. The output format can be selected according to actual needs, such as generating a text file containing all incorrect differential paths and improperly named differential paths and their corresponding text descriptions; or displaying them as a list on the design software interface for designers to directly review and process.

[0149] Through the above process of output report compilation and inspection result output, the problems found during the differential network review process can be presented in a clear and easy-to-understand manner, providing strong support for the optimization and improvement of circuit design, and ensuring that the final circuit design meets the correctness and naming standardization requirements of the differential network.

[0150] The technical solution of the present application can automatically obtain chip pins, electrical networks and other data by traversing the circuit schematic file in EDIF200 format, screen differential pins according to set rules, obtain differential paths, review correctness and naming standards, and organize and output the results. This automated process can improve the efficiency of review, avoid errors caused by human negligence, and improve the accuracy of review. The technical solution of the present application is based on predetermined rules for review and is not affected by design revisions. Therefore, no matter how the design is changed, as long as it complies with the EDIF200 standard format, it can be automatically reviewed according to established rules, and has strong adaptability. At the same time, the technical solution of the present application has no restrictions on the scale and complexity of the circuit design project. Whether it is a simple small circuit or a large circuit containing many chips and complex topology structures, it can accurately review the differential network. In addition, it has cross-platform compatibility and can run stably in different design environments such as operating systems and EDA tools. It is also robust and can deal with special situations such as missing data and format anomalies, ensuring the stability and reliability of the review work.

[0151] The technical solution of this application is described below with a complete embodiment. A complete example according to the present invention is as follows:

[0152] Step 1: Read the schematic diagram in EDIF200 format and obtain information such as chip pins, capacitors, resistors, inductors and related electrical networks in the schematic diagram. Figure 2 This is a schematic diagram of a circuit that contains differential pairs. Figure 2 The chip device information matrix Part_U and the non-chip device information matrix Part_other obtained after reading the schematic diagram corresponding to the partial circuit shown are as follows Figure 3 As shown, Figure 3 Some matrix data in contains Figure 2 The relevant pin information of U1400, U401 and R414 is shown in the table below. Figure 3 The contents of the chip device information matrix Part_U and the non-chip device information matrix Part_other.

[0153] Part of the chip device information matrix Part_U

[0154]

[0155]

[0156] The chip device information matrix Part_U is mainly used to store relevant information about chip devices. The matrix contains 8 columns, each with a specific meaning. Specifically, it stores the chip bit number (used to uniquely identify a chip), the pin number (the number of each pin on the chip), the pin name (such as "SENSE+", "MDIP", etc., used to describe the function of the pin), the pin type (such as "passive", etc., which describes the electrical characteristics of the pin), the network to which the pin is connected (indicating which electrical network the pin is connected to), the pin starting point coordinates (position information in the schematic diagram), the pin ending point coordinates (also position information), and the total number of pins on the current chip (the total number of pins on the chip). By storing this information in the chip device information matrix Part_U, all aspects of the chip can be comprehensively described and managed.

[0157] Part of the non-chip device information matrix Part_other

[0158]

[0159]

[0160] The non-chip device information matrix, Part_other, stores information about other devices, such as resistors, capacitors, and inductors. This matrix also contains eight columns and stores information similar to the chip device information matrix, Part_U, except that it contains information about resistors, capacitors, and inductors. For example, information about the resistor's bit number and the network its pins connect to can be stored in separate matrices, facilitating classification, processing, and analysis.

[0161] Step 2: This method identifies the differential pins based on step 1. Based on the chip device information matrix Part_U obtained in step 1, this method identifies the differential pins in the currently read schematic diagram in combination with the five differential pin identification standards described in step 2, such as Figure 4 The figure shows part of the differential pin data in the differential pair pin information matrix Dif_pin obtained by filtering the current input schematic diagram in step 2. Figure 4 The adjacent rows in the Dif_pin part of the differential pair pin information matrix show a pair of differential pin data that meets the differential pin screening criteria, such as "SENSE+", "SENSE-" and "MDIP", "MDIN", etc. Figure 4 The overall content is shown in the following table:

[0162]

[0163]

[0164] Step 3: Acquire the differential pin path. Based on step 2, this method splits the differential pair pin information matrix Dif_pin into the first differential pin matrix Dif_pin1 and the second differential pin matrix Dif_pin2, traverses the first differential pin matrix Dif_pin1 and the second differential pin matrix Dif_pin2 row by row, and acquires the differential path based on the electrical network matching and retrieval method described in step 3, as shown in FIG. Figure 5 The figure shows some differential paths in the first differential path matrix DiffNet1 and the second differential path matrix DiffNet2 obtained by traversal. The differential paths corresponding to the same row in the DiffNet1 matrix and the DiffNet2 matrix belong to the same differential pair. Figure 5 reflects Figure 2 The differential paths of U1400 and U401 in the partial circuit shown.

[0165] Step 4: This method checks the correctness of the differential pair. Based on the first differential path matrix DiffNet1 and the second differential path matrix DiffNet2 obtained in step 3, this method examines the correctness of the differential pair, that is, the symmetry of each differential path in the differential pair. This method traverses the DiffNet1 matrix and the DiffNet2 matrix at the same time, and compares the same row data. Each row of the matrix is a one-dimensional list composed of nodes in the format of "device bit number_pin number_network name". After obtaining the two lists of differential paths corresponding to each differential pair, this method first compares whether the list lengths are the same. If they are different, it is directly determined that the differential pair is incorrect. If they are the same, it is determined whether the starting bit number mark of each node in the list is the same. If they are the same, it is determined to be correct. Otherwise, it is incorrect. The incorrect differential path is removed from the DiffNet1 matrix and the DiffNet2 matrix and saved in the Diff_no_cor matrix. If no incorrect differential pair is checked, the Diff_no_cor matrix is empty. Figure 5 As shown in the figure, the data length of the corresponding rows in the DiffNet1 matrix and the DiffNet2 matrix is the same, and the starting flag of the bit number corresponding to each node is also the same. Therefore, the differential pairs corresponding to U401, U1002 and U1400 shown in the figure can be determined to be correct.

[0166] Step 5: This method performs differential network naming standardization. Based on steps 3 and 4, this method obtains the current differential network name from the end of each differential path in the first differential path matrix DiffNet1 and the second differential path matrix DiffNet2, and reviews the differential network name based on the four differential network naming standards proposed in step 5, such as Figure 5The differential pair corresponding to U401 and U1002 in the differential path shown in FIG does not meet the differential network naming specification and can be determined as non-standard naming. The non-standard named differential pair is stored in the Diff_name_no_cor matrix.

[0167] Step 6: Organize the inspection results and output the report. Based on the previous steps, this method adds text descriptions to the data in the Diff_no_cor and Diff_name_no_cor matrices and converts them into strings, which are output as the output results. If the Diff_no_cor matrix and the Diff_name_no_cor matrix are empty, the output is not found. Figure 6 for Figure 2 The inspection report content corresponding to the partial circuit diagram shown.

[0168] Figure 5 Shown are the first differential path matrix DiffNet1 and the second differential path matrix DiffNet2 in the example. Figure 6 This is the result of reviewing the contents of these matrices, including differential pair correctness checks and incorrectly named differential networks. The following briefly explains the derivation process: Elements at the same position in the DiffNet1 and DiffNet2 matrices represent two differential paths in a differential pair. Both matrices are traversed simultaneously, with the first row of the DiffNet1 matrix and the first row of the DiffNet2 matrix grouped together (they belong to the two paths of the same differential pair), and each subsequent group of corresponding rows is checked in turn.

[0169] For example, for the first row of the first differential path matrix DiffNet1, '["U401_13_N19697327","R414_2_N21905941","R401_4_N21906016"]', and the first row of DiffNet2, '["U401_12_N19697329","R415_2_N21906016","R401_3_N21905941"]', count the types and quantities of devices connected in series in each of these two paths. Device types can be identified by their name prefixes, such as "U" for chips and "R" for resistors. Statistics show that the device types and quantities on both paths are identical (three devices each). Repeat this process for all corresponding rows, comparing the types and quantities of devices connected in series on the two differential paths within the same differential pair. After checking all corresponding rows in the first differential path matrix DiffNet1 and the second differential path matrix DiffNet2, it was found that there was no inconsistency in the type and number of devices connected in series on the two differential paths in the same differential pair, so it was concluded that Figure 6The result "Incorrect differential pair is: Not found" is displayed.

[0170] From the first differential path matrix DiffNet1 and the second differential path matrix DiffNet2, for each group of corresponding rows (ie, two paths of the same differential pair), the differential pin information is obtained from the beginning of the path, and the differential network name is obtained from the end of the path.

[0171] For example, consider the pair '["U1002_1_AP_USB_DP"]' in the first differential path matrix DiffNet1 and '["U1002_2_AP_USB_DM"]' in DiffNet2. First, consider the character lengths; they are identical. Next, consider the correspondence with the differential pair pins. For now, there are no obvious polarity issues (no polarity identifiers such as [+, -], [N, P], or [n, p] appear). Next, consider all characters except for a single character. Aside from "DP" and "DM," the characters "U1002_1_AP_USB_" and "U1002_2_AP_USB_" are not identical (numbers 1 and 2 are different), thus failing the "all characters except a single character should be identical" specification. In this manner, review the differential network names in all corresponding rows of the DiffNet1 and DiffNet2 matrices one by one, combining the four naming conventions described above. The differential paths corresponding to the differential networks that do not fully meet the four naming specifications are filtered out and recorded in Figure 6 Below the "Differential network with irregular naming is", the relevant content is formed, and finally it is concluded that Figure 6 The review result of "The incorrectly named differential network is:..."

[0172] Based on the same idea, the embodiments of this specification also provide a device corresponding to the above method. Figure 7 The embodiments of this specification provide corresponding Figure 1 A schematic diagram of the structure of an automatic review device for the correctness of a circuit schematic differential network. Figure 7 As shown, the device may include:

[0173] A circuit schematic parsing module 702 is configured to parse a target EDIF200 format circuit schematic file, store the parsed attribute information of chip components in a chip component information matrix Part_U, and store the parsed attribute information of non-chip components in a non-chip component information matrix Part_other; wherein the chip component information matrix Part_U and the non-chip component information matrix Part_other have the same column index;

[0174] A differential pair pin screening module 704 is configured to obtain differential pair pins from the chip device information matrix Part_U that meet a preset differential pair pin screening condition set, and sequentially store attribute information of all screened differential pair pins into the differential pair pin information matrix Dif_pin. The differential pair pin screening condition set is used to screen pins belonging to the same pair of differential pins.

[0175] A differential signal transmission path set acquisition module 706 is configured to obtain, based on the differential pair pin information matrix Dif_pin and the non-chip device information matrix Part_other, a first differential signal transmission path set including differential signal transmission paths for all pins in the differential pair pin information matrix Dif_pin; wherein any differential signal transmission path in the first differential signal transmission path set is sequentially composed of a plurality of path nodes, wherein the first path node of the plurality of path nodes represents the pin of a source device that generates a corresponding differential signal, and the last path node represents the pin of a destination device that generates and processes the corresponding differential signal;

[0176] A differential path screening module 708 is configured to remove differential signal transmission paths from the first differential signal transmission path set that do not meet a predetermined rule, thereby obtaining a second differential signal transmission path set; the predetermined rule being that the types and quantities of resistor and capacitor components on the differential signal transmission paths corresponding to the two pins of a differential pair of pins are completely consistent in sequence;

[0177] The differential network naming review module 710 is used to review whether the differential network naming of the differential signal transmission paths of the two pins constituting a pair of differential pair pins in the second differential signal transmission path set meets the predetermined requirements based on the predetermined differential network naming specification.

[0178] Those skilled in the art will appreciate that the accompanying drawings are merely schematic diagrams of an embodiment, and the modules or processes in the accompanying drawings are not necessarily required to implement the present invention.

[0179] Those skilled in the art will appreciate that the modules in the apparatuses of the embodiments may be distributed in the apparatuses of the embodiments as described in the embodiments, or may be located in one or more apparatuses different from the embodiments with corresponding changes. The modules in the above embodiments may be combined into one module or further divided into multiple sub-modules.

[0180] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for automatically reviewing the correctness of differential networks in circuit schematics, characterized in that: The method is executed by a script program and includes the following steps: Parse the target EDIF200 format circuit schematic file, store the parsed attribute information of chip devices in the chip device information matrix Part_U, and store the parsed attribute information of non-chip devices in the non-chip device information matrix Part_other; wherein the chip device information matrix Part_U and the non-chip device information matrix Part_other have the same column index; Obtaining the differential pair pins that meet a preset differential pair pin screening condition set in the chip device information matrix Part_U, and sequentially storing the attribute information of all the screened differential pair pins into the differential pair pin information matrix Dif_pin; wherein the differential pair pin screening condition set is used to screen pins belonging to the same pair of differential pins; Based on the differential pair pin information matrix Dif_pin and the non-chip device information matrix Part_other, a first differential signal transmission path set is obtained, which includes differential signal transmission paths of all pins in the differential pair pin information matrix Dif_pin; wherein any differential signal transmission path in the first differential signal transmission path set is composed of a plurality of path nodes in sequence, a first path node among the plurality of path nodes represents a pin of a source device that generates a corresponding differential signal, and a last path node represents a pin of a destination device that generates and processes the corresponding differential signal; Eliminating the differential signal transmission paths that do not meet a predetermined rule from the first differential signal transmission path set to obtain a second differential signal transmission path set; the predetermined rule being that the types and quantities of resistor and capacitor components on the differential signal transmission paths corresponding to the two pins in a pair of differential pair pins are completely consistent in order; Based on a predetermined differential network naming specification, it is examined whether the differential network naming of the differential signal transmission paths of the two pins constituting a pair of differential pair pins in the second differential signal transmission path set meets predetermined requirements.

2. The automatic review method for the correctness of the differential network of the circuit schematic diagram according to claim 1 is characterized in that: The target EDIF200 format circuit schematic file is parsed, and the attribute information of the chip devices obtained by the parsing is stored in the chip device information matrix Part_U, and the attribute information of the non-chip devices obtained by the parsing is stored in the non-chip device information matrix Part_other; wherein the chip device information matrix Part_U and the non-chip device information matrix Part_other have the same column index, specifically including: Traversing the project matrix structure of the target EDIF200 format circuit schematic file layer by layer, and identifying the version declaration segment, design hierarchy segment, and library definition segment in the header of the file; Recursively parse the hierarchical data blocks formed by bracket syntax in the file based on a predefined keyword processing priority order, wherein the connection topology relationship between network nodes is synchronously recorded when extracting electrical network information; During the component instantiation processing stage, the device bit number identifier is matched by regular expression, and the chip device classification containing the U character prefix is stored in the chip device information matrix Part_U, and the device classification containing the character prefix of the non-chip device is stored in the non-chip device information matrix Part_other.

3. The automatic review method for the correctness of the differential network of the circuit schematic diagram according to claim 1 is characterized in that: The column indexes of the chip device information matrix Part_U and the non-chip device information matrix Part_other include, in sequence, the bit number, pin number, pin name, pin type, the network to which the pin is connected, the pin starting point coordinates, the pin ending point coordinates and the total number of pins.

4. The method for automatically checking the correctness of the differential network of a circuit schematic diagram according to claim 1, characterized in that: The preset differential pair pin screening condition set is: (1) The two pins that constitute a differential pair of pins are adjacent pins on the same chip; (2) Both pins in a differential pair are passive pins; (3) The pin names of the two pins that form a differential pair of pins have the same character length; (4) The pin names of the two pins that form a differential pair of pins are identical except for a single character, and the identical and different characters are in the same position in the pin names; (5) The different characters in the names of the two pins constituting a differential pair of pins are selected from one of the three combinations of [+, -], [N, P], and [n, p]; The process of storing the attribute information of all the screened differential pair pins in the differential pair pin information matrix Dif_pin in order specifically includes: Performing a nested loop traversal on the chip device information matrix Part_U, wherein an outer loop in the nested loop scans the pin data in the chip device information matrix Part_U row by row, and an inner loop in the nested loop performs pairing analysis on the pin data of the current row with the pin data of each row after the current row according to the preset differential pair pin screening condition set, and writes the complete attribute information of the two pins in a pair of successfully paired differential pair pins into two consecutive rows in the differential pair pin information matrix Dif_pin in the traversal order, thereby forming a paired storage structure; The above operation is executed in a loop until all the data in the chip device information matrix Part_U is traversed, and until the pin attribute information of all differential pair pins in the chip device information matrix Part_U is filled into the differential pair pin information matrix Dif_pin.

5. The method for automatically checking the correctness of the differential network of a circuit schematic diagram according to claim 1, characterized in that: The step of obtaining, based on the differential pair pin information matrix Dif_pin and the non-chip device information matrix Part_other, a first differential signal transmission path set including differential signal transmission paths of all pins in the differential pair pin information matrix Dif_pin specifically includes: The pin information of the two pins belonging to the same pair of differential pins in the differential pair pin information matrix Dif_pin is split into the first differential pin matrix Dif_pin1 and the second differential pin matrix Dif_pin2 in sequence; based on the non-chip device information matrix Part_other, the first differential pin matrix Dif_pin1 and the second differential pin matrix Dif_pin2, a first differential signal transmission path set of the differential signal transmission paths of all pins in the differential pair pin information matrix Dif_pin is obtained.

6. The method for automatically checking the correctness of the differential network of a circuit schematic diagram according to claim 5, characterized in that: The step of obtaining a first differential signal transmission path set of differential signal transmission paths of all pins in the differential pair pin information matrix Dif_pin based on the non-chip device information matrix Part_other, the first differential pin matrix Dif_pin1, and the second differential pin matrix Dif_pin2 specifically includes: S1. Obtaining the differential signal transmission paths corresponding to a pair of differential pair pins located at the starting position in the differential pair pin information matrix Dif_pin, specifically comprising: S11, starting from a first initial differential pin in the first differential pin matrix Dif_pin1 and a second initial differential pin in the second differential pin matrix Dif_pin2, respectively, initiating a recursive traversal operation, wherein the first initial differential pin and the second initial differential pin belong to a pair of differential pair pins located at a starting position in the differential pair pin information matrix Dif_pin; S12. In the recursive process, according to the non-chip device information matrix Part_other, the resistor and capacitor devices that are directly electrically connected to the current traversal node are searched level by level, and the following two recursive paths are generated: The first recursive path: starting from the initial node of the first differential pin matrix Dif_pin1, and extending along the connection relationship between the resistor and capacitor components; The second recursive path: starting from the initial node of the second differential pin matrix Dif_pin2, and extending along the connection relationship between the resistor and capacitor components; S13. Stop the recursion when any of the following termination conditions is met: (1) There is no associated resistor / capacitor device at the end of the current path; (2) The first recursive path and the second recursive path intersect at the same resistor-capacitor device node; S14. Encode each node in the first recursive path according to a coding format of "device bit number_pin number_net name" to obtain a first differential signal transmission path of the first initial differential pin; and encode each node in the second recursive path according to a coding format of "device bit number_pin number_net name" to obtain a second differential signal transmission path of the second initial differential pin. The first differential signal transmission path is stored in a first differential path matrix DiffNet1, and the second differential signal transmission path is stored in a second differential path matrix DiffNet2, and the network name at the end of the path is bound to the differential network identifier of the corresponding differential pin; S2. Obtain the differential signal transmission paths corresponding to the pair of differential pair pins located at the starting position in the differential pair pin information matrix Dif_pin in the same manner as that of the differential signal transmission paths corresponding to the pair of differential pair pins located at the starting position in the differential pair pin information matrix Dif_pin, and store them in the first differential path matrix DiffNet1 and the second differential path matrix DiffNet2 in sequence.

7. The method for automatically checking the correctness of the differential network of a circuit schematic diagram according to claim 6, characterized in that: The step of removing the differential signal transmission paths that do not meet a predetermined rule from the first differential signal transmission path set specifically includes: Simultaneously traversing the first differential path matrix DiffNet1 and the second differential path matrix DiffNet2, screening out all differential signal transmission paths belonging to the same pair of differential pins that do not satisfy the predetermined rule, and then removing the screened differential signal transmission paths that do not satisfy the predetermined rule from the corresponding first differential path matrix DiffNet1 or second differential path matrix DiffNet2, to obtain an updated first differential path matrix DiffNet1 and an updated second differential path matrix DiffNet2; The step of removing the screened differential signal transmission paths that do not meet the symmetry condition from the corresponding first differential path matrix DiffNet1 or the second differential path matrix DiffNet2 includes: The filtered differential signal transmission paths that do not meet the predetermined rule are stored in the Diff_no_cor matrix in order.

8. The method for automatically checking the correctness of the differential network of a circuit schematic diagram according to claim 7, characterized in that: The reviewing, based on a predetermined differential network naming specification, whether the differential network naming of the differential signal transmission paths of the two pins constituting a pair of differential pair pins in the second differential signal transmission path set meets predetermined requirements includes: Reviewing the naming standardization of the differential networks in the updated first differential path matrix DiffNet1 and the updated second differential path matrix DiffNet2, specifically including: According to the differential network naming specification, after filtering out incorrect differential paths, the first differential path matrix DiffNet1 and the second differential path matrix DiffNet2 are obtained, and the differential pins are obtained from the beginning of the differential path and the differential network name is obtained from the end. The differential network naming specification is reviewed. If it does not meet the specification, the differential path corresponding to the differential pair is stored in the Diff_name_no_cor matrix. The differential network naming specification is as follows: (1) The differential network name should be consistent with the current differential pin. (1) The pins of the two differential pairs correspond to each other, that is, in the combination of [+, -], [N, P], [n, p], "-", "N", and "n" correspond to each other, and "+", "P", and "p" correspond to each other; (2) The character length of the differential network name in the same differential pair is the same; (3) Except for a single character, the other characters in the names of the two differential networks in the differential pair should be the same, and the different single characters should be one of the combinations of [+, -], [N, P], and [n, p]; (4) The positions of the same characters and different characters in the differential network names are consistent.

9. The method for automatically checking the correctness of the differential network of a circuit schematic diagram according to claim 8, characterized in that: The method further comprises: The incorrect differential pairs, differential paths, and differential paths with irregular naming in the Diff_no_cor matrix and the Diff_name_no_cor matrix are converted into character strings row by row, and output as inspection results after adding relevant text descriptions. The inspection results include the following: (1) incorrect differential paths and their asymmetry reasons; (2) irregularly named differential networks and the specific rules they violate.

10. An automatic review device for the correctness of a schematic diagram differential network, characterized in that: The device includes various functional modules in the script program, including: A circuit schematic parsing module, configured to parse a target EDIF200 format circuit schematic file, store the parsed attribute information of chip components in a chip component information matrix Part_U, and store the parsed attribute information of non-chip components in a non-chip component information matrix Part_other; wherein the chip component information matrix Part_U and the non-chip component information matrix Part_other have the same column index; A differential pair pin screening module is configured to obtain differential pair pins that meet a preset differential pair pin screening condition set in the chip device information matrix Part_U, and sequentially store attribute information of all screened differential pair pins into the differential pair pin information matrix Dif_pin; wherein the differential pair pin screening condition set is used to screen pins belonging to the same pair of differential pins; a differential signal transmission path set acquisition module, configured to obtain, based on the differential pair pin information matrix Dif_pin and the non-chip device information matrix Part_other, a first differential signal transmission path set including differential signal transmission paths for all pins in the differential pair pin information matrix Dif_pin; wherein any differential signal transmission path in the first differential signal transmission path set is sequentially composed of a plurality of path nodes, wherein the first path node of the plurality of path nodes represents the pin of a source device that generates a corresponding differential signal, and the last path node represents the pin of a destination device that generates and processes the corresponding differential signal; a differential path screening module, configured to remove differential signal transmission paths from the first differential signal transmission path set that do not meet a predetermined rule, thereby obtaining a second differential signal transmission path set; the predetermined rule being that the types and quantities of resistor and capacitor components on the differential signal transmission paths corresponding to the two pins of a differential pair of pins are completely consistent in order; The differential network naming review module is used to review whether the differential network naming of the differential signal transmission paths of the two pins constituting a pair of differential pair pins in the second differential signal transmission path set meets the predetermined requirements based on the predetermined differential network naming specification.

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