CPU-FPGA (Central Processing Unit-Field Programmable Gate Array) heterogeneous acceleration method and device for monitoring short-circuit current fault of power distribution network

Abstract

The invention discloses a CPU-FPGA heterogeneous acceleration method, device and equipment for monitoring a short-circuit current fault of a power distribution network and a storage medium, relates to the technical field of relay protection of the power distribution network, and solves the problem of how to accelerate a neural network algorithm to accurately monitor the short-circuit current fault of the power distribution network in real time. Three-phase fault current and voltage time domain signals of a power system are collected through a sensor, fault features are extracted on a CPU through fast Fourier transform, and then a fault feature matrix is constructed; building a neural network model comprising a convolution layer, a pooling layer, a full connection layer and an SVM classification layer, inputting the fault feature matrix into the neural network model, obtaining a discrimination result through forward propagation calculation, and triggering a circuit breaker tripping instruction if the output label is in a fault state. According to the method, the calculation speed of the neural network algorithm for monitoring the short-circuit current fault of the power distribution network can be remarkably improved, so that the real-time performance and accuracy of fault monitoring are improved.

Description

Technical Field

[0001] The present invention relates to the technical field of distribution network relay protection, and in particular to a CPU-FPGA heterogeneous acceleration method, device, equipment and storage medium for short-circuit current fault monitoring in a distribution network. Background Art

[0002] As a crucial component of the power supply system, the stability and reliability of the distribution network directly impact the quality of electricity users receive. Short-circuit faults in distribution networks are a common problem in power systems. Rapidly and accurately identifying and locating faults is crucial for ensuring power supply stability and minimizing economic losses. With the development of smart grid technology, fault monitoring methods based on convolutional neural networks have attracted widespread attention due to their efficiency and accuracy. For example, Chinese patent application publication number CN119199405A describes a distribution network fault location method and device based on a graph convolutional neural network. The method preprocesses a collected dataset to obtain a target dataset; constructs an optimization matrix based on the target dataset and a topological diagram of the distribution network to be measured; extracts node features from the topological diagram to obtain node feature vectors; trains a graph convolutional neural network using the optimized matrix and node feature vectors, and performs sample balancing to obtain a distribution network fault location model. The measured data is then input into the distribution network fault location model for identification, obtaining the state parameters of each node. Based on these node state parameters, the faulty node is located. However, neural network algorithms are computationally complex and require significant computing power. Therefore, studying a calculation method that can accelerate the neural network algorithm is of great significance to improving the real-time performance and accuracy of distribution network short-circuit current fault monitoring. Summary of the Invention

[0003] The technical problem to be solved by the present invention is how to accelerate the neural network algorithm to realize real-time and accurate monitoring of short-circuit current faults in the distribution network.

[0004] The present invention solves the above technical problems by the following technical means: a CPU-FPGA heterogeneous acceleration method for short-circuit current fault monitoring in a distribution network, the method comprising the following steps:

[0005] Step S1: Fault feature extraction: The time domain signals of the three-phase fault current and voltage of the power system are collected by sensors, and a fast Fourier transform (FFT) is executed on the CPU to extract fault features from the time domain signals. The fault features are arranged in rows to construct a two-dimensional fault feature matrix, which is then transmitted to the field programmable gate array (FPGA). Each row corresponds to a feature type, and each column corresponds to a phase of the power system or a fault time window.

[0006] Step S2: Building a neural network model, including convolutional layers, pooling layers, fully connected layers, and SVM layers;

[0007] Step S3: short circuit fault discrimination, inputting the two-dimensional fault feature matrix into the neural network model, obtaining the discrimination result through forward propagation calculation, and triggering the circuit breaker tripping instruction if the output label is a fault state.

[0008] This method uses Fast Fourier Transform (FFT) to extract the fundamental wave, harmonic amplitude, and phase difference from time-domain signals, accurately capturing short-circuit fault characteristics and constructing a structured matrix. This improves feature characterization capabilities and adapts to hardware computation. The neural network model utilizes FPGA parallel acceleration to achieve high-precision, low-latency fault feature mapping and classification. If the output label indicates a fault state, a circuit breaker trip command is triggered, meeting the need for rapid fault removal in the distribution network. The CPU handles flexible preprocessing, while the FPGA focuses on real-time computation. High-speed PCIE interaction significantly improves the algorithm's computational speed.

[0009] Furthermore, the fault characteristics include: three-phase current fundamental amplitude, three-phase voltage fundamental amplitude; three-phase current odd harmonic amplitude, three-phase current even harmonic amplitude; three-phase voltage odd harmonic amplitude, three-phase voltage even harmonic amplitude; three-phase voltage phase difference between current and voltage.

[0010] Furthermore, the neural network model utilizes the multi-core parallel computing capability of FPGA to perform calculations on the convolution layer, pooling layer, fully connected layer, and SVM layer.

[0011] Furthermore, the FPGA exchanges data with the CPU via a PCIE interface, and the CPU is responsible for preprocessing the feature matrix and outputting the results.

[0012] The present invention also provides a CPU-FPGA heterogeneous acceleration device for a neural network algorithm for monitoring short-circuit current faults in a distribution network, the device comprising the following modules:

[0013] The fault feature extraction module collects the three-phase current and voltage time domain signals of the power system, processes them through fast Fourier transform (FFT), and extracts fault features.

[0014] a fault feature matrix construction module, which arranges the fault features in rows to construct a 7×8 two-dimensional fault feature matrix, where each row corresponds to a feature type and each column corresponds to a phase of the power system or a fault time window;

[0015] Build a neural network model, including convolutional layers, pooling layers, fully connected layers, and SVM layers;

[0016] The short-circuit fault discrimination module inputs the two-dimensional fault feature matrix into the neural network model, obtains a discrimination result through forward propagation calculation, and triggers a circuit breaker tripping instruction if the output label is a fault state.

[0017] Furthermore, the fault characteristics include: three-phase current fundamental amplitude, three-phase voltage fundamental amplitude; three-phase current odd harmonic amplitude, three-phase current even harmonic amplitude; three-phase voltage odd harmonic amplitude, three-phase voltage even harmonic amplitude; three-phase voltage phase difference between current and voltage.

[0018] Furthermore, the neural network model utilizes the multi-core parallel computing capability of FPGA to perform calculations on the convolution layer, pooling layer, fully connected layer, and SVM layer.

[0019] Furthermore, the FPGA exchanges data with the CPU via a PCIE interface, and the CPU is responsible for preprocessing the feature matrix and outputting the results.

[0020] The present invention also provides a processing device, comprising at least one processor and at least one memory communicatively connected to the processor, wherein: the memory stores program instructions that can be executed by the processor, and the processor can execute the above method steps by calling the program instructions.

[0021] The present invention also provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer instructions, and the computer instructions enable the computer to execute the above method steps.

[0022] The advantages of the present invention are: designing a neural network structure suitable for implementation on FPGA, and making full use of the multi-core parallel computing capability of FPGA to significantly improve the calculation speed of the distribution network short-circuit current fault monitoring neural network algorithm, thereby improving the real-time and accuracy of fault monitoring. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 This is a flow chart of short-circuit current fault monitoring in a distribution network according to embodiment 1 of the present invention;

[0024] Figure 2 This is a CPU-FPGA heterogeneous block diagram of Example 1 of the present invention. DETAILED DESCRIPTION

[0025] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0026] Example 1

[0027] like Figure 1The figure shows a flow chart of the CPU-FPGA heterogeneous acceleration method for short-circuit current fault monitoring in distribution networks, specifically:

[0028] CPU part: Responsible for collecting the time domain signals of the three-phase fault current and voltage of the power system through sensors, performing fast Fourier transform (FFT) to extract fault features from the time domain signals, arranging the fault features in rows, constructing a 7×8 fault feature matrix, and transmitting it to the field programmable gate array (FPGA), where each row corresponds to a feature type and each column corresponds to a phase of the power system or a fault time window; the fault features include: three-phase current fundamental amplitude, three-phase voltage fundamental amplitude; three-phase current odd harmonic amplitude, three-phase current even harmonic amplitude; three-phase voltage odd harmonic amplitude, three-phase voltage even harmonic amplitude; and the phase difference between current and voltage.

[0029] FPGA part: Neural network model construction, build a neural network model with the following layers: Convolution layer: 32 3×3 convolution kernels, convolution operation on the 7×8 feature matrix, output 32×7×8 convolution matrix; Pooling layer: Maximum pooling operation, reduce the 32×7×8 convolution matrix to a 32×1×2 pooling matrix; Fully connected layer: Map the 32×1×2 pooling matrix to a 64-dimensional feature space; SVM classification layer: Perform binary classification on the 64-dimensional features and output the short-circuit fault status label; Synchronize the SVM fault classification layer back to the CPU.

[0030] The convolutional layer convolves the input 7×8 fault feature matrix with 32 3×3 convolution kernels to extract local features. Each convolution kernel slides over the input matrix and calculates the dot product between the kernel and a local region of the input matrix to generate a new feature map. Multiple convolution kernels can extract local features of varying orientations and shapes. The convolution kernel computation is distributed across multiple FPGA cores, with each core performing a portion of the convolution calculation, enabling parallel processing. By optimizing data flow and memory access, inter-core communication overhead is reduced. This allows for efficient extraction of local information about fault features, providing rich feature representations for subsequent pooling and fully connected layers.

[0031] The pooling layer uses max pooling to downsample the feature maps output by the convolutional layer. Max pooling selects the maximum value within each local region as a representative, thereby reducing the size of the feature map while retaining important feature information. For example, for each of the 32 feature maps, the pooling layer downsamples the 7×8 feature map to a 1×2 feature map. The computational tasks of the pooling layer are also distributed to multiple cores of the FPGA, with each core responsible for a portion of the pooling operation, enabling parallel processing. Efficient data scheduling and core collaboration improve the computational speed of the pooling layer. Reducing the size of the feature map reduces computational complexity while retaining key features, providing a more compact feature representation for the fully connected layer.

[0032] The fully connected layer flattens the feature map output by the pooling layer into a one-dimensional vector. This is then processed through neurons using a weighted summation and a nonlinear activation function (such as ReLU). The output of each neuron is a weighted sum of the input features. The introduction of nonlinearity through the activation function enables the neural network to learn complex feature maps. When implementing the fully connected layer on an FPGA, fixed-point arithmetic is used to improve computational efficiency. Furthermore, by optimizing weight storage and data transmission, memory access latency is reduced. Local features are integrated into global features, providing a more comprehensive feature representation for final fault classification.

[0033] The SVM layer uses the support vector machine (SVM) algorithm for fault classification. SVM is a supervised learning algorithm that separates data of different categories by finding the optimal segmentation hyperplane in the feature space. In the present invention, the SVM layer uses the 64 neurons output by the fully connected layer as input features and outputs the fault category (such as short circuit fault or normal state). When the computing task of the SVM layer is implemented on the FPGA, an efficient algorithm implementation and hardware resource optimization are adopted. By optimizing the kernel function calculation and classification decision process of the SVM, the classification efficiency is improved. Accurately classify the short-circuit current faults in the distribution network and provide reliable fault monitoring results.

[0034] For short-circuit fault discrimination, the 7×8 fault feature matrix is input into the neural network model, and a discrimination result is obtained through forward propagation calculation. If the output label is a fault state, a circuit breaker tripping instruction is triggered.

[0035] Data synchronization:

[0036] Data synchronization is performed between the CPU and FPGA via PCIE to ensure the continuity and accuracy of calculations.

[0037] Example 2

[0038] The present invention also provides a CPU-FPGA heterogeneous acceleration device for monitoring short-circuit current faults in a distribution network, the device comprising the following modules:

[0039] Step S1: A fault feature extraction module collects the three-phase current and voltage time domain signals of the power system, processes the three-phase current and voltage time domain signals through fast Fourier transform (FFT), and extracts fault features; the fault features include: three-phase current fundamental amplitude, three-phase voltage fundamental amplitude; three-phase current odd harmonic amplitude, three-phase current even harmonic amplitude; three-phase voltage odd harmonic amplitude, three-phase voltage even harmonic amplitude; and phase difference between current and voltage.

[0040] Step S2: a fault feature matrix construction module arranges the fault features in rows to construct a 7×8 two-dimensional fault feature matrix, where each row corresponds to a feature type and each column corresponds to a phase of the power system or a fault time window;

[0041] Step S3: A neural network model building module is constructed, which includes the following layers: Convolutional layer: 32 3×3 convolution kernels perform convolution operations on the 7×8 feature matrix, outputting a 32×7×8 convolution matrix; Pooling layer: Maximum pooling operation, reducing the 32×7×8 convolution matrix to a 32×1×2 pooling matrix; Fully connected layer: Mapping the 32×1×2 pooling matrix to a 64-dimensional feature space; SVM classification layer: Performing binary classification on the 64-dimensional features and outputting a short-circuit fault status label. The neural network model utilizes the multi-core parallel computing power of the FPGA to perform calculations on the convolutional layer, pooling layer, fully connected layer, and SVM layer. The FPGA exchanges data with the CPU via the PCIE interface, and the CPU is responsible for preprocessing the feature matrix and outputting the results.

[0042] Step S4: The short-circuit fault discrimination module inputs the 7×8 fault feature matrix into the neural network model, obtains the discrimination result through forward propagation calculation, and triggers the circuit breaker tripping instruction if the output label is a fault state.

[0043] Example 3

[0044] Based on Example 1, Example 3 of the present invention also provides a processing device, including at least one processor and at least one memory communicatively connected to the processor, wherein: the memory stores program instructions that can be executed by the processor, and when the processor calls the program instructions, the method steps described in Example 1 are implemented.

[0045] Example 4

[0046] Based on Example 1, Example 4 of the present invention further provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer instructions, and the computer instructions enable the computer to implement the method steps described in Example 1 when executed.

[0047] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A CPU-FPGA heterogeneous acceleration method for short-circuit current fault monitoring in distribution networks, characterized in that: The following steps are involved: Step S1: Fault feature extraction: sensors are used to collect time domain signals of the three-phase fault current and voltage of the power system. Fast Fourier transform (FFT) is performed on the CPU to extract fault features from the time domain signals. The fault features are arranged in rows to construct a two-dimensional fault feature matrix, which is then transmitted to the field programmable gate array (FPGA). Each row corresponds to a feature type, and each column corresponds to a phase of the power system or a fault time window. Step S2: Building a neural network model, including convolutional layers, pooling layers, fully connected layers, and SVM layers; Step S3: short circuit fault discrimination, inputting the two-dimensional fault feature matrix into the neural network model, obtaining the discrimination result through forward propagation calculation, and triggering the circuit breaker tripping instruction if the output label is a fault state.

2. The CPU-FPGA heterogeneous acceleration method for short-circuit current fault monitoring in distribution network according to claim 1, characterized in that: The fault characteristics include: three-phase current fundamental amplitude, three-phase voltage fundamental amplitude; three-phase current odd harmonic amplitude, three-phase current even harmonic amplitude; three-phase voltage odd harmonic amplitude, three-phase voltage even harmonic amplitude; three-phase voltage phase difference between current and voltage.

3. The CPU-FPGA heterogeneous acceleration method for short-circuit current fault monitoring in distribution network according to claim 1, characterized in that: The neural network model uses the multi-core parallel computing capability of FPGA to perform calculations on the convolution layer, pooling layer, fully connected layer, and SVM layer.

4. The CPU-FPGA heterogeneous acceleration method for short-circuit current fault monitoring in distribution network according to claim 3, characterized in that: The FPGA exchanges data with the CPU via the PCIE interface, and the CPU is responsible for preprocessing the feature matrix and outputting the results.

5. A CPU-FPGA heterogeneous acceleration device for short-circuit current fault monitoring in distribution networks, characterized in that: The device comprises the following modules: The fault feature extraction module collects the time domain signals of the three-phase fault current and voltage of the power system through sensors, executes Fast Fourier Transform (FFT) on the CPU to extract fault features from the time domain signals, arranges the fault features in rows, constructs a two-dimensional fault feature matrix, and transmits it to the FPGA, where each row corresponds to a feature type and each column corresponds to a phase of the power system or a fault time window; Neural network model building module, neural network model building, building a neural network model including convolution layer, pooling layer, fully connected layer and SVM layer; The short-circuit fault discrimination module inputs the two-dimensional fault feature matrix into the neural network model, obtains a discrimination result through forward propagation calculation, and triggers a circuit breaker tripping instruction if the output label is a fault state.

6. The CPU-FPGA heterogeneous acceleration device for short-circuit current fault monitoring in a distribution network according to claim 5, characterized in that: The fault characteristics include: three-phase current fundamental amplitude, three-phase voltage fundamental amplitude; three-phase current odd harmonic amplitude, three-phase current even harmonic amplitude; three-phase voltage odd harmonic amplitude, three-phase voltage even harmonic amplitude; three-phase voltage phase difference between current and voltage.

7. The CPU-FPGA heterogeneous acceleration device for short-circuit current fault monitoring in a distribution network according to claim 5, characterized in that: The neural network model uses the multi-core parallel computing capability of FPGA to perform calculations on the convolution layer, pooling layer, fully connected layer, and SVM layer.

8. The CPU-FPGA heterogeneous acceleration device for short-circuit current fault monitoring in a distribution network according to claim 7, characterized in that: The FPGA exchanges data with the CPU via the PCIE interface, and the CPU is responsible for preprocessing the feature matrix and outputting the results.

9. A processing device, characterized in that: The method comprises at least one processor and at least one memory in communication with the processor, wherein the memory stores program instructions executable by the processor, and the processor calls the program instructions to execute the method according to any one of claims 1 to 4.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer instructions, and the computer instructions enable the computer to execute the method according to any one of claims 1 to 4.

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