Pixel circuit
By combining pulse amplitude and pulse width modulation transistors and driving circuits, sharing the data voltage modulation current intensity and time, the problems of inaccurate brightness regulation and complex layout in existing pixel circuits are solved, and accurate current control and simplified circuit design are achieved.
Patent Information
- Application Number
- CN202510775466.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2025-03-05
- Filing Date
- 2025-06-11
- Publication Date
- 2025-08-08
AI Technical Summary
In the existing pixel circuits, when only the pulse amplitude modulation circuit is used to modulate the driving current intensity, the brightness regulation is inaccurate, and when the pulse amplitude and pulse width modulation circuit are used at the same time, the circuit layout area and signal supply complexity need to be increased.
The pulse amplitude modulation transistor and the pulse width modulation transistor are combined with the first and second driving circuits to modulate the current intensity and time by sharing the data voltage, and the control transistor switches the state of the pulse width modulation transistor in response to the time-varying voltage to achieve accurate control of the current.
Accurate control of the current of the light emitting element is achieved, and the problem of uneven brightness in the medium and low gray scale is improved, while avoiding the increase in circuit area and signal supply complexity.
Smart Images
Figure CN120452377A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to a pixel circuit. Background Art
[0002] In existing pixel circuits, using only pulse amplitude modulation (PAM) to modulate the driving current flowing through light-emitting elements results in an inability to precisely control the brightness of the light-emitting elements. This is especially true when the pixel circuits are displaying medium or low grayscales, as even slight current variations can cause brightness differences between pixels, adversely affecting the user's visual experience.
[0003] Furthermore, if both a pulse amplitude modulation circuit and a pulse width modulation circuit are used to simultaneously adjust the intensity and flow duration of the driving current, at least two data voltage lines are required to supply respective data voltages to the pulse amplitude modulation circuit and the pulse width modulation circuit, respectively. This not only increases the circuit layout area but also increases the complexity of the signal supply. Summary of the Invention
[0004] Therefore, embodiments of the present disclosure provide a pixel circuit comprising a pulse amplitude modulation transistor, a pulse width modulation transistor, a light-emitting element, a first driver circuit, and a second driver circuit. A first terminal of the pulse amplitude modulation transistor is coupled to a system high voltage. A first terminal of the pulse width modulation transistor is coupled to a second terminal of the pulse amplitude modulation transistor. The light-emitting element is coupled between the second terminal of the pulse width modulation transistor and a system low voltage. The first driver circuit is coupled to a control terminal of the pulse amplitude modulation transistor and the second terminal of the pulse amplitude modulation transistor and is configured to modulate the intensity of a current flowing through the light-emitting element based on a data voltage. The second driver circuit is coupled to the first driver circuit and the control terminal of the pulse width modulation transistor and is configured to modulate the duration of the current flowing through the light-emitting element based on the data voltage and a time-varying voltage. The second driver circuit comprises a control transistor. A first terminal of the control transistor is coupled to the control terminal of the pulse width modulation transistor, and a second terminal thereof receives a first reference voltage. The control transistor is turned on in response to a change in the time-varying voltage, causing the control terminal of the pulse width modulation transistor to receive the first reference voltage via the control transistor, thereby turning off the pulse width modulation transistor.
[0005] According to an embodiment of the present disclosure, the first driving circuit includes a first transistor, a second transistor, a first capacitor, a third transistor, a fourth transistor, and a fifth transistor. The first end of the first transistor is coupled to the second end of the pulse amplitude modulation transistor, and the control end thereof receives the second scan signal. The first end of the second transistor is coupled to the second end of the first transistor, the second end of the second transistor is coupled to the control end of the pulse amplitude modulation transistor, and the control end thereof receives the second scan signal. The first end of the first capacitor is coupled to the second end of the second transistor. The first end of the third transistor receives a system high voltage, the second end of the third transistor is coupled to the second end of the first capacitor, and the control end thereof receives the third scan signal. The first end of the fourth transistor receives a data voltage, the second end of the fourth transistor is coupled to the second end of the third transistor, and the control end thereof receives the second scan signal. The first end of the fifth transistor is coupled to the second end of the first transistor, the second end of the fifth transistor receives a second reference voltage, and the control end thereof receives the first scan signal.
[0006] According to an embodiment of the present disclosure, the second driving circuit includes a sixth transistor, a second capacitor, a seventh transistor, and a third capacitor. A first terminal of the sixth transistor receives a data voltage, a second terminal of the sixth transistor is coupled to the control terminal of the control transistor, and the control terminal thereof receives a second scan signal. A first terminal of the second capacitor receives a time-varying voltage, and a second terminal of the second capacitor is coupled to the second terminal of the sixth transistor. A first terminal of the seventh transistor is coupled to the first terminal of the control transistor, a second terminal of the seventh transistor receives a third reference voltage, and the control terminal thereof receives a light-emitting control signal. A first terminal of the third capacitor is coupled to the first terminal of the seventh transistor, and a second terminal of the third capacitor is coupled to the second terminal of the seventh transistor.
[0007] According to an embodiment of the present disclosure, in a first operating range, the first transistor, the second transistor, and the fifth transistor are turned on to reset the first end of the first capacitor and the second end of the pulse amplitude modulation transistor to a second reference voltage, and the fourth transistor and the sixth transistor are turned on to write the data voltage to the second end of the first capacitor and the second end of the second capacitor.
[0008] According to an embodiment of the present disclosure, in the second operating range, the first transistor, the second transistor, the fourth transistor, and the sixth transistor remain turned on, and the fifth transistor is turned off. The potential of the control terminal of the PWM transistor is compensated to the system high voltage minus the threshold voltage of the PWM transistor.
[0009] According to an embodiment of the present disclosure, during a third operating interval, the third and seventh transistors are turned on, and the first, second, fourth, fifth, and sixth transistors are turned off. A system high voltage is written to the second terminal of the first capacitor. The voltage difference between the data voltage and the system high voltage is coupled to the control terminal of the pulse amplitude modulation transistor via the first capacitor. The control terminal of the pulse width modulation transistor receives a third reference voltage and is turned on, allowing current to flow through the light-emitting element.
[0010] According to an embodiment of the present disclosure, in a fourth operating interval, the third transistor is turned on and the first, second, fourth, fifth, sixth, and seventh transistors are turned off. Furthermore, the control terminal of the pulse width modulation transistor is maintained at a third reference voltage via a third capacitor, turning on the pulse width modulation transistor to maintain current flowing through the light-emitting element.
[0011] According to an embodiment of the present disclosure, in the fifth operating interval, the voltage of the time-varying voltage coupled to the control terminal of the control transistor via the second capacitor is sufficient to turn on the control transistor, causing the control terminal of the pulse width modulation transistor to change from the third reference voltage to the first reference voltage, thereby turning off the pulse width modulation transistor.
[0012] According to an embodiment of the present disclosure, the time-varying voltage is a ramp signal, so that the second driving circuit modulates the time of the current flowing through the light-emitting element according to the speed at which the data voltage and the ramp signal linearly change.
[0013] According to an embodiment of the present disclosure, the time-varying voltage is a step wave signal, so that the second driving circuit modulates the time of the current flowing through the light-emitting element according to the data voltage and the voltage level variation of the step wave signal. BRIEF DESCRIPTION OF THE DRAWINGS
[0014] To make the above and other features, advantages and embodiments of the present invention more easily understood, the accompanying drawings are described as follows:
[0015] Figure 1 is a schematic diagram of a pixel circuit according to an embodiment of the present invention;
[0016] Figure 2 is a schematic diagram of the internal structure of a pixel circuit according to an embodiment of the present invention;
[0017] Figure 3 is a timing diagram of driving signals of a pixel circuit according to an embodiment of the present invention;
[0018] Figure 4 is a schematic diagram illustrating the operation of a pixel circuit in a first operation interval according to an embodiment of the present invention;
[0019] Figure 5 is a schematic diagram of the operation of the pixel circuit in the second operation range according to an embodiment of the present invention;
[0020] Figure 6 is a schematic diagram illustrating the operation of the pixel circuit in the third operation range according to an embodiment of the present invention;
[0021] Figure 7is a schematic diagram of the operation of the pixel circuit in the fourth operation range according to an embodiment of the present invention; and
[0022] Figure 8 FIG. 1 is a schematic diagram illustrating the operation of a pixel circuit in a fifth operation interval according to an embodiment of the present invention.
[0023] Description of reference numerals:
[0024] 100: Pixel circuit
[0025] 110: First drive circuit
[0026] 120: Second drive circuit
[0027] C1: First capacitor
[0028] C2: Second capacitor
[0029] C3: The third capacitor
[0030] Data: data voltage
[0031] EMS: Lighting control signal
[0032] LED: Light Emitting Device
[0033] PH: First reference voltage
[0034] PL: Third reference voltage
[0035] Sweep: Time-varying voltage
[0036] S1: First scanning signal
[0037] S2: Second scanning signal
[0038] S3: The third scanning signal
[0039] TA: Pulse Amplitude Modulation Transistor
[0040] TC: Control transistor
[0041] TP: Pulse Width Modulation Transistor
[0042] T1: first transistor
[0043] T2: Second transistor
[0044] T3: The third transistor
[0045] T4: fourth transistor
[0046] T5: Fifth transistor
[0047] T6: Sixth transistor
[0048] T7: Seventh transistor
[0049] t1: first operating interval
[0050] t2: Second operating interval
[0051] t3: The third operating interval
[0052] t4: fourth operating interval
[0053] t5: fifth operating interval
[0054] VDD: system high voltage
[0055] VSS: system low voltage
[0056] Vn: Second reference voltage DETAILED DESCRIPTION
[0057] The following disclosure provides many different embodiments or examples for implementing different features of the provided inventions. The embodiments of components and configurations described below are provided as examples only and are not intended to be limiting. In addition, for the purposes of simplicity and clarity, the disclosure repeats reference symbols and / or numbers throughout the examples, which in themselves do not limit the relationship between the various embodiments and / or components discussed.
[0058] Please refer to Figure 1 , Figure 1 FIG. 1 is a schematic diagram of a pixel circuit 100 according to an embodiment of the present invention. The pixel circuit 100 includes a pulse amplitude modulation transistor TA, a pulse width modulation transistor TP, a light emitting element LED, a first driving circuit 110 and a second driving circuit 120 .
[0059] The first driver circuit 110 is coupled to the control terminal and the second terminal of the pulse amplitude modulation transistor TA and is configured to receive the data voltage Data. The second driver circuit 120 is coupled to the first driver circuit 110 and the control terminal of the pulse width modulation transistor TP and is configured to receive the data voltage Data, a time-varying voltage Sweep, and a first reference voltage PH. In an embodiment of the present invention, the first driver circuit 110 is a pulse amplitude modulation circuit and is configured to modulate the intensity of the current flowing through the light-emitting element LED according to the data voltage Data, while the second driver circuit 120 is a pulse width modulation circuit and is configured to modulate the duration of the current flowing through the light-emitting element LED according to the data voltage Data, the first reference voltage PH, and the time-varying voltage Sweep.
[0060] It's worth noting that the first driver circuit 110 and the second driver circuit 120 share the same data voltage Data, thereby simultaneously modulating the current intensity (e.g., the height of the current signal) and the duration (e.g., the width of the current signal) flowing through the light-emitting element LED. This not only improves the uneven pixel brightness caused by current variations in low and medium grayscale applications, but also avoids increasing the circuit layout area and signal supply complexity.
[0061] Specifically, the second driving circuit 120 includes a control transistor TC, a first terminal ( Figure 1 Not shown) is coupled to the control terminal of the pulse width modulation transistor TP, and its second terminal ( Figure 1 Not shown) receives the first reference voltage PH, and its control terminal ( Figure 1 The control transistor TC (not shown) is controlled by a time-varying voltage Sweep. The control transistor TC is turned on in response to changes in the time-varying voltage Sweep and the data voltage Data. As a result of this conduction, the control transistor TC transmits the first reference voltage PH, connected to its second terminal, to the control terminal of the pulse-width modulation transistor TP, thereby turning off the pulse-width modulation transistor TP. Thus, by controlling the on and off states of the pulse-width modulation transistor TP, the duration of current flowing through the light-emitting element LED can be controlled.
[0062] In some embodiments, the time-varying voltage Sweep is a ramp signal, and the time-varying voltage Sweep varies linearly over time. For example, when the control transistor TC is a P-type transistor, the time-varying voltage Sweep decreases linearly over time until the voltage at the control terminal of the control transistor TC is low enough to turn on the control transistor TC. When the control transistor TC is an N-type transistor, the time-varying voltage Sweep increases linearly over time until the voltage at the control terminal of the control transistor TC is high enough to turn on the control transistor TC.
[0063] In such an embodiment, the variation speed (e.g., linear decreasing speed) of the time-varying voltage Sweep can be used to control the turn-on timing of the transistor TC, thereby controlling the turn-off timing of the pulse width modulation transistor TP, so that the duration of the current flowing through the light-emitting element LED can be regulated.
[0064] In some embodiments, the time-varying voltage Sweep is a step wave signal, and the time-varying voltage Sweep exhibits a step-like variation over time. For example, when the control transistor TC is a P-type transistor, the time-varying voltage Sweep decreases from an original voltage level to a first voltage level at a first time point, and then decreases from the first voltage level to a second voltage level at a second time point, and so on, until the voltage difference between the time-varying voltage Sweep and the data voltage Data is low enough to turn on the control transistor TC. When the control transistor TC is an N-type transistor, the time-varying voltage Sweep increases from the original voltage level to a first voltage level at a first time point, and then increases from the first voltage level to the second voltage level at a second time point, and so on, until the voltage difference between the time-varying voltage Sweep and the data voltage Data is high enough to turn on the control transistor TC.
[0065] In such an embodiment, the number of steps of the voltage level variation of the time-varying voltage Sweep can be used to control the conduction timing of the transistor TC (for example, by dividing the voltage level into more levels to increase the time during which the transistor TC is controlled to remain non-conducting; or by increasing the duration of each voltage level step to increase the time during which the transistor TC is controlled to remain non-conducting). This can further control the turn-off timing of the pulse-width modulation transistor TP, thereby regulating the duration of the current flowing through the light-emitting element LED.
[0066] Please refer to Figure 2 , Figure 2 FIG1 is a schematic diagram illustrating the internal architecture of a pixel circuit 100 according to an embodiment of the present invention. The first driver circuit 110 includes a first transistor T1, a second transistor T2, a first capacitor C1, a third transistor T3, a fourth transistor T4, and a fifth transistor T5. The second driver circuit 120 includes a control transistor TC, a sixth transistor T6, a second capacitor C2, a seventh transistor T7, and a third capacitor C3.
[0067] A first terminal of the first transistor T1 is coupled to the second terminal of the pulse amplitude modulation transistor TA, and a control terminal thereof receives the second scanning signal S2. A first terminal of the second transistor T2 is coupled to the second terminal of the first transistor T1, a second terminal thereof is coupled to the control terminal of the pulse amplitude modulation transistor TA, and a control terminal thereof receives the second scanning signal S2. A first terminal of the first capacitor C1 is coupled to the second terminal of the second transistor T2 and the control terminal of the pulse amplitude modulation transistor TA.
[0068] A first terminal of the third transistor T3 receives the system high voltage VDD, a second terminal of the third transistor T3 is coupled to the second terminal of the first capacitor C1, and a control terminal of the third transistor T4 receives the third scan signal S3. A first terminal of the fourth transistor T4 receives the data voltage Data, a second terminal of the fourth transistor T4 is coupled to the second terminal of the third transistor T3, and a control terminal of the fourth transistor T4 receives the second scan signal S2. A first terminal of the fifth transistor T5 is coupled to the second terminal of the first transistor T1 and the first terminal of the second transistor T2, a second terminal of the fifth transistor T5 receives the second reference voltage Vn, and a control terminal of the fifth transistor T5 receives the first scan signal S1.
[0069] The sixth transistor T6 has a first terminal that receives the data voltage Data, a second terminal that is coupled to the control terminal of the control transistor TC, and a control terminal that receives the second scan signal S2. The second capacitor C2 has a first terminal that receives the time-varying voltage Sweep, and a second terminal that is coupled to the second terminal of the sixth transistor T6. The seventh transistor T7 has a first terminal that is coupled to the first terminal of the control transistor TC, a second terminal that receives the third reference voltage PL, and a control terminal that receives the light-emitting control signal EMS. The third capacitor C3 has a first terminal that is coupled to the first terminal of the seventh transistor T7, and a second terminal that is coupled to the second terminal of the seventh transistor T7 and the third reference voltage PL.
[0070] Please refer to Figure 3 , Figure 3 is a timing diagram of the driving signal of the pixel circuit 100 according to an embodiment of the present invention, and is used in conjunction with Figures 4 to 8 The schematic diagrams of the pixel circuit 100 operating in the first operating interval t1, the second operating interval t2, the third operating interval t3, the fourth operating interval t4 and the fifth operating interval t5 respectively are provided for a better understanding of the present invention. Figures 4 to 8 In the figure, the transistors with a cross represent the off state, and the transistors without a cross represent the on state.
[0071] In the following exemplary embodiments, the order of the supply voltages from large to small is: system high voltage VDD=first reference voltage PH>system low voltage VSS=second reference voltage Vn>third reference voltage PL.
[0072] In the first operation interval t1, corresponding to Figure 4 In the reset and data voltage writing period shown, the first transistor T1, the second transistor T2, the fourth transistor T4, and the sixth transistor T6 are turned on in response to the low logic level of the second scan signal S2, and the fifth transistor T5 is turned on in response to the low logic level of the first scan signal S1. The third transistor T3 is turned off in response to the high logic level of the third scan signal S3, and the seventh transistor T7 is turned off in response to the high logic level of the emission control signal EMS. The pulse width modulation transistor TP and the control transistor TC are also turned off.
[0073] The first end of the first capacitor C1, the control end, and the second end of the pulse amplitude modulation transistor TA are reset to the second reference voltage Vn due to the conduction of the first transistor T1, the second transistor T2, and the fifth transistor T5. The second end of the first capacitor C1 and the second end of the second capacitor C2 are written with the data voltage Data due to the conduction of the fourth transistor T4 and the sixth transistor T6. At this point, the resetting steps for each node of the pixel circuit 100 are complete.
[0074] In the second operation interval t2, corresponding to Figure 5 In the compensation and data voltage writing period shown, the first transistor T1, the second transistor T2, the fourth transistor T4, and the sixth transistor T6 remain turned on in response to the low logic level of the second scan signal S2. The third transistor T3 is turned off in response to the high logic level of the third scan signal S3, the fifth transistor T5 is turned off in response to the high logic level of the first scan signal S1, and the seventh transistor T7 is turned off in response to the high logic level of the emission control signal EMS. The pulse width modulation transistor TP and the control transistor TC are also turned off.
[0075] The conduction of the first transistor T1 and the second transistor T2 enables the pulse amplitude modulation transistor TA to form a diode connection, so as to adjust the threshold voltage V TH_TA In the second operation interval t2, the potential of the control terminal of the pulse amplitude modulation transistor TA is compensated to the system high voltage VDD minus the threshold voltage V of the pulse amplitude modulation transistor TA. TH_TA At this point, the gate compensation step of the pulse amplitude modulation transistor TA of the pixel circuit 100 has been completed.
[0076] In the third operation interval t3, corresponding to Figure 6 In the first light-emitting interval shown, the first transistor T1, the second transistor T2, the fourth transistor T4, and the sixth transistor T6 are turned off in response to the high logic level of the second scan signal S2, while the fifth transistor T5 is turned off in response to the high logic level of the first scan signal S1. The third transistor T3 is turned on in response to the low logic level of the third scan signal S3, and the seventh transistor T7 is turned on in response to the low logic level of the light-emitting control signal EMS. The control transistor TC remains off.
[0077] The control terminal of the pulse width modulation transistor TP is written to the third reference voltage PL due to the conduction of the seventh transistor T7, so that the pulse width modulation transistor TP is turned on. The second terminal of the first capacitor C1 is written to the system high voltage VDD due to the conduction of the third transistor T3, so that the potential of the control terminal of the pulse amplitude modulation transistor TA changes to (2*VDD-V TH_TA-Data).
[0078] Based on the potential of each node, the current I flowing through the light emitting element LED D Can be expressed as:
[0079]
[0080] Among them, μ n is carrier mobility, C ox is the unit capacitance of the gate oxide layer, W is the gate width, and L is the gate length. The above parameters depend on the process parameters of the PWM transistor TA and vary according to the type of the PWM transistor TA selected.
[0081] In the fourth operation interval t4, corresponding to Figure 7 In the second light-emitting interval shown, the first transistor T1, the second transistor T2, the fourth transistor T4, and the sixth transistor T6 are turned off in response to the high logic level of the second scan signal S2, the fifth transistor T5 is turned off in response to the high logic level of the first scan signal S1, and the seventh transistor T7 is turned off in response to the high logic level of the light-emitting control signal EMS. The third transistor T3 remains on in response to the low logic level of the third scan signal S3, the control transistor TC remains off, and the pulse-width modulation transistor TP remains on.
[0082] Although the seventh transistor T7 is turned off by the high logic level of the light-emitting control signal EMS, the control terminal of the pulse-width modulation transistor TP is maintained at the third reference voltage PL due to the voltage regulation of the third capacitor C3, causing the pulse-width modulation transistor TP to remain conductive and maintain current flow through the light-emitting element LED. In the embodiment where the time-varying voltage Sweep is a step waveform, the time-varying voltage Sweep decreases from the original voltage level to the first voltage level, and the voltage at the control terminal of the control transistor TC decreases accordingly through the coupling effect of the second capacitor C2.
[0083] It is worth noting that in the fourth operation interval t4, the decrease degree of the time-varying voltage Sweep is still not low enough to turn on the control transistor TC. Therefore, the potential of the control terminal of the pulse width modulation transistor TP is still maintained at the third reference voltage PL, so that the pulse width modulation transistor TP is continuously turned on and current flows to the light-emitting element LED.
[0084] In the fifth operation interval t5, corresponding to Figure 8During the non-light-emitting period shown, the first transistor T1, the second transistor T2, the fourth transistor T4, and the sixth transistor T6 are turned off in response to the high logic level of the second scan signal S2. The fifth transistor T5 is turned off in response to the high logic level of the first scan signal S1. The seventh transistor T7 is turned off in response to the high logic level of the light-emitting control signal EMS. The third transistor T3 remains on in response to the low logic level of the third scan signal S3. The control transistor TC transitions from the off state to the on state, and the pulse-width modulation transistor TP transitions from the on state to the off state.
[0085] During the fifth operating interval t5, because the time-varying voltage Sweep has dropped from the first voltage level to the second voltage level, the voltage coupled to the control terminal of the control transistor TC via the second capacitor C2 is sufficient to turn on the control transistor TC. At this point, the first reference voltage PH is transmitted through the turned-on control transistor TC to the control terminal of the pulse-width modulation transistor TP, causing the control terminal of the pulse-width modulation transistor TP to change from the third reference voltage PL to the first reference voltage PH, turning off the pulse-width modulation transistor TP. At this point, current no longer flows through the light-emitting element LED. At this point, the driving steps of the pixel circuit 100 are substantially completed.
[0086] In summary, the pixel circuit of the present invention integrates a pulse-width modulation circuit and a pulse-amplitude modulation circuit to simultaneously control the intensity and duration of current flowing through the light-emitting element, enabling more accurate current control and improving the problem of uneven pixel brightness in low and medium grayscale applications. The pulse-width modulation circuit includes a control transistor coupled to a pulse-width modulation transistor. This circuit automatically switches the pulse-width modulation transistor to an off state through a time-varying voltage mechanism, thereby controlling the duration of current flowing through the light-emitting element. Furthermore, the pulse-width modulation circuit and the pulse-amplitude modulation circuit share the same data voltage, which avoids increasing the circuit layout area, reduces the pixel circuit footprint, and eliminates the need to supply multiple signals that would complicate the application.
[0087] Although the present invention has been disclosed above in various embodiments, they are not intended to limit the present invention. Any person skilled in the art may make slight changes and modifications without departing from the concept and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the claims.
Claims
1. A pixel circuit comprising: a pulse amplitude modulation transistor, a first terminal of which is coupled to a system high voltage; a pulse width modulation transistor, a first terminal of which is coupled to a second terminal of the pulse amplitude modulation transistor; a light emitting element coupled between a second terminal of the pulse width modulation transistor and a system low voltage; a first driving circuit coupled to a control terminal of the PWM transistor and the second terminal of the PWM transistor and configured to modulate the intensity of a current flowing through the light-emitting element according to a data voltage; as well as a second driving circuit coupled to the first driving circuit and a control terminal of the pulse width modulation transistor, and configured to modulate the duration of the current flowing through the light-emitting element according to the data voltage and a time-varying voltage, the second driving circuit comprising: a control transistor having a first terminal coupled to the control terminal of the PWM transistor and a second terminal receiving a first reference voltage, wherein the control transistor is turned on in response to a change in the time-varying voltage, so that the control terminal of the PWM transistor receives the first reference voltage through the control transistor, thereby turning off the PWM transistor.
2. The pixel circuit as claimed in claim 1 , wherein the first driving circuit comprises: a first transistor, a first terminal of which is coupled to the second terminal of the pulse amplitude modulation transistor, and a control terminal of which receives a second scan signal; a second transistor, having a first terminal coupled to a second terminal of the first transistor, a second terminal coupled to the control terminal of the pulse amplitude modulation transistor, and a control terminal receiving the second scan signal; a first capacitor, a first terminal of which is coupled to the second terminal of the second transistor; a third transistor, having a first terminal receiving the system high voltage, a second terminal coupled to a second terminal of the first capacitor, and a control terminal receiving a third scan signal; a fourth transistor, having a first terminal receiving the data voltage, a second terminal coupled to the second terminal of the third transistor, and a control terminal receiving the second scan signal; and A fifth transistor has a first terminal coupled to the second terminal of the first transistor, a second terminal receiving a second reference voltage, and a control terminal receiving a first scan signal.
3. The pixel circuit as claimed in claim 2, wherein the second driving circuit comprises: a sixth transistor, having a first terminal receiving the data voltage, a second terminal coupled to a control terminal of the control transistor, and a control terminal receiving the second scan signal; a second capacitor, a first terminal of which receives the time-varying voltage, and a second terminal of which is coupled to the second terminal of the sixth transistor; a seventh transistor, having a first terminal coupled to the first terminal of the control transistor, a second terminal receiving a third reference voltage, and a control terminal receiving a light-emitting control signal; and A third capacitor has a first terminal coupled to the first terminal of the seventh transistor, and a second terminal coupled to the second terminal of the seventh transistor.
4. The pixel circuit of claim 3 , wherein in a first operation interval, the first transistor, the second transistor, and the fifth transistor are turned on to reset the first end of the first capacitor and the second end of the pulse amplitude modulation transistor to the second reference voltage, and wherein the fourth transistor and the sixth transistor are turned on to write the data voltage into the second end of the first capacitor and the second end of the second capacitor.
5. The pixel circuit as claimed in claim 4 , wherein in a second operation range, the first transistor, the second transistor, the fourth transistor, and the sixth transistor remain turned on and the fifth transistor is turned off, and the potential of the control terminal of the PWM transistor is compensated to be the system high voltage minus a threshold voltage of the PWM transistor.
6. The pixel circuit of claim 5 , wherein in a third operating interval, the third transistor and the seventh transistor are turned on and the first transistor, the second transistor, the fourth transistor, the fifth transistor, and the sixth transistor are turned off, the system high voltage is written to the second terminal of the first capacitor, the voltage difference between the data voltage and the system high voltage is coupled to the control terminal of the pulse amplitude modulation transistor via the first capacitor, and the control terminal of the pulse width modulation transistor receives the third reference voltage and is turned on, allowing the current to flow through the light-emitting element.
7. The pixel circuit of claim 6 , wherein in a fourth operating range, the third transistor is turned on and the first transistor, the second transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor are turned off, and wherein the control terminal of the pulse width modulation transistor is maintained at the third reference voltage via the third capacitor, thereby turning on the pulse width modulation transistor to maintain the current flowing through the light-emitting element.
8. The pixel circuit of claim 7 , wherein in a fifth operating interval, a voltage of the time-varying voltage coupled to the control terminal of the control transistor via the second capacitor is sufficient to turn on the control transistor, causing the control terminal of the pulse width modulation transistor to change from the third reference voltage to the first reference voltage, thereby turning off the pulse width modulation transistor.
9. The pixel circuit as claimed in claim 1, wherein the time-varying voltage is a ramp signal, and the second driving circuit modulates the time of the current flowing through the light-emitting element according to the speed at which the data voltage and the ramp signal linearly vary.
10. The pixel circuit of claim 1, wherein the time-varying voltage is a staircase wave signal, and the second driving circuit modulates the time of the current flowing through the light-emitting element according to the data voltage and the voltage level variation order of the staircase wave signal.