Semiconductor memory device and operating method of semiconductor memory device

Abstract

The invention relates to a semiconductor memory device and an operating method of the semiconductor memory device. A semiconductor memory device is configured to perform a mismatch compensation operation of a bit line sense amplifier and enable a word line electrically coupled to the bit line after electrically isolating the bit line and an input node of the sense amplifier. When a mismatch compensation operation of the bit line sense amplifier is completed, the semiconductor memory device is configured to electrically couple the bit line and an input node of the bit line sense amplifier to generate a voltage level difference between the bit line and the negated bit line.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Korean Patent Application No. 10-2024-0018352 filed on February 6, 2024, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments relate generally to integrated circuit technology, and more particularly, to a semiconductor memory device and a method for operating the semiconductor memory device. Background Art

[0004] A semiconductor memory device may include a memory cell array and a bit line sense amplifier. The memory cell array may include a plurality of bit lines and a plurality of word lines connected to a plurality of memory cells. The semiconductor memory device may enable a word line based on a row series command address signal and select a bit line pair based on a column series command address signal. The bit line sense amplifier may sense and amplify the voltage level of a bit line pair (i.e., a bit line and a bit line bar) to read data stored in a memory cell associated with the word line and bit line, or write data to the memory cell.

[0005] A bitline sense amplifier can include multiple transistors. With the increasing integration and miniaturization of semiconductor devices, process variations and PVT (process, voltage, temperature) variations in MOS (metal oxide semiconductor) transistors are increasing. Even MOS transistors manufactured simultaneously on the same wafer and in the same environment inevitably experience process variations. Process variations or offsets between MOS transistors can significantly reduce the operational reliability of a semiconductor device. In particular, mismatches (such as threshold voltage differences) between the transistors that comprise a bitline sense amplifier (which must detect and amplify small voltage level differences) can be a significant factor in determining the quality of a semiconductor device. Therefore, an operation can be performed to compensate for the mismatch between the transistors that comprise the bitline sense amplifier before the bitline sense amplifier senses and amplifies the voltage level of the bitline pair. However, performing the mismatch compensation operation can delay the timing of wordline enablement and the timing of the bitline sense amplifier amplifying the voltage level of the bitline pair, and can reduce timing specifications (such as tRCD (RAS (row address strobe) to CAS (column address strobe) delay time)), thereby degrading the performance of the semiconductor memory device. Summary of the Invention

[0006] In one embodiment, a semiconductor memory device may include a sub-wordline driver, a bitline sense amplifier, and a bitline switch circuit. The sub-wordline driver may be configured to enable a wordline electrically coupled to a bitline based on a wordline control signal, and may be configured to delay the wordline control signal to generate a bitline switch signal. The bitline sense amplifier may be configured to amplify and latch a signal received through a first input node and a second input node. The bitline switch circuit may be configured to electrically couple the bitline to the first input node and electrically couple the bitline bar to the second input node in response to the bitline switch signal.

[0007] In one embodiment, a method for operating a semiconductor memory device may include: electrically isolating a bit line from a first input node of a bit line sense amplifier, and electrically isolating a bit line inversion from a second input node of the bit line sense amplifier; performing a mismatch compensation operation of the bit line sense amplifier, and enabling a word line to electrically couple a memory cell and the bit line; electrically coupling a first input node to the bit line, and electrically coupling a second input node to the bit line inversion; and generating a voltage level difference between a first node and a second node by amplifying a voltage level between the first input node and the second input node.

[0008] In an embodiment, a semiconductor memory device may include a sub-word line driver, a bit line sense amplifier, and a bit line switch circuit. The sub-word line driver may be configured to enable one of a first word line electrically coupled to a first bit line and a second word line electrically coupled to a second bit line based on a word line control signal, and may be configured to delay the word line control signal to generate one of a first bit line switch signal and a second bit line switch signal. The bit line sense amplifier may be configured to amplify and latch the voltage levels of a global bit line and a global bit line inversion. The bit line switch circuit may be configured to electrically couple the first bit line and the first bit line inversion to the global bit line and the global bit line inversion, respectively, in response to the first bit line switch signal, and may be configured to electrically couple the second bit line and the second bit line inversion to the global bit line and the global bit line inversion, respectively, in response to the second bit line switch signal.

[0009] In an embodiment, a method for operating a semiconductor memory device may include: electrically isolating a first bit line and a second bit line from a global bit line, and electrically isolating a first inverted bit line and a second inverted bit line from a global inverted bit line; performing a mismatch compensation operation of a bit line sense amplifier; enabling one of a first word line and a second word line to electrically couple one of the first bit line and the second bit line to a memory cell; electrically coupling a bit line among the first bit line and the second bit line that is electrically coupled to the enabled word line to a global bit line; and generating a voltage level difference between a first node and a second node by amplifying a voltage level between the global bit line and the global inverted bit line. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1is a diagram showing a configuration of a semiconductor memory device according to an embodiment.

[0011] Figure 2 is a diagram showing a configuration of a semiconductor memory device according to an embodiment.

[0012] Figure 3 is a diagram showing a configuration of a semiconductor memory device according to an embodiment.

[0013] Figure 4 It shows Figure 3 The configuration of the sense amplifier control circuit is shown in the diagram.

[0014] Figure 5 is a timing chart illustrating the operation of the semiconductor memory device according to the embodiment.

[0015] Figure 6A is a timing chart showing the operation of a comparative example of a semiconductor memory device, and Figure 6B is a timing chart illustrating the operation of the semiconductor memory device according to the embodiment.

[0016] Figure 7 is a timing chart illustrating the operation of the semiconductor memory device according to the embodiment.

[0017] Figure 8 is a diagram showing a configuration of a semiconductor memory device according to an embodiment.

[0018] Figure 9 is a diagram showing a configuration of a semiconductor memory device according to an embodiment.

[0019] Figure 10 is a timing chart illustrating the operation of the semiconductor memory device according to the embodiment.

[0020] Figure 11 is a timing chart illustrating the operation of the semiconductor memory device according to the embodiment. DETAILED DESCRIPTION

[0021] Figure 1 is a diagram showing a configuration of a semiconductor memory device 100 according to an embodiment. The semiconductor memory device 100 may include a data storage area 110, a command control circuit 120, an address control circuit 130, a clock control circuit 140, a power management circuit 150, a row decoder 160, a column decoder 170, a read / write circuit 180, and a data input / output circuit 190. The data storage area 110 may include a plurality of memory cell array blocks. The plurality of memory cell array blocks may include a plurality of memory cells capable of storing data. For example, the plurality of memory cell array blocks may include a first memory cell array block 111 and a second memory cell array block 112. In Figure 1, the number of memory cell array blocks included in the data storage area 110 is shown as two, but the number of memory cell array blocks included in the data storage area 110 may be four, eight or more. The first and second memory cell array blocks 111, 112 may each include a plurality of unit cell arrays. For example, the first memory cell array block 111 may include a first unit cell array MA1 and a second unit cell array MA2. The unit cell array may be a memory tile or a memory cell matrix area (mat). The first and second unit cell arrays MA1, MA2 may each include a plurality of word lines WL and a plurality of bit lines BL, BLB, and a plurality of memory cells MC may be electrically coupled at points where the plurality of word lines WL intersect with the plurality of bit lines BL, BLB, respectively. The bit line sense amplifier array SA may be disposed between the first and second unit cell arrays MA1, MA2. The bit line sense amplifier array SA may include a plurality of bit line sense amplifiers, and the number of bit line sense amplifiers may vary according to the number of bit lines provided in the first and second unit cell arrays MA1, MA2. The bit line sense amplifiers provided in the bit line sense amplifier array SA can be electrically coupled to the bit line BL and the inverted bit line BLB to amplify and latch the voltage levels of the bit line pairs BL and BLB. On the sides of the first and second unit cell arrays MA1 and MA2, sub-word line drivers SWD can be provided. The sub-word line driver SWD can enable a specific word line among the multiple word lines WL based on the word line control signal WCS provided from the row decoder 160 (described later). The first and second unit cell arrays MA1 and MA2 can be provided with a local input / output line LIO and an inverted local input / output line LIOB. The local input / output line pairs LIO and LIOB can be electrically coupled to the bit line pairs BL and BLB respectively through the column decoder 170 described later. In an embodiment, the sub-word line driver can be implemented in hardware, software, or a combination of the two. For example, the sub-word line driver can be implemented as a sub-word line driver circuit that operates according to an algorithm.

[0022] The command control circuit 120 may receive a command signal CMD and may decode the command signal CMD to generate an internal command signal. The internal command signal may include an activation signal ACT, a read signal RD, a write signal WT, and a refresh signal REF. The command signal CMD may be a signal provided by a host device (not shown) electrically coupled to the semiconductor memory device 100. The host device may provide the command signal CMD to the semiconductor memory device 100 to enable the semiconductor memory device 100 to perform various operations. The operation of outputting data stored in the semiconductor memory device 100 to the host device may be a read operation, while the operation of storing data received from the host device in the semiconductor memory device 100 may be a write operation. The operation of activating the data storage area 110 and / or the first and second memory cell array blocks 111 and 112 before the semiconductor memory device 100 performs a read operation and a write operation may be an activation operation. The operation of the semiconductor memory device 100 deactivating the data storage area 110 and / or the first and second memory cell array blocks 111 and 112 may be a precharge operation. When the host device provides a command signal CMD for performing an activate operation, the command control circuit 120 may decode the command signal CMD to generate an activate signal ACT. When the host device provides a command signal CMD for performing a precharge operation, the command control circuit 120 may decode the command signal CMD to generate a precharge signal PCG. In one embodiment, rather than receiving the command signal CMD from the host device to generate the precharge signal PCG, the command control circuit 120 may delay the activate signal ACT to generate the precharge signal PCG. When the host device provides a command signal CMD for performing a read operation, the command control circuit 120 may decode the command signal CMD to generate a read signal RD. When the host device provides a command signal CMD for performing a write operation, the command control circuit 120 may decode the command signal CMD to generate a write signal WT. The semiconductor memory device 100 may perform a refresh operation to retain data stored in memory cells that have not undergone a read or write operation. When the host device provides a command signal CMD for performing a refresh operation, the command control circuit 120 may decode the command signal CMD to generate a refresh signal REF. In an embodiment, even if the command signal CMD is not received from the host device, the command control circuit 120 may generate a refresh signal REF to periodically perform a refresh operation when the semiconductor memory apparatus 100 enters a low power mode. The command control circuit 120 may provide internal command signals to the row decoder 160, the read / write circuit 180, and the data input / output circuit 190. For example, the command control circuit 120 may provide an activation signal ACT, a precharge signal PCG, and a refresh signal REF to the row decoder 160, and may provide a read signal RD and a write signal WT to the read / write circuit 180 and the data input / output circuit 190.

[0023] The address control circuit 130 may receive an address signal ADD and may generate a row address signal RADD and a column address signal CADD based on the address signal ADD. The address signal ADD may be a signal provided by a host device to the semiconductor memory device 100. The host device may provide the address signal ADD to the semiconductor memory device 100 to access the first and second unit cell arrays MA1 and MA2 of the semiconductor memory device 100. The address control circuit 130 may latch the address signal ADD and output the latched address signal as a row address signal RADD or a column address signal CADD. For example, the address control circuit 130 may output the address signal ADD received during an activation operation of the semiconductor memory device 100 as the row address signal RADD. During the activation operation, the semiconductor memory device 100 may enable word lines of the first and second unit cell arrays MA1 and MA2 based on the row address signal RADD. The address control circuit 130 may output the address signal ADD received during one of a read operation and a write operation of the semiconductor memory device 100 as the column address signal CADD. During read and write operations, the semiconductor memory device 100 may select bit lines BL of the first and second unit cell arrays MA1 and MA2 based on a column address signal CADD. When a specific word line among the word lines WL of the first and second unit cell arrays MA1 and MA2 is enabled and a specific bit line among the bit lines BL of the first and second unit cell arrays MA1 and MA2 is selected, memory cells electrically coupled between the enabled word line and the selected bit line may be accessed.

[0024] The clock control circuit 140 may receive a clock signal CLK and may generate multiple internal clock signals based on the clock signal CLK. The clock signal CLK may be a signal provided from a host device to the semiconductor memory device 100. The clock control circuit 140 may buffer the clock signal CLK to generate a first internal clock signal CLK1 and may perform a delay locking operation on the first internal clock signal CLK1 to generate a second internal clock signal CLK2. The clock control circuit 140 may include a delay-locked loop circuit capable of performing a delay locking operation. The clock control circuit 140 may provide at least one of the first internal clock signal CLK1 and the second internal clock signal CLK2 to an internal circuit of the semiconductor memory device 100 that operates synchronously with the clock signal. For example, the clock control circuit 140 may provide the first internal clock signal CLK1 and the second internal clock signal CLK2 to the command control circuit 120. The command control circuit 120 may latch a command signal CMD in synchronization with the first internal clock signal CLK1 and may decode the latched command signal. When the command control circuit 120 receives a command signal CMD for performing a read operation or a write operation, the command control circuit 120 may delay the decoded command signal by a time corresponding to the read latency or the write latency in synchronization with the first internal clock signal CLK1. The command control circuit 120 may output the delayed command signal as a read signal RD or a write signal WT in synchronization with the second internal clock signal CLK2. In addition, the clock control circuit 140 may provide the second internal clock signal CLK2 to the read / write circuit 180 and the data input / output circuit 190.

[0025] The power management circuit 150 may receive an external voltage VEXT from a power source and may generate a plurality of internal voltages based on the external voltage VEXT. In an embodiment, the power management circuit 150 may receive the external voltage VEXT from a power source external to the power management circuit 150. In an embodiment, the power management circuit 150 may receive the external voltage VEXT from a power source external to the semiconductor memory device 100. The plurality of internal voltages may have different voltage levels. The power management circuit 150 may include a voltage generating circuit capable of generating the plurality of internal voltages, such as a voltage distribution circuit, a voltage pump circuit, or a voltage regulator. The power management circuit 150 may distribute the plurality of internal voltages to the internal circuits of the semiconductor memory device 100 via a voltage network (not shown) provided in the semiconductor memory device 100. The plurality of internal voltages may include a first internal voltage V1, a second internal voltage V2, a third internal voltage V3, and a fourth internal voltage V4. In an embodiment, the number of internal voltages generated by the power management circuit 150 may be five or more. For example, the voltage level of the second internal voltage V2 may be higher than the first internal voltage V1, the voltage level of the third internal voltage V3 may be lower than the first internal voltage V1, and the voltage level of the fourth internal voltage V4 may be equal to or lower than the first internal voltage V1. The first internal voltage V1 may be a base power supply voltage, the second internal voltage V2 may be a pumping voltage, the third internal voltage V3 may be a core voltage, and the fourth internal voltage V4 may be a peripheral voltage. The power management circuit 150 may provide the first internal voltage V1 and the third internal voltage V3 to the unit cell arrays MA1 and MA2 and the bit line sense amplifier array SA. The power management circuit 150 may provide the second internal voltage V2 to the row decoder 160. The power management circuit 150 may provide the fourth internal voltage V4 to the command control circuit 120, the address control circuit 130, the clock control circuit 140, the row decoder 160, the column decoder 170, the read / write circuit 180, and the data input / output circuit 190.

[0026] The row decoder 160 may receive a row address signal RADD. The row decoder 160 may decode the row address signal RADD to generate a word line control signal WCS. The word line control signal WCS may include any signal for selecting a word line, such as a main word line signal and a sub-word line select signal. The row decoder 160 may provide the word line control signal WCS to a sub-word line driver SWD. The sub-word line driver SWD may enable a specific word line from a plurality of word lines WL based on the word line control signal WCS. The column decoder 170 may receive a column address signal CADD. Based on the column address signal CADD, the column decoder 170 may select a bit line pair BL, BLB to electrically couple to a local input / output line pair LIO, LIOB. The column decoder 170 may generate a column select signal based on the column address signal CADD. The column decoder 170 may include a column switch that electrically couples the bit line BL to the local input / output line LIO and the bit line bar BLB to the local input / output line bar LIOB. The column switch can electrically couple the local input / output line pair LIO, LIOB to the bit line pair BL, BLB based on the column selection signal. The bit line pair BL, BLB can be electrically coupled to the read / write circuit 180 through the local input / output line pair LIO, LIOB.

[0027] The read / write circuit 180 may be electrically coupled to the bit line pair BL, BLB via the column decoder 170 and the local input / output line pair LIO, LIOB. The read / write circuit 180 may receive a read signal RD and a write signal WT from the command control circuit 120. The read / write circuit 180 may be electrically coupled to the data input / output circuit 190 via the global input / output (input and output) line GIO. During a read operation of the semiconductor memory device 100, the read / write circuit 180 may amplify data output from the first and second unit cell arrays MA1, MA2 via the bit line pair BL, BLB and the local input / output line pair LIO, LIOB based on the read signal RD, and output the amplified data to the global input / output line GIO. During a write operation of the semiconductor memory device 100, the read / write circuit 180 may amplify data received via the global input / output line GIO based on the write signal WT, and provide the amplified data to the first and second unit cell arrays MA1, MA2 via the local input / output line pair LIO, LIOB and the bit line pair BL, BLB. The read / write circuit 180 may receive the second internal clock signal CLK2 from the clock control circuit 140 and may transmit data to the global input / output line GIO or receive data transmitted through the global input / output line GIO in synchronization with the second internal clock signal CLK2 .

[0028] The data input / output circuit 190 may be electrically coupled to the global input / output line GIO and the data bus 101. The data bus 101 may be a signal transmission line connecting the host device and the semiconductor memory apparatus 100. The data input / output circuit 190 may receive a read signal RD and a write signal WT from the command control circuit 120, and may receive a second internal clock signal CLK2 from the clock control circuit 140. During a read operation of the semiconductor memory apparatus 100, the data input / output circuit 190 may receive data transmitted via the global input / output line GIO based on the read signal RD, generate a data stream DQ based on the received data, and transmit the data stream DQ to the host device via the data bus 101 in synchronization with the second internal clock signal CLK2. During a write operation of the semiconductor memory apparatus 100, the data input / output circuit 190 may receive a data stream DQ transmitted from the host device via the data bus 101 based on the write signal WT. The data input / output circuit 190 can generate data based on the data stream DQ in synchronization with the second internal clock signal CLK2 and transmit the data to the read / write circuit 180 through the global input / output line GIO. The data input / output circuit 190 may include a serializer / deserializer (SerDes) that serializes the data transmitted through the global input / output line GIO to generate the data stream DQ and deserializes the data stream DQ to generate data output to the global input / output line GIO.

[0029] Figure 2 is a diagram showing a configuration of a semiconductor memory device 200 according to an embodiment. The semiconductor memory device 200 may include a Figure 1 , and a configuration of at least one of the first and second memory cell array blocks 111, 112 shown in . In an embodiment, the semiconductor memory device 200 may include a first unit cell array MA1, a second unit cell array MA2, a bit line sense amplifier array SA, a sub-word line driver SWD, and a bit line switch circuit BLSW. The first and second unit cell arrays MA1, MA2 may include a plurality of bit lines and a plurality of word lines, and a plurality of memory cells may be electrically coupled at points where the plurality of bit lines intersect the plurality of word lines. For example, the first unit cell array MA1 may include at least a first bit line BL1 and a second bit line BL2, and may include at least a first word line WL1 and a second word line WL2. The second unit cell array MA2 may include at least a first inverted bit line BLB1 and a second inverted bit line BLB2, and may include at least a third word line WLn+1 and a fourth word line WLn+2. n may be an integer of 2 or greater.

[0030] The bit line sense amplifier array SA may be disposed between the first unit cell array MA1 and the second unit cell array MA2. The bit line sense amplifier array SA may be electrically coupled to the bit lines of the first unit cell array MA1 and the second unit cell array MA2, respectively, to perform an amplification operation. The bit line sense amplifier array SA may include a plurality of bit line sense amplifiers. For example, the bit line sense amplifier array SA may include a bit line sense amplifier BLSA. The bit line sense amplifier BLSA may be electrically coupled to the first bit line BL1 and the first bit line inversion BLB1 to amplify and latch the voltage levels of the first bit line BL1 and the first bit line inversion BLB1. Although not shown, the bit line sense amplifier array SA may further include a bit line sense amplifier electrically coupled to the second bit line BL2 and the second bit line inversion BLB2. The bit line sense amplifier BLSA may include a plurality of transistors to amplify and latch the voltage levels of the first bit line BL1 and the first bit line inversion BLB1. The bit line sense amplifier BLSA may perform a mismatch compensation operation to compensate for process mismatch or offset between the plurality of transistors before amplifying the voltage levels of the first bit line BL1 and the first bit line inversion BLB1.

[0031] The sub-wordline driver SWD may receive a wordline control signal WCS. The sub-wordline driver SWD may enable one of the first to fourth wordlines WL1, WL2, WLn+1, and WLn+2 based on the wordline control signal WCS. The sub-wordline driver SWD may generate at least one bitline switch signal BISO based on the wordline control signal WCS. The sub-wordline driver SWD may delay the wordline control signal WCS to generate the bitline switch signal BISO. The sub-wordline driver SWD may generate the bitline switch signal BISO by delaying the wordline control signal WCS by the time at which the mismatch compensation operation of the bitline sense amplifier BLSA is performed. The sub-wordline driver SWD may provide the bitline switch signal BISO to the bitline switch circuit BLSW.

[0032] The bit line switch circuit BLSW may be electrically coupled to the first bit line BL1, the first bit line bar BLB1, and the bit line sense amplifier BLSA, and may receive a bit line switch signal BISO. The bit line switch circuit BLSW may electrically couple the first bit line BL1 and the first bit line bar BLB1 to the bit line sense amplifier BLSA based on the bit line switch signal BISO. When the bit line switch signal BISO is disabled, the bit line switch circuit BLSW may electrically isolate the first bit line BL1 and the first bit line bar BLB1 from the input node of the bit line sense amplifier BLSA. When the bit line switch signal BISO is enabled, the bit line switch circuit BLSW may electrically couple the first bit line BL1 and the first bit line bar BLB1 to the input node of the bit line sense amplifier BLSA.

[0033] Figure 3is a diagram showing a configuration of a semiconductor memory device 300 disclosed according to an embodiment. The semiconductor memory device 300 may include a Figure 2 . The configuration of the connection relationship between the bit line sense amplifier BLSA and the first and second unit cell arrays MA1 and MA2 of the semiconductor memory device 200 shown in FIG. In an embodiment, the semiconductor memory device 300 may include a bit line sense amplifier 310 and a bit line switch circuit 320. In an embodiment, the semiconductor memory device 300 may include a bit line sense amplifier 310, a bit line switch circuit 320, and a sub-word line driver SWD. The bit line sense amplifier 310 may amplify and latch a signal received through the first input node IN1 and the second input node IN2. The bit line sense amplifier 310 may change the voltage levels of the first node IBLB and the second node IBL based on the signals received through the first and second input nodes IN1 and IN2. The bit line sense amplifier 310 may change the voltage level of the first node IBLB based on the voltage level of the first input node IN1, and may change the voltage level of the second node IBL based on the voltage level of the second input node IN2.

[0034] The bit line switch circuit 320 may receive a bit line switch signal BISO. The bit line switch signal BISO may be a Figure 2 The bit line switch circuit 320 can electrically couple the bit line BL and the bit line bar BLB to the bit line sense amplifier 310 based on the bit line switch signal BISO. Based on the bit line switch signal BISO, the bit line switch circuit 320 can electrically couple the bit line BL to the first input node IN1 and the bit line bar BLB to the second input node IN2. When the bit line switch signal BISO is disabled, the bit line switch circuit 320 can electrically isolate the bit line BL from the first input node IN1 and the bit line bar BLB from the second input node IN2. When the bit line switch signal BISO is enabled, the bit line switch circuit 320 can electrically couple the bit line BL to the first input node IN1 and the bit line bar BLB to the second input node IN2. When the word line WL1 is enabled, the bit line BL can be electrically coupled to the first memory cell MC1. When the word line WLn+1 is enabled, the bit line bar BLB can be electrically coupled to the second memory cell MC2.

[0035] The semiconductor memory device 300 may further include a sense amplifier control circuit 330 and a column switch 340. The sense amplifier control circuit 330 may receive a sense amplifier control signal and provide voltages to the first power supply terminal RTO and the second power supply terminal SB of the bit line sense amplifier 310. The sense amplifier control circuit 330 may receive at least a first control signal SAP1 and a second control signal SAN1. The sense amplifier control circuit 330 may provide a first internal voltage V1 to the first power supply terminal RTO based on the first control signal SAP1. The first internal voltage V1 may be Figure 1 The first internal voltage V1 is shown. The sense amplifier control circuit 330 may provide the first internal voltage V1 to the first power supply terminal RTO when the first control signal SAP1 is enabled, and may not provide the first internal voltage V1 to the first power supply terminal RTO when the first control signal SAP1 is disabled. The sense amplifier control circuit 330 may electrically couple the second power supply terminal SB to the ground voltage VSS based on the second control signal SAN1. The sense amplifier control circuit 330 may electrically couple the second power supply terminal SB to the ground voltage VSS when the second control signal SAN1 is enabled, and may not electrically couple the second power supply terminal SB to the ground voltage VSS when the second control signal SAN1 is disabled.

[0036] The sense amplifier control circuit 330 may also receive a third control signal SAP2, a fourth control signal SAP3, and a fifth control signal SAN2. The sense amplifier control circuit 330 may provide a third internal voltage V3 to the first power supply terminal RTO based on the third control signal SAP2. The third internal voltage V3 may be Figure 1The sense amplifier control circuit 330 may provide the third internal voltage V3 to the first power supply terminal RTO when the third control signal SAP2 is enabled, and may not provide the third internal voltage V3 to the first power supply terminal RTO when the third control signal SAP2 is disabled. The third control signal SAP2 may be a signal controlled independently of the first control signal SAP1. In an embodiment, the sense amplifier control circuit 330 may be modified to provide the first internal voltage V1 instead of the third internal voltage V3 based on the third control signal SAP2. The sense amplifier control circuit 330 may provide the first internal voltage V1 to the first power supply terminal RTO based on the fourth control signal SAP3. The sense amplifier control circuit 330 may provide the first internal voltage V1 to the first power supply terminal RTO when the fourth control signal SAP3 is enabled, and may not provide the first internal voltage V1 to the first power supply terminal RTO when the fourth control signal SAP3 is disabled. The fourth control signal SAP3 may be a signal controlled together with the third control signal SAP2. The sense amplifier control circuit 330 can electrically couple the second power supply terminal SB to the ground voltage VSS based on the fifth control signal SAN2. The sense amplifier control circuit 330 can electrically couple the second power supply terminal SB to the ground voltage VSS when the fifth control signal SAN2 is enabled, and may not electrically couple the second power supply terminal SB to the ground voltage VSS when the fifth control signal SAN2 is disabled. The fifth control signal SAN2 may be a signal controlled together with the second control signal SAN1.

[0037] The column switch 340 can be electrically coupled to the bit line BL, the bit line bar BLB, the local input / output line LIO, and the local input / output line bar LIOB, and can receive a column select signal YI. Based on the column select signal YI, the column switch 340 can electrically couple the bit line BL to the local input / output line LIO and the bit line bar BLB to the local input / output line bar LIOB. When the column select signal YI is disabled, the column switch 340 can electrically isolate the bit line BL from the local input / output line LIO and the bit line bar BLB from the local input / output line bar LIOB. When the column select signal YI is enabled, the column switch 340 can electrically couple the bit line BL to the local input / output line LIO and the bit line bar BLB to the local input / output line bar LIOB.

[0038] The bit line sense amplifier 310 may include an input circuit 311, a latch circuit 312, an isolation switch circuit 313, and a compensation switch circuit 314. The input circuit 311 is electrically coupled to a first input node IN1, a second input node IN2, a first node IBLB, and a second node IBL. The input circuit 311 may change the voltage level of the first node IBLB and the second node IBL according to the voltage levels of the first input node IN1 and the second input node IN2. The input circuit 311 may change the voltage level of the first node IBLB according to the voltage level of the first input node IN1 and may change the voltage level of the second node IBL according to the voltage level of the second input node IN2. The input circuit 311 may include a first transistor T11 and a second transistor T12. The first transistor T11 and the second transistor T12 may be N-channel MOS transistors. The gate of the first transistor T11 may be connected to the first input node IN1, the drain of the first transistor T11 may be connected to the first node IBLB, and the source of the first transistor T11 may be connected to the second power supply terminal SB. A gate of the second transistor T12 is connected to the second input node IN2 , a drain of the second transistor T12 is connected to the second node IBL, and a source of the second transistor T12 may be connected to the second power supply terminal SB.

[0039] The latch circuit 312 can latch the voltage levels of the first node IBLB and the second node IBL based on the voltage levels of the first node IBLB and the second node IBL. The latch circuit 312 can change the voltage level of the second node IBLB based on the voltage level of the first node IBLB, and can change the voltage level of the first node IBLB based on the voltage level of the second node IBLB. The latch circuit 312 can include a third transistor T13 and a fourth transistor T14. The third transistor T13 and the fourth transistor T14 can be P-channel MOS transistors. The gate of the third transistor T13 can be connected to the second node IBLB, the source of the third transistor T13 can be connected to the first power supply terminal RTO, and the drain of the third transistor T13 can be connected to the first node IBLB. The gate of the fourth transistor T14 can be connected to the first node IBLB, the source of the fourth transistor T14 can be connected to the first power supply terminal RTO, and the drain of the fourth transistor T14 can be connected to the second node IBL.

[0040] The isolation switch circuit 313 can be electrically coupled to the first input node IN1, the second input node IN2, the first node IBLB, and the second node IBLB, and can receive an isolation switch signal ISOB. Based on the isolation switch signal ISOB, the isolation switch circuit 313 can electrically couple the first input node IN1 to the second node IBL and the second input node IN2 to the first node IBLB. When the isolation switch signal ISOB is disabled, the isolation switch circuit 313 can electrically isolate the first input node IN1 from the second node IBL and the second input node IN2 from the first node IBLB. When the isolation switch signal ISOB is enabled, the isolation switch circuit 313 can electrically couple the first input node IN1 to the second node IBL and the second input node IN2 to the first node IBLB. The isolation switch circuit 313 can include a fifth transistor T15 and a sixth transistor T16. The fifth transistor T15 and the sixth transistor T16 can be N-channel MOS transistors. The fifth transistor T15 is connected between the first input node IN1 and the second node IBL, and a gate of the fifth transistor T15 can receive the isolation switch signal ISOB. The sixth transistor T16 is connected between the second input node IN2 and the first node IBLB, and a gate of the sixth transistor T16 can receive the isolation switch signal ISOB.

[0041] The compensation switch circuit 314 is electrically coupled to the first input node IN1, the second input node IN2, the first node IBLB, and the second node IBL, and can receive a mismatch compensation signal MCS. Based on the mismatch compensation signal MCS, the compensation switch circuit 314 can electrically couple the first input node IN1 to the first node IBLB and the second input node IN2 to the second node IBL. When the mismatch compensation signal MCS is disabled, the compensation switch circuit 314 can electrically isolate the first input node IN1 from the first node IBLB and the second input node IN2 from the second node IBL. When the mismatch compensation signal MCS is enabled, the compensation switch circuit 314 can electrically couple the first input node IN1 to the first node IBLB and the second input node IN2 to the second node IBL. The compensation switch circuit 314 can include a seventh transistor T17 and an eighth transistor T18. The seventh transistor T17 and the eighth transistor T18 can be N-channel MOS transistors. The seventh transistor T17 is connected between the first input node IN1 and the first node IBLB, and a gate of the seventh transistor T17 can receive the mismatch compensation signal MCS. The eighth transistor T18 is connected between the second input node IN2 and the second node IBL, and a gate of the eighth transistor T18 can receive the mismatch compensation signal MCS.

[0042] The bit line sense amplifier 310 may further include a bit line precharge circuit 315. The bit line precharge circuit 315 may precharge the second node IBL with the bit line precharge voltage VBLP based on the bit line precharge signal BLPCG. For example, the bit line precharge voltage VBLP may have a voltage level corresponding to half of the first internal voltage V1 or a voltage level corresponding to half of the third internal voltage V3. The bit line precharge circuit 315 may include a ninth transistor T19. The ninth transistor T19 may be an N-channel MOS transistor. The gate of the ninth transistor T19 may receive the bit line precharge signal BLPCG, one of the drain and source of the ninth transistor T19 may be connected to the second node IBL, and the other of the drain and source of the ninth transistor T19 may be connected to a terminal to which the bit line precharge voltage VBLP is supplied. The first to fifth control signals SAP1, SAN1, SAP2, SAP3, SAN2, the isolation switch signal ISOB, the mismatch compensation signal MCS, and the bit line precharge signal BLPCG may be based on Figure 1 The activation signal ACT shown is generated and can be enabled and disabled at a predetermined timing when the activation signal ACT is enabled. As used herein, the term "predetermined" with respect to a parameter (such as a predetermined timing, time, or voltage level) means that the value of the parameter is determined before the parameter is used in a process or algorithm. For some embodiments, the value of the parameter is determined before the process or algorithm begins. In other embodiments, the value of the parameter is determined during the process or algorithm but before the parameter is used in the process or algorithm.

[0043] The bit line switch circuit 320 may include a first switch 321 and a second switch 322. Figure 3denoted by 320 / 321 and 320 / 322, respectively. The first switch 321 can electrically couple the bit line BL to the first input node IN1 based on a bit line switch signal BISO. When the bit line switch signal BISO is disabled, the first switch 321 can electrically isolate the bit line BL from the first input node IN1. When the bit line switch signal BISO is enabled, the first switch 321 can electrically couple the bit line BL to the first input node IN1. The first switch 321 can include a first transistor T21. The first transistor T21 can be an N-channel MOS transistor. The first transistor T21 is connected between the bit line BL and the first input node IN1, and the gate of the first transistor T21 can receive the bit line switch signal BISO. The second switch 322 can electrically couple the bit line bar BLB to the second input node IN2 based on the bit line switch signal BISO. When the bit line switch signal BISO is disabled, the second switch 322 can electrically isolate the bit line bar BLB from the second input node IN2. When the bit line switch signal BISO is enabled, the second switch 322 can electrically couple the bit line bar BLB to the second input node IN2. The second switch 322 can include a second transistor T22. The second transistor T22 can be an N-channel MOS transistor. The second transistor T22 is connected between the bit line bar BLB and the second input node IN2, and the gate of the second transistor T22 can receive the bit line switch signal BISO.

[0044] The column switch 340 may include a first transistor T31 and a second transistor T32. The first transistor T31 and the second transistor T32 may be N-channel MOS transistors. The first transistor T31 is connected between the first input node IN1 and the local input / output line LIO, and the gate of the first transistor T31 may receive a column select signal YI. The second transistor T32 is connected between the second input node IN2 and the local input / output line bar LIOB, and the gate of the second transistor T32 may receive a column select signal YI.

[0045] In an embodiment, the bit line BL and the bit line bar BLB may each be electrically coupled to a bleeder circuit BD. The bleeder circuit BD may precharge the voltage levels of the bit line BL and the bit line bar BLB to a predetermined voltage level. For example, the bleeder circuit BD may precharge the bit line BL and the bit line bar BLB to the bit line precharge voltage VBLP by electrically coupling a terminal supplied with the bit line precharge voltage VBLP to the bit line BL and the bit line bar BLB.

[0046] Figure 4 It shows Figure 3 FIG. 3 is a diagram showing the configuration of the sense amplifier control circuit 330. Figure 4The sense amplifier control circuit 330 may include a first transistor T41, a second transistor T42, a third transistor T43, a fourth transistor T44, a fifth transistor T45, a sixth transistor T46, a seventh transistor T47, and an eighth transistor T48. The first to eighth transistors T41-T48 may be N-channel MOS transistors. The sense amplifier control circuit may also receive a driver pre-charge signal DPCG. The first transistor T41 may be connected between a first power supply terminal RTO and a second power supply terminal SB, and the gate of the first transistor T41 may receive the driver pre-charge signal DPCG. The second transistor T42 may be connected between the first power supply terminal RTO and a terminal to which a bitline pre-charge voltage VBLP is supplied, and the gate of the second transistor T42 may receive the driver pre-charge signal DPCG. The third transistor T43 may be connected between the second power supply terminal SB and a terminal to which a bitline pre-charge voltage VBLP is supplied, and the gate of the third transistor T43 may receive the driver pre-charge signal DPCG. The gate of the fourth transistor T44 may receive the first control signal SAP1, the drain of the fourth transistor T44 may receive the first internal voltage V1, and the source of the fourth transistor T44 may be connected to the first power supply terminal RTO. The gate of the fifth transistor T45 may receive the second control signal SAN1, the drain of the fifth transistor T45 may be connected to the second power supply terminal SB, and the source of the fifth transistor T45 may be connected to the ground voltage VSS. The gate of the sixth transistor T46 may receive the third control signal SAP2, the drain of the sixth transistor T46 may receive the third internal voltage V3, and the source of the sixth transistor T46 may be connected to the first power supply terminal RTO. In an embodiment, the drain of the sixth transistor T46 may be modified to receive the first internal voltage V1 instead of the third internal voltage V3. The gate of the seventh transistor T47 may receive the fourth control signal SAP3, the drain of the seventh transistor T47 may receive the first internal voltage V1, and the source of the seventh transistor T47 may be connected to the first power supply terminal RTO. A gate of the eighth transistor T48 may receive the fifth control signal SAN2 , a drain of the eighth transistor T48 is connected to the second power supply terminal SB, and a source of the eighth transistor T48 is connected to the ground voltage VSS.

[0047] When the driver precharge signal DPCG is enabled, the first to third transistors T41, T42, and T43 can be turned on. The first transistor T41 can electrically couple the first and second power supply terminals RTO and SB, and the second and third transistors T42 and T43 can provide the bit line precharge voltage VBLP to the first and second power supply terminals RTO and SB. When the driver precharge signal DPCG is disabled, the sense amplifier control circuit 330 can supply power to the first and second power supply terminals RTO and SB. When at least one of the first, third, and fourth control signals SAP1, SAP2, and SAP3 is enabled, the fourth, sixth, and seventh transistors T44, T46, and T47 can provide the first internal voltage V1 or the third internal voltage V3 to the first power supply terminal RTO. When at least one of the second and fifth control signals SAN1 and SAN2 is enabled, the fifth and eighth transistors T45 and T48 can electrically couple the second power supply terminal SB to the ground voltage VSS.

[0048] Figure 5 1 is a timing diagram showing the operation of the semiconductor memory device 300 according to the embodiment. Figures 1 to 5, the operating method of the semiconductor memory device 300 according to the embodiment will be described as follows. Before t0, the bit line precharge signal BLPCG, the isolation switch signal ISOB, and the mismatch compensation signal MCS may be enabled. The bit line switch signal BISO may remain disabled. Therefore, the first node IBLB, the second node IBL, the first input node IN1, and the second input node IN2 may be in a precharge state having the bit line precharge voltage VBLP. At t0, when the activation signal ACT is received, the bit line precharge signal BLPCG and the isolation switch signal ISOB may be disabled, the first input node IN1 and the second node IBL may be electrically isolated, and the second input node IN2 and the first node IBLB may be electrically isolated. Since the mismatch compensation signal MCS remains enabled, the electrical coupling between the first input node IN1 and the first node IBLB and the electrical coupling between the second input node IN2 and the second node IBL may be maintained. At t1, the first control signal SAP1, the second control signal SAN1, the fourth control signal SAP3, and the fifth control signal SAN2 are enabled, and the sense amplifier control circuit 330 can provide the first internal voltage V1 to the first power supply terminal RTO and electrically couple the second power supply terminal SB to the ground voltage VSS. As power is supplied to the first power supply terminal RTO and the second power supply terminal SB of the bitline sense amplifier 310, the bitline sense amplifier 310 is activated and can perform a mismatch compensation operation. Depending on the threshold voltage mismatch or offset between the first transistor T11 and the second transistor T12, and the threshold voltage mismatch or offset between the third transistor T13 and the fourth transistor T14, the voltage levels of the first input node IN1 and the second input node IN2 can be set to different levels. In addition, the word line WL1 can be enabled at t1. When the word line WL1 is enabled, the bit line BL and the first memory cell MC1 can be electrically coupled, and charge sharing between the bit line BL and the memory cell MC1 can be performed. When the data stored in memory cell MC1 is 1, the voltage level of bit line BL may be slightly higher than the bit line precharge voltage VBLP. When the data stored in memory cell MC1 is 0, the voltage level of bit line BL may be slightly lower than the bit line precharge voltage VBLP.

[0049] At t2, the mismatch compensation signal MCS may be disabled, the first input node IN1 may be electrically isolated from the first node ILB, and the second input node IN2 may be electrically isolated from the second node IBL. After the mismatch compensation signal MCS is disabled, the first, second, fourth, and fifth control signals SAP1, SAN1, SPA3, and SAN2 may be disabled. At t3, the bit line switch signal BISO may be enabled. When the bit line switch signal BISO is enabled, the first switch 321 may electrically couple the first input node IN1 to the bit line BL, and the second switch 322 may electrically couple the second input node IN2 to the bit line bar BLB. Therefore, the voltage level of the first input node IN1 may change according to the voltage level of the bit line BL, while the voltage level of the second input node IN2 may change according to the voltage level of the bit line bar BLB. At t3, the driver precharge signal DPCG is enabled, and the sense amplifier control circuit 330 disables the bit line sense amplifier 310 by setting the first power supply terminal RTO and the second power supply terminal SB to the voltage level of the bit line precharge voltage VBLP. At t4, the isolation switch signal ISOB may be enabled. When the isolation switch signal ISOB is enabled, the first input node IN1 may be electrically coupled to the second node IBL, and the second input node IN2 may be electrically coupled to the first node IBLB. At t5, the driver precharge signal DPCG may be disabled, and after the driver precharge signal DPCG is disabled, the first, second, fourth, and fifth control signals SAP1, SAN1, SAP3, and SAN2 may be enabled. When the sense amplifier control circuit 330 provides the first internal voltage V1 to the first power supply terminal RTO and electrically couples the second power supply terminal SB to the ground voltage VSS, the bit line sense amplifier 310 is enabled. The bit line sense amplifier 310 may amplify the voltage levels of the bit line BL and the bit line bar BLB to cause the first node IBLB and the second node IBL to develop to opposite logic levels. At t6, the first and fourth control signals SAP1 and SAP3 may be disabled, the third control signal SAP2 may be enabled, and the voltage levels of the bit line BL, the bit line bar BLB, the first node IBLB, and the second node IBL may continue to develop. When the data stored in the first memory cell MC1 electrically coupled to the bit line BL is 1, the input circuit 311 may lower the voltage level of the first node IBLB to below the voltage level of the second node IBL based on the voltage level of the first input node IN1. Therefore, the latch circuit 312 may drive the second node IBL to a high logic level and the first node IBLB to a low logic level.

[0050] When the precharge signal PCG is received at t7, the word line WL1 may be disabled and the bit line switch signal BISO may be disabled. Subsequently, the second, third, and fifth control signals SAN1, SAP2, and SAN2 may be disabled. In addition, with the bit line precharge signal BLPCG and the mismatch compensation signal MCS enabled, the first input node IN1, the second input node IN2, the first node IBLB, and the second node IBL may be precharged to the bit line precharge voltage VBLP.

[0051] Figure 6A is a timing chart showing the operation of a comparative example of a semiconductor memory device, and Figure 6B is a timing diagram showing the operation of the semiconductor memory device according to the embodiment. Figure 6A and Figure 6B In the timing diagram, the horizontal axis may be time t (eg, seconds), and the vertical axis may be voltage level V. Figure 6A In a comparative example of a semiconductor memory device, the bit line BL' and the input node of the bit line sense amplifier are not electrically isolated, allowing the word line WL to be enabled after the mismatch compensation operation of the bit line sense amplifier has been performed. If the word line is enabled at approximately the same time as the mismatch compensation operation of the bit line sense amplifier begins, the mismatch compensation operation and the amplification operations of the bit line BL' and the bit line bar BLB' cannot proceed normally. This is because the voltage level change caused by the mismatch compensation operation conflicts with the voltage level change caused by charge sharing, making it difficult to define the voltage level of the input node of the bit line sense amplifier. Therefore, the word line WL cannot be enabled until the mismatch compensation operation is completed. When the word line WL is enabled, charge sharing occurs on the bit line BL', and the bit line sense amplifier can amplify the bit line BL' and the bit line bar BLB', resulting in a voltage level difference between the bit line BL' and the bit line bar BLB'.

[0052] See also Figure 3 and Figure 6B, the semiconductor memory device 300 according to the embodiment can electrically isolate the bit line BL and the input node of the bit line sense amplifier 310. Therefore, in one embodiment, the word line WL can be enabled substantially simultaneously with the start of the mismatch compensation operation of the bit line sense amplifier 310. When the word line WL is enabled, charge sharing of the bit line BL is performed, but since the bit line BL and the input node of the bit line sense amplifier 310 are electrically isolated, the mismatch compensation operation can be performed normally regardless of how the voltage level of the bit line BL changes. In one embodiment, when the mismatch compensation operation is completed, the semiconductor memory device 300 can electrically couple the bit line BL to the input node of the bit line sense amplifier 310. In one embodiment, since the charge sharing of the bit line BL has been completed, the bit line sense amplifier 310 can immediately generate a voltage level difference between the bit line BL and the inverted bit line BLB, and the timing of generating the voltage level difference between the bit line BL and the inverted bit line BLB can be earlier than Figure 6A In one embodiment, if the timing at which the voltage level difference between the bit line BL and the bit line bar BLB is generated is accelerated, the timing at which the read and write operations of the semiconductor memory device 300 are performed can be accelerated, and tRCD (RAS to CAS delay), one of the timing specifications of the semiconductor memory device 300, can be reduced, thereby improving the performance of the semiconductor memory device 300. The words "simultaneously" and "simultaneously" used herein with respect to processes mean that the processes occur in overlapping time intervals. For example, if a first process occurs in a first time interval and a second process occurs simultaneously in a second time interval, the first interval and the second interval at least partially overlap with each other so that there is a time when both the first process and the second process occur.

[0053] Figure 7 is a timing chart illustrating the operation of the semiconductor memory device 300 according to the embodiment. Figure 7 Can be shown when not provided Figure 3 The bleeder circuit BD shown is an operation of the semiconductor memory device 300. When the bleeder circuit BD is not provided and the bit line BL is electrically isolated from the bit line sense amplifier 310, a situation may occur in which the bit line BL and the inverted bit line BLB float because the bit line BL and the inverted bit line BLB are difficult to precharge with the bit line precharge voltage VBLP. Therefore, the semiconductor memory device 300 may enable the bit line switch signal BISO for a predetermined time before the mismatch compensation operation is performed and before the word line WL is enabled. When the bit line switch signal BISO is enabled for a predetermined time, the bit line BL and the inverted bit line BLB may be electrically coupled to the first and second input nodes IN1 and IN2 of the bit line sense amplifier 310, and the bit line BL and the inverted bit line BLB may be precharged to the bit line precharge voltage VBLP through the bit line precharge circuit 315. The operation after the activation signal ACT is received may be the same as Figure 5The same as in.

[0054] Figure 8 is a diagram showing a configuration of a semiconductor memory device 400 according to an embodiment. The semiconductor memory device 400 may include a Figure 1 , at least one of the first and second memory cell array blocks 111, 112 shown in FIG. In an embodiment, the semiconductor memory device 400 may include a first unit cell array MA1, a second unit cell array MA2, a bit line sense amplifier array SA, a sub-word line driver SWD, and a bit line switch circuit BLSW. The first and second unit cell arrays MA1, MA2 may include a plurality of bit lines and a plurality of word lines, and a plurality of memory cells may be electrically coupled at points where the plurality of bit lines and the plurality of word lines intersect. For example, the first unit cell array MA1 may include at least a first bit line BL1 and a second bit line BL2, and may include at least a first word line WL1 and a second word line WL2. The second unit cell array MA2 may include at least a first bit line BLB1 and a second bit line BLB2, and may include at least a third word line WLn+1 and a fourth word line WLn+2. n may be an integer of 2 or greater. The semiconductor memory device 400 may have a hierarchical bit line structure. The first bit line BL1 may be electrically coupled to the first word line WL1, and the second bit line BL2 may be electrically coupled to the second word line WL2. The first bit line bar BLB1 can be electrically coupled to the third word line WLn+1, and the second bit line bar BLB2 can be electrically coupled to the fourth word line WLn+2. The first and second unit cell arrays MA1 and MA2 can be arranged with a global bit line GBL and a global bit line bar GBLB. The first and second bit lines BL1 and BL2 can be selectively electrically coupled to the global bit line GBL, and the first and second bit lines bar BLB1 and BLB2 can be selectively electrically coupled to the global bit line bar GBLB. In an embodiment, the number of bit lines electrically coupled to one global bit line can be four or more.

[0055] The bit line sense amplifier array SA may be disposed between the first unit cell array MA1 and the second unit cell array MA2. The bit line sense amplifier array SA may be electrically coupled to the global bit line GBL and the global bit line bar GBLB to perform an amplification operation. The bit line sense amplifier array SA may include a plurality of bit line sense amplifiers. The number of bit line sense amplifiers included in the bit line sense amplifier array SA may vary depending on the number of global bit lines GBL. For example, the bit line sense amplifier array SA may include a bit line sense amplifier BLSA. The bit line sense amplifier BLSA may be electrically coupled to the global bit line GBL and the global bit line bar GBLB to amplify and latch the voltage levels of the global bit line GBL and the global bit line bar GBLB.

[0056] The sub-wordline driver SWD may receive a wordline control signal WCS. Based on the wordline control signal WCS, the sub-wordline driver SWD may enable one of the first to fourth wordlines WL1, WL2, WLn+1, and WLn+2. Based on the wordline control signal WCS, the sub-wordline driver SWD may generate at least a first bitline switch signal BISO1 and a second bitline switch signal BISO2. The sub-wordline driver SWD may delay the wordline control signal WCS to generate the first and second bitline switch signals BISO1 and BISO2. When one of the first and third wordlines WL1 and WLn+1 is enabled by the wordline control signal WCS, the sub-wordline driver SWD may delay the wordline control signal WCS to generate the first bitline switch signal BISO1. When one of the second and fourth wordlines WL2 and WLn+2 is enabled by the wordline control signal WCS, the sub-wordline driver SWD may delay the wordline control signal WCS to generate the second bitline switch signal BISO2. The sub word line driver SWD can generate the first and second bit line switch signals BISO1 and BISO2 by delaying the word line control signal WCS by the time when the mismatch compensation operation of the bit line sense amplifier BLSA is performed. The sub word line driver SWD can provide the first and second bit line switch signals BISO1 and BISO2 to the bit line switch circuit BLSW.

[0057] The bitline switch circuit BLSW can be electrically coupled to the first bitline BL1, the second bitline BL2, the first bitline bar BLB1, the second bitline bar BLB2, the global bitline GBL, and the global bitline bar GBLB, and can receive first and second bitline switch signals BISO1 and BISO2. The bitline switch circuit BLSW can electrically couple the first bitline BL1 and the first bitline bar BLB1 to the global bitline GBL and the global bitline bar GBLB, respectively, based on the first bitline switch signal BISO1. When the first bitline switch signal BISO1 is disabled, the bitline switch circuit BLSW can electrically isolate the first bitline BL1 and the first bitline bar BLB1 from the global bitline GBL and the global bitline bar GBLB, respectively. When the first bitline switch signal BISO1 is enabled, the bitline switch circuit BLSW can electrically couple the first bitline BL1 to the global bitline GBL and the first bitline bar BLB1 to the global bitline bar GBLB. The bit line switch circuit BLSW can electrically couple the second bit line BL2 and the second bit line bar BLB2 to the global bit line GBL and the global bit line bar GBLB, respectively, based on a second bit line switch signal BISO2. When the second bit line switch signal BISO2 is disabled, the bit line switch circuit BLSW can electrically isolate the second bit line BL2 and the second bit line bar BLB2 from the global bit line GBL and the global bit line bar GBLB, respectively. When the second bit line switch signal BISO2 is enabled, the bit line switch circuit BLSW can electrically couple the second bit line BL2 to the global bit line GBL and the second bit line bar BLB2 to the global bit line bar GBLB.

[0058] Figure 9 is a diagram showing a configuration of a semiconductor memory device 500 according to an embodiment. The semiconductor memory device 500 may include a Figure 8 . A configuration of a connection relationship between a bit line sense amplifier BLSA and first and second unit cell arrays MA1 and MA2 of a semiconductor memory device 400 is shown in FIG. In an embodiment, the semiconductor memory device 500 may include a bit line sense amplifier 510 and a bit line switch circuit 520. The bit line sense amplifier 510 may amplify and latch a signal received through a global bit line GBL and a global bit line bar GBLB. The bit line sense amplifier 510 may change the voltage levels of a first node IBLB and a second node IBL based on the signal received through the global bit line GBL and the global bit line bar GBLB. The bit line sense amplifier 510 may change the voltage level of the first node IBLB based on the voltage level of the global bit line GBL, and may change the voltage level of the second node IBL based on the voltage level of the global bit line GBL.

[0059] The bit line switch circuit 520 can receive the first and second bit line switch signals BISO1 and BISO2. The first and second bit line switch signals BISO1 and BISO2 can be generated by Figure 8 . Based on the first and second bit line switch signals BISO1 and BISO2, the bit line switch circuit 520 can electrically couple the first bit line BL1 and the first bit line bar BLB1 or one of the second bit line BL2 and the second bit line bar BLB2 to the global bit line GBL and the global bit line bar GBLB. The bit line switch circuit 520 can electrically couple the first bit line BL1 and the first bit line bar BLB1 to the global bit line GBL and the global bit line bar GBLB, respectively, based on the first bit line switch signal BISO1. When the first bit line switch signal BISO1 is disabled, the bit line switch circuit 520 can electrically isolate the first bit line BL1 from the global bit line GBL and the first bit line bar BLB1 from the global bit line bar GBLB. When the first bit line switch signal BISO1 is enabled, the bit line switch circuit 520 can electrically couple the first bit line BL1 to the global bit line GBL and the first bit line bar BLB1 to the global bit line bar GBLB. The bit line switch circuit 520 can electrically couple the second bit line BL2 and the second bit line bar BLB2 to the global bit line GBL and the global bit line bar GBLB, respectively, based on a second bit line switch signal BISO2. When the second bit line switch signal BISO2 is disabled, the bit line switch circuit 520 can electrically isolate the second bit line BL2 from the global bit line GBL and the second bit line bar BLB2 from the global bit line bar GBLB. When the second bit line switch signal BISO2 is enabled, the bit line switch circuit 520 can electrically couple the second bit line BL2 to the global bit line GBL and the second bit line bar BLB2 to the global bit line bar GBLB.

[0060] The semiconductor memory device 500 may further include a sense amplifier control circuit 530 and a column switch 540. The sense amplifier control circuit 530 and the column switch 540 may have the same Figure 3 The sense amplifier control circuit 330 and the column switch 340 shown in FIG. 3 are substantially the same configuration. Repeated descriptions of the same elements will be omitted. The bit line sense amplifier 510 may include an input circuit 511, a latch circuit 512, an isolation switch circuit 513, and a compensation switch circuit 514. The bit line sense amplifier 510 may also include a bit line precharge circuit 515. The bit line sense amplifier 510 may have the same Figure 3 The bit line sense amplifier 310 shown in FIG has substantially the same configuration except that the first input node IN1 is replaced by the global bit line GBL and the second input node IN2 is replaced by the global bit line bar GBLB. Repeated descriptions of the same elements will be omitted.

[0061] The bit line switch circuit 520 may include a first switch 521, a second switch 522, a third switch 523, and a fourth switch 524. The first switch 521 may receive a first bit line switch signal BISO1 and may electrically couple the first bit line BL1 to the global bit line GBL based on the first bit line switch signal BISO1. The first switch 521 may include a first transistor T51. The first transistor T51 may be an N-channel MOS transistor. The gate of the first transistor T51 may receive the first bit line switch signal BISO1, one of the drain and source of the first transistor T51 may be connected to the first bit line BL1, and the other of the drain and source of the first transistor T51 may be connected to the global bit line GBL. The second switch 522 may receive the first bit line switch signal BISO1 and may connect the first bit line bar BLB1 to the global bit line bar GBLB based on the first bit line switch signal BISO1. The second switch 522 may include a second transistor T52. The second transistor T52 may be an N-channel MOS transistor. The gate of the second transistor T52 may receive the first bit line switch signal BISO1, one of the drain and source of the second transistor T52 may be connected to the first bit line bar BLB1, and the other of the drain and source of the second transistor T52 may be connected to the global bit line bar GBLB. The third switch 523 may receive the second bit line switch signal BISO2 and, based on the second bit line switch signal BISO2, connect the second bit line BL2 to the global bit line GBL. The third switch 523 may include a third transistor T53. The third transistor T53 may be an N-channel MOS transistor. The gate of the third transistor T53 may receive the second bit line switch signal BISO2, one of the drain and source of the third transistor T53 may be connected to the second bit line BL2, and the other of the drain and source of the third transistor T53 may be connected to the global bit line GBL. The fourth switch 524 may receive the second bit line switch signal BISO2 and, based on the second bit line switch signal BISO2, connect the second bit line bar BLB2 to the global bit line bar GBLB. The fourth switch 524 may include a fourth transistor T54. The fourth transistor T54 may be an N-channel MOS transistor. The gate of the fourth transistor T54 may receive the second bit line switch signal BISO2, one of the drain and source of the fourth transistor T54 may be connected to the second bit line bar BLB2, and the other of the drain and source of the fourth transistor T54 may be connected to the global bit line bar GBLB.

[0062] Figure 10 is a timing diagram illustrating the operation of the semiconductor memory device 500 according to the embodiment. Figure 1 、 Figures 8 to 10, an operating method of the semiconductor memory device 500 according to an embodiment will be described as follows. Before t0, the bitline precharge signal BLPCG, the isolation switch signal ISOB, and the mismatch compensation signal MCS may be enabled. The first and second bitline switch signals BISO1 and BISO2 may remain disabled. Therefore, the first node IBLB, the second node IBL, the global bitline GBL, and the global bitline bar GBLB may be precharged with the bitline precharge voltage VBLP. At t0, when the activation signal ACT is received, the bitline precharge signal BLPCG and the isolation switch signal ISOB may be disabled, the global bitline GBL and the second node IBL may be electrically isolated, and the global bitline bar GBLB and the first node IBLB may be electrically isolated. Since the mismatch compensation signal MCS remains enabled, the electrical coupling between the global bitline GBL and the first node IBLB and the electrical coupling between the global bitline bar GBLB and the second node IBL may be maintained. At t1, the first control signal SAP1, the second control signal SAN1, the fourth control signal SAP3, and the fifth control signal SAN2 are enabled, and the sense amplifier control circuit 530 can provide the first internal voltage V1 to the first power supply terminal RTO and electrically couple the second power supply terminal SB to the ground voltage VSS. As power is supplied to the first power supply terminal RTO and the second power supply terminal SB of the bitline sense amplifier 510, the bitline sense amplifier 510 is activated and can perform a mismatch compensation operation. Depending on the threshold voltage mismatch or offset between the transistors of the input circuit 511 and the threshold voltage mismatch or offset between the transistors of the latch circuit 512, the voltage levels of the first input node IN1 and the second input node IN2 can be set differently. In addition, the word line can be enabled at t1. For example, assume that the first word line WL1 is enabled. With the first word line WL1 enabled, the first bit line BL1 can be electrically coupled to the memory cell, and charge sharing can be performed between the first bit line BL1 and the memory cell. When the data stored in the memory cell is 1, the voltage level of the first bit line BL1 may be slightly higher than the bit line precharge voltage VBLP. When the data stored in the memory cell is 0, the voltage level of the first bit line BL1 may be slightly lower than the bit line precharge voltage VBLP.

[0063] At t2, the mismatch compensation signal MCS may be disabled, the global bit line GBL may be electrically isolated from the first node IBLB, and the global bit line bar GBLB may be electrically isolated from the second node IBL. After the mismatch compensation signal MCS is disabled, the first, second, fourth, and fifth control signals SAP1, SAN1, SAP3, and SAN2 may be disabled. At t3, the first bit line switch signal BISO1 may be enabled. The second bit line switch signal BISO2 may remain disabled. When the first bit line switch signal BISO1 is enabled, the first switch 521 may electrically couple the global bit line GBL to the first bit line BL1, and the second switch 522 may electrically couple the global bit line bar GBLB to the first bit line bar BLB1. Therefore, the voltage level of the global bit line GBL may change according to the voltage level of the first bit line bar BL1, and the voltage level of the global bit line bar GBLB may change according to the voltage level of the first bit line bar BLB1. At t3, the driver precharge signal DPCG may be enabled, and the sense amplifier control circuit 530 may disable the bitline sense amplifier 510 by setting the first and second power supply terminals RTO and SB to the voltage level of the bitline precharge voltage VBLP. At t4, the isolation switch signal ISOB may be enabled. When the isolation switch signal ISOB is enabled, the global bitline GBL may be electrically coupled to the second node IBL, and the global bitline bar GBLB may be electrically coupled to the first node IBLB. At t5, the driver precharge signal DPCG may be disabled, and after the driver precharge signal DPCG is disabled, the first, second, fourth, and fifth control signals SAP1, SAN1, SAP3, and SAN2 may be enabled. When the first internal voltage V1 is provided to the first power supply terminal RTO and the second power supply terminal SB is electrically coupled to the ground voltage VSS, the bitline sense amplifier 510 is enabled. The bitline sense amplifier 510 may amplify the voltage levels of the global bitline GBL and the global bitline bar GBLB to cause the first and second nodes IBLB and IBL to develop to opposite logic levels. At t6, the first and fourth control signals SAP1 and SAP3 may be disabled, the third control signal SAP2 may be enabled, and the voltage levels of the global bit line GBL, the global bit line bar GBLB, the first node IBLB, and the second node IBL may continue to develop. When the data stored in the memory cell electrically coupled to the first bit line BL1 is 1, the bit line sense amplifier 510 may lower the voltage level of the first node IBLB below the voltage level of the second node IBL based on the voltage level of the global bit line GBL. As a result, the latch circuit 512 may drive the voltage level of the second node IBL to a high logic level and the voltage level of the first node IBLB to a low logic level.

[0064] When the precharge signal PCG is received at t7, the first word line WL1 may be disabled and the first bit line switch signal BISO1 may be disabled. Subsequently, the second, third, and fifth control signals SAN1, SAP2, and SAN2 may be disabled. In addition, when the bit line precharge signal BLPCG and the mismatch compensation signal MCS are enabled, the global bit line GBL, the global bit line bar GBLB, the first node IBLB, and the second node IBL may be precharged to the bit line precharge voltage VBLP.

[0065] Figure 11 is a timing diagram showing the operation of the semiconductor memory device according to the embodiment. Figure 11 In the timing diagram, the horizontal axis may be time t (eg, seconds), and the vertical axis may be voltage level V. Figure 9 and Figure 11 , the semiconductor memory device 500 can electrically isolate the bit line BL from the global bit line GBL. Therefore, in one embodiment, the word line WL can be enabled substantially simultaneously with the start of the mismatch compensation operation of the bit line sense amplifier 510. When the word line WL is enabled, charge sharing is performed on the bit line BL. However, since the bit line BL and the global bit line GBL are electrically isolated, the mismatch compensation operation can be performed normally regardless of how the voltage level of the bit line BL changes. In one embodiment, when the mismatch compensation operation is completed, the semiconductor memory device 500 can electrically couple the bit line BL and the global bit line GBL. Since charge sharing on the bit line BL has been completed, the voltage level of the global bit line GBL can immediately change according to the voltage level of the bit line BL, and the bit line sense amplifier 510 can generate a voltage level difference between the global bit line GBL and the global bit line bar GBLB. In one embodiment, by accelerating the timing of word line WL being enabled, the timing of generating the voltage level difference between the global bit line GBL and the global bit line bar GBLB can be accelerated. Therefore, in an embodiment, the timing of the semiconductor memory device 500 performing read and write operations can be accelerated, and tRCD (RAS to CAS delay), one of the timing specifications of the semiconductor memory device 500, can be reduced, thereby improving the performance of the semiconductor memory device 500.

[0066] Those skilled in the art will appreciate that the present disclosure can be implemented in other specific forms without changing its technical spirit or basic features. Therefore, it should be understood that the above-described embodiments are illustrative in all respects and not restrictive. The scope of the present disclosure is defined by the following claims, not by the detailed description, and it should be understood that the meaning and scope of the claims and all variations or modifications derived from their equivalents are encompassed within the scope of the present disclosure.

Claims

1. A semiconductor memory device comprising: a sub-word line driver that: receives a word line control signal to enable a word line coupled to a bit line; and delays the word line control signal to generate a bit line switch signal; a bit line sense amplifier that amplifies and latches a signal received through a first input node and a second input node; and The bit line switch circuit electrically couples the bit line to the first input node and electrically couples a bit line bar to the second input node in response to the bit line switch signal.

2. The semiconductor memory device according to claim 1, wherein The sub-word line driver generates the bit line switch signal by delaying the word line control signal by a time when a mismatch compensation operation of the bit line sense amplifier is performed.

3. The semiconductor memory device according to claim 1, wherein The bit line sense amplifier comprises: an input circuit that: changes a voltage level of a first node based on a signal received through the first input node; and changes a voltage level of a second node based on a signal received through the second input node; a latch circuit that: changes the voltage level of the first node and the voltage level of the second node based on the voltage level of the first node and the voltage level of the second node; an isolation switch circuit that: electrically couples the first input node to the second node and electrically couples the second input node to the first node based on an isolation switch signal; and A compensation switch circuit electrically couples the first input node to the first node and the second input node to the second node based on a mismatch compensation signal. 4 . The semiconductor memory device according to claim 3 , further comprising a bit line precharge circuit configured to precharge the second node to a bit line precharge voltage based on a bit line precharge signal.

5. The semiconductor memory device according to claim 1, wherein The bit line switch circuit comprises: a first switch electrically coupling the bit line to the first input node in response to the bit line switch signal; and A second switch electrically couples the bit line bar to the second input node in response to the bit line switch signal.

6. A method for operating a semiconductor memory device, the method comprising: electrically isolating the bit line from a first input node of a bit line sense amplifier and electrically isolating the bit line bar from a second input node of the bit line sense amplifier; performing a mismatch compensation operation with the bit line sense amplifier and enabling a word line to electrically couple a memory cell to the bit line; electrically coupling the first input node to the bit line, and electrically coupling the second input node to the bit line bar; as well as A voltage level difference between a first node and a second node is generated by amplifying a voltage level of the first input node and a voltage level of the second input node.

7. The method according to claim 6, wherein: Performing the mismatch compensation operation includes electrically coupling the first input node to the first node and electrically coupling the second input node to the second node.

8. The method according to claim 6, further comprising: Before enabling the word line, the second node is precharged.

9. The method according to claim 6, further comprising: Before enabling the word line, the bit line is electrically coupled to the first input node and the bit line bar is electrically coupled to the second input node for a predetermined time.

10. The method according to claim 6, further comprising: After electrically coupling the first input node to the bit line and electrically coupling the second input node to the bit line bar, the first input node is electrically coupled to the second node and the second input node is electrically coupled to the first node.

11. A semiconductor memory device comprising: a sub word line driver that: receives a word line control signal and enables one of a first word line coupled to the first bit line and a second word line coupled to the second bit line based on the word line control signal; and delays the word line control signal to generate one of a first bit line switch signal and a second bit line switch signal; a bit line sense amplifier that amplifies and latches a voltage level of a global bit line and a voltage level of a global bit line bar; and A bit line switch circuit, which: electrically couples the first bit line and the first inverted bit line to the global bit line and the global inverted bit line, respectively, in response to the first bit line switch signal; and electrically couples the second bit line and the second inverted bit line to the global bit line and the global inverted bit line, respectively, in response to the second bit line switch signal.

12. The semiconductor memory device according to claim 11, wherein The sub word line driver generates the first and second bit line switch signals by delaying the word line control signal by a time when a mismatch compensation operation of the bit line sense amplifier is performed.

13. The semiconductor memory device according to claim 11, wherein The bit line sense amplifier comprises: an input circuit that: changes a voltage level of a first node based on a voltage level of the global bit line, and changes a voltage level of a second node based on a voltage level of the global bit line bar; a latch circuit that: changes a voltage level of the first node and a voltage level of the second node based on a voltage level of the first node and a voltage level of the second node; an isolation switch circuit that: electrically couples the global bit line to the second node and electrically couples the global bit line bar to the first node based on an isolation switch signal; and A compensation switch circuit electrically couples the global bit line to the first node and the global bit line bar to the second node based on a mismatch compensation signal. 14 . The semiconductor memory device according to claim 13 , further comprising a bit line precharge circuit configured to precharge the second node to a bit line precharge voltage based on a bit line precharge signal.

15. The semiconductor memory device according to claim 11, wherein The bit line switch circuit comprises: a first switch electrically coupling the first bit line to the global bit line in response to the first bit line switch signal; a second switch electrically coupling the first bit line bar to the global bit line bar in response to the first bit line switch signal; a third switch electrically coupling the second bit line to the global bit line in response to the second bit line switch signal; and A fourth switch electrically couples the second bit line bar to the global bit line bar in response to the second bit line switch signal.

16. A method for operating a semiconductor memory device, the method comprising: electrically isolating the first bit line and the second bit line from the global bit line, and electrically isolating the first bit line bar and the second bit line bar from the global bit line bar; performing a mismatch compensation operation using a bit line sense amplifier; enabling one of a first word line and a second word line to electrically couple one of the first bit line and the second bit line to a memory cell; electrically coupling the bit line electrically coupled to the enabled word line among the first bit line and the second bit line to the global bit line; as well as A voltage level difference between the first node and the second node is generated by amplifying a voltage level of the global bit line and a voltage level of the global bit line bar.

17. The method according to claim 16, wherein Performing the mismatch compensation operation includes electrically coupling the global bit line to the first node and electrically coupling the global bit line bar to the second node.

18. The method according to claim 16, further comprising: Before enabling one of the first word line and the second word line, the second node is precharged.

19. The method according to claim 16, further comprising: After electrically coupling the global bit line and the bit line electrically coupled to the enabled word line, the global bit line is electrically coupled to the second node, and the global bit line bar is electrically coupled to the first node.

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