Storage system

Abstract

The invention relates to a storage system. The storage system includes: a normal storage area suitable for storing normal data; a secure storage area adapted to store secure data; a first row hammer detection circuit adapted to sample and count partial rows activated in the normal memory area to select a first row that needs to be refreshed; and a second row hammer detection circuit adapted to count all rows activated in the secure storage area to select a second row that needs to be refreshed.

Description

[0001] This application is a divisional application of the Chinese invention patent application with application number 202111482681.6, application date December 7, 2021, and name "Storage System".

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS

[0003] This application claims priority to U.S. Provisional Patent Application No. 63 / 123,703, filed on December 10, 2020, and Korean Patent Application No. 10-2021-0154680, filed on November 11, 2021, the entire contents of which are incorporated herein by reference. Technical Field

[0004] Various embodiments of the present invention relate to a storage system. Background Art

[0005] As the integration density of a memory increases, the spacing between a plurality of word lines included in the memory decreases. As the spacing between word lines decreases, the coupling effect between adjacent word lines increases.

[0006] Furthermore, each time data is input to or output from a memory cell, a word line switches between an active state and an inactive state. As the coupling effect between adjacent word lines increases, data stored in a memory cell coupled to a word line adjacent to a frequently activated word line may be damaged (i.e., lost). This phenomenon is known as "word line disturb" or "row hammering." The concern is that the data in a memory cell may be damaged due to row hammering before the memory cell is refreshed.

[0007] Figure 1 It is a schematic diagram used to describe hammering.

[0008] exist Figure 1 In the figure, "WLL" represents a word line that has been activated too many times (i.e., excessively), and "WLL-1" and "WLL+1" represent word lines arranged adjacent to the word line "WLL". In addition, "CL" represents a memory cell coupled to the excessively activated word line "WLL", and "CL-1" and "CL+1" respectively represent memory cells coupled to the adjacent word lines "WLL-1" and "WLL+1". Each memory cell includes a cell transistor TL, TL-1, or TL+1 and a cell capacitor CAPL, CAPL-1, or CAPL+1. In addition, "BL0" and "BL1" represent bit lines.

[0009] When word line "WLL" is activated or deactivated, the voltage levels of adjacent word lines "WLL-1" and "WLL+1" may increase or decrease due to the coupling effect between the overactivated word line "WLL" and the adjacent word lines "WLL-1" and "WLL+1", thereby affecting the amount of charge stored in cell capacitors CL-1 and CL+1. Therefore, the more word line "WLL" switches between the activated state and the inactivated state, the greater the change in the amount of charge stored in the cell capacitors CAPL-1 and CAPL+1 of the adjacent memory cells "CL-1" and "CL+1", resulting in degradation of the data stored in the memory cells.

[0010] Furthermore, electromagnetic waves generated when a word line switches between active and inactive states may destroy data by charging or discharging electrons into or from cell capacitors of memory cells coupled to adjacent word lines.

[0011] In order to solve the row hammering problem, a method of detecting a row (ie, a word line) that has been activated multiple times and refreshing adjacent rows of the row that has been activated multiple times is mainly used. Summary of the Invention

[0012] Embodiments of the present invention are directed to improving the ability to protect storage systems from row hammering attacks.

[0013] According to one embodiment of the present invention, a storage system includes: a normal storage area, which is suitable for storing normal data; a security storage area, which is suitable for storing security data; a first row hammer detection circuit, which is suitable for sampling some rows that are activated in the normal storage area and counting the number of activations of the sampled rows to select a first row to be refreshed among the sampled rows; and a second row hammer detection circuit, which is suitable for counting the number of activations of all rows in the security storage area to select a second row to be refreshed.

[0014] According to another embodiment of the present invention, a storage system includes: a memory, which includes a normal area suitable for storing normal data and a security area suitable for storing security data; and a host, which includes: an error correction code storage area, which is suitable for storing error correction codes corresponding to the security data; and an error correction circuit, which is suitable for correcting errors in data read from the security area based on the error correction codes stored in the error correction code storage area.

[0015] According to another embodiment of the present invention, a storage system includes: a normal storage area, which is suitable for storing normal data; a secure storage area, which is suitable for storing secure data; and a processor, which includes a cache memory, wherein the processor is only allowed to access the secure storage area via the cache memory.

[0016] According to another embodiment of the present invention, a storage system includes: a normal storage area, which is suitable for storing normal data; a secure storage area, which is suitable for storing secure data; a first row hammer detection circuit, which is suitable for sampling part of the rows activated in the normal storage area and counting the number of activations of the sampled rows to select a first row to be refreshed; and a second row hammer detection circuit, which is suitable for counting the number of activations of all rows in the secure storage area to select a second row to be refreshed; a cache memory, which is suitable for storing error correction codes corresponding to the secure data; and an error correction circuit, which is suitable for correcting errors in data read from the secure area based on the error correction codes stored in the cache memory.

[0017] According to another embodiment of the present invention, a storage system includes: a memory, which includes: a normal area, which is suitable for storing normal data; a security area, which is suitable for storing security data; and a first row hammer detection circuit, which is suitable for counting the number of activations of rows in the normal area in a random row counting manner to detect rows to be refreshed; and a processor, which includes: a second row hammer detection circuit, which is suitable for counting the number of activations of rows in the security area in a full row counting manner to detect rows to be refreshed. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a schematic diagram used to describe hammering.

[0019] Figure 2 is a block diagram illustrating a storage system according to one embodiment of the present invention.

[0020] Figure 3 is a diagram showing an embodiment of the present invention Figure 2 Detailed block diagram of the memory shown in .

[0021] Figure 4 is a diagram showing an embodiment of the present invention Figure 2 A detailed block diagram of the memory controller is shown in .

[0022] Figure 5 is a diagram showing an embodiment of the present invention Figure 2 . A table showing an example of counting results stored in the last-level cache memory is shown in FIG. DETAILED DESCRIPTION

[0023] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. However, the present invention may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to make this disclosure thorough and complete and to fully convey the scope of the invention to those skilled in the art. Throughout this disclosure, in the various figures and embodiments of the present invention, like reference numerals refer to like parts.

[0024] Figure 2 is a block diagram illustrating a storage system 200 according to one embodiment of the present invention.

[0025] refer to Figure 2 , the storage system 200 may include a processor 210 and a memory 250 .

[0026] The processor 210 may include a processor core 211, a cache controller 213, different levels of cache memory 215, 217, and 219, and a memory controller 221. The components included in the processor 210 may communicate via a memory bus 223. The processor 210 may be an entity that processes data or signals. Examples of the processor 210 may include a microprocessor, a central processing unit (CPU), a graphics processing unit (GPU), an application processor (AP), a digital signal processor (DSP), and the like.

[0027] Processor core 211 may include circuitry that processes instructions for a computing system. Processor core 211 may be a single core or multiple cores. Processor core 211 may use different levels of cache memory 215, 217, and 219 to access data stored in memory 250.

[0028] Cache memories 215, 217, and 219 can be divided into several levels. The lower the cache level, the faster the operation speed may be, but the cache memory capacity may be reduced. The cache controller 213 can manage the cache memories 215, 217, and 219 and determine whether to obtain data for the processor core 211 from one of the cache memories 215, 217, and 219 or from the memory 250. The processor core 211 can preferentially obtain the required data from the cache memories 215, 217, and 219. If the required data is not cached in the cache memories 215, 217, and 219, the processor core 211 can obtain the required data from the memory 250 via the memory controller 221.

[0029] The memory controller 221 may control the operation of the memory 250. The processor 210 may access the memory 250 via the memory controller 221. That is, the processor 210 may write data to the memory 250 and read data stored in the memory 250 via the memory controller 221. The memory controller 221 may transmit commands / addresses CA to the memory 250 to control the operation of the memory 250 and may transmit and receive data DATA to and from the memory 250.

[0030] Here, although the memory controller 221 is shown herein as being included in the processor 210, it is obvious to those skilled in the art that the memory controller 221 may exist outside the processor 210. A device including the memory controller 221 in the memory system 200 is generally referred to as a host. Figure 2 In the embodiment, the processor 210 may be a host.

[0031] Memory 250 can perform operations instructed by memory controller 221. Memory 250 can be a type of random access memory such as dynamic random access memory (DRAM), static RAM (SRAM), phase change RAM (PCRAM), magnetic RAM (MRAM), resistive RAM (ReRAM), etc. It can also be another type of memory that requires a refresh operation. For example, memory 250 can be a memory in which data may be lost due to row hammering.

[0032] Figure 3 is a diagram showing an embodiment of the present invention Figure 2 A detailed block diagram of the memory 250 is shown in FIG.

[0033] refer to Figure 3 , the memory 250 may include a control circuit 310 , a first-row hammer detection circuit 320 , and a cell array 330 .

[0034] The control circuit 310 may control the overall operation of the memory 250. The control circuit 310 may control the internal constituent elements of the memory 250 so that the memory may perform operations indicated by the command / address CA, such as an activation operation, a precharge operation, a read operation, a write operation, and a refresh operation.

[0035] The cell array 330 may include a plurality of memory cells arranged in a plurality of rows and a plurality of columns. The cell array 330 may include a normal area 331 and a security area 333. The normal area 331 may be a memory cell area (i.e., a storage area or memory area) for storing general data, and the security area 333 may be a memory cell area for storing security-critical data. Since the normal area 331 and the security area 333 are used to distinguish between different policies applied thereto, the normal area 331 and the security area 333 may be distinguished by address. For example, when the number of rows of the cell array is N+1, the normal area 331 may range from row 0 to row K, while the security area 333 may range from row K+1 to row N. Since the security area 333 may only store a portion of security-critical data, the size of the security area 333 may be much smaller than the size of the normal area 331. For example, the size of the normal area 331 may be tens to thousands of times the size of the security area 333.

[0036] The first row hammer detection circuit 320 can select rows to be refreshed by sampling some of the activated rows in the cell array 330 and counting the number of activations of the sampled rows. Specifically, there may be numerous activated rows in the cell array 330, and the first row hammer detection circuit 320 can detect over-activated rows by randomly sampling some of the numerous activated rows in the cell array 330 and counting the number of activations of the sampled rows. Furthermore, neighboring rows of the over-activated rows (i.e., rows that may have lost data due to row hammering) can be classified as rows to be refreshed.

[0037] The first row hammer detection circuit 320 does not count the number of activations of all activated rows in the cell array 330, but only counts the number of activations of some sampled rows. This is because it is difficult for the first row hammer detection circuit 320 to count the number of activations of all activated rows in the cell array 330, and implementing such a circuit is too cumbersome in terms of area and current consumption. Rows classified as needing to be refreshed by the first row hammer detection circuit 320 can be refreshed preferentially or additionally during normal refresh operations, or can be refreshed when a command (e.g., a refresh management command) is applied.

[0038] The memory controller 221 may classify rows in the security area 333 of the cell array 330 that may lose data due to row hammering as rows to be refreshed. Therefore, the first row hammering detection circuit 320 may exclude the security area 333 from management targets and select rows to be refreshed by sampling only a portion of activated rows in the normal area 231 to count the number of activations of the sampled rows.

[0039] Figure 4is a diagram showing an embodiment of the present invention Figure 2 A detailed block diagram of the memory controller 221 is shown in FIG.

[0040] refer to Figure 4 The memory controller 221 may include a host interface 401 , a scheduler 403 , a command generator 405 , a second row hammer detection circuit 407 , an error correction circuit (ECC) 409 , and a memory interface 411 .

[0041] The host interface 401 may be used for an interface between the memory controller 221 and other components of the processor 210. The memory controller 221 may be coupled to the memory bus 223 through the host interface 401.

[0042] The scheduler 403 can schedule operations of the memory 250. The scheduler 403 can determine the order of requests to be directed to the memory 250, which are sent through the memory bus 223. To improve performance, when operations corresponding to the requests are directed to the memory 250, the scheduler 403 can change the order of the requests received through the memory bus 223. For example, even if a read operation of the memory 250 is first requested and then a write operation is requested through the memory bus 223, the order of the operations can be changed so that the write operation of the memory 250 is performed before the read operation.

[0043] The command generator 405 may generate commands to be applied to the memory 250 according to the order of operations determined by the scheduler 403 .

[0044] The memory interface 411 may be used for an interface between the memory controller 221 and the memory 250. Commands / addresses CA may be transmitted from the memory controller 221 to the memory 250 through the memory interface 411, and data DATA may be transmitted / received. The memory interface 411 may also be referred to as a physical layer (PHY) interface.

[0045] The second row hammer detection circuit 407 can select a row that needs to be refreshed by counting the number of activations of all activated rows in the security area 333 of the memory 250. The second row hammer detection circuit 407 can detect overactivated rows by counting the number of activations of all activated rows in the security area. Furthermore, neighboring rows of overactivated rows (i.e., rows that may have lost data due to row hammering) can also be classified as rows that need to be refreshed. Since the activation operation of the memory 250 is performed according to a command of the memory controller 221, the second row hammer detection circuit 407 of the memory controller 221 can detect which row in the security area 333 of the memory 250 is activated. For rows classified as to be refreshed by the second row hammer detection circuit 407, the memory controller 221 can command the memory 250 to perform an activation operation or a refresh operation, which can also prevent data loss. Therefore, data loss corresponding to the rows to be refreshed can be prevented.

[0046] Since the second-row hammer detection circuit 407 counts the number of activations for all rows of the security area 333 using a full-row count, this operation may be very burdensome. However, since the size of the security area 333 is relatively small, this operation is possible. The second-row hammer detection circuit 407 requires a storage circuit for counting, and one of the cache memories 215, 217, and 219 of the processor 210 can be used as the storage circuit for storing the counting results. Since the last-level cache memory 219 has the largest capacity among the cache memories 215, 217, and 219, it is desirable for the second-row hammer detection circuit 407 to use the cache memory 219 as the storage circuit. Furthermore, a storage circuit for storing the counting results can be provided in the second-row hammer detection circuit 407. Figure 5 FIG2 shows an example of the counting result stored in the last level cache memory 219. Figure 5 , it can be seen that the number of activations is counted for each row of the security area 333. The last level cache memory 219 may have a lowest level.

[0047] The error correction circuit 409 may be a circuit for performing error correction on the security area 333. During a write operation to the security area 333, the error correction circuit 409 may generate an error correction code for correcting errors in the write data, and store the error correction code in one of the cache memories 215, 217, and 219 (i.e., an error correction code storage area). It may be desirable to store the error correction code in the last-level cache memory 219 among the cache memories 215, 217, and 219. During a read operation from the security area 333, the error correction circuit 409 may correct errors in the data read from the security area 333 based on the error correction code stored in the cache memory 219. That is, during a write operation, the error correction circuit 409 may store an error correction code for correcting errors in data stored in the security area 333 in the cache memory 219, and during a read operation, the error correction circuit 409 may correct errors in data read from the security area 333 based on the error correction code stored in the cache memory 219.

[0048] The storage system 200 can protect the security data stored in the security area 333 by distinguishing the normal area 331 from the security area 333 in the following three aspects.

[0049] 1. Count of activated rows

[0050] The number of activations of rows activated in the normal region 331 can be counted by the first row hammer detection circuit 320 using a random row counting method. This counting method is often less reliable because not all activated rows are counted, but rather only some rows are randomly selected and counted. The reliability of this method for selecting rows from row hammer attacks in the normal region 331 may not be 100%.

[0051] On the other hand, the number of activations of rows activated in the security area 333 can be counted by the second row hammer detection circuit 407 using a full row count. Since all rows activated in the security area 333 are counted, the row attacked by row hammering can be selected with almost 100% confidence. Therefore, data stored in the security area 333 can be more protected than data stored in the normal area 331.

[0052] 2. Error Correction Method

[0053] The error correction circuit 409 can perform error correction operations only on data stored in the security area 333. Therefore, the data stored in the security area 333 can be more protected than the data stored in the normal area 331. Although an additional error correction circuit can be provided in the storage system 200 in addition to the error correction circuit 409, the error correction circuit can protect the data stored in the security area 333 and the data stored in the normal area 331. Therefore, the fact that the data stored in the security area 333 is more protected than the data stored in the normal area 331 does not change.

[0054] 3. Access Method

[0055] The memory 250 is generally accessible via the cache memories 215, 217, and 219. That is, the processor core 211 does not directly access the memory 250 to obtain data, but instead sends data from the memory 250 to the cache memories 215, 217, and 219. The processor core 211 can access the cache memories 215, 217, and 219 to obtain data. Exceptionally, when the processor core 211 needs to directly access the memory 250 due to a cache flush or other circumstances, the processor core 211 can directly access the memory 250.

[0056] Direct access to memory 250 and indirect access to memory 250 via these cache memories 215, 217 and 219 can be controlled by a cache controller 213, which allows the processor core 211 to directly access the normal area 331 of memory 250, but prohibits the processor core 211 from directly accessing the security area 333 of memory 250.

[0057] If processor core 211 were allowed to directly access memory 250, memory 250 would be vulnerable to hacker attacks. However, because cache controller 213 prohibits processor core 211 from directly accessing secure area 333 of memory 250, secure area 333 is less vulnerable to attacks. In short, data stored in secure area 333 can be protected.

[0058] According to embodiments of the present invention, the ability to protect a storage system from row hammer attacks can be improved.

[0059] Effects expected to be obtained by the embodiments of the present invention are not limited to the above-mentioned effects, and those skilled in the art to which the present invention pertains can also clearly understand other effects not mentioned above from the description.

[0060] Although the present invention has been described with respect to specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the present invention as defined in the appended claims. Furthermore, these embodiments may be combined to form additional embodiments.

Claims

1. A storage system comprising: a memory comprising a normal area adapted to store normal data and a secure area adapted to store secure data; as well as A host, comprising: an error correction code storage area, wherein the error correction code storage area is suitable for storing an error correction code corresponding to the security data; as well as An error correction circuit is adapted to correct errors in data read from the security area based on the error correction code stored in the error correction code storage area.

2. The storage system according to claim 1, wherein: The host comprises a processor, Wherein, the processor includes different levels of cache memory, and The error correction code storage area is included in a cache memory among the cache memories of different levels.

3. The storage system according to claim 2, wherein: The processor includes a memory controller, and the memory controller includes the error correction circuit.

4. The storage system according to claim 2, wherein: The error correction code storage area is included in a last-level cache memory among the different levels of cache memories.

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