Memory device

Abstract

A memory device includes: a memory cell array connected to a plurality of word lines; and a row hammer protector including processing circuitry configured to activate a count for each of the plurality of word lines based on an adjacent word line activation count for each of the plurality of word lines during a first bank refresh period, an additional refresh operation is probabilistically performed for each of the plurality of word lines within a second bank refresh period following the first bank refresh period.

Description

TECHNICAL FIELD

[0001] Example embodiments of the inventive concept relate to semiconductor memory devices. More specifically, example embodiments of the inventive concept relate to a memory device capable of resisting row hammering. BACKGROUND

[0002] A volatile memory device such as a dynamic random access memory (DRAM) can store data in the form of electric charges charged in a storage cell. The electric charges charged in the storage cell of the volatile memory device can leak due to various reasons. Accordingly, the DRAM can perform a refresh operation to recharge the electric charges stored in the storage cell.

[0003] Recently, according to a trend of higher integration of the volatile memory device, a gap between a plurality of word lines controlling the storage cell is gradually being reduced. Accordingly, when one word line is activated, a coupling phenomenon in which an amount of electric charges stored in a storage cell connected to a word line adjacent thereto is unintentionally changed can occur. In particular, when a word line (e.g., an aggressor word line) adjacent to a specific word line (e.g., a victim word line) is repeatedly activated for a short period of time, a probability that data stored in a storage cell connected to the victim word line is corrupted can increase. The corruption of the data stored in the storage cell connected to the victim word line in this manner can be referred to as row hammering or row hammering attack. SUMMARY

[0004] Example embodiments of the inventive concept aim to address the above technical objects. For example, some example embodiments of the inventive concept provide a memory device capable of resisting row hammering.

[0005] According to some example embodiments of the inventive concept, a memory device can include a storage cell array connected to a plurality of word lines, and a row hammering protector including processing circuitry configured to probabilistically perform an additional refresh operation for each of the plurality of word lines within a second bank refresh period following a first bank refresh period based on an adjacent word line activation count for each of the plurality of word lines during the first bank refresh period.

[0006] According to some example embodiments of inventive concepts, a memory device configured to operate in response to control from an external device can include an array of memory cells connected to a plurality of word lines, and processing circuitry configured to: generate a first count value by counting a number of activation commands received from the external device for a second word line and a third word line adjacent to a first word line among the plurality of word lines between a first time point at which a first bank refresh command is received from the external device and a second time point at which a second bank refresh command is received from the external device, determine a first probability corresponding to the first count value, and issue a first row refresh command for the first word line according to the first probability at a fourth time point between the second time point and a third time point at which a third bank refresh command is received from the external device.

[0007] A memory device configured to receive first and second bank refresh commands from an external device at first and second time points, respectively, can include an array of memory cells connected to first and second aggressor word lines and a sacrificial word line located between the first and second aggressor word lines, and processing circuitry configured to probabilistically issue a row refresh command for the sacrificial word line after a predetermined time interval elapses from the second time point and before a third bank refresh command is received based on a number of activation commands received for the first and second aggressor word lines between the first and second time points. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 is a block diagram illustrating a memory system according to some example embodiments.

[0009] Figure 2 is a block diagram of a memory device of Figure 1 in more detail.

[0010] Figure 3 is a block diagram of an array of memory cells of Figure 2 in more detail.

[0011] Figure 4 is a timing diagram illustrating an operation of the memory device of Figure 2 according to some example embodiments.

[0012] Figure 5 is a block diagram of a row hammer protector of Figure 2 according to some example embodiments in more detail.

[0013] Figure 6To show in more detail Figure 5 A block diagram showing the configuration of the line hammer protection circuit.

[0014] Figure 7 It is shown Figure 5 Plotting the global probability table.

[0015] Figure 8 It is a graph showing the relationship between the probability of issuing a refresh command and the count value.

[0016] Figure 9 This is a timing diagram illustrating the operation of a storage device according to some example embodiments.

[0017] Figure 10 and Figure 11 To show in more detail Figure 9 A time series diagram of a portion of a time period.

[0018] Figure 12 This is a timing diagram illustrating the operation of a storage device according to some example embodiments.

[0019] Figure 13 This is a more detailed illustration based on some example embodiments. Figure 2 Block diagram of the hammer impact protector.

[0020] Figure 14 This illustrates some example embodiments. Figure 13 A plot showing the relationship between the local probability table and the global probability table.

[0021] Figure 15 This illustrates an update based on some example embodiments. Figure 13 The method of plotting local probability tables.

[0022] Figure 16 This is a more detailed illustration based on some example embodiments. Figure 2 Block diagram of the hammer impact protector.

[0023] Figure 17 and Figure 18 This illustrates some example embodiments. Figure 16 Plotting the relationship between the adjusted weight table and the local probability table.

[0024] Figure 19 and Figure 20 It shows the basis Figure 18 Timing diagrams of the operation of storage devices in some example embodiments.

[0025] Figure 21 This illustrates some example embodiments. Figure 2 The timing diagram of the operation of the hammer protection circuit.

[0026] Figure 22 This shows the storage devices in more detail. Figure 21 Timing diagram of operations during the extended memory refresh period. Detailed Implementation

[0027] In the following description, some exemplary embodiments will be described in detail and clearly to enable those skilled in the art to readily implement the inventive concept. Details such as components and structures described in the specification are provided only to aid in a comprehensive understanding of some exemplary embodiments. Therefore, it will be clear to those skilled in the art that various changes and modifications can be made to the exemplary embodiments described herein without departing from the scope and spirit of the inventive concept. Furthermore, for clarity and brevity, descriptions of well-known functions and structures have been omitted. In the accompanying drawings or in the detailed description, components may be connected to any other components besides those illustrated in the drawings or described in the detailed description. The following terms are defined in consideration of function and are not limited to specific functions. The definitions of the terms should be determined based on the entire contents of the specification.

[0028] The components described in the detailed description using terms such as "driver," "controller," and "block" can be implemented using software, hardware, or a combination thereof. For example, software can be machine code, firmware, embedded code, and / or application software. Hardware can include circuits, electronic circuits, processors, microprocessors, computers, integrated circuit cores, pressure sensors, inertial sensors, microelectromechanical systems (MEMS), passive components, and / or combinations thereof.

[0029] Figure 1 This is a block diagram illustrating a memory system according to some example embodiments of the inventive concept. Reference Figure 1 The memory system MS may include a memory controller 10 and / or a memory device 100 as a host device.

[0030] In some example embodiments, the memory controller 10 may be included in one of various types of processors such as a central processing unit (CPU), a graphics processing unit (GPU), and / or the like.

[0031] For the sake of brevity, it is assumed below that storage device 100 is dynamic random access memory (DRAM), and that memory controller 10 and storage device 100 communicate with each other via a low-power double data rate (LPDDR) interface. However, the example embodiment is not limited to this. For example, memory controller 10 and storage device 100 may communicate with each other via a low-power double data rate (LPDDR) interface.

[0032] The memory controller 10 can store data DATA in the memory device 100, or read data DATA from the memory device 100. For example, the memory controller 10 can control the memory device 100 by transmitting various types of commands CMD and / or addresses ADDR to the memory device 100 based on the command / address signal C / A. That is, the memory controller 10 can control the memory device 100 by issuing various types of commands CMD and / or addresses ADDR in the form of command / address signal C / A.

[0033] The storage device 100 may include multiple storage cells. These multiple storage cells may be connected to multiple word lines and / or multiple bit lines.

[0034] In some example embodiments, storage device 100 may correspond to a memory bank. However, the example embodiments are not limited thereto.

[0035] Storage device 100 may include a row hammer protector (RH protector) 170. The row hammer protector 170 can determine whether there is a possibility that data stored in storage device 100 is likely to be damaged due to a row hammer. When there is a possibility that data stored in storage device 100 is likely to be damaged due to a row hammer, the row hammer protector 170 can perform an additional refresh operation to protect the data stored in storage device 100. The detailed configuration and operation of the row hammer protector 170 will be described in detail below with reference to the accompanying drawings.

[0036] Figure 2 To show in more detail Figure 1 A block diagram of the storage device. (See reference) Figure 2 The storage device 100 may include a command / address decoder (C / A decoder) 110, a memory cell array 120, a row decoder 130, a sense amplifier 140, an input / output circuit (I / O circuit) 150, a control logic circuit 160 and / or a row hammer protector 170.

[0037] Command / address decoder 110 can receive command / address signals C / A provided by memory controller 10. Command / address decoder 110 can decode command / address signals C / A into command CMD and / or address ADDR.

[0038] The command CMD can include various types of commands, such as read commands, write commands, activation commands, and / or memory refresh commands. The address ADDR can include memory address, row address, and / or column address. However, the example embodiment is not limited to this, and the command / address signal C / A can represent many more types of commands and / or addresses.

[0039] The memory cell array 120 may include a plurality of memory cells arranged along the row and column directions. These memory cells may be connected to a plurality of word lines WL extending in the row direction and / or a plurality of bit lines BL extending in the column direction. For example, the memory cell array 120 may be connected to first word lines WL1 through nth word lines WLn.

[0040] The line decoder 130 can control multiple word lines WL. For example, the line decoder 130 can activate one of the multiple word lines WL based on the line address.

[0041] The sense amplifier 140 can be connected to the memory cell array 120 via multiple bit lines BL. The sense amplifier 140 can temporarily store data provided from the memory cell array 120. For example, the sense amplifier 140 can temporarily store data stored in a memory cell connected to an active word line.

[0042] In some example embodiments, the sense amplifier 140 can recover data provided from the memory cell array 120. For example, in response to control by the control logic circuit 160, the sense amplifier 140 can recover data in a memory cell connected to an active word line.

[0043] I / O circuit 150 can receive data DATA from memory controller 10 and / or can transmit data DATA to memory controller 10. For example, I / O circuit 150 can write data DATA received from memory controller 10 into memory cell array 120 through sense amplifier 140, and / or can output data DATA stored in sense amplifier 140 to memory controller 10.

[0044] The control logic circuit 160 can receive commands CMD and / or addresses ADDR from the command / address decoder 110. The control logic circuit 160 can control the overall operation of the storage device 100 based on the commands CMD and / or addresses ADDR.

[0045] In some example embodiments, in response to a memory refresh command, control logic circuitry 160 can control row decoder 130 and / or sense amplifier 140 such that all memory cells in memory cell array 120 are refreshed.

[0046] In some example embodiments, in response to an activation command, control logic 160 may provide row address corresponding to the activation command to row decoder 130. In this case, row decoder 130 may activate the word line corresponding to the row address.

[0047] The horizontal hammer protector 170 can receive command CMD and / or address ADDR from command / address decoder 110. For example, the horizontal hammer protector 170 can receive the same command CMD and / or the same address ADDR as provided to control logic circuitry 160. For a more concise description, in Figure 2 The diagram illustrates some example embodiments in which the command / address decoder 110 provides both command CMD and address ADDR to each of the line hammer protector 170 and the control logic circuitry 160; however, the example embodiments are not limited thereto. For instance, the line hammer protector 170 may receive command CMD and / or address ADDR from the control logic circuitry 160, and / or may obtain command CMD and / or address ADDR by sniffing the command CMD and / or address ADDR provided to the control logic circuitry 160.

[0048] Row hammer protector 170 can determine word lines connected to memory cells storing data highly susceptible to damage from row hammer attacks based on commands CMD and / or addresses ADDR. For example, after the last bank refresh command is provided from memory controller 10, row hammer protector 170 can monitor the number of "adjacent word line activations" for each or one or more word lines from the first word line WL1 to the nth word line WLn. More specifically, for each or one or more word lines from the first word line WL1 to the nth word line WLn, row hammer protector 170 can monitor the number of activation commands for adjacent word lines issued from memory controller 10. Row hammer protector 170 can identify word lines corresponding to a large number of adjacent word line activations as word lines connected to memory cells storing data highly susceptible to damage from row hammer attacks.

[0049] Row hammer protector 170 can perform refresh operations on word lines connected to memory cells storing data that is highly susceptible to damage from row hammering. For example, row hammer protector 170 can issue an additional refresh command CMD_AREF to one or more word lines connected to memory cells storing data that is highly susceptible to damage from row hammering. Row hammer protector 170 can provide the additional refresh command CMD_AREF to control logic circuitry 160.

[0050] Control logic circuit 160 can receive an additional refresh command CMD_AREF. In this case, control logic circuit 160 can control row decoder 130 and / or sense amplifier 140 to refresh memory cells storing data that is highly likely to be damaged by row hammering. For example, control logic circuit 160 can control row decoder 130 and can sequentially activate one or more word lines. Control logic circuit 160 can control sense amplifier 140 and can recover data in memory cells connected to the activated word lines.

[0051] Figure 3 To show in more detail Figure 2 A block diagram of a storage cell array. (See reference) Figures 1 to 3 The storage cell array 120 may include multiple storage cells MC. The multiple storage cells MC can form a matrix structure arranged along the row and column directions. In the following text, for the sake of simplicity, storage cells arranged in the same row of the storage cell array 120 will be referred to as a "storage cell row".

[0052] Multiple memory cells (MCs) can be connected to multiple word lines (WLs). For a more concise description, as an example, Figure 3 The illustration shows adjacent first word lines WL1 to third word lines WL3 and the memory cells connected thereto, but the example embodiment is not limited thereto. For example, the example embodiment is not limited to the number of word lines and the number of memory cells.

[0053] Multiple memory cells (MCs) can be connected to multiple bit lines (BLs). For example, multiple memory cells (MCs) can be connected to bit line BL1 through bit line BLm.

[0054] Each or one or more of the multiple memory cells MC can be a DRAM cell. For example, each or one or more of the multiple memory cells MC can include a transistor TR and / or a capacitor CAP, and data can be stored based on the amount of charge stored in the capacitor CAP.

[0055] The amount of charge in each or more memory cells (MCs) stored in a plurality of memory cells can unintentionally change as word lines connected to another adjacent memory cell are activated. For example, as first word line WL1 and third word line WL3 are activated, the amount of charge in the memory cell MC connected to second word line WL2 increases or decreases. In particular, even if the memory cell connected to second word line WL2 is not refreshed, the amount of charge in the memory cell MC connected to second word line WL2 can increase or decrease significantly when first word line WL1 and third word line WL3 are repeatedly activated. In this case, the data represented by the memory cell MC connected to second word line WL2 will be corrupted.

[0056] In the following text, for the sake of brevity, the word line connected to the memory cell whose charge has been unintentionally altered will be referred to as the sacrificial word line WL_VCT, and the word lines adjacent to the sacrificial word line WL_VCT will be referred to as the first attack word line WL_AGGRa and the second attack word line WL_AGGRb, respectively. For example, see reference... Figure 3The second word line WL2 can be the sacrificial word line WL_VCT, while the first word line WL1 and the third word line WL3 can be called the first attack word line WL_AGGRa and the second attack word line WL_AGGRb, respectively.

[0057] For the sake of brevity, it is assumed in the following text that the word line immediately adjacent to the sacrificial word line WL_VCT is the attacking word line WL_AGGR. However, the example embodiments are not limited to this, and word lines separated from the sacrificial word line WL_VCT by one or more word lines can also be the attacking word line WL_AGGR of the sacrificial word line WL_VCT. For example, the first word line WL1 can be the attacking word line relative to the third word line WL3, and / or the third word line WL3 can be the attacking word line relative to the first word line WL1. That is, the example embodiments are not limited to the spacing between the sacrificial word line WL_VCT and the attacking word line WL_AGGR.

[0058] In some example embodiments, although attack word lines WL_AGGRa and WL_AGGRb are repeatedly activated, the probability of data corruption in the memory cell MC connected to the sacrifice word line WL_VCT is reduced or minimized when the memory cell MC connected to the sacrifice word line WL_VCT is refreshed more frequently (e.g., when the memory cell MC connected to the sacrifice word line WL_VCT is additionally refreshed). In this way, the row hammer protector 170 can perform additional refresh operations on the sacrifice word line WL_VCT, thereby reducing or minimizing the probability of data corruption in the memory cell MC connected to the sacrifice word line WL_VCT.

[0059] Figure 4 This illustrates some example embodiments. Figure 2 Timing diagrams for the operation of the memory devices. (Reference) Figures 1 to 4 At a first time point t1, storage device 100 may perform a memory refresh operation. For example, storage device 100 may perform a memory refresh operation in response to a memory refresh command provided from memory controller 10. In this case, all memory cells included in the memory cell array 120 may be refreshed. Similarly, at a second time point t2 following the first time point t1, storage device 100 may perform a memory refresh operation. In the following text, for the sake of brevity, the time period between the first time point t1 and the second time point t2 may be referred to as the first memory refresh period P1_REF.

[0060] However, during the first memory refresh period P1_REF, the storage device 100 may repeatedly perform the attack word line WL_AGGR activation operation. For example, during the first memory refresh period P1_REF, the storage device 100 may activate the first attack word line WL_AGGRa and / or the second attack word line WL_AGGRb a total of 'k' times.

[0061] The probability of data corruption in memory cells connected to the sacrificial word line WL_VCT can vary depending on the value of 'k'. For example, a large 'k' value may indicate a high probability of data corruption in memory cells connected to the sacrificial word line WL_VCT, while a small 'k' value may indicate a low probability of data corruption in memory cells connected to the sacrificial word line WL_VCT.

[0062] In some example embodiments, during the first memory bank refresh period P1_REF, the row hammer protector 170 may perform an additional refresh operation on the sacrificial word line WL_VCT. That is, between the first time point t1 and the second time point t2, the row hammer protector 170 may additionally refresh the memory cell MC connected to the sacrificial word line WL_VCT. In this case, even if the 'k' value is large, the probability of data corruption in the memory cell connected to the sacrificial word line WL_VCT during the first memory bank refresh period P1_REF can be reduced or minimized. The method in which the row hammer protector 170 additionally refreshes the memory cell MC connected to the sacrificial word line WL_VCT will be described in detail below with reference to the accompanying drawings.

[0063] In some example embodiments, the row hammer protector 170 may perform additional refresh operations on the sacrifice word line WL_VCT within the first memory refresh period P1_REF based on the number of times the attack word line WL_AGGR is activated during the 0th memory refresh period P0_REF prior to the first memory refresh period P1_REF. For example, the row hammer protector 170 may perform additional refresh operations on each of the first word lines WL1 to the nth word lines WLn within the first memory refresh period P1_REF based on the number of times adjacent word lines corresponding to each of the first word lines WL1 to the nth word lines WLn are activated during the 0th memory refresh period P0_REF. Similarly, the row hammer protector 170 can perform additional refresh operations on each or more word lines from the first word line WL1 to the nth word line WLn during the second memory refresh period P2_REF, based on the number of times adjacent word lines corresponding to each or more word lines from the first word line WL1 to the nth word line WLn are activated during the first memory refresh period P1_REF. In other words, across multiple memory refresh periods, the row hammer protector 170 can perform additional refresh operations on each or more word lines from the first word line WL1 to the nth word line WLn based on the number of times adjacent word lines corresponding to each or more word lines from the first word line WL1 to the nth word line WLn are activated during the previous memory refresh period.

[0064] Figure 5 This is a more detailed illustration based on some example embodiments. Figure 2 A block diagram of a horizontal hammer protection device. The horizontal hammer protection device 170 may include multiple horizontal hammer protection circuits 171, a probability memory 172, a timer 173, and / or an additional refresh circuit 174. Referring below... Figures 1 to 5 As an example, some example embodiments in which the line hammer protector 170 performs additional refresh operations on the sacrificial word line WL_VCT during the first memory refresh period P1_REF will be described in detail.

[0065] Multiple row hammer protection circuits 171 may include a first row hammer protection circuit 171_1 to an nth row hammer protection circuit 171_n. The first row hammer protection circuit 171_1 to an nth row hammer protection circuit 171_n may correspond to the first word line WL1 to the nth word line WLn, respectively.

[0066] The first row hammer protection circuit 171_1 to the nth row hammer protection circuit 171_n can perform row hammer protection operations for different word lines. For example, the first row hammer protection circuit 171_1 can resist row hammer attacks on the first word line WL1; and the second row hammer protection circuit 171_2 can resist row hammer attacks on the second word line WL2. Similarly, the third row hammer protection circuit 171_3 to the nth row hammer protection circuit 171_n can respectively resist row hammer attacks on the third word line WL3 to the nth word line WLn. In other words, in the case where the corresponding word line is the sacrificial word line WL_VCT, the first row hammer protection circuit 171_1 to the nth row hammer protection circuit 171_n can respectively resist row hammer attacks on the first word line WL1 to the nth word line WLn.

[0067] For example, the first row hammer protection circuit 171_1 to the nth row hammer protection circuit 171_n can generate first count values ​​CV1 to nth count values ​​CVn respectively by counting the number of times adjacent word lines are activated for the first word line WL1 to the nth word line WLn. For example, the second row hammer protection circuit 171_2 can generate a second count value CV2 by counting the number of times activation commands are received for word lines adjacent to the second word line WL2 (e.g., the first word line WL1 and the third word line WL3) during the 0th memory refresh period P0_REF.

[0068] The probability memory 172 can store a global probability table (GPT) comprising multiple probabilities corresponding to multiple counting ranges, respectively. (Refer to below.) Figure 7 A more detailed description of the configuration of the Global Probability Table (GPT) is provided.

[0069] Each or more of the first row of hammer impact protection circuits 171_1 to the nth row of hammer impact protection circuits 171_n can identify the probability corresponding to the count value CV from a plurality of probabilities included in the global probability table GPT. For example, the second row of hammer impact protection circuits 171_2 can identify the probability corresponding to the second count value CV2 based on the global probability table GPT.

[0070] Timer 173 can measure the length of time elapsed since the memory controller 10 provides the memory refresh command. When a predetermined or given time has elapsed since the memory controller 10 provides the memory refresh command, timer 173 can provide a trigger signal TS to each or one or more of the plurality of row hammer protection circuits 171. For example, after a predetermined or given time has elapsed from the first time point t1, timer 173 can provide a trigger signal TS to each or one or more of the first row hammer protection circuit 171_1 to the nth row hammer protection circuit 171_n.

[0071] In response to the trigger signal TS, the first row hammer protection circuit 171_1 to the nth row hammer protection circuit 171_n can issue a row refresh command CMD_RREF for the corresponding word line based on the probability determined by the global probability table GPT. For example, the second row hammer protection circuit 171_2 can issue a row refresh command CMD_RREF probabilistically for the second word line WL2 in response to the trigger signal TS. In this way, the first row hammer protection circuit 171_1 to the nth row hammer protection circuit 171_n can issue a row refresh command CMD_RREF probabilistically for the first word line WL1 to the nth word line WLn, respectively.

[0072] Additional refresh circuit 174 can receive one or more row refresh commands CMD_RREF from the first row hammer protection circuit 171_1 to the nth row hammer protection circuit 171_n. Additional refresh circuit 174 can issue additional refresh command CMD_AREF based on one or more row refresh commands CMD_RREF. Additional refresh circuit 174 can provide additional refresh command CMD_AREF to control logic circuit 160. In this case, control logic circuit 160 can sequentially perform additional refresh operations for one or more word lines. (Referring below) Figure 10 and Figure 11 The method in which the control logic circuit 160 sequentially performs additional refresh operations for one or more word lines is described in more detail.

[0073] In some example embodiments, the command sequence of the additional refresh command CMD_AREF may include one or more row refresh commands CMD_RREF provided in the additional refresh circuit 174. In this case, the additional refresh circuit 174 may include a command queue storing one or more row refresh commands CMD_RREF.

[0074] Figure 6 To show in more detail Figure 5 A block diagram of the configuration of the line hammer protection circuit. For the sake of brevity, refer to [reference needed] below. Figures 1 to 6 As an example, the configuration and operation of the second row hammer impact protection circuit 171_2 will be described in detail. However, the example embodiment is not limited thereto, and each of the first row hammer impact protection circuits 171_1 to the nth row hammer impact protection circuits 171_n can be configured in a similar manner.

[0075] The second-row hammer protection circuit 171_2 may include a counting circuit CNT, a probability determination circuit PDC, a probability buffer circuit PBC, and / or a command issuing circuit CIC.

[0076] The counting circuit CNT can generate a second count value CV2 by counting the number of activation commands received from the memory controller 10 for the attack word line WL_AGGR (e.g., the first word line WL1 and / or the third word line WL3) during the 0th memory refresh period P0_REF. For example, the counting circuit CNT can accumulate the second count value CV2 until a first time point t1 (e.g., the time point at which the memory refresh command is received from the memory controller 10) at the end of the 0th memory refresh period P0_REF.

[0077] The probability determination circuit (PDC) can determine the probability corresponding to the second count value CV2 based on the global probability table (GPT). For example, the probability determination circuit (PDC) can look up the probability corresponding to the second count value CV2 from the global probability table (GPT).

[0078] The probability buffer circuit PBC can store the probabilities determined by the probability determination circuit PDC. The probability buffer circuit PBC can store the probabilities determined by the probability determination circuit PDC until the trigger signal TS is received.

[0079] In response to the trigger signal TS, the command issuing circuit CIC can issue a line refresh command CMD_RREF for the second word line WL2 based on the probability stored in the probability buffer circuit PBC. For example, depending on the probability stored in the probability buffer circuit PBC, the command issuing circuit CIC may or may not issue a line refresh command CMD_RREF and an address for the second word line WL2.

[0080] In other words, according to some example embodiments, based on the count value of the activation commands received for the first word line WL1 and the third word line WL3 during the first memory refresh period P0_REF, the second row hammer protection circuit 171_2 can determine whether to perform an additional refresh operation for the second word line WL2 during the first memory refresh period P1_REF.

[0081] In some example embodiments, across multiple memory bank refresh periods, the second row hammer protection circuit 171_2 can determine whether to perform an additional refresh operation on the second word line WL2 in a subsequent memory bank refresh period, based on the number of times adjacent word lines for the second word line WL2 are activated during a previous memory bank refresh period. For example, even during the first memory bank refresh period P1_REF, the counting circuit CNT can generate a second count value CV2 in a similar manner as described above. In this case, the second row hammer protection circuit 171_2 can determine whether to perform an additional refresh operation on the second word line WL2 during the second memory bank refresh period P2_REF based on the second count value CV2. Reference will be made below. Figure 12 A more detailed description of the operation of the row hammer protector 170 across multiple memory bank refresh periods.

[0082] Figure 7 It is shown Figure 5 A plot of the global probability table. (See reference) Figures 1 to 7 The Global Probability Table (GPT) can include probabilities P0 to P12, corresponding to hammer threat levels L0 in row 0 to L12 in row 12, respectively. For a more concise description, as an example, Figure 7 The illustration shows the Global Probability Table (GPT) storing 13 rows of hammer threat levels and their corresponding 13 probabilities. However, the example embodiment is not limited to the number of rows of hammer threat levels and / or probabilities included in the Global Probability Table (GPT).

[0083] Each of the hammer threat levels L0 in row 0 to L12 in row 12 can correspond to a different counting range. In this case, the counting ranges corresponding to hammer threat levels L0 in row 0 to L12 in row 12 can be consecutive to each other and may not overlap. For example, hammer threat level L0 in row 0 can correspond to a counting range of "0 to B0", while hammer threat level L1 in row 1 can correspond to a counting range of "B0+1 to B1". In this way, hammer threat level L11 in row 11 can correspond to a counting range of "B10+1 to B11". Hammer threat level L12 in row 12 can correspond to a counting range of "B11+1 and above".

[0084] The upper limit of the count range corresponding to the hammer threat levels L0 in row 0 to L11 in row 11 can be B0 to B11, respectively. B0 to B11 can be integers greater than or equal to 0 and can form an increasing sequence. For example, B1 can be an integer greater than B0, and B2 can be an integer greater than B1. In this case, the count range corresponding to the hammer threat level L1 in the first row can be higher than the count range corresponding to the hammer threat level L0 in row 0, and the count range corresponding to the hammer threat level L2 in the second row can be higher than the count range corresponding to the hammer threat level L1 in the first row.

[0085] Each or more probability determination circuits in the probability determination circuits PDC of the first row hammer protection circuit 171_1 to the nth row hammer protection circuit 171_n can identify the probability corresponding to the count value CV from the global probability table GPT. For example, when the second count value CV2 is "B3", the probability determination circuit PDC included in the second row hammer protection circuit 171_2 can identify a third probability P3 corresponding to the count range including "B3". In this case, the second row hammer protection circuit 171_2 can determine the identified third probability P3 as the probability of issuing a row refresh command CMD_RREF for the second word line WL2 during the first memory refresh period P1_REF. In the following, for the sake of simplicity, the operation of the second row hammer protection circuit 171_2 will be described in detail as an example. However, the example embodiment is not limited thereto, and the probability of issuing the row refresh command CMD_RREF can also be determined based on the global probability table GPT.

[0086] In some example embodiments, each or more of the first row hammer protection circuits 171_1 to the nth row hammer protection circuits 171_n may share the Global Probability Table (GPT). That is, each or more of the first row hammer protection circuits 171_1 to the nth row hammer protection circuits 171_n may determine the probability of issuing a row refresh command CMD_RREF for the corresponding word line based on the Global Probability Table (GPT).

[0087] The probabilities P0 to P12, from 0 to 1, can be integers greater than or equal to 0 and less than or equal to 1, and can form an increasing sequence. For example, P1 can be a real number greater than or equal to P0, and P2 can be a real number greater than or equal to P1. Therefore, according to some exemplary embodiments of the inventive concept, as the count value CV increases, each of the first row hammer protection circuit 171_1 to the nth row hammer protection circuit 171_n can issue the row refresh command CMD_RREF with a higher probability. In other words, as the count value CV increases, the probability corresponding to the corresponding count value CV can gradually increase. Reference will be made below. Figure 8 The relationship between the counter value CV and the probability of issuing the line refresh command CMD_RREF is described in more detail.

[0088] According to some example embodiments, the counting ranges corresponding to hammer threat levels L0 in row 0 to L12 in row 12 can be divided into multiple segments. For example, the counting range corresponding to hammer threat level L0 in row 0 can be included in the no-response segment SEC_NR; the counting range corresponding to hammer threat levels L1 in row 1 to L7 in row 7 can be included in the rapidly increasing segment SEC_SHP; the counting range corresponding to hammer threat levels L8 in row 8 to L11 in row 11 can be included in the gradually increasing segment SEC_GRD; and the counting range corresponding to hammer threat level L12 in row 12 can be included in the specific response segment SEC_CR.

[0089] When the count range corresponding to the count value CV is included in the non-response segment SEC_NR, the second row hammer protection circuit 171_2 may not issue the row refresh command CMD_RREF during the first memory refresh period P1_REF. For example, the 0th probability P0 can be 0.

[0090] When the counting range corresponding to the count value CV is included in the rapidly increasing segment SEC_SHP, as the count value CV increases, the probability of the second row hammer protection circuit 171_2 issuing the row refresh command CMD_RREF during the first memory refresh period P1_REF will increase rapidly.

[0091] In some example embodiments, the probabilities corresponding to the range of counts included in the rapidly increasing segment SEC_SHP (e.g., first probability P1 to seventh probability P7) may be logarithmic relative to the upper limit of the range of counts included in the rapidly increasing segment SEC_SHP (e.g., B1 to B7).

[0092] When the counting range corresponding to the count value CV is included in the gradually increasing segment SEC_GRD, as the count value CV increases, the probability of the second row hammer protection circuit 171_2 issuing the row refresh command CMD_RREF during the first memory refresh period P1_REF can gradually (e.g., gently) increase.

[0093] In some example embodiments, the probabilities corresponding to the range of counts included in the progressively increasing segment SEC_GRD (e.g., the eighth probability P8 to the eleventh probability P11) may be linear with respect to the upper limit of the range of counts included in the progressively increasing segment SEC_GRD (e.g., B8 to B11).

[0094] When the count range corresponding to the count value CV is included in the specific response segment SEC_CR, the second row hammer protection circuit 171_2 can explicitly issue a row refresh command CMD_RREF within the first memory refresh period P1_REF. For example, the twelfth probability P12 can be 1.

[0095] For a more concise description, as an example, Figure 7 The illustration shows some example embodiments in which the counting range corresponding to hammer threat level L0 in row 0 to hammer threat level L12 in row 12 is divided into 4 segments (also referred to herein as the first to the fourth segments), but the example embodiments are not limited thereto.

[0096] In some example embodiments, B0 to B11 and probabilities P0 to P12 of 0th probability can be generated based on the 4th-order Runge-Kutta algorithm. However, the example embodiments are not limited to specific methods for determining B0 to B11 and probabilities P0 to P12 of 0th probability.

[0097] In some example embodiments, the intervals from B0 to B11 can form an increasing sequence. For example, the interval between Bi and Bi+1 can be greater than or equal to the interval between the limit value Bi and Bi-1 (where "i" is an integer greater than or equal to 1). In this case, the size of the count range included in the gradually increasing segment SEC_GRD can be greater than or equal to the size of the count range included in the sharply increasing segment SEC_SHP. However, the example embodiments are not limited to this.

[0098] In some example embodiments, the differences between the 0th probability P0 and the twelfth probability P12 can form a decreasing sequence. For example, the interval between the i-th probability Pi and the (i+1)-th probability Pi+1 can be less than or equal to the interval between the i-th probability Pi and the (i-1)-th probability Pi-1 (where "i" is an integer greater than or equal to 1). However, the example embodiments are not limited to this.

[0099] Figure 8 It is a graph showing the relationship between the probability of issuing a refresh command and the count value. Figures 1 to 8 The horizontal axis can represent the magnitude of the count value CV, and the vertical axis can represent the probability that the command issuing circuit CIC issues the row refresh command CMD_RREF.

[0100] refer to Figure 8 The global probability table GPT, with probabilities P0 to P11 from 0th to 11th and their corresponding upper limits for the counting range (e.g., B0 to B11), can be... Figure 9The values ​​are represented as points. For example, the upper limit of the counting range corresponding to the hammer threat level L0 in row 0 (e.g., B0) and the 0th probability P0 can be represented as point PT0; the upper limit of the counting range corresponding to the hammer threat level L1 in row 1 (e.g., B1) and the first probability P1 can be represented as point PT1. In this way, the upper limit of the counting range corresponding to the hammer threat levels L0 in row 0 to L11 in row 11, and the 0th probability P0 to the 11th probability P11, can be represented as points PT0 to PT11, respectively.

[0101] When the count value CV corresponds to the unresponsive segment SEC_NR, the probability that the second row hammer protection circuit 171_2 issues the row refresh command CMD_RREF can be 0.

[0102] In other words, even if the count value CV increases as the memory controller 10 generates activation for a specific word line for normal operation of the memory device 100, the row hammer protector 170 will not perform an additional refresh operation for it. For example, even if the memory device 100 activates a word line adjacent to the second word line WL2 for normal operation and thus the second count value CV2 increases, the second row hammer protection circuit 171_2 may not issue a row refresh command CMD_RREF for the second word line WL2. That is, according to some example embodiments of the inventive concept, the operating delay and power consumption of the memory device 100 that may occur due to the row hammer protector 170 unnecessarily performing additional refresh operations can be reduced or minimized.

[0103] When the count value CV corresponds to the rapidly increasing segment SEC_SHP, the probability that the second row hammer protection circuit 171_2 will issue a row refresh command CMD_RREF can increase rapidly according to the count value CV. In the following description, for the sake of brevity, it is assumed that points 0 to 7 (PT7) included in the rapidly increasing segment SEC_SHP are illustrated using a logarithmic graph. However, the example embodiment is not limited to this. For example, points 0 to 7 (PT7) can be illustrated by any type of function graph, such as a polynomial function, a logarithmic function, an exponential function, and / or similar functions.

[0104] In other words, according to some exemplary embodiments of the inventive concept, since the probability of the second row hammer protection circuit 171_2 issuing the row refresh command CMD_RREF increases sharply according to the count value CV in the sharply increasing segment SEC_SHP, the second row hammer protection circuit 171_2 can operate more sensitively to the possibility that adjacent word row activation against the second word line WL2 has been performed due to a row hammer attack. Therefore, according to some exemplary embodiments of the inventive concept, the probability of the second row hammer protection circuit 171_2 resisting a row hammer attack can be increased or maximized.

[0105] When the count value CV corresponds to the gradually increasing segment SEC_GRD, the probability that the second row hammer protection circuit 171_2 will issue a row refresh command CMD_RREF can gradually increase according to the count value CV. In the following description, for the sake of simplicity, it is assumed that points 8 to 11, including the gradually increasing segment SEC_GRD, are illustrated in a line graph. However, the example embodiment is not limited to this. For example, points 8 to 11 can be illustrated by any type of function graph, such as a polynomial function, a logarithmic function, an exponential function, and / or similar functions.

[0106] In other words, according to some exemplary embodiments of the inventive concept, since the probability of the second row hammer protection circuit 171_2 issuing the row refresh command CMD_RREF gradually increases according to the count value CV in the gradually increasing segment SEC_GRD, the second row hammer protection circuit 171_2 can operate more delicately due to the possibility that an adjacent word row activation against the second word line WL2 has already been performed due to a row hammer attack. Therefore, according to some exemplary embodiments of the inventive concept, the probability of performing unnecessary additional refresh operations against the second word line WL2 when the memory device 100 is operating normally can be reduced or minimized. In other words, according to some exemplary embodiments of the inventive concept, the "false positive rate" of the second row hammer protection circuit 171_2 can be reduced or minimized.

[0107] In some example embodiments, the slopes between points in the progressively increasing segment SEC_GRD can be the same. For example, the slope between point PT8 (eighth point) and point PT9 (ninth point) can be the same as the slope between point PT10 (tenth point) and point PT11 (eleventh point).

[0108] In some example embodiments, the rate of change of probability relative to count value CV in the sharply increasing segment SEC_SHP can be greater than the rate of change of probability relative to count value CV in the gradually increasing segment SEC_GRD. For example, the slope between point 0 PT0 and point 7 PT7 can be greater than the slope between point 8 PT8 and point 11 PT11.

[0109] When the count value CV corresponds to a specific response segment SEC_CR, the probability that the second row hammer protection circuit 171_2 issues a row refresh command CMD_RREF can be 1. That is, when the affirmative memory controller 10 is performing a row hammer attack, the second row hammer protection circuit 171_2 can issue a row refresh command CMD_RREF for the second word line WL2. Therefore, according to some exemplary embodiments of the inventive concept, when the affirmative memory controller 10 is performing a row hammer attack, the second row hammer protection circuit 171_2 can reduce or prevent damage to the data stored in the second word line WL2 by performing an additional refresh operation for the second word line WL2.

[0110] Figures 1 to 9 This is a timing diagram illustrating the operation of a storage device according to some example embodiments. Reference Figure 10 The storage device 100 can receive the storage refresh command BREF and the storage address BA at time point 0, time point t1, and / or time point t2. The storage device 100 can perform a storage refresh operation at time point 0, time point t1, and / or time point t2 in response to the storage refresh command BREF.

[0111] During the 0th memory refresh period P0_REF between time point 0 and time point t1, memory device 100 may receive multiple activation commands ACT. In this case, row hammer protector 170 may count the number of times adjacent word lines are activated for each of the multiple word lines WL, based on the row address RA received along with the multiple activation commands ACT. For example, the first row hammer protector circuit 171_1 to the nth row hammer protector circuit 171_n may generate first count values ​​CV1 to nth count values ​​CVn by counting the number of times the activation commands ACT are received for adjacent word lines for each of the first word lines WL1 to the nth word lines WLn, respectively. For a more specific example, each or one or more of the counting circuits CNT of the first row hammer protector circuit 171_1 to the nth row hammer protector circuit 171_n may count the number of times the activation commands ACT are received along with the row address RA for the word lines adjacent to the corresponding word lines.

[0112] After the first time point t1, each or more probability determination circuits in the probability determination circuits PDC of the first row hammer protection circuit 171_1 to the nth row hammer protection circuit 171_n can identify the probability corresponding to the count value CV based on the global probability table GPT. For example, from multiple probabilities included in the global probability table GPT, each or more probability determination circuits in the probability determination circuits PDC of the first row hammer protection circuit 171_1 to the nth row hammer protection circuit 171_n can identify the probability corresponding to the count range including the count value CV. Each or more probability determination circuits in the probability determination circuits PDC of the first row hammer protection circuit 171_1 to the nth row hammer protection circuit 171_n can store the identified probability in the probability buffer circuit PBC. That is, the probability buffer circuit PBC of the first row hammer protection circuit 171_1 to the nth row hammer protection circuit 171_n can store the additional refresh probabilities of the first word line WL1 to the nth word line WLn respectively.

[0113] During the first memory refresh period P1_REF between the first time point t1 and the second time point t2, the row hammer protector 170 can issue an additional refresh command CMD_AREF. For example, the row hammer protector 170 can provide the additional refresh command CMD_AREF to the control logic circuit 160 at the third time point t3 within the first memory refresh period P1_REF. In this case, the memory device 100 can perform an additional refresh operation between the third time point t3 and the fourth time point t4 in response to the additional refresh command CMD_AREF.

[0114] More specifically, timer 173 can generate a trigger signal TS at a third time point t3 after a predetermined or given time length has elapsed since the first time point t1. In response to the trigger signal TS, the command issuing circuit CIC of each or more of the first row hammer protection circuits 171_1 to the nth row hammer protection circuits 171_n can issue a row refresh command CMD_RREF based on the probability stored in the probability buffer circuit PBC included therein. The additional refresh circuit 174 can generate an additional refresh command CMD_AREF based on one or more row refresh commands CMD_RREF provided from the plurality of row hammer protection circuits 171. The storage device 100 can perform an additional refresh operation based on the additional refresh command CMD_AREF.

[0115] In other words, according to some example embodiments of the inventive concept, during the first memory refresh period P1_REF, an additional refresh can be performed with high probability for word lines with a large number of adjacent word lines active during the 0th memory refresh period P0_REF.

[0116] Figure 11 and Figure 9 To show in more detail Figure 10 A time series diagram of a portion of the time period. This will be referenced in the following text. Figure 11 Some example embodiments in which the storage device 100 performs additional refresh operations in Target Line Refresh (TRR) mode are described; and reference will be made to Figures 1 to 10 Some example embodiments are described in which the storage device 100 performs additional refresh operations on multiple word lines based on multiple row refresh commands CMD_RREF.

[0117] First, refer to Figure 9 The storage device 100 can perform an additional refresh operation between the third time point t3 and the fourth time point t4 in response to the additional refresh command CMD_AREF.

[0118] The TRRE mode entry command and / or one or more row refresh commands CMD_RREF can be included in the command sequence of the additional refresh command CMD_AREF. In the following, for the sake of brevity, as examples, some exemplary embodiments in which a first row refresh command CMD_RREFa and / or a second row refresh command CMD_RREFb are included in the command sequence of the additional refresh command CMD_AREF will be described in detail. However, the exemplary embodiments are not limited to the number of row refresh commands included in the command sequence of the additional refresh command CMD_AREF.

[0119] The additional refresh circuit 174 can issue a TRR mode entry command TRRE and a memory bank address BA corresponding to the memory cell array 120 at a third time point t3. In this case, the memory device 100 can enter TRR mode for the memory bank address BA.

[0120] In some example embodiments, the TRR mode enter command TRRE can be implemented as a mode register write (MRW) command. However, the example embodiments are not limited to this.

[0121] The additional refresh circuit 174 can issue a first refresh command CMD_RREFa at a fifth time point t5, following the third time point t3. The first refresh command CMD_RREFa may include an activation command ACT for the first sacrificial word line WL_VCTa and / or a precharge command PRE for the memory cell array 120. In this case, the memory device 100 can refresh the memory cells connected to the first sacrificial word line WL_VCTa based on the activation command ACT for WL_VCTa.

[0122] In some example embodiments, the additional refresh circuit 174 may issue a row address RA_VCTa for the first sacrificial word line WL_VCTa and an activation command ACT for the first sacrificial word line WL_VCTa. The additional refresh circuit 174 may issue a bank address BA corresponding to the memory cell array 120 and a precharge command PRE for the memory cell array 120.

[0123] Subsequently, the additional refresh circuit 174 can issue a second refresh command CMD_RREFb at a sixth time point t6, following the fifth time point t5. The second refresh command CMD_RREFb may include an activation command ACT for the second sacrificial word line WL_VCTb and / or a precharge command PRE for the memory cell array 120. In this case, the memory device 100 can refresh the memory cells connected to the second sacrificial word line WL_VCTb based on the activation command ACT for WL_VCTb.

[0124] In this way, the storage device 100 can enter TRR mode and can sequentially perform additional refresh operations for multiple word lines.

[0125] In some example embodiments, the first sacrificial word line WL_VCTa and the second sacrificial word line WL_VCTb can be different word lines.

[0126] In some example embodiments, the first row refresh command CMD_RREFa and the second row refresh command CMD_RREFb may correspond to two different row refresh commands issued from the first row hammer protection circuit 171_1 to the nth row hammer protection circuit 171_n, respectively.

[0127] The additional refresh circuit 174 can issue all or one or more row refresh commands CMD_RREF provided by the first row hammer protection circuit 171_1 to the nth row hammer protection circuit 171_n, and then issue a TRR mode termination command TRRX. In this case, the storage device 100 can enter an idle state from TRR mode.

[0128] For a more concise description, as an example, Figures 1 to 9 The illustrations show some example embodiments in which the additional refresh circuit 174 issues a TRR mode termination command TRRX, but the example embodiments are not limited thereto. For example, the storage device 100 may perform a row refresh operation corresponding to a predetermined or given number of word lines and then return to an idle state on its own, and / or may return to an idle state after a predetermined time has elapsed since entering TRR mode.

[0129] refer to Figure 11 and Figure 10The storage device 100 can perform an additional refresh operation between the third time point t3 and the fourth time point t4 in response to the additional refresh command CMD_AREF. The following will focus on the reference... Figure 12 Differences in some example embodiments described.

[0130] One or more row refresh commands CMD_RREF may be included in the command sequence of the additional refresh command CMD_AREF. For example, the first row refresh command CMD_RREFa and / or the second row refresh command CMD_RREFb may be included in the command sequence of the additional refresh command CMD_AREF. However, the example embodiment is not limited to the number of row refresh commands included in the command sequence of the additional refresh command CMD_AREF.

[0131] The supplementary refresh circuit 174 can issue a first refresh command CMD_RREFa at a third time point t3. The supplementary refresh circuit 174 can issue a second refresh command CMD_RREFb at a seventh time point t7 after the third time point t3. That is, the supplementary refresh circuit 174 can perform the supplementary refresh operation without entering TRR mode. Each or more of the first refresh command CMD_RREFa and / or the second refresh command CMD_RREFb may include an activation command CMD and a precharge command PRE.

[0132] In some example embodiments, the additional refresh circuit 174 may issue an activation command ACT for the first sacrificial word line WL_VCTa, including the row address RA_VCTa and / or the bank address BA. The additional refresh circuit 174 may also issue an activation command ACT for the second sacrificial word line WL_VCTb, including the row address RA_VCTb and / or the bank address BA.

[0133] Figures 1 to 12 This is a timing diagram illustrating the operation of a storage device according to some example embodiments. Reference Figure 13 The storage device 100 can perform a memory refresh operation from a first time point ta to a fourth time point td. In the following text, the time period between the first time point ta and the second time point tb can be referred to as the first memory refresh period Pa_REF; the time period between the second time point tb and the third time point tc can be referred to as the second memory refresh period Pb_REF; and the time period between the third time point tc and the fourth time point td can be referred to as the third memory refresh period Pc_REF.

[0134] The storage device 100 may determine whether to perform an additional refresh operation for each or one or more word lines in the multiple word lines WL during the first memory refresh period Pa_REF based on the number of times adjacent word lines are activated for each or one or more word lines in the multiple word lines WL.

[0135] The row hammer protector 170 can generate a first count value CV1 to an nth count value CVn based on the number of times adjacent word lines of each or one or more word lines in the plurality of word lines WL are activated during the first memory refresh period Pa_REF. At a subsequent second time point tb, the row hammer protector 170 can determine an additional refresh probability for each or one or more word lines in the plurality of word lines WL based on the first count value CV1 to the nth count value CVn. After a predetermined or given time has elapsed from the second time point tb, based on the determined probability, the row hammer protector 170 can issue an additional refresh command for each or one or more word lines in the plurality of word lines WL.

[0136] Similarly, storage device 100 may determine whether to perform an additional refresh operation for each or one or more word lines in the multiple word lines WL during the third memory refresh period Pc_REF based on the number of times adjacent word lines are activated for each or one or more word lines in the multiple word lines WL during the second memory refresh period Pb_REF. Storage device 100 may also determine whether to perform an additional refresh operation for each or one or more word lines in the multiple word lines WL during the third memory refresh period Pc_REF based on the number of times adjacent word lines are activated for each or one or more word lines in the multiple word lines WL.

[0137] In this way, across multiple memory bank refresh periods, based on the number of times adjacent word lines are activated for each or more word lines in the multiple word lines WL during the previous memory bank refresh period, the storage device 100 can probabilistically perform additional refresh operations for each or more word lines in the multiple word lines WL during subsequent memory bank refresh periods. In this case, even if the storage device 100 is subjected to a hammer attack across multiple memory bank refresh periods, the probability of increasing or ensuring the integrity of the data stored in the storage device 100 is increased.

[0138] Figure 2 This is a more detailed illustration based on some example embodiments. Figures 1 to 4 Block diagram of a hammer impact protector. (Reference) Figure 13 and Figure 2 , Figure 5The row hammer strike protector 170 can be implemented as the row hammer strike protector 270.

[0139] The horizontal hammer protector 270 may include multiple horizontal hammer protection circuits 271, a probability memory 272, a timer 273, and / or an additional refresh circuit 274. The configuration and / or operation of the probability memory 272, the timer 273, and / or the additional refresh circuit 274 are similar to those described in the reference above. Figure 14 As described, but without further detail.

[0140] Multiple row hammer protection circuits 271 may include a first row hammer protection circuit 271_1 to an nth row hammer protection circuit 271_n.

[0141] The first row hammer protection circuit 271_1 to the nth row hammer protection circuit 271_n can generate the first count value CV1 to the nth count value CVn by counting the number of times adjacent word lines are activated for the first word line WL1 to the nth word line WLn respectively.

[0142] Each or more of the first row of hammer impact protection circuits 271_1 to the nth row of hammer impact protection circuits 271_n can manage the local probability table LPT. For example, the probability determination circuit PDC included in the first row of hammer impact protection circuits 271_1 to the nth row of hammer impact protection circuits 271_n can manage the first local probability table LPT1 to the nth local probability table LPTn, respectively.

[0143] Each or more of the first local probability table LPT1 to the nth local probability table LPTn can be a part of the global probability table GPT. For example, each or more of the first local probability table LPT1 to the nth local probability table LPTn can include a portion of the multiple probabilities included in the global probability table GPT. This will be referenced below. Figure 14 The configuration of each or more of the first local probability table LPT1 to the nth local probability table LPTn is described in more detail.

[0144] In some example embodiments, the capacities of the first local probability table LPT1 to the nth local probability table LPTn can be the same.

[0145] In some example embodiments, multiple probabilities included in each or more of the first local probability table LPT1 to the nth local probability table LPTn may correspond to a continuous range of counts. For example, multiple probabilities included in the second local probability table LPT2 may correspond to a continuous row of hammer threat levels within the global probability table GPT.

[0146] The first row of hammer impact protection circuits 271_1 to the nth row of hammer impact protection circuits 271_n can identify the probability corresponding to the count value CV from the multiple probabilities included in the first local probability table LPT1 to the nth local probability table LPTn. For example, the probability determination circuit PDC included in the second row of hammer impact protection circuits 271_2 can identify the probability corresponding to the second count value CV2 from the second local probability table LPT2.

[0147] In response to the trigger signal TS, the first row hammer protection circuit 271_1 to the nth row hammer protection circuit 271_n can issue a row refresh command for the corresponding word line based on the recognized probability. For example, the command issuing circuit CIC included in the second row hammer protection circuit 271_2 can issue a row refresh command CMD_RREF for the second word line WL2 based on the probability recognized by the probability determination circuit PDC.

[0148] In other words, according to some exemplary embodiments of the inventive concept, the first row of hammer impact protection circuits 271_1 to the nth row of hammer impact protection circuits 271_n can determine the probability corresponding to the count value CV based on the local probability table LPT. In this case, the number of times the first row of hammer impact protection circuits 271_1 to the nth row of hammer impact protection circuits 271_n accesses the probability memory 272 can be reduced or minimized, and therefore, the operational performance of the memory device 100 can be improved.

[0149] Figure 13 This illustrates some example embodiments. Figures 1 to 4 A plot showing the relationship between the local and global probability tables. (Reference) Figures 13 to 14 and Figure 15 Each or more of the first local probability tables LPT1 to the nth local probability table LPTn can be part of the global probability table GPT. The sizes of the first local probability tables LPT1 to the nth local probability table LPTn can be the same. In the following description, for the sake of simplicity, it is assumed that each of the first local probability tables LPT1 to the nth local probability table LPTn corresponds to three rows of hammer strike threat levels. However, the example embodiment is not limited to this.

[0150] The first local probability table LPT1, the third local probability table LPT3, and the fourth local probability table LPT4 correspond to hammer threat levels L0 in row 0 of the global probability table GPT to L2 in row 2. The fifth local probability table LPT5 corresponds to hammer threat levels L3 in row 3 of the global probability table GPT to L5 in row 5. The second local probability table LPT2 corresponds to hammer threat levels L10 in row 10 of the global probability table GPT to L12 in row 12.

[0151] The first local probability table LPT1 to the nth local probability table LPTn can be updated based on the first count value CV1 to the nth count value CVn, respectively. For example, when the second local probability table LPT2 does not include the count range corresponding to the second count value CV2, the second local probability table LPT2 can be updated to include the count range corresponding to the second count value CV2. This will be referred to below. Figure 15 The method for updating the first local probability table LPT1 to the nth local probability table LPTn is described in further detail.

[0152] Figure 13 This illustrates an update based on some example embodiments. Figures 1 to 4 The method of plotting local probability tables. As an example, references will be made below. Figures 13 to 15 and Figure 16 A method for updating the second local probability table LPT2 is described. However, the example embodiment is not limited thereto, and the first local probability table LPT1 to the nth local probability table LPTn can also be updated in a similar manner.

[0153] The second local probability table LPT2 can be updated in real time based on the second count value CV2. For example, during the 0th memory refresh period P0_REF, as adjacent word lines relative to the second word line WL2 are repeatedly activated, the second count value CV2 can sequentially increase. In this case, the second count value CV2 may become outside the count range relative to the probabilities included in the second local probability table LPT2. In this case, the probability determination circuit PDC of the second row hammer protection circuit 271_2 can update the second local probability table LPT2.

[0154] The probability determination circuit PDC of the second row hammer strike protection circuit 271_2 can update the second local probability table LPT2 using a window sliding scheme. For example, when the second count value CV2 exceeds “B2”, the probability determination circuit PDC of the second row hammer strike protection circuit 271_2 can update the second local probability table LPT2 to correspond to the hammer strike threat levels L3 to L5 of the third row of the global probability table GPT; when the second count value CV2 exceeds “B5”, the probability determination circuit PDC of the second row hammer strike protection circuit 271_2 can update the second local probability table LPT2 to correspond to the hammer strike threat levels L6 to L8 of the sixth row of the global probability table GPT; and when the second count value CV2 exceeds “B8”, the probability determination circuit PDC of the second row hammer strike protection circuit 271_2 can update the second local probability table LPT2 to correspond to the hammer strike threat levels L9 to L11 of the ninth row of the global probability table GPT. In other words, whenever the second count value CV2 becomes outside the count range corresponding to the second local probability table LPT2, the probability determination circuit PDC of the second row hammer strike protection circuit 271_2 can update the second local probability table LPT2 based on the hammer strike threat level of the next three rows of the global probability table GPT (e.g., the number corresponding to the size of the second local probability table LPT2).

[0155] According to some example embodiments, when the second count value CV2 exceeds “B11”, the probability determination circuit PDC of the second row hammer strike protection circuit 271_2 can update the second local probability table LPT2 to correspond to the first three rows of hammer strike threat levels of the global probability table GPT (e.g., the number corresponding to the size of the second local probability table LPT2). For example, the probability determination circuit PDC of the second row hammer strike protection circuit 271_2 can update the second local probability table LPT2 to correspond to the hammer strike threat levels L10 to L12 of the tenth row of the global probability table GPT.

[0156] Therefore, according to some exemplary embodiments of the inventive concept, the capacity of the mapping table stored in each or more of the first row hammer protection circuits 271_1 to the nth row hammer protection circuits 271_n can be reduced or minimized. For example, the size of the first local probability table LPT1 to the nth local probability table LPTn can be smaller than the global probability table GPT, and thus, the row hammer protector 270 can be implemented in a further smaller size.

[0157] Figure 2 This is a more detailed illustration based on some example embodiments. Figures 1 to 4 Block diagram of a hammer impact protector. (Reference) Figure 13 and Figure 2 , Figure 5The row hammer strike protector 170 can be implemented as the row hammer strike protector 370.

[0158] The horizontal hammer protection device 370 may include multiple horizontal hammer protection circuits 371, a probability memory 372, a timer 373, and / or an additional refresh circuit 374. The configuration and operation of the probability memory 372, the timer 373, and the additional refresh circuit 374 are similar to those described in the reference above. Figure 17 As described, and / or without further detail.

[0159] Multiple row hammer protection circuits 371 may include first row hammer protection circuits 371_1 to nth row hammer protection circuits 371_n. In the following text, the differences between first row hammer protection circuits 371_1 to nth row hammer protection circuits 371_n and first row hammer protection circuits 271_1 to nth row hammer protection circuits 271_n will be the focus.

[0160] The first row hammer protection circuit 371_1 to the nth row hammer protection circuit 371_n can generate the first count value CV1 to the nth count value CVn by counting the number of times adjacent word lines are activated for the first word line WL1 to the nth word line WLn respectively.

[0161] The first row of hammer impact protection circuits 371_1 to the nth row of hammer impact protection circuits 371_n can manage the first local probability table LPT1 to the nth local probability table LPTn.

[0162] Each or more of the first row of hammer impact protection circuits 371_1 to the nth row of hammer impact protection circuits 371_n can manage the adjustment weight table AWT. For example, the probability determination circuit PDC included in the first row of hammer impact protection circuits 371_1 to the nth row of hammer impact protection circuits 371_n can manage the first adjustment weight table AWT1 to the nth adjustment weight table AWTn respectively.

[0163] Each or more of the first adjustment weight tables AWT1 to the nth adjustment weight table AWTn may include multiple adjustment weights corresponding to the hammer threat levels of multiple rows in the Global Probability Table GPT. For example, each or more of the first adjustment weight tables AWT1 to the nth adjustment weight table AWTn may include multiple adjustment weights corresponding to the hammer threat level L0 in row 0 to the hammer threat level L12 in row 12.

[0164] The first row of hammer impact protection circuits 371_1 to the nth row of hammer impact protection circuits 371_n can adjust the counting range of the first local probability table LPT1 to the nth local probability table LPTn based on each or more of the first adjustment weight table AWT1 to the nth adjustment weight table AWTn. For example, the second row of hammer impact protection circuits 371_2 can adjust the counting range of the second local probability table LPT2 based on the second adjustment weight table AWT2.

[0165] In other words, each or more of the first row hammer protection circuits 371_1 to the nth row hammer protection circuits 371_n can independently manage the adjustment weight table AWT, and therefore, the first local probability table LPT1 to the nth local probability table LPTn can be adjusted independently. Therefore, the additional refresh probability for each or more word lines from the first word line WL1 to the nth word line WLn can be determined based on different local counting tables. In this case, the additional refresh probability for each or more word lines from the first word line WL1 to the nth word line WLn can be determined individually according to the characteristics of the data stored in the memory cells connected to each or more word lines from the first word line WL1 to the nth word line WLn. As a result, according to some example embodiments of the inventive concept, since the additional refresh probability for each or more word lines from the first word line WL1 to the nth word line WLn can be optimally determined, the possibility of unnecessarily performing additional refresh operations can be reduced or minimized, and the possibility of data stored in the storage device 100 being corrupted due to the lack of additional refresh operations can be reduced or minimized.

[0166] Figure 18 and Figure 16 This illustrates some example embodiments. Figure 17 A plot of the relationship between the adjusted weight table and the local probability table. This will be referenced below. Figure 18 Describe the adjustment of the weight table AWT, and refer to... Figures 1 to 4 This describes a local probability table LPT adjusted based on the adjusted weight table AWT. However, for the sake of brevity, the relationship between the second adjusted weight table AWT2 and the second local probability table LPT2 will be described in detail below as an example. However, the example embodiment is not limited to this, and the relationship between the first adjusted weight tables AWT1 to the nth adjusted weight table AWTn and the first local probability table LPT1 to the nth local probability table LPTn can also be implemented in a similar manner.

[0167] refer to Figures 16 to 17 and Figure 18The second adjustment weight table AWT2 may include adjustment weights W0 through W12. Each or more of adjustment weights W0 through W12 may correspond to hammer threat levels L0 in row 0 of the global probability table GPT through L12 in row 12. Each or more of adjustment weights W0 through W12 may be used to adjust the upper limit of the count range relative to the hammer threat level of the corresponding row.

[0168] For example, refer to the same Figure 14 The second local probability table LPT2 can correspond to the hammer threat level from row 9 (L9) to row 11 (L11) of the global probability table GPT. In this case, the ninth adjustment weight W9 to the eleventh adjustment weight W11 can be used to adjust the upper limit of the count range within the second local probability table LPT2.

[0169] For example, the upper limit of the count range corresponding to the hammer threat level L9 in the ninth row can be adjusted based on the ninth adjustment weight W9. For instance, the upper limit of the count range corresponding to the hammer threat level L9 in the ninth row can be determined by subtracting the ninth adjustment weight W9 from B9. Similarly, the upper limit of the count range corresponding to the hammer threat level L10 in the tenth row can be adjusted based on the tenth adjustment weight W10; and the upper limit of the count range corresponding to the hammer threat level L11 in the eleventh row can be adjusted based on the eleventh adjustment weight W11.

[0170] In some example embodiments, the lower limit of the counting range of the second local probability table LPT2 can be adjusted based on the upper limit of the prior counting range. For example, the lower limit of the counting range corresponding to the hammer threat level L10 in the tenth row can be adjusted to be 1 greater than the upper limit of the counting range corresponding to the hammer threat level L9 in the ninth row. Similarly, referring to the above... Figure 19 Before updating the second local probability table LPT2 in the described method, the lower limit of the count range corresponding to the hammer threat level L9 in the ninth row can be adjusted to be 1 greater than the upper limit of the count range corresponding to the hammer threat level L8 in the eighth row.

[0171] In other words, according to some example embodiments of the inventive concept, as the adjustment weight increases, additional refresh operations can be performed on word lines corresponding to other lower count values ​​with gradually increasing probability.

[0172] Figure 20 and Figure 18 It shows the basis Figures 1 to 4 Timing diagrams of the operation of the storage devices in some example embodiments. First, refer to... Figures 16 to 19 and Figure 20The storage device 100 can perform a memory refresh operation from a first time point ta to a fourth time point td. The time period between the first time point ta and the second time point tb can be referred to as the first memory refresh period Pa_REF; the time period between the second time point tb and the third time point tc can be referred to as the second memory refresh period Pb_REF; and the time period between the third time point tc and the fourth time point td can be referred to as the third memory refresh period Pc_REF. In the following text, for the sake of brevity, it is assumed that the first time point ta includes weights 0 to 12 in the second adjusted weight table AWT2, which are 0. However, the example embodiment is not limited to this.

[0173] When a memory refresh is performed (e.g., at a second time point tb, etc.), the probability determination circuit PDC can update the second adjustment weight table AWT2 based on the second count value CV2 of the previous memory refresh period. In the following description, for the sake of brevity, some example embodiments in which the probability determination circuit PDC updates the second adjustment weight table AWT2 whenever a refresh is performed are described as examples, but the example embodiments are not limited thereto. For example, the probability determination circuit PDC can also be configured to update the second adjustment weight table AWT2 whenever a memory refresh is performed a predetermined number of times or a given number of times.

[0174] During the first memory refresh period Pa_REF, the second count value CV2 can be B9-1. In this case, the second count value CV2 can be included in the count range corresponding to the hammer threat level L9 in the ninth row of the second local probability table LPT2. Therefore, during the second memory refresh period Pb_REF, the probability determination circuit PDC can perform an additional refresh operation based on the ninth probability P9 corresponding to the hammer threat level L9 in the ninth row.

[0175] For example, the probability determination circuit PDC can update the adjustment weights corresponding to the count range, which includes the second count value CV2. For example, at the second time point tb, the ninth adjustment weight W9 included in the second adjustment weight table AWT2 can increase from 0 to 1. Therefore, the upper limit of the count range corresponding to the hammer threat level L9 in the ninth row of the second local probability table LPT2 can decrease from B9 to B9-1.

[0176] According to some example embodiments, during the second memory refresh period Pb_REF, the second count value CV2 can be B9-1. In this case, the second count value CV2 can be included in the count range corresponding to the hammer threat level L9 in the ninth row of the second local probability table LPT2. Therefore, during the third memory refresh period Pc_REF, the probability determination circuit PDC can perform an additional refresh operation based on the ninth probability P9 corresponding to the hammer threat level L9 in the ninth row. At the third time point tc, the probability determination circuit PDC can increase the ninth adjustment weight W9 included in the second adjustment weight table AWT2 from 1 to 2. Therefore, the upper limit of the count range corresponding to the hammer threat level L9 in the ninth row of the second local probability table LPT2 can be reduced from B9-1 to B9-2.

[0177] Subsequently, during the third memory refresh period Pc_REF, the second count value CV2 can be B9-1. The second count value CV2 may not be included in the count range corresponding to the hammer threat level L9 in the ninth row of the second local probability table LPT2, but may be included in the count range corresponding to the hammer threat level L10 in the tenth row. Therefore, at the subsequent fourth time point td, the probability determination circuit PDC can perform an additional refresh operation based on the tenth probability P10 corresponding to the hammer threat level L10 in the tenth row.

[0178] In other words, according to some exemplary embodiments of the inventive concept, even if adjacent word line activations for a specific word line are generated a uniform number of times throughout multiple memory refresh periods, additional refresh operations can be performed with a gradually increasing probability as the adjustment weight increases. In this case, even if the storage device 100 is subjected to a row hammer attack for a long time, additional refresh operations can be performed with a gradually increasing probability, and therefore, the stability of the data stored in the storage device 100 can be improved or ensured.

[0179] In some example embodiments, at the fourth time point td, the probability determination circuit PDC can increase the tenth adjustment weight W10, which is included in the second adjustment weight table AWT2, from 2 to 3. Therefore, the upper limit of the count range corresponding to the hammer threat level L9 in the ninth row of the second local probability table LPT2 can be reduced from B9-2 to B9-3.

[0180] Further reference Figure 20The storage device 100 can perform a memory refresh operation from the third time point tc to the sixth time point tf. The time period between the third time point tc and the fourth time point td can be called the third memory refresh period Pc_REF; the time period between the fourth time point td and the fifth time point te can be called the fourth memory refresh period Pd_REF; and the time period between the fifth time point te and the sixth time point tf can be called the fifth memory refresh period Pe_REF.

[0181] During multiple memory refresh periods following the fourth time point td, the second count value CV2 may not be included in the count range corresponding to the hammer threat level L10 in the tenth row of the second local probability table LPT2. For example, during the fourth memory refresh period Pd_REF, the second count value CV2 could be B8, and it could correspond to the hammer threat level L8 in the eighth row. During the fifth memory refresh period Pe_REF, the second count value CV2 could be B3, and it could correspond to the hammer threat level L3 in the third row. In this case, the probability determination circuit PDC can reduce the adjustment weights that have not yet been used after the fourth time point td. For example, the probability determination circuit PDC can reduce the ninth weight W9 from 2 to 0.

[0182] For example, according to Figure 20 Some example implementations can reduce or prevent the excessive execution of additional refresh operations as the adjustment weight value increases excessively.

[0183] For a more concise description, Figure 21 The illustrations show some example embodiments where the probability determination circuit (PDC) initializes adjustment weights that have not been used within two memory bank refresh periods; however, these example embodiments are not limited to these. For instance, the probability determination circuit (PDC) can be configured to reduce adjustment weights that have not been used within any number of memory bank refresh periods to any size.

[0184] Figure 2 This illustrates some example embodiments. Figures 1 to 21 The timing diagram for the operation of the impact protection circuit is shown below. (Reference) Figure 22 The storage device 100 can perform memory refresh operations at predetermined or given time intervals. For example, the storage device 100 can perform memory refresh operations at tenth time point t10, twentieth time point t20, thirtieth time point t30, and / or fortieth time point t40 in response to the control of the memory controller 10. In this case, the time intervals between the tenth time point t10, twentieth time point t20, thirtieth time point t30, and fortieth time point t40 can be the same for each other.

[0185] Meanwhile, to ensure the operational flexibility of the memory system MS, the storage device 100 may omit the memory refresh operation for a predetermined number or a given number of times. For example, the memory controller 10 may not issue a memory refresh command at the thirtieth time point t30, and / or the storage device 100 may not perform a memory refresh operation at the thirtieth time point t30. That is, the length of the memory refresh period between the twentieth time point t20 and the fortieth time point t40 may be longer than the length of the memory refresh period between the tenth time point t10 and the twentieth time point t20.

[0186] In the following text, for the sake of brevity, the memory refresh period when memory refresh is performed at regular intervals (e.g., between time point 10 t10 and time point 20 t20) can be referred to as the normal memory refresh period PN_REF, while the memory refresh period when partial memory refresh is omitted (e.g., between time point 20 t20 and time point 40 t40) can be referred to as the extended memory refresh period PX_REF.

[0187] The number of times each or one or more word lines in a multi-word-line network are activated by adjacent word lines during the extended memory refresh period PX_REF can be higher than the number of times each or one or more word lines in a multi-word-line network are activated by adjacent word lines during the normal memory refresh period PN_REF. In this case, the probability of data in storage device 100 being corrupted due to a row hammer attack during the extended memory refresh period PX_REF may be relatively high.

[0188] Therefore, storage device 100 can perform additional refresh operations according to some example embodiments more often during the extended memory refresh period PX_REF than during the normal memory refresh period PN_REF. For example, storage device 100 can perform an additional refresh operation once during the normal memory refresh period PN_REF and multiple times during the extended memory refresh period PX_REF. For example, storage device 100 can perform an additional refresh operation once based on a trigger signal TS issued after a predetermined time length or a given time length has elapsed since the tenth time point t10. Similarly, storage device 100 can perform additional refresh operations multiple times (e.g., 3 times) based on a trigger signal TS repeatedly issued every time a predetermined time length has elapsed since the twentieth time point t20. Reference will be made below. Figure 22 This describes in more detail the method for performing additional refresh operations within the extended memory refresh period PX_REF.

[0189] Figure 21 This shows the storage devices in more detail. Figures 1 to 22The timing diagram for operations during the extended memory refresh period is shown below. As an example, reference will be made to... Figure 21 A detailed description of storage devices in Figure 9 The operations between the twentieth time point t20 and the fortieth time point t40.

[0190] At the twentieth time point t20, storage device 100 may receive the memory refresh command BREF. Storage device 100 may perform a memory refresh operation at the twentieth time point t20 in response to the memory refresh command BREF.

[0191] Whenever the additional refresh interval INTV_AFR occurs starting from the twentieth time point t20, storage device 100 can perform an additional refresh operation. For example, as referenced above. ​ As described, the line hammer protector 170 can issue an additional refresh command CMD_AREF. In this case, the storage device 100 can perform an additional refresh operation in response to the additional refresh command CMD_AREF.

[0192] In some example embodiments, the length of the additional refresh interval INTV_AFR may be predetermined or given. In the following, for the sake of brevity, as examples, some example embodiments in which the length of the additional refresh interval INTV_AFR is half the normal memory refresh period PN_REF will be described in detail. However, the example embodiments are not limited to this, and the length of the additional refresh interval INTV_AFR may be determined regardless of the normal memory refresh period PN_REF.

[0193] At time point t25, which is the twentyth time point since t20 and has passed the additional refresh interval INTV_AFR, storage device 100 can perform an additional refresh operation. At time point t30, which is the twenty-fifth time point since t25 and has passed the additional refresh interval INTV_AFR, storage device 100 can perform an additional refresh operation. At time point t35, which is the thirtieth time point since t30 and has passed the additional refresh interval INTV_AFR, storage device 100 can perform an additional refresh operation. For example, at time points t25, t30, and / or t35, row hammer protector 170 can issue an additional refresh command CMD_AREF and its corresponding row address.

[0194] In some example embodiments, the row addresses issued from the row hammer protector 170 at the 25th time point t25, the 30th time point t30, and the 35th time point t35 may be the same or different from each other.

[0195] In some example embodiments, at the 25th time point t25, the 30th time point t30, and / or the 35th time point t35, the row hammer protector 170 may issue an additional refresh command CMD_AREF and / or its corresponding row address with the same probability. For example, the row hammer protector 170 may determine the additional refresh probability at the 25th time point t25, the 30th time point t30, and / or the 35th time point t35 based on the number of times adjacent word lines from the first word line WL1 to the nth word line WLn have been activated during the memory refresh interval (e.g., the normal memory refresh interval PN_REF) prior to the 20th time point t20. However, the example embodiments are not limited thereto.

[0196] In some example embodiments, at the 25th time point t25, the 30th time point t30, and / or the 35th time point t35, the line hammer protector 170 may issue an additional refresh command CMD_AREF and / or its corresponding line address with progressively higher probabilities. For example, the line hammer protector 170 may perform an additional refresh operation at the 30th time point t30 with a higher probability for each or one or more word lines than at the 25th time point t25; and the line hammer protector 170 may perform an additional refresh operation at the 35th time point t35 with a higher probability for each or one or more word lines than at the 30th time point t30. For a more specific example, the line hammer protector 170 may perform an additional refresh operation on each or one or more word lines at the twenty-fifth time point t25 based on a probability previously determined based on the tenth time point t10 to the twentieth time point t20; and may perform the additional refresh operation on each or one or more word lines at the thirtieth time point t30 based on a value obtained by multiplying the aforementioned probability by a predetermined scaling factor or a given scaling factor. However, the example embodiment is not limited to the specific method by which the line hammer protector 170 determines the additional refresh probability for the multiple word lines at each of the multiple time points.

[0197] In other words, according to some example embodiments of the inventive concept, additional refresh operations can be performed multiple times within a single memory refresh period. In this case, the possibility of data stored in the storage device 100 being damaged due to row hammering can be reduced or minimized.

[0198] The one or more elements disclosed above may include or be implemented in: one or more processing circuitry systems, such as hardware including logic circuitry; hardware / software combinations, such as processors running software; or combinations thereof. For example, processing circuitry systems may more specifically include, but are not limited to, central processing units (CPUs), arithmetic logic units (ALUs), digital signal processors, microcomputers, field-programmable gate arrays (FPGAs), system-on-a-chip (SoCs), programmable logic units, microprocessors, application-specific integrated circuits (ASICs), etc.

[0199] The foregoing description provides exemplary embodiments for implementing the inventive concept. The inventive concept includes not only the exemplary embodiments described above, but also embodiments that can be easily modified or altered. Furthermore, the inventive concept also includes techniques that can be readily modified and implemented using the exemplary embodiments. While the inventive concept has been described with reference to exemplary embodiments, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the inventive concept set forth in the appended claims.

Claims

1. A storage device, the storage device comprising: A memory cell array connected to multiple word lines; as well as A row hammer protector, the row hammer protector including a processing circuit system configured to perform an additional refresh operation probabilistically for each of the plurality of word lines during a second memory refresh period following the first memory refresh period, based on adjacent word line activation counts for each of the plurality of word lines during a first memory refresh period.

2. The storage device according to claim 1, wherein, The hammer impact protector also includes: A probability memory, configured to store a global probability table, the global probability table including multiple probabilities corresponding to multiple counting ranges respectively; and The first row hammer protection circuit is configured to issue a first row refresh command for the first word line during the second memory refresh period based on the global probability table and the first number of times the word line adjacent to the first word line among the plurality of word lines is activated during the first memory refresh period.

3. The storage device according to claim 2, wherein, The hammer impact protector also includes: The second row hammer protection circuit is configured to issue a second row refresh command probabilistically for the second word line during the second memory refresh period based on the global probability table and the second number of times the word line adjacent to the second word line among the plurality of word lines is activated during the first memory refresh period.

4. The storage device according to claim 3, wherein, The first row of hammer impact protection circuits is further configured as follows: Identify a first probability corresponding to a counting range that includes a first count value among the plurality of counting ranges, wherein the first count value corresponds to the first number of times; and Based on the first probability, the first refresh command is issued during the refresh period of the second storage bank, and The second row of hammer impact protection circuits is further configured as follows: Identify a second probability corresponding to a count range that includes a second count value among the plurality of count ranges, wherein the second count value corresponds to the second number; and The second line refresh command is issued during the second storage refresh period based on the second probability.

5. The storage device according to claim 4, wherein: The first refresh command includes a first activation command for the first word line and a first precharge command for the memory cell array; and The second row refresh command includes a second activation command for the second word line and a second precharge command for the memory cell array.

6. The storage device according to claim 4, wherein: The first row of hammer impact protection circuits is further configured as follows: Store a first local probability table corresponding to the first part of the global probability table; and The first probability is determined based on the count range corresponding to the first count value within the count range included in the first local probability table, and The second row of hammer impact protection circuits is further configured as follows: Store a second local probability table corresponding to the second part of the global probability table; and The second probability is determined based on the count range corresponding to the second count value within the count range included in the second local probability table.

7. The storage device according to claim 6, wherein: The first row of hammer strike protection circuits is further configured to dynamically adjust each of the count ranges included in the first local probability table based on the first count value; and The second row of hammer protection circuitry is further configured to dynamically adjust each of the count ranges included in the second local probability table based on the second count value.

8. The storage device according to claim 6, wherein: The first row of hammer strike protection circuitry is further configured to update the first local probability table based on a third portion of the global probability table in response to the first count value not being included in the count range of the first local probability table; and The second row of hammer impact protection circuitry is further configured to update the second local probability table based on the fourth portion of the global probability table in response to the second count value not being included in the count range of the second local probability table.

9. The storage device according to claim 2, wherein: The plurality of counting ranges includes a first plurality of counting ranges and a second plurality of counting ranges that are higher than the first plurality of counting ranges; The plurality of probabilities includes a first plurality of probabilities corresponding to the first plurality of counting ranges and a second plurality of probabilities corresponding to the second plurality of counting ranges; The upper limits of the first plurality of counting ranges are respectively the first plurality of upper limits; The upper limits of the second plurality of counting ranges are respectively the second plurality of upper limits; and The first ratio of the second value to the first value is greater than the second ratio of the fourth value to the third value, where The second value corresponds to the difference between the maximum probability and the minimum probability among the first plurality of probabilities. The first value corresponds to the difference between the largest upper limit value and the smallest upper limit value among the first plurality of upper limit values. The fourth value corresponds to the difference between the maximum probability and the minimum probability among the second plurality of probabilities, and The third value corresponds to the difference between the largest upper limit value and the smallest upper limit value among the second plurality of upper limit values.

10. The storage device according to claim 9, wherein: The first plurality of probabilities are logarithmic with respect to the first plurality of upper limits; and The second plurality of probabilities are linear with respect to the second plurality of upper limits.

11. The storage device according to claim 9, wherein, The size of the first plurality of counting ranges is less than or equal to the size of the second plurality of counting ranges.

12. The storage device according to claim 9, wherein, The size of the first counting range among the first plurality of counting ranges is less than or equal to the size of the second counting range among the first plurality of counting ranges.

13. A storage device configured to operate in response to control from an external device, the storage device comprising: A memory cell array connected to multiple word lines; as well as Processing circuitry system, the processing circuitry system being configured to: A first count value is generated by counting the number of activation commands received from the external device between a first time point and a second time point for the second and third word lines adjacent to the first word line among the plurality of word lines. A first memory refresh command is received from the external device at the first time point, and a second memory refresh command is received from the external device at the second time point. Determine the first probability corresponding to the first count value; and At a fourth time point between the second time point and the third time point when a third memory refresh command is received from the external device, a first refresh command is issued for the first word line according to the first probability.

14. The storage device according to claim 13, wherein: The storage device further includes a probability memory configured to store a global probability table comprising multiple probabilities corresponding to multiple counting ranges, respectively. and The processing circuit system is further configured to determine the first probability based on the counting range corresponding to the first count value among the plurality of counting ranges.

15. The storage device according to claim 13, wherein, The time interval between the second time point and the fourth time point is the first time length.

16. The storage device according to claim 15, wherein, The processing circuit system is further configured to: in response to a fifth time point after the first time length from the fourth time point and before the third time point, issue a second line refresh command for the first word line at the fifth time point based on a second probability determined based on the first probability.

17. The storage device according to claim 16, wherein, The second probability is higher than or equal to the first probability.

18. The storage device according to claim 13, wherein, The first refresh command includes an activation command for the first word line and a precharge command for the memory cell array.

19. The storage device according to claim 18, wherein, The processing circuit system is further configured to generate a first additional refresh command that includes a target row refresh mode entry command and the first row refresh command.

20. A storage device configured to receive a first memory refresh command and a second memory refresh command from an external device at a first time point and a second time point, the storage device comprising: A storage cell array connected to a first attack word line, a second attack word line, and a sacrificial word line located between the first attack word line and the second attack word line; as well as A processing circuit system configured to probabilistically issue a row refresh command for the sacrificial word line after a predetermined time interval has elapsed from the second time point and before receiving a third memory refresh command, based on the number of activation commands received for the first attack word line and the second attack word line between the first time point and the second time point.

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