Semiconductor device with mode register

Abstract

The embodiment of the invention relates to a semiconductor device with a mode register. An example apparatus includes a command decoder configured to supply a plurality of mode parameters including a first mode parameter; a master mode register including a plurality of unit registers each configured to store an associated one of the plurality of mode parameters; a first local mode register configured to store at least a portion of the first mode parameter; and a first circuit configured to be controlled by at least the portion of the first mode parameter supplied from the first local mode register. A distance between the first local mode register and the first circuit is shorter than a distance between the main mode register and the first circuit. In response to a mode register write signal, the first mode parameter supplied from the command decoder is stored in each of the main mode register and the first local mode register.

Description

Technical Field

[0001] Embodiments of the present application relate to a semiconductor device having a mode register. Background Art

[0002] There are cases where a semiconductor device (eg, DRAM) includes a mode register that stores various mode parameters. The various mode parameters stored in the mode register are supplied to corresponding associated circuits. Summary of the Invention

[0003] According to an embodiment of the present disclosure, a device is provided. The device includes: a command decoder configured to supply a plurality of mode parameters including a first mode parameter; a master mode register including a plurality of unit registers each configured to store an associated one of the plurality of mode parameters; a first local mode register configured to store at least a portion of the first mode parameters; and a first circuit configured to be controlled by at least the portion of the first mode parameters supplied from the first local mode register. A distance between the first local mode register and the first circuit is shorter than a distance between the master mode register and the first circuit. In response to a mode register write signal, the first mode parameter supplied from the command decoder is stored in each of the master mode register and the first local mode register.

[0004] According to an embodiment of the present disclosure, a device is provided. The device includes: a command decoder configured to supply a plurality of mode parameters including a first mode parameter and a second mode parameter; a master mode register including a plurality of unit registers each configured to store an associated one of the plurality of mode parameters except the second mode parameter; a local mode register configured to store the second mode parameter; a first circuit configured to be controlled by at least the portion of the first mode parameters supplied from the master mode register; and a second circuit configured to be controlled by the second mode parameter supplied from the local mode register. A distance between the local mode register and the second circuit is shorter than a distance between the master mode register and the second circuit.

[0005] According to an embodiment of the present disclosure, a device is provided. The device includes: a command decoder configured to supply a plurality of mode parameters including a first mode parameter; a plurality of first signal lines coupled to the command decoder to deliver the plurality of mode parameters; a main mode register including a plurality of unit registers each configured to store an associated one of the plurality of mode parameters, the main mode register being coupled to the command decoder via the plurality of first signal lines; a first partial mode register configured to store a portion of the first mode parameter, the first partial mode register being coupled to the command decoder via a portion of the plurality of first signal lines; and a first circuit configured to be controlled by the portion of the first mode parameter supplied from the first partial mode register. A distance between the first partial mode register and the first circuit is shorter than a distance between the main mode register and the first circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a schematic plan view for explaining the configuration of a semiconductor device according to an embodiment of the present disclosure;

[0007] Figure 2 is a schematic diagram for explaining the configuration of the central area;

[0008] Figure 3 is a table representing a portion of the various mode parameters assigned to the master mode register;

[0009] Figure 4 、 7 , 9, 11A and 11B are schematic diagrams showing the layout of the master mode register and the local mode register respectively; and

[0010] Figure 5 、 6 , 8, 10 and 12 are circuit diagrams for explaining the connection relationship between the command decoder and the main mode register and the connection relationship between the command decoder and the local mode register, respectively. DETAILED DESCRIPTION

[0011] Various embodiments of the present disclosure will be explained in detail below with reference to the accompanying drawings. The following detailed description refers to the accompanying drawings that show specific aspects and various embodiments of the present disclosure by way of illustration. The detailed description provides sufficient detail to enable those skilled in the art to practice these embodiments of the present disclosure. Other embodiments may be utilized, and structural changes, logical changes, and electrical changes may be made without departing from the scope of the present disclosure. The various embodiments disclosed herein are not necessarily mutually exclusive, as some disclosed embodiments may be combined with one or more other disclosed embodiments to form new embodiments.

[0012] Figure 1is a schematic plan view for explaining the configuration of the semiconductor device 10 according to the embodiment of the present disclosure. Figure 1 The semiconductor device 10 shown in FIG. 1 is a DDR5 DRAM and includes two memory cell array regions 11 and 12 and a central region 20. The central region 20 extends in the X direction and is sandwiched between the memory cell array regions 11 and 12 in the Y direction. A plurality of data I / O pads 21 and a plurality of command address pads 22 are provided in the central region 20. A command address signal CA is externally input to the command address pads 22. When a command included in the command address signal CA indicates a read operation, memory cells included in the memory cell array regions 11 and 12 are read-accessed based on the address included in the command address signal CA. Read data DQ read from the accessed memory cells is output externally from the data I / O pads 21. When a command included in the command address signal CA indicates a write operation, write data DQ externally input to the data I / O pads 21 is transferred to the memory cell array regions 11 and 12. The write data DQ transferred to the memory cell array regions 11 and 12 is written into the memory cells indicated by the addresses included in the command address signal CA.

[0013] Figure 2 is a schematic diagram for explaining the configuration of the central area 20. Figure 2 In the example shown in FIG, a power supply circuit region 31 (GenL), a data input / output circuit region 32 (DQU), a data bonding region 33, a data input / output circuit region 34 (DQL), a DLL circuit region 35, a command-address control circuit region 36, a data bonding region 37, and a power supply circuit region 38 (GenR) are sequentially arranged in the X direction in the center region 20. Power supply circuits that generate various internal potentials based on external power supplied from the outside are provided in the power supply circuit regions 31 and 38, respectively. A data input / output circuit that controls the input and output of upper bits of read and write data is provided in the data input / output circuit region 32. A data input / output circuit that controls the input and output of lower bits of read and write data is provided in the data input / output circuit region 34. Data splicing circuits are provided in data splicing regions 33 and 37. These circuits include a circuit for connecting a global data bus and a data bus provided for each bank group, a circuit for controlling burst length and a circuit for classifying burst orders, and a driver for signals sent from central region 20 to memory cell array regions 11 and 12. Circuits for decoding command and address signals, counting delays, and the like are provided in command-address control circuit region 36. A master mode register 40, which stores various mode parameters, is also provided in command-address control circuit region 36.

[0014] Figure 3 This is a table showing a portion of various mode parameters assigned to the master mode register 40. In the DDR5 DRAM, there are 256 unit mode registers MR0 to MR255. Each of the unit mode registers MR0 to MR255 is selected using an 8-bit mode address MRADD. <0> To OP <7> The associated mode parameters MR#<7:0> are stored in each unit mode register MR# (#=0 to 255). As an example, the mode parameter MR0<7:2> associated with the operand OP<7:2> of the unit mode register MR0 indicates the CAS latency. The mode parameter MR0<1:0> associated with the operand OP<1:0> of the unit mode register MR0 indicates the burst length. The mode parameter MR6<7:4> associated with the operand OP<7:4> of the unit mode register MR6 indicates the read to precharge delay (tRTP). The mode parameter MR6<3:0> associated with the operand OP<3:0> of the unit mode register MR6 indicates the write recovery time. The mode parameters MR6<3:0> associated with the operands OP<7:6>, OP<5:4>, OP<5:4>, OP<5:4> of the unit mode register MR59, respectively, indicate the write recovery time. <3> , OP<2:1> and OP <0> The associated mode parameters MR59<7:6>, MR59<5:4>, MR59 <3> , MR59<2:1> and MR59 <0> Indicates the RFM counter, ARFM, BRC support level, bounded refresh configuration, and DRFM enable, respectively. Various mode parameters MR128<7:0> to MR134<7:0> related to data DQ0 are stored in each of the unit mode registers MR128 to MR134, respectively. Various mode parameters MR136<7:0> to MR143<7:0> related to data DQ1 are stored in each of the unit mode registers MR136 to MR143, respectively.

[0015] Figure 3 Most of the unit mode registers MR0 to MR255 shown in FIG are stored in the master mode register 40. A portion of the unit mode registers is not stored in the master mode register 40 but is stored in a local mode register described later. Another portion of the unit mode registers is stored in both the master mode register 40 and the local mode registers. Still another portion of the unit mode registers is stored in the master mode register 40, and a plurality of local mode registers are divided into a plurality like the operand OP of the unit mode register.

[0016] Figure 4 4 is a schematic diagram showing the layout of the master mode register 40 and the local mode registers 41 to 44. Figure 4As shown in FIG4 , data splicing circuits 51 and 52 are provided in data splicing regions 33 and 37, respectively. DLL circuit 53 is provided in DLL circuit region 35. In addition to master mode register 40, latency control circuit 54, column control circuit 55, and command decoder 56 are also provided in command-address control circuit region 36. Although unit register MR0, which stores mode parameters MR0<7:2> indicating CAS latency and mode parameters MR0<1:0> indicating burst length, is included in master mode register 40, mode parameters MR0<7:2> and MR0<1:0> stored in master mode register 40 are not used to count CAS latency and control burst length, but are stored in master mode register 40 to be read separately during a mode register read operation.

[0017] The local mode register 41 is arranged to be adjacent to the data bonding circuit 51 in the data bonding area 33. Therefore, the distance between the data bonding circuit 51 and the local mode register 41 is shorter than the distance between the data bonding circuit 51 and the main mode register 40. Similarly, the local mode register 42 is arranged to be adjacent to the data bonding circuit 52 in the data bonding area 37. Therefore, the distance between the data bonding circuit 52 and the local mode register 41 is shorter than the distance between the data bonding circuit 51 and the main mode register 40. Each of the local mode registers 41 and 42 is a partial mode register that stores the mode parameter MR0<1:0>. The mode parameter MR0<1:0> stored in each of the local mode registers 41 and 42 is supplied to the data bonding circuits 51 and 52, respectively. Figure 3 As shown in FIG. 4 , the mode parameter MR0<1:0> indicates the burst length. Therefore, the burst length set in the data splicing circuits 51 and 52 is determined by the mode parameter MR0<1:0> stored in the local mode registers 41 and 42, respectively.

[0018] The local mode register 43 is provided adjacent to the DLL circuit 53 in the DLL circuit area 35. Therefore, the distance between the DLL circuit 53 and the local mode register 43 is shorter than the distance between the DLL circuit 53 and the main mode register 40. The local mode register 43 is a partial mode register that stores the mode parameters MR0<7:2>. The mode parameters MR0<7:2> stored in the local mode register 43 are supplied to the DLL circuit 53. Figure 3 As shown in FIG. 4 , the mode parameter MR0<7:2> indicates the CAS latency. Therefore, the CAS latency set in the DLL circuit 53 is determined by the mode parameter MR0<7:2> stored in the local mode register 43 .

[0019] The local mode register 44 is located adjacent to the latency control circuit 54 and the column control circuit 55 in the command-address control circuit area 36. Therefore, the distances between the local mode register 44 and the latency control circuit 54, and the distances between the local mode register 44 and the column control circuit 55, are shorter than the distances between the master mode register 40 and the latency control circuit 54, and the distances between the master mode register 40 and the column control circuit 55, respectively. The local mode register 44 stores mode parameters MR0<7:0>. The mode parameters MR0<7:0> stored in the local mode register 44 are supplied to the latency control circuit 54 and the column control circuit 55. Therefore, the CAS latency and burst length set in the latency control circuit 54 and the column control circuit 55, respectively, are determined using the mode parameters MR0<7:0> stored in the local mode register 44.

[0020] Figure 5 This is a circuit diagram for explaining the connection relationship between command decoder 56 and master mode register 40, and the connection relationship between command decoder 56 and local mode registers 41 to 44. A large number of wires extending in the X direction and a large number of wires extending in the Y direction are arranged in central area 20. The wire located on the lowest layer is wire M1 and extends primarily in the X direction. Wire M2 is located on a layer above wire M1 and extends primarily in the Y direction. Wire M3 is located on a layer above wire M2 and extends primarily in the X direction. Another wire is arranged on a layer above wire M3. When a wire is located on an upper layer, the cross-sectional area of the wire is larger, and therefore the wire on the upper layer has a lower resistance value. That is, the resistance value of wire M3 is lower than that of wire M1.

[0021] The command decoder 56, the main mode register 40, and the local mode registers 41 to 44 are connected to each other via lines M1 to M3. Since the length of the central region 20 in the X direction is longer than the length in the Y direction, most of the lines connecting the command decoder 56, the main mode register 40, and the local mode registers 41 to 44 are formed by lines M3. Consequently, the resistance of the long lines connecting the command decoder 56, the main mode register 40, and the local mode registers 41 to 44 is reduced. At the same time, the local mode registers 41 and 42 are connected to the data splicing circuits 51 and 52, the local mode register 43 is connected to the DLL circuit 53, and the local mode register 44 is connected to the delay control circuit 54 and the column control circuit 55 primarily via lines M1. Lines M3 do not need to exist between the local mode registers 41 to 44 and the corresponding circuits mentioned above. Consequently, the length of the lines connecting the local mode registers 41 to 44 and the corresponding circuits mentioned above is shortened. That is, if part or all of the mode parameters MR0<7:0> are supplied from the master mode register 40 to the data splicing circuits 51 and 52, the DLL circuit 53, the delay control circuit 54, and the column control circuit 55, the length of the line required for this supply becomes long, making it necessary to mainly use the line M3. However, in the present embodiment, it is not necessary to use the line M3 in order to supply part or all of the mode parameters MR0<7:0> to the data splicing circuits 51 and 52, the DLL circuit 53, the delay control circuit 54, and the column control circuit 55, and thus the number of lines M3 is reduced.

[0022] Figure 6 is used to explain in more detail Figure 5 FIG. 4 is a circuit diagram showing the lines of the command decoder 56 outputting various signals to supply to the master mode register 40 and the local mode registers 41 to 44. Figure 6 , the signals supplied from the command decoder 56 to the master mode register 40 are 18-bit signals of a mode address MRADD<7:0>, an operand OP<7:0>, a mode register write signal MRW, and a mode register read signal MRR used to select any of the unit mode registers MR0 to MR255. The mode address MRADD<7:0> is transmitted via line 80, the operand OP<1:0> is transmitted via line 81, the operand OP<7:2> is transmitted via line 82, the mode register write signal MRW is transmitted via line 83, and the mode register read signal MRR is transmitted via line 84. Lines 80 to 84 are connected to the master mode register 40, and all the signals mentioned above are supplied to the master mode register 40.

[0023] At the same time, although the mode address MRADD<7:0>, the operand OP<1:0>, and the mode register write signal MRW are supplied to the local mode registers 41 and 42 via the lines 80, 81, and 83, the lines 82 and 84 are not connected to the local mode registers 41 and 42, and thus the operand OP<7:2> and the mode register read signal MRR are not supplied to the local mode registers 41 and 42. Furthermore, although the mode address MRADD<7:0>, the operand OP<7:2>, and the mode register write signal MRW are supplied to the local mode register 43 via the lines 80, 82, and 83, the lines 81 and 84 are not connected to the local mode register 43, and thus the operand OP<1:0> and the mode register read signal MRR are not supplied to the local mode register 43. Although the mode address MRADD<7:0>, operand OP<7:0>, and mode register write signal MRW are supplied to the local mode register 44 via lines 80 to 83 , line 84 is not connected to the local mode register 44 , and thus the mode register read signal MRR is not supplied to the local mode register 44 .

[0024] With this configuration, when an external mode register write command instructs rewriting of mode parameters MR0<7:0>, command decoder 56 activates mode register write signal MRW and outputs mode address MRADD<7:0> and operand OP<7:0>. Consequently, mode parameters MR0<7:0> are overwritten in unit register U0 contained in master mode register 40 and in local mode register 44, mode parameters MR0<1:0> are overwritten in local mode registers 41 and 42, and mode parameters MR0<7:2> are overwritten in local mode register 43. In this manner, mode parameters MR0<7:0> are stored not only in master mode register 40 but also in a plurality of dispersed local mode registers 41 to 44. Simultaneously, when an external mode register read command instructs reading of mode parameters MR0<7:0>, command decoder 56 activates mode register read signal MRR and outputs mode address MRADD<7:0>. Therefore, the mode parameter MR0<7:0> is read from the unit register U0 included in the master mode register 40. Meanwhile, the mode register read signal MRR is not supplied to the local mode registers 41 to 44, and thus the mode parameter MR0<7:0> is not read from the local mode registers 41 to 44.

[0025] In this manner, the mode parameter MR0<7:0> is not only held in the master mode register 40, but also a portion or all thereof is held in the local mode registers 41 to 44. Since the local mode registers 41 to 44 are provided adjacent to the corresponding associated circuits 51 to 55, the length of the line used to supply the mode parameter MR0<7:0> to the circuits 51 to 55 is shortened.

[0026] Figure 7 is a schematic diagram showing the layout of the master mode register 40 and the local mode register 45. The local mode register 45 is arranged adjacent to the column control circuit 55 in the command-address control circuit area 36. Therefore, the distance between the column control circuit 55 and the local mode register 45 is shorter than the distance between the column control circuit 55 and the master mode register 40. The local mode register 45 stores the mode parameter MR6<7:0>. Figure 3 As shown in FIG. 4 , mode parameters MR6<7:4> and mode parameters MR6<3:0> represent tRTP (read to precharge time) and tWR (write recovery time), respectively. Mode parameters MR6<7:0> stored in the local mode register 44 are supplied to the column control circuit 55. Although the unit register storing mode parameters MR6<7:0> is included in the master mode register 40, the mode parameters MR6<7:0> stored in the master mode register 40 are not used for column control of tRTP and tWR. Instead, they are stored in the master mode register 40 so that they can be read separately during a mode register read operation.

[0027] Figure 8 is used to explain the Figure 5 FIG. 4 is a circuit diagram showing various signals output by the command decoder 56 and supplied to the master mode register 40 and the local mode register 45. Figure 8 , although the mode address MRADD<7:0>, the operand OP<7:0>, and the mode register write signal MRW are supplied to the local mode register 45 via lines 80, 85, and 83, the line 84 is not connected to the local mode register 45, and thus the mode register read signal MRR is not supplied to the local mode register 45. The line 85 is a line for transmitting the operand OP<7:0> and corresponds to Figure 6, shown in lines 81 and 82. With this configuration, when an external mode register write command instructs overwriting of mode parameters MR6<7:0>, command decoder 56 activates mode register write signal MRW and outputs mode address MRADD<7:0> and operand OP<7:0>. Consequently, mode parameters MR0<7:0> are overwritten in unit register U6 included in master mode register 40 and in local mode register 45. In this manner, mode parameters MR6<7:0> are stored not only in master mode register 40 but also in local mode register 45. Simultaneously, when an external mode register read command instructs reading of mode parameters MR6<7:0>, mode parameters MR6<7:0> are read from unit register U6 included in master mode register 40. Simultaneously, mode register read signal MRR is not supplied to local mode register 45, and therefore mode parameters MR6<7:0> are not read from local mode register 45.

[0028] Figure 9 is a schematic diagram showing the layout of the main mode register 40 and the local mode registers 46 and 47. The refresh control circuit 57 is arranged adjacent to the main mode register 40 in the command-address control circuit area 36. The local mode register 46 is arranged adjacent to the data splicing circuit 51 in the data splicing area 33. Therefore, the distance between the data splicing circuit 51 and the local mode register 46 is shorter than the distance between the data splicing circuit 51 and the main mode register 40. Similarly, the local mode register 47 is arranged adjacent to the data splicing circuit 52 in the data splicing area 37. Therefore, the distance between the data splicing circuit 52 and the local mode register 47 is shorter than the distance between the data splicing circuit 52 and the main mode register 40. Each of the local mode registers 46 and 47 is a partial mode register that stores the mode parameter MR59<5,4,0>. The mode parameters MR59<5:4> and MR59<5:4> are 1:1 and 2:2. <0> The mode parameters MR59<5,4,0> stored in each of the local mode registers 46 and 47 are supplied to the memory cell array regions 11 and 12 through the data splicing circuits 51 and 52, respectively. The unit register storing the mode parameters MR59<7:0> is included in the master mode register 40. Figure 3 As shown in FIG. 5 , the mode parameter MR59<7:0> is a mode parameter related to refresh. The mode parameter MR59<7:0> stored in the master mode register 40 is supplied to the refresh control circuit 57 .

[0029] Figure 10 is used to explain the Figure 5FIG. 4 is a circuit diagram showing the lines of the various signals output by the command decoder 56 and supplied to the master mode register 40 and the local mode registers 46 and 47. Figure 10 , although the mode address MRADD<7:0>, operand OP<5,4,0>, and mode register write signal MRW are supplied to local mode registers 46 and 47 via lines 80 and 83 and line 86, lines 84 and 87 are not connected to local mode registers 46 and 47, and therefore operand OP<7,6,3,2,1> and mode register read signal MRR are not supplied to local mode registers 46 and 47. Line 86 is a line for transmitting operand OP<5,4,0>, and line 87 is a line for transmitting operand OP<7,6,3,2,1>. With this configuration, when a mode register write command from an external source instructs overwriting of mode parameter MR59<7:0>, command decoder 56 activates mode register write signal MRW and outputs mode address MRADD<7:0> and operand OP<7:0>. Therefore, the mode parameter MR59<7:0> is overwritten in the unit register U59 included in the master mode register 40, and the mode parameter MR59<5,4,0> is overwritten in the local mode registers 46 and 47. In this way, the mode parameter MR59<7:0> is not only stored in the master mode register 40, but also a portion thereof is stored in the local mode registers 46 and 47. At the same time, when a mode register read command from the outside instructs the reading of the mode parameter MR59<7:0>, the mode parameter MR59<7:0> is read out from the unit register U59 included in the master mode register 40.

[0030] In this way, there is no need to allocate any local mode register to circuits (such as the refresh control circuit 57 ) provided near the main mode register 40 , and mode parameters can be supplied directly from the main mode register 40 to these circuits.

[0031] Figure 11A and 11B are schematic diagrams showing the layout of the master mode register 40 and the local mode registers 70 to 77, respectively. Figure 11A Show the entire central area 20 and Figure 11BThe data input / output circuit region 34 is shown in an enlarged manner. Data control circuits 60 to 67, which control the input and output of data signals DQ0 to DQ7, and data strobe control circuits 68 and 69, which control the input and output of data strobe signals DQS and DQSF, are provided in the data input / output circuit region 34. Local mode registers 70 to 77 are provided adjacent to the data control circuits 60 to 67, respectively. Local mode register 70 stores mode parameters MR128<7:0> to MR134<7:0>. Local mode register 71 stores mode parameters MR136<7:0> to MR142<7:0>. Local mode register 72 stores mode parameters MR144<7:0> to MR150<7:0>. Local mode register 73 stores mode parameters MR152<7:0> to MR158<7:0>. Local mode register 74 stores mode parameters MR160<7:0> to MR166<7:0>. Local mode register 75 stores mode parameters MR168<7:0> to MR174<7:0>. Local mode register 76 stores mode parameters MR176<7:0> to MR182<7:0>. Local mode register 77 stores mode parameters MR184<7:0> to MR190<7:0>.

[0032] Mode parameters MR128<7:0> to MR134<7:0> for data DQ0 stored in local mode register 70 are supplied to data control circuit 60 associated with data DQ0. Mode parameters MR136<7:0> to MR142<7:0> for data DQ1 stored in local mode register 71 are supplied to data control circuit 61 associated with data DQ1. Mode parameters MR144<7:0> to MR150<7:0> for data DQ2 stored in local mode register 72 are supplied to data control circuit 62 associated with data DQ2. Mode parameters MR152<7:0> to MR158<7:0> for data DQ3 stored in local mode register 73 are supplied to data control circuit 63 associated with data DQ3. Mode parameters MR160<7:0> to MR166<7:0> for data DQ4 stored in local mode register 74 are supplied to data control circuit 64 associated with data DQ4. Mode parameters MR168<7:0> to MR174<7:0> for data DQ5 stored in local mode register 75 are supplied to data control circuit 65 associated with data DQ5. Mode parameters MR176<7:0> to MR182<7:0> for data DQ6 stored in local mode register 76 are supplied to data control circuit 66 associated with data DQ6. Mode parameters MR184<7:0> to MR190<7:0> for data DQ7 stored in local mode register 77 are supplied to data control circuit 67 associated with data DQ7.

[0033] The master mode register 40 does not include any single-bit registers for storing mode parameters MR128<7:0> to MR134<7:0> associated with data DQ0 , nor does the master mode register 40 include any mode parameters associated with data DQ1 to DQ7 .

[0034] Figure 12 is used to explain the Figure 5 FIG. 5 is a circuit diagram showing various signals output by the command decoder 56 and supplied to the master mode register 40 and the local mode register 70. Figure 12As shown in FIG. 1 , the mode address MRADD<7:0>, operand OP<7:0>, mode register write signal MRW, and mode register read signal MRR are supplied to the local mode register 70 via lines 80, 85, 83, and 84. With this configuration, when an external mode register write command instructs the overwriting of mode parameters MR128<7:0>, the command decoder 56 activates the mode register write signal MRW and outputs the mode address MRADD<7:0> and operand OP<7:0>. Consequently, the mode parameters MR128<7:0> are overwritten in the local mode register 70. Since the master mode register 40 does not include any unit registers for storing the mode parameters MR128<7:0>, the mode parameters MR128<7:0> are not written to the master mode register 40. Furthermore, when an external mode register read command instructs the reading of the mode parameters MR128<7:0>, the mode parameters MR128<7:0> are read from the local mode register 70.

[0035] In this manner, a portion of the mode parameters is held only in the local mode register, and is not held in the master mode register 40. Therefore, the circuit size of the master mode register 40 can be reduced.

[0036] Although various embodiments have been disclosed in the context of certain preferred embodiments and examples, it will be understood by those skilled in the art that the scope of the present disclosure extends beyond the specifically disclosed embodiments to other alternative embodiments and / or uses of the described embodiments, as well as obvious modifications and equivalents thereof. Additionally, other modifications within the scope of the present disclosure will be readily apparent to those skilled in the art based on the present disclosure. It is also contemplated that various combinations or sub-combinations of the specific features and aspects of the described embodiments may be made and still fall within the scope of the present disclosure. It should be understood that the various features and aspects of the disclosed embodiments may be combined or replaced with one another to form different modes of the disclosed embodiments. Therefore, it is desired that the scope of at least some of the present disclosure should not be limited by the specific disclosed embodiments described above.

Claims

1. A device comprising: a command decoder configured to supply a plurality of mode parameters including a first mode parameter; a master mode register comprising a plurality of single-bit registers each configured to store an associated one of the plurality of mode parameters; a first local mode register configured to store at least a portion of the first mode parameters; and a first circuit configured to be controlled by at least said portion of said first mode parameters supplied from said first local mode register, wherein a distance between the first local mode register and the first circuit is shorter than a distance between the main mode register and the first circuit, and wherein the first mode parameter supplied from the command decoder is stored in each of the master mode register and the first local mode register in response to a mode register write signal. 2 . The apparatus of claim 1 , wherein the first mode parameter is read from the master mode register in response to a mode register read signal, but is not read from the first local mode register.

3. The device according to claim 2, wherein the plurality of mode parameters further include a second mode parameter, The device further comprises: a second local mode register configured to store the second mode parameter; and a second circuit configured to be controlled by the second mode parameter supplied from the second local mode register, wherein a distance between the second local mode register and the second circuit is shorter than a distance between the main mode register and the second circuit, and In response to the mode register write signal, the second mode parameter supplied from the command decoder is stored in the second local mode register instead of in the main mode register. 4 . The apparatus of claim 3 , wherein the second mode parameter is read out from the second local mode register in response to the mode register read signal.

5. The device according to claim 1, wherein the plurality of mode parameters further comprises a third mode parameter, The device further comprises: a first partial mode register configured to store a portion of the third mode parameters; a second partial mode register configured to store another portion of the third mode parameters; a third circuit configured to be controlled by the portion of the third mode parameters supplied from the first partial mode register; and a fourth circuit configured to be controlled by the other portion of the third mode parameters supplied from the second portion of the mode register, and wherein in response to the mode register write signal, the portion of the third mode parameter and the other portion of the third mode parameter supplied from the command decoder are stored in the first partial mode register and the second partial mode register, respectively. 6 . The apparatus of claim 5 , wherein the third mode parameter supplied from the command decoder is stored in the master mode register in response to the mode register write signal.

7. The device according to claim 6, wherein the distance between the first partial mode register and the third circuit is shorter than the distance between the main mode register and the third circuit, and The distance between the second partial mode register and the fourth circuit is shorter than the distance between the main mode register and the fourth circuit.

8. The apparatus of claim 7, further comprising: a third local mode register configured to store the third mode parameter; and a fifth circuit configured to be controlled by the third mode parameter supplied from the third local mode register, The distance between the third local mode register and the fifth circuit is shorter than the distance between the main mode register and the fifth circuit.

9. The device according to claim 1, wherein the plurality of mode parameters further include a fourth mode parameter, and The device further comprises: a third partial mode register configured to store a portion of the fourth mode parameters; a sixth circuit configured to be controlled by the portion of the fourth mode parameters supplied from the third partial mode register; and A seventh circuit is configured to be controlled by the fourth mode parameter supplied from the master mode register.

10. The apparatus of claim 9, wherein the fourth mode parameter and the portion of the fourth mode parameter supplied from the command decoder are stored in the main mode register and the third partial mode register, respectively, in response to the mode register write signal.

11. The apparatus of claim 1 , further comprising: a plurality of first signal lines connecting the command decoder to the master mode register and the first local mode register; and a plurality of second signal lines connecting the first local mode register to the first circuit, wherein a portion of the plurality of first signal lines is disposed on an upper-level wiring layer, wherein another portion of the plurality of first signal lines is disposed on a lower-level wiring layer, and The plurality of second signal lines are provided on the lower-level wiring layer but not on the upper-level wiring layer.

12. A device comprising: a command decoder configured to supply a plurality of mode parameters including a first mode parameter and a second mode parameter; a master mode register comprising a plurality of single-bit registers each configured to store an associated one of the plurality of mode parameters other than the second mode parameter; a local mode register configured to store the second mode parameter; a first circuit configured to be controlled by at least the portion of the first mode parameters supplied from the master mode register; and A second circuit is configured to be controlled by the second mode parameter supplied from the local mode register, wherein a distance between the local mode register and the second circuit is shorter than a distance between the main mode register and the second circuit.

13. The apparatus of claim 12, wherein each of the first mode parameter and the second mode parameter is supplied from the command decoder to both the master mode register and the local mode register in response to a mode register write signal.

14. The device according to claim 13, The first mode parameter supplied from the command decoder is stored in the master mode register, but not in the local mode register.

15. The device according to claim 14, wherein in response to a mode register read signal, the first mode parameter is read from the master mode register, and In response to the mode register read signal, the second mode parameter is read from the local mode register.

16. An apparatus comprising: a command decoder configured to supply a plurality of mode parameters including a first mode parameter; a plurality of first signal lines coupled to the command decoder to deliver the plurality of mode parameters; a master mode register comprising a plurality of single-bit registers each configured to store an associated one of the plurality of mode parameters, the master mode register coupled to the command decoder via the plurality of first signal lines; a first partial mode register configured to store a portion of the first mode parameter, the first partial mode register coupled to the command decoder via a portion of the plurality of first signal lines; and a first circuit configured to be controlled by the portion of the first mode parameters supplied from the first partial mode register, The distance between the first partial mode register and the first circuit is shorter than the distance between the main mode register and the first circuit.

17. The apparatus of claim 16, further comprising: a second partial mode register configured to store another portion of the first mode parameters, the second partial mode register coupled to the command decoder via another portion of the plurality of first signal lines; and a second circuit configured to be controlled by the other portion of the first mode parameters supplied from the second portion of the mode register, The distance between the second partial mode register and the second circuit is shorter than the distance between the main mode register and the second circuit.

18. The apparatus of claim 17, further comprising: a local mode register configured to store the first mode parameter, the local mode register coupled to the command decoder via the plurality of first signal lines; and A third circuit is configured to be controlled by the first mode parameter supplied from the local mode register, wherein a distance between the local mode register and the third circuit is shorter than a distance between the main mode register and the third circuit.

19. The apparatus of claim 16, further comprising a fourth circuit configured to be controlled by the first mode parameter supplied from the master mode register.

20. The apparatus of claim 16, wherein the first mode parameter on the plurality of first signal lines and the portion of the first mode parameter on the portion of the plurality of first signal lines are simultaneously stored in the main mode register and the first partial mode register, respectively, in response to a mode register write signal.

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