Data writing circuit and memory chip

Abstract

The invention provides a data write-in circuit and a memory chip, on the basis of the architecture of the existing data write-in circuit, a single-end transmission circuit coupled with a data input node IO of a memory such as a DRAM or a PSRAM is replaced by a double-end transmission circuit (which is provided with a single data input end and two data output ends), so that when the double-end transmission circuit is switched on, the data input node IO of the memory such as the DRAM or the PSRAM is switched on; the potential of a first bit line node bla or a second bit line node b1b can be rapidly pulled down by rapidly pulling down the potential of an LIOT node or an LIOB node of the memory, so that the first bit line node bla and the second bit line node b1b can be rapidly separated by a larger voltage difference, and the speed of writing '0' and '1' into a memory unit of the memory is further increased; and the speed difference of writing '0' and '1' into the memory is greatly reduced (the speeds of writing '0' and '1' can be approximately the same), so that the performance of the memory is improved, and the requirements of products with higher performance are met.

Description

Technical Field

[0001] The present invention relates to the technical field of memory chips, and in particular to a data writing circuit and a memory chip. Background Art

[0002] Each binary bit of data stored in memories such as dynamic random access memory (DRAM) and pseudo static random access memory (PSRAM) requires only a capacitor and a transistor. Therefore, DRAM and PSRAM offer advantages such as high capacity per unit volume and low cost, making them widely used in various fields.

[0003] Today, with the rapid development of technology, every field—from financial transactions and complex scientific computing to high-definition video processing, large-scale gaming, and AI applications—requires extremely fast and reliable read and write speeds for memories like DRAM and PSRAM to ensure stable system operation and a smooth user experience. However, existing DRAM and PSRAM memory devices struggle to meet these demands because their data write circuits vary in speed between writing "0" and "1." Summary of the Invention

[0004] The purpose of the present invention is to provide a data writing circuit and memory chip that can greatly reduce the speed difference when writing "0" and "1" to memories such as DRAM and PSRAM, thereby improving the performance of the memory to meet the needs of higher performance products.

[0005] To achieve the above-mentioned object, the present invention provides a data writing circuit, which includes a two-terminal transmission circuit, a column selection circuit, and a bit line sense amplifier circuit coupled in sequence, wherein the bit line sense amplifier circuit is coupled to a memory array of a memory; wherein:

[0006] The two-terminal transmission circuit has a single data input terminal and two data output terminals, and the data input terminal is coupled to the data input node of the memory, and one of the data output terminals is coupled to the first local input / output line node, and the other data output terminal is coupled to the second local input / output line node. The two-terminal transmission circuit is configured to be turned on under the control of a write enable signal and transmit the data received by the data input node to the first local input / output line node and the second local input / output line node in a complementary form.

[0007] The column gating circuit is used to transmit data of the first local input / output line node and the second local input / output line node to complementary first bit line nodes and second bit line nodes inside the bit line sense amplifier circuit;

[0008] The bit line sense amplifier circuit is used to write the data or data opposite to the data into a corresponding memory cell in the memory array through at least one of the first bit line node and the second bit line node.

[0009] Optionally, the two-terminal transmission circuit includes a first switch tube, a second switch tube, and a third switch tube, wherein the gate of the first switch tube and the gate of the third switch tube are both coupled to the write enable signal, the source of the first switch tube is coupled to the first local input / output line node, the drain of the first switch tube and the gate of the second switch tube are both coupled to the data input node, the drain of the second switch tube is coupled to the second local input / output line node, and the source of the second switch tube is coupled to the drain of the third switch tube;

[0010] Alternatively, the two-terminal transmission circuit includes a first switch tube, a second switch tube, a third switch tube and an inversion circuit, the gate of the first switch tube and the input end of the inversion circuit are both coupled to the data input node, the drain of the first switch tube is coupled to the second local input / output line node, the gate of the second switch tube is coupled to the output end of the inversion circuit, the drain of the second switch tube is coupled to the first local input / output line node, the source of the first switch tube and the source of the second switch tube are both coupled to the drain of the third switch tube, and the gate of the third switch tube is coupled to the write enable signal.

[0011] Optionally, the first switch tube, the second switch tube and the third switch tube are all n-type transistors.

[0012] Optionally, the column gating circuit includes:

[0013] A first gating switch tube, having a gate coupled to a column gating signal, a source coupled to the first local input / output line node, and a drain coupled to the first bit line node;

[0014] The second selection switch tube has a gate coupled to the column selection signal, a source coupled to the second local input / output line node, and a drain coupled to the second bit line node.

[0015] Optionally, both the first gate switch tube and the second gate switch tube are n-type transistors.

[0016] Optionally, the data writing circuit further includes:

[0017] a first pre-charging circuit coupled to a pre-charging control signal and the first local input / output line node, and configured to pre-charge the potential of the first local input / output line node to a first preset potential under the control of the pre-charging control signal before the two-terminal transmission circuit is turned on for data transmission; and / or

[0018] A second pre-charging circuit couples the pre-charging control signal and the second local input / output line node, and is used to pre-charge the potential of the second local input / output line node to the first preset potential under the control of the pre-charging control signal before the two-terminal transmission circuit is turned on for transmitting data.

[0019] Optionally, the first pre-charging circuit includes a first pre-charging switch tube, a gate of the first pre-charging switch tube coupled to the pre-charging control signal, a source of the first pre-charging switch tube coupled to the first preset potential, and a drain of the first pre-charging switch tube coupled to the first local input / output line node; and / or,

[0020] The second pre-charging circuit includes a second pre-charging switch tube, the gate of the second pre-charging switch tube is coupled to the pre-charging control signal, the source of the second pre-charging switch tube is coupled to the first preset potential, and the drain of the second pre-charging switch tube is coupled to the second local input and output line node.

[0021] Optionally, the bit line sense amplifier circuit includes a latch circuit coupled to the storage array and the column selection circuit, configured to provide the first bit line node and the second bit line node, and to perform charge sharing between the first bit line node and the first local input / output line node and between the second bit line node and the second local input / output line node, respectively, and to amplify the potential difference between the first bit line node and the second bit line node.

[0022] Optionally, the latch circuit includes a first inverter and a second inverter that are cross-coupled, the input of the first inverter is coupled to the first bit line node and the output of the second inverter, and the input of the second inverter is coupled to the second bit line node and the output of the first inverter.

[0023] Optionally, the bit line sense amplifier circuit further includes:

[0024] a third precharge circuit coupled to a precharge control signal and the first bit line node, and configured to precharge the potential of the first bit line node to a second preset potential under the control of the precharge control signal before the two-terminal transmission circuit is turned on for data transmission; and / or

[0025] A fourth precharge circuit couples the precharge control signal and the second bit line node, and is used to precharge the potential of the second bit line node to the second preset potential under the control of the precharge control signal before the two-terminal transmission circuit is turned on for transmitting data.

[0026] Optionally, the third pre-charging circuit includes a third pre-charging switch tube, a gate of the third pre-charging switch tube is coupled to the pre-charging control signal, a source of the third pre-charging switch tube is coupled to the second preset potential, and a drain of the third pre-charging switch tube is coupled to the first bit line node; and / or,

[0027] The fourth pre-charging circuit includes a fourth pre-charging switch tube, the gate of the fourth pre-charging switch tube is coupled to the pre-charging control signal, the source of the fourth pre-charging switch tube is coupled to the second preset potential, and the drain of the fourth pre-charging switch tube is coupled to the second bit line node.

[0028] Based on the same inventive concept, the present invention further provides a memory chip, which includes the data writing circuit as described in the present invention.

[0029] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:

[0030] (1) Based on the architecture of the existing data write circuit, the single-ended transmission circuit of the data input node IO coupled to the memory (such as DRAM / PSRAM, etc.) is replaced with a dual-ended transmission circuit (which has a single data input terminal and two data output terminals). Therefore, when the dual-ended transmission circuit is turned on, the potential of the first local input / output line node (LIOT) or the second local input / output line node (LIOB) can be quickly pulled down to quickly pull down the potential of the first bit line node bla or the second bit line node blb, so that the first bit line node bla and the second bit line node blb can be quickly separated by a larger voltage difference, thereby improving the speed of writing "0" and writing "1" to the storage unit of the memory, and greatly reducing the speed difference when writing "0" and writing "1" to the memory (the speed of writing "0" and writing "1" can be made roughly the same), thereby improving the performance of the memory and meeting the requirements of higher performance products.

[0031] (2) The data writing circuit of the present invention also has first to fourth precharging circuits, so that before writing "0" or "1" to the storage array of the memory coupled thereto, the first local input-output line node LIOT and the second local input-output line node LIOB can be precharged to a first preset potential through the first precharging circuit and the second precharging circuit, and the first bit line node bla and the second bit line node blb can be precharged to a second precharging position through the third precharging circuit and the fourth precharging circuit. When the two-terminal transmission circuit is turned on, the potential difference between the LIOT node and the LIOB node and the potential difference between the bla node and the blb node can be increased, so that the first bit line node bla and the second bit line node blb can quickly separate a larger voltage difference, thereby improving the speed of writing "0" and writing "1" to the storage unit of the memory, thereby improving the overall data writing speed of the memory.

[0032] (3) The two-terminal transmission circuit and column selection circuit in the data writing circuit of the present invention are both constructed by n-type transistors (such as NMOS), which can simplify the circuit and reduce costs. The characteristic of n-type transistors that they can transmit "0" faster can be used to increase the speed of writing "0" and "1" to the storage cells of the memory, thereby improving the overall data writing speed and performance of the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 This is a schematic diagram of the architecture of a data writing circuit inside a DRAM memory chip in the prior art.

[0034] Figure 2 yes Figure 1 The working timing diagram of the data writing circuit shown is as follows.

[0035] Figure 3 2 is a schematic diagram of the architecture of a data reading and writing circuit according to a specific embodiment of the present invention.

[0036] Figure 4A and Figure 4B They are two exemplary structural diagrams of a two-terminal transmission circuit in a data read and write circuit according to a specific embodiment of the present invention.

[0037] Figure 5 FIG. 1 is a schematic diagram of the structure of a bit line sense amplifier circuit in a data read / write circuit according to a specific embodiment of the present invention.

[0038] Figure 6 This is a schematic diagram of an exemplary structure of a data reading and writing circuit according to a specific embodiment of the present invention.

[0039] Figure 7 yes Figure 6 A working timing diagram of the data reading and writing circuit shown. DETAILED DESCRIPTION

[0040] In the following description, a large number of specific details are given to provide a more thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention can be implemented without one or more of these details. In other examples, some technical features known in the art are not described to avoid confusion with the present invention. It should be understood that the present invention can be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, providing these embodiments will make the disclosure thorough and complete and fully convey the scope of the present invention to those skilled in the art. The same reference numerals throughout represent the same elements. It should be understood that when an element is referred to as being "connected to" or "coupled to" another element, it can be directly connected to the other element, or there can be intervening elements. Conversely, when an element is referred to as being "directly connected to" another element, there are no intervening elements. When used herein, the singular forms "a," "an," and "said / the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "comprising" is used to identify the presence of certain features, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups. As used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0041] Please refer to Figure 1 In memory chips such as dynamic random access memory (DRAM) or pseudo static random access memory (PSRAM), a memory array generally has a number of memory cells (not shown) arranged in rows and columns, and the storage of data in each memory cell requires only a capacitor C0 and a transistor M0. When writing data, the corresponding data "0" or "1" is input from the outside through the data input node IO of the memory, and after being controlled by the write enable signal WREN to turn on the switch tube N1 (i.e., a single-ended transmission circuit), it is transmitted to the first local input and output line (also called local input and output line or local input and output line) LIOT node of the memory, and then after being controlled by the column select signal YST0 to turn on the switch tube N2 (which is coupled to the LIOT node), it is transmitted to the latch circuit (latch) of the bit line sense amplifier circuit (sense amplifier) SA. Figure 1The latch circuit is labeled as latch, and the latch circuit is, for example, implemented by a back-to-back inverter circuit) and then passes through the transistor M0 coupled to the bit line bla node of the latch circuit latch (which is turned on by the row selection signal vwlp) to write into the storage cell where M0 is located (that is, the conduction of transistor M0 will change the amount of charge stored in capacitor C0, thereby realizing the storage of binary bit data "1" or "0"). The working sequence of this process is as follows Figure 2 As shown, it specifically includes the following stages:

[0042] (1) Precharge Phase: When the precharge control signal prec is 0, switch P1 is turned on, precharging the LIOT node to vcc. Simultaneously, the nodes bla / blb in the latch circuit are precharged to vcc / 2. Then, the precharge control signal prec is pulled high (i.e., prec = 1), and the LIOT node and the bla / blb node are briefly in a floating state.

[0043] (2) "1" data transmission phase (i.e., IO=1): After the write enable signal WREN controls the switch tube N1 to turn on, the data input node IO and the LIOT node share charge. Since the LIOT node is precharged to the vcc potential in advance, the potentials at the source and drain of the switch tube N1 are equal, so the LIOT node still maintains the vcc potential unchanged. The column selection signal YST0 controls the switch tube N2 to turn on, and the LIOT node and the bla node share charge. The potential of the bla node will be higher than vcc / 2. Under the action of the latch circuit latch, the bla node is further pulled up to vcc, and the blb node is pulled down to the ground vss of the memory (for example, vss=0). Finally, after the row selection signal vwlp controls the transistor M0 to turn on, the blb node writes the data "0" opposite to the data "0" received by the IO node into the corresponding storage cell cell through the transistor M0 (i.e., IO=1, cell=0).

[0044] (3) Data transmission phase (IO=0): After the write enable signal WREN controls the switch tube N1 to turn on, the IO node and the LIOT node share charge. Since the LIOT node is precharged to the vcc potential in advance, the voltage difference between the source and drain of N1 is vcc, so the LIOT node is quickly pulled to vss. The column selection signal YST0 controls the switch tube N2 to turn on, and the LIOT node and the bla node share charge. The potential of the bla node will be lower than vcc / 2. Under the action of the latch circuit latch, the bla node is quickly pulled down to vss, and the blb node is pulled up to vcc. Finally, after the row selection signal vwlp controls the transistor M0 to turn on, the blb node writes the data "1" opposite to the data "0" received by the IO node into the cell through the transistor M0 (i.e., IO=0, cell=1).

[0045] As can be seen from the above description, when writing a "1" (i.e., IO = 1) in the existing solution, the voltage difference across N2 is only vcc / 2. This voltage difference is even smaller when the vcc voltage is lower. This prolongs the charge sharing time between the LIOT and bla nodes, ultimately slowing down the writing of the opposite data "0" into the memory cell. However, when writing a "0" (i.e., IO = 0), the voltage difference across the source and drain of switch N1 is vcc. LIO is quickly pulled low by leveraging the fast "0" transmission speed of switch N1 (which is an NMOS). Once N2 (also an NMOS, also with the fast "0" transmission speed) is turned on, the bla node is also quickly pulled to VSS, ultimately accelerating the writing of the opposite data "1" into the memory cell. This results in a significant difference in the speed of writing "0" and "1" data into the memory cell, impacting the performance of the memory device and making it difficult to meet the demands of higher-performance products.

[0046] Based on this, the present invention provides a data write circuit and a memory chip. While maintaining the original bit line sense amplifier circuit SA architecture, the single-ended transmission circuit coupled to the SA is converted into a dual-ended transmission circuit. Therefore, whether writing "0" data or "1" data to a storage array of a memory (such as a DRAM / PSRAM, etc.), the potential of the bit line node bla or blb inside the SA can be quickly pulled down, so that a larger voltage difference can be quickly separated between the bit line nodes bla and blb, and the data "0" or "1" can be written to the corresponding memory cell more quickly. The speed difference between writing "0" data and writing "1" data to the memory cell is greatly reduced (for example, the two are basically the same), thereby improving the performance of the memory chip (such as a DRAM / PSRAM, etc.) and meeting the demand for higher performance products.

[0047] The technical solutions proposed by the present invention are further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are all in a very simplified form and are not to exact scale, and are only used to facilitate and clearly illustrate the embodiments of the present invention.

[0048] Please refer to Figure 3 An embodiment of the present invention provides a data writing circuit, which includes a two-terminal transmission circuit 10, a column selection circuit YST and a bit line sense amplifier circuit SA coupled in sequence, and the bit line sense amplifier circuit SA is coupled to a storage array 20 of a memory.

[0049] The dual-end transmission circuit 10 has a single data input terminal (not shown). Figure 3 and two data outputs (not shown in Figure 3 ), a data input terminal of the two-port transmission circuit 10 is coupled to the data input node IO of the memory, one data output terminal of the two-port transmission circuit 10 is coupled to the first local input / output line node LIOT, and the other data output terminal of the two-port transmission circuit 10 is coupled to the second local input / output line node LIOB. The two-port transmission circuit 10 is configured to be turned on under the control of a write enable signal WREN and to transmit the data "0" or "1" received at the data input node IO to the first local input / output line node LIOT and the second local input / output line node LIOB in a complementary manner, respectively.

[0050] The column selection circuit YST can be coupled to a corresponding column address decoder (not shown), thereby transmitting the data of the first local input / output line node LIOT and the second local input / output line node LIOB to the complementary first bit line node bla and the second bit line node blb inside the bit line sense amplifier circuit SA according to the column selection signal YST0 output by the column address decoder.

[0051] The bit line sense amplifier circuit SA is used to write data externally input to the data input node IO or data opposite to the data received by the data input node IO into the corresponding storage cell cell in the storage array 20 through at least one of the first bit line node bla and the second bit line node blb. For example, when the data received by the IO node is "1" (i.e., IO=1), "0" is written into the storage cell cell; when the data received by the IO node is "0", "1" is written into the storage cell cell.

[0052] The data write circuit of this embodiment is integrated with the memory array 20 inside the memory chip. The memory can be any suitable memory such as dynamic random access memory (DRAM) or pseudo static random access memory (PSRAM). The memory array (DRAM array) 20 is used to store data. It is generally arranged in rows and columns with a number of memory cells. The memory cells in the same row are coupled to the same word line (WL) and the memory cells in the same column are coupled to the same bit line (BL). The storage of data in each memory cell only requires a capacitor C0 and a transistor M0. In one example, please refer to Figure 3 The bit line sense amplifier circuit SA is coupled to the drain of the transistor M0 via the second bit line node blb. In other examples, the bit line sense amplifier circuit SA may be coupled to the drain or source of the transistor M0 via the first bit line node bla, or the bit line sense amplifier circuit SA may be coupled to the transistor M0 via the first bit line node bla and the second bit line node blb.

[0053] It is noteworthy that the first local input / output line node LIOT and the second local input / output line node LIOB are a pair of nodes, each at a positive voltage level and an inverted voltage level (in other words, they are arranged in a pair and are complementary). The LIOB node and the LIOT node can provide a corresponding voltage difference, so that during a write operation of the memory, the column selection circuit YST can sense this voltage difference and transmit the data on the LIOB node and the LIOT node to the first bit line node bla and the second bit line node blb within the bit line sense amplifier circuit SA. The first bit line node bla and the second bit line node blb are also arranged in a pair and are complementary.

[0054] Optionally, the data writing circuit of this embodiment may further include a first pre-charging circuit 11 and a second pre-charging circuit 12 .

[0055] In which, the first pre-charging circuit 11 is coupled to the pre-charging control signal prec and the first local input / output line node LIOT, and is used to pre-charge the potential of the first local input / output line node LIOT to a first preset potential (for example, vcc) under the control of the pre-charging control signal prec before the two-terminal transmission circuit 10 is turned on for data transmission.

[0056] The second pre-charging circuit 12 is coupled to the pre-charging control signal prec and the second local input-output line node LIOB, and is used to pre-charge the potential of the second local input-output line node LIOB to a first preset potential (for example, vcc) under the control of the pre-charging control signal prec before the two-terminal transmission circuit 10 is turned on for transmitting data.

[0057] It should be understood that the two-terminal transmission circuit 10, the column selection circuit YST, the bit line sense amplifier circuit SA, the first pre-charging circuit 11 and the second pre-charging circuit 12 can be implemented using any appropriate circuit design, and the present invention does not make specific limitations on this.

[0058] In an example, see Figure 4A The two-terminal transmission circuit 10 includes a first switch transistor N11, a second switch transistor N12, and a third switch transistor N13. The gates of the first switch transistor N11 and the third switch transistor N13 are both coupled to a write enable signal WREN. The source of the first switch transistor N11 is coupled to a first local input / output line node LIOT. The drain of the first switch transistor N11 and the gate of the second switch transistor N12 are both coupled to a data input node IO. The drain of the second switch transistor N12 is coupled to a second local input / output line node LIOB. The source of the second switch transistor N12 is coupled to the drain of the third switch transistor N13. The source of the third switch transistor N13 is connected to ground VSS. Optionally, the first switch transistor N11, the second switch transistor N12, and the third switch transistor N13 are all n-type transistors (e.g., NMOS transistors or NPN transistors). Using n-type transistors (e.g., NMOS transistors) to construct the two-terminal transmission circuit 10 can simplify the circuit and reduce costs.

[0059] In this example, combine Figure 3 and Figure 4AWhen IO = 1, ION = 0, LIOB = 0, and the potential of the LIOT node remains unchanged at vcc. After the column select circuit YST is turned on, the LIOB node shares charge with the blb node, and the potential of the blb node is quickly pulled to vss, ultimately writing a "0" to the memory cell. When IO = 0, ION = 1, the LIOT node shares charge with the IO node, and the potential of the LIOT node is quickly pulled to vss. After the column select circuit YST is turned on, the LIOT node shares charge with the bla node, and the potential of the bla node is quickly pulled to vss, and the potential of the blb node is pulled to vcc, ultimately writing a "1" to the memory cell. Obviously, in this example, the fast "0" transmission characteristic of n-type transistors can be utilized to increase the speed of writing "0" and "1" to the memory cell, thereby ultimately improving the overall data writing speed of the memory. The LIOT node side uses the source-drain of N11 (ie, nmos) to write data into the IO node, and the LIOB node side uses the gate-drain of N12 (ie, nmos) to write data into the IO node.

[0060] In another example, see Figure 4B The two-terminal transmission circuit includes a first switch transistor N11, a second switch transistor N12, a third switch transistor N13, and an inverter circuit inv. The gate of the first switch transistor N11 and the input terminal of the inverter circuit inv are both coupled to the data input node IO. The drain of the first switch transistor N11 is coupled to the second local input / output line node LIOB. The gate of the second switch transistor N12 is coupled to the output terminal of the inverter circuit inv to receive data ION opposite to the data input node IO (for example, when IO=1, ION=0). The drain of the second switch transistor N12 is coupled to the first local input / output line node LIOT. The sources of the first switch transistor N11 and the second switch transistor N12 are both coupled to the drain of the third switch transistor N13. The gate of the third switch transistor N13 is coupled to the write enable signal WREN. The inverter circuit inv can be any suitable inversion logic circuit such as a NOT gate or an inverter. Optionally, the first switch tube N11, the second switch tube N12 and the third switch tube N13 are all n-type transistors (such as nmos tubes or npn transistors, etc.), thereby constructing a two-terminal transmission circuit 10 using n-type transistors (such as nmos), which can simplify the circuit and reduce costs.

[0061] In this example, combine Figure 3 and Figure 4BWhen IO = 1, ION = 0, LIOB = 0, and the potential of the LIOT node remains unchanged at vcc. After the column select circuit YST is turned on, the LIOB node shares charge with the blb node, and the potential of the blb node is quickly pulled to vss, ultimately writing a "0" into the memory cell. When IO = 0, ION = 1, LIOT = 0, the potential of the LIOB node remains unchanged at vcc. After the column select circuit YST is turned on, the LIOT node shares charge with the bla node, and the potential of the bla node is quickly pulled to vss, and the potential of the blb node is pulled to vcc, ultimately writing a "1" into the memory cell. Obviously, in this example, the characteristic of n-type transistors that they transmit "0" faster can also be used to increase the speed of writing "0" and "1" to the memory cells of the memory, thereby ultimately improving the overall data writing speed of the memory. The LIOT node side uses the gate-drain of N11 (ie, nmos) to write data into the IO node, and the LIOB side uses the gate-drain of N12 (ie, nmos) to write data into the IO node.

[0062] In an example, see Figure 6 The column selection circuit YST includes a first selection switch transistor N21 and a second selection switch transistor N22. The gate of the first selection switch transistor N21 is coupled to the column selection signal YST0, the source of the first selection switch transistor N21 is coupled to the first local input / output line node LIOT, and the drain of the first selection switch transistor N21 is coupled to the first bit line node bla. The gate of the second selection switch transistor N22 is coupled to the column selection signal YST0, the source of the second selection switch transistor N22 is coupled to the second local input / output line node LIOB, and the drain of the second selection switch transistor N22 is coupled to the second bit line node blb. Optionally, the first selection switch tube N21 and the second selection switch tube N22 are both n-type transistors (such as nmos tubes or npn transistors, etc.), thereby constructing a column selection circuit YST through n-type transistors (such as nmos), which can simplify the circuit and reduce costs, and can utilize the characteristic of n-type transistors that transmit "0" faster to increase the speed of writing "0" and writing "1" to the storage unit, thereby ultimately improving the overall data writing speed of the memory.

[0063] In an example, see Figure 6 The first pre-charging circuit 11 includes a first pre-charging switch transistor P1. The gate of the first pre-charging switch transistor P1 is coupled to the pre-charging control signal prec, the source of the first pre-charging switch transistor P1 is coupled to the first preset potential vcc, and the drain of the first pre-charging switch transistor P1 is coupled to the first local input / output line node LIOT. Optionally, the first pre-charging switch transistor P1 is a p-type transistor (e.g., a pmos transistor or a pnp transistor).

[0064] In an example, see Figure 6The second pre-charging circuit 12 includes a second pre-charging switch transistor P2. The gate of the second pre-charging switch transistor P2 is coupled to the pre-charging control signal prec. The source of the second pre-charging switch transistor P2 is coupled to the first preset potential vcc. The drain of the second pre-charging switch transistor P2 is coupled to the second local input / output line node LIOB. Optionally, the second pre-charging switch transistor P2 is a p-type transistor (e.g., a pmos transistor or a pnp transistor).

[0065] In an example, see Figure 3 The bit line sense amplifier circuit SA includes a latch circuit, coupled to the memory array 20 and the column select circuit YST, for providing a first bit line node bla and a second bit line node blb, and for distributing charge sharing between the bla node and the LIOT node, and between the blb node and the LOTB node, and amplifying the potential difference between the first bit line node bla and the second bit line node blb. The latch circuit latch can adopt any suitable circuit design. Alternatively, please refer to Figure 6 The latch circuit latch includes a cross-coupled first inverter inv1 and a second inverter inv2, an input end of the first inverter inv1 is coupled to the first bit line node bla and the output end of the second inverter inv2, and an input end of the second inverter inv2 is coupled to the second bit line node blb and the output end of the first inverter inv1.

[0066] The first inverter inv1 and the second inverter inv2 can adopt any suitable circuit design. For example, the first inverter inv1 includes a pmos transistor P5 and an nmos transistor N3, and the second inverter inv1 includes a pmos transistor P6 and an nmos transistor N4. The source of the pmos transistor P5 and the source of the pmos transistor P6 are both coupled to the first preset potential VCC, the source of the nmos transistor N3 and the source of the nmos transistor N4 are both coupled to the memory ground VSS, the drain of the pmos transistor P5 and the drain of the nmos transistor N3 are coupled to form the output end of the first inverter inv1, and are also coupled to the gate of the pmos transistor P6 and the gate of the nmos transistor N4. The gate of the pmos transistor P5 and the gate of the nmos transistor N3 are coupled to form the input end of the first inverter inv1, and are also coupled to the drain of the pmos transistor P6 and the drain of the nmos transistor N4. The drain of the pmos transistor P6 and the drain of the nmos transistor N4 are coupled to form the output end of the second inverter inv2. The gate of the pmos transistor P6 and the gate of the nmos transistor N4 are coupled to form the input end of the second inverter inv2.

[0067] Alternatively, refer to Figure 5, the bit line sense amplifier circuit SA also includes a third pre-charge circuit 13 and a fourth pre-charge circuit 14. Among them, the third pre-charge circuit 13 is coupled to the pre-charge control signal prec and the first bit line node bla, and is used to pre-charge the potential of the first bit line node bla to a second preset potential (for example, vcc / 2) under the control of the pre-charge control signal prec before the two-terminal transmission circuit 10 is turned on for transmitting data. The fourth pre-charge circuit 14 is coupled to the pre-charge control signal prec and the second bit line node blb, and is used to pre-charge the potential of the second bit line node blb to a second preset potential (for example, vcc / 2) under the control of the pre-charge control signal prec before the two-terminal transmission circuit 10 is turned on for transmitting data. In addition, the second preset potential can be half of the first preset potential, or other values. The third pre-charge circuit 13 and the fourth pre-charge circuit 14 can adopt any suitable circuit design.

[0068] In an example, see Figure 6 The third pre-charging circuit 13 includes a third pre-charging switch transistor P3. The gate of the third pre-charging switch transistor P3 is coupled to the pre-charging control signal prec. The source of the third pre-charging switch transistor P3 is coupled to the second preset potential vcc / 2. The drain of the third pre-charging switch transistor P3 is coupled to the first bit line node bla. Optionally, the third pre-charging switch transistor P2 is a p-type transistor (e.g., a pmos transistor or a pnp transistor).

[0069] In an example, see Figure 6 The fourth pre-charging circuit 14 includes a fourth pre-charging switch transistor P4. The gate of the fourth pre-charging switch transistor P4 is coupled to the pre-charging control signal prec. The source of the fourth pre-charging switch transistor P4 is coupled to the second preset potential vcc / 2. The drain of the fourth pre-charging switch transistor P4 is coupled to the second bit line node blb. Optionally, the fourth pre-charging switch transistor P4 is a p-type transistor (e.g., a pmos transistor or a pnp transistor).

[0070] It is worth noting that since the source and drain are made consistent in the MOS tube, the source can be used as the drain, and the drain can be used as the source. The low-voltage end of the NMOS transistor can be used as the source, and the high-voltage end of the PMOS tube can be used as the source. The naming of the source and drain has no effect on the circuit. The actual voltage of the MOS transistor is different, and the analysis of the circuit is also different. Therefore, in the above example description, the drain of N11~N13, N21~N22 and N3~N4, P1~P4 can be replaced with the source, and the source can also be replaced with the drain. In addition, in other embodiments, at least one of N11~N13, N21~N22 and N3~N4, P1~P4 can be replaced with a MOS tube of the inverse type of the above example, and its source and drain connection method can be adaptively changed according to the conductivity type of the MOS tube.

[0071] In this embodiment, when writing data to the memory array, the corresponding data "0" or "1" is input from the outside through the data input node IO of the memory, and after passing through the two-terminal transmission circuit 10 controlled by the write enable signal WREN, it is transmitted to the first local input / output line node LIOT and the second local input / output line node LIOB, and then after passing through the column selection circuit YST controlled by the column selection signal YST0, it is transmitted to the first bit line node bla and the second bit line node blb in the latch circuit latch in the bit line sense amplifier circuit SA; then, it passes through the transistor M0 coupled to the second bit line node blb of the latch circuit latch (which is controlled by the row selection control signal vwlp) and is written into the memory cell where M0 is located (that is, the conduction of the transistor M0 will change the amount of charge stored in the capacitor C0, thereby realizing the storage of the binary bit data "1" or "0").

[0072] Below Figure 4A and Figure 6 Take the combined example circuit as an example (wherein the first preset potential is vcc and the second preset potential is vcc / 2), and combine Figure 7 The signal timing shown is used to explain in detail the working process of the data writing circuit of this embodiment.

[0073] Please refer to Figure 6 and Figure 7 The working process of the data writing circuit in this example includes the following stages:

[0074] (1) Precharge Phase: When the precharge control signal prec is low (i.e., prec = 0), P1, P2, P3, and P4 are all turned on, and the LIOT and LIOB nodes are precharged to the first preset potential vcc. The bit line nodes bla and blb within the latch circuit latch are precharged to vcc / 2. Then, prec is pulled high (i.e., prec = 1), and the LIOT and LIOB nodes, as well as the bla and blb nodes, are briefly in a floating state.

[0075] (2) "1" data transmission stage: IO = 1, the write enable signal WREN controls the two-terminal transmission circuit 10 to be turned on (i.e. Figure 4A and Figure 4B Since the LIOT node is pre-charged to the first preset potential vcc, the potential of the IO node is the same as that of the LIOT node, so the LIOT node maintains the first preset potential vcc unchanged. The IO node can be discharged to the ground through the discharge path (e.g. Figure 4AThe LIOB node is pulled down by the channel formed by N12 and N13 being turned on, discharging the LIOB node. The LIOB node is quickly discharged from vcc to vss. The column select signal YST0 controls the column select circuit YST to turn on (i.e., N21 and N22 are turned on). The LIOB node shares charge with the blb node, and the potential of the blb node is quickly lowered to vss. Under the action of the latch circuit latch, the voltage difference between the bla node and the blb node will be opened more quickly, and the bla node will be further pulled up to vcc. Finally, after the row select control signal vwlp controls the transistor M0 to turn on (i.e., the word line WL coupled to the memory cell cell is turned on), the blb node writes "0" to the memory cell cell where M0 is located through the transistor M0.

[0076] (3) During the data transmission phase of “0”, IO=0, the write enable signal WREN controls the dual-end transmission circuit 10 to be turned on (i.e. Figure 4A and Figure 4B The discharge path from the IO node to the LIOB node is cut off, and the IO node and the LIOT node share charge. Since the LIOT node is pre-charged to the VCC potential in advance, the switch tube coupled to the LIOT node in the two-terminal transmission circuit 10 (for example, Figure 4A The voltage difference across N11 in the circuit is Vcc, so the LIOT node is quickly pulled to Vss by the IO node. Column select signal YST0 turns on column select circuit YST (i.e., N21 and N22). Charge is shared between the LIOT node and the bla node, causing the bla node's potential to fall below a second predetermined potential of Vcc / 2. Latch circuit latch quickly pulls bla node down to Vss, while blb node is pulled up to Vcc. Finally, row select control signal vwlp turns on transistor M0, and blb node writes a "1" to the memory cell where M0 resides.

[0077] In each of the above embodiments, since the blb node is coupled to the transistor M0 of the memory cell, the data written into the memory cell is opposite to the data received by the IO node. In other embodiments, when the transistor M0 of the memory cell is coupled via the bla node, the data written into the memory cell is the same as the data received by the IO node. It should be understood that when writing data to the entire memory array of the memory, data written from the bla node and the blb node are generally stored simultaneously. The data written into the corresponding memory cell via the bla node is positive (i.e., the data written into the memory cell is the same as the data received by the IO node), while the data written into the corresponding memory cell via the blb node is negative (i.e., the data written into the memory cell is opposite to the data received by the IO node). For example, the memory array of a memory (such as a DRAM or PSRAM) is divided into multiple sections in the row direction (the direction of the word lines WL) (which can be data segments or code segments, the smallest logical units that can be placed in the memory). In two adjacent sections, one is written via blb and the other is written via bla.

[0078] In summary, the data write circuit of the present invention, based on the architecture of the existing data write circuit, replaces the single-ended transmission circuit of the data input node IO coupled to the memory (such as DRAM, PSRAM, etc.) with a dual-ended transmission circuit (which has a single data input terminal and two data output terminals). Therefore, when the dual-ended transmission circuit is turned on, the potential of the first bit line node bla or the second bit line node blb can be quickly pulled down by quickly pulling down the potential of the LIOT node or the LIOB node of the memory, so that the first bit line node bla and the second bit line node blb can be quickly separated by a larger voltage difference, thereby improving the speed of writing "0" and writing "1" to the storage cell of the memory, and greatly reducing the speed difference when writing "0" and writing "1" to the memory (the speed of writing "0" and writing "1" can be made roughly the same), thereby improving the performance of the memory to meet the needs of higher performance products. Furthermore, the data write circuit of the present invention also has first to fourth precharging circuits, so that before writing "0" or "1" to the storage array of the memory, the first local input and output line node LIOT and the second local input and output line node LIOB can be precharged to a first preset potential through the first precharging circuit and the second precharging circuit, and the first bit line node bla and the second bit line node blb can be precharged to a second precharge position through the third precharging circuit and the fourth precharging circuit. When the two-terminal transmission circuit is turned on, the potential difference between the LIOT node and the LIOB node and the potential difference between the bla node and the blb node can be increased, so that the first bit line node bla and the second bit line node blb can quickly separate a larger voltage difference, thereby improving the speed of writing "0" and writing "1" to the storage cell of the memory, thereby improving the overall data writing speed of the memory. In addition, the two-terminal transmission circuit and column selection circuit in the data writing circuit of the present invention are both constructed using n-type transistors (such as NMOS), which can simplify the circuit and reduce costs. By utilizing the characteristic of n-type transistors that they can transmit "0" faster, the speed of writing "0" and "1" to the storage cells of the memory is increased, thereby ultimately improving the overall data writing speed and performance of the memory.

[0079] This embodiment further provides a memory chip, which includes the data writing circuit as described in any embodiment of the present invention. The memory chip can be any suitable memory chip such as DRAM, PSRAM, etc.

[0080] Since the memory chip of this embodiment adopts the data writing circuit of the present invention, the speed difference between writing "0" and writing "1" is small, and the performance is improved.

[0081] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure are within the scope of the technical solution of the present invention.

Claims

1. A data writing circuit, characterized in that: The invention comprises a two-terminal transmission circuit, a column selection circuit and a bit line sensing amplifier circuit coupled in sequence, wherein the bit line sensing amplifier circuit is coupled to a memory array of a memory; wherein: The two-terminal transmission circuit has a single data input terminal and two data output terminals, and the data input terminal is coupled to the data input node of the memory, and one of the data output terminals is coupled to the first local input / output line node, and the other data output terminal is coupled to the second local input / output line node. The two-terminal transmission circuit is configured to be turned on under the control of a write enable signal and transmit the data received by the data input node to the first local input / output line node and the second local input / output line node in a complementary form. The column gating circuit is used to transmit data of the first local input / output line node and the second local input / output line node to complementary first bit line nodes and second bit line nodes inside the bit line sense amplifier circuit; The bit line sense amplifier circuit is used to write the data or data opposite to the data into a corresponding memory cell in the memory array through at least one of the first bit line node and the second bit line node.

2. The data writing circuit according to claim 1, wherein: The two-terminal transmission circuit includes a first switch tube, a second switch tube, and a third switch tube, wherein the gate of the first switch tube and the gate of the third switch tube are both coupled to the write enable signal, the source of the first switch tube is coupled to the first local input / output line node, the drain of the first switch tube and the gate of the second switch tube are both coupled to the data input node, the drain of the second switch tube is coupled to the second local input / output line node, and the source of the second switch tube is coupled to the drain of the third switch tube; Alternatively, the two-terminal transmission circuit includes a first switch tube, a second switch tube, a third switch tube and an inversion circuit, the gate of the first switch tube and the input end of the inversion circuit are both coupled to the data input node, the drain of the first switch tube is coupled to the second local input / output line node, the gate of the second switch tube is coupled to the output end of the inversion circuit, the drain of the second switch tube is coupled to the first local input / output line node, the source of the first switch tube and the source of the second switch tube are both coupled to the drain of the third switch tube, and the gate of the third switch tube is coupled to the write enable signal.

3. The data writing circuit according to claim 2, wherein: The first switching tube, the second switching tube and the third switching tube are all n-type transistors.

4. The data writing circuit according to claim 1, wherein: The column gating circuit comprises: A first gating switch tube, having a gate coupled to a column gating signal, a source coupled to the first local input / output line node, and a drain coupled to the first bit line node; The second selection switch tube has a gate coupled to the column selection signal, a source coupled to the second local input / output line node, and a drain coupled to the second bit line node.

5. The data writing circuit according to claim 4, wherein: The first gate switch tube and the second gate switch tube are both n-type transistors.

6. The data writing circuit according to any one of claims 1 to 5, wherein: Also includes: a first pre-charging circuit coupled to a pre-charging control signal and the first local input / output line node, and configured to pre-charge the potential of the first local input / output line node to a first preset potential under the control of the pre-charging control signal before the two-terminal transmission circuit is turned on for data transmission; and / or, A second pre-charging circuit couples the pre-charging control signal and the second local input / output line node, and is used to pre-charge the potential of the second local input / output line node to the first preset potential under the control of the pre-charging control signal before the two-terminal transmission circuit is turned on for transmitting data.

7. The data writing circuit according to claim 6, wherein: The first pre-charging circuit includes a first pre-charging switch tube, wherein a gate of the first pre-charging switch tube is coupled to the pre-charging control signal, a source of the first pre-charging switch tube is coupled to the first preset potential, and a drain of the first pre-charging switch tube is coupled to the first local input / output line node; and / or, The second pre-charging circuit includes a second pre-charging switch tube, the gate of the second pre-charging switch tube is coupled to the pre-charging control signal, the source of the second pre-charging switch tube is coupled to the first preset potential, and the drain of the second pre-charging switch tube is coupled to the second local input and output line node.

8. The data writing circuit according to any one of claims 1 to 5 or 7, wherein: The bit line sense amplifier circuit includes a latch circuit coupled to the memory array and the column selection circuit, configured to provide the first bit line node and the second bit line node, and to perform charge sharing between the first bit line node and the first local input / output line node and between the second bit line node and the second local input / output line node, respectively, and to amplify the voltage difference between the first bit line node and the second bit line node.

9. The data writing circuit according to claim 8, wherein: The latch circuit includes a first inverter and a second inverter that are cross-coupled. The input of the first inverter is coupled to the first bit line node and the output of the second inverter. The input of the second inverter is coupled to the second bit line node and the output of the first inverter.

10. The data writing circuit according to claim 8, wherein: The bit line sense amplifier circuit further includes: a third precharge circuit coupled to a precharge control signal and the first bit line node, and configured to precharge the potential of the first bit line node to a second preset potential under the control of the precharge control signal before the two-terminal transmission circuit is turned on for data transmission; and / or A fourth precharge circuit couples the precharge control signal and the second bit line node, and is used to precharge the potential of the second bit line node to the second preset potential under the control of the precharge control signal before the two-terminal transmission circuit is turned on for transmitting data.

11. The data writing circuit according to claim 10, wherein: The third pre-charging circuit includes a third pre-charging switch tube, wherein a gate of the third pre-charging switch tube is coupled to the pre-charging control signal, a source of the third pre-charging switch tube is coupled to the second preset potential, and a drain of the third pre-charging switch tube is coupled to the first bit line node; and / or, The fourth pre-charging circuit includes a fourth pre-charging switch tube, the gate of the fourth pre-charging switch tube is coupled to the pre-charging control signal, the source of the fourth pre-charging switch tube is coupled to the second preset potential, and the drain of the fourth pre-charging switch tube is coupled to the second bit line node.

12. A memory chip, characterized in that: The data writing circuit comprises the data writing circuit according to any one of claims 1 to 11.

Images