Three-dimensional memory device, operation circuit and operation method

Abstract

The invention provides a three-dimensional memory device, an operation circuit and an operation method. The three-dimensional memory device comprises a three-dimensional memory array, an encoding circuit, a sensing circuit and a processing circuit. The three-dimensional memory array includes a plurality of two-dimensional memory arrays for receiving a plurality of input voltages and outputting a plurality of output currents. Each two-dimensional memory array includes a plurality of memory cells and a plurality of array edges. The coding circuit and the sensing circuit are coupled to the plurality of array sides and are respectively used for inputting a plurality of input voltages to the two-dimensional memory array and receiving a plurality of output currents from the two-dimensional memory array. The processing circuit is coupled to the coding circuit and the sensing circuit, and is used for performing in-memory operation according to a plurality of input voltages and a plurality of output currents. When one of the plurality of array sides is used for receiving a plurality of input voltages, the other of the plurality of array sides is used for outputting a plurality of output currents, and the one of the plurality of array sides is not parallel to the other of the plurality of array sides.

Description

Technical Field

[0001] The present disclosure relates to in-memory computing technology for a three-dimensional memory device, and more particularly to a three-dimensional memory device, computing circuit, and computing method that utilize input voltages and output currents of the three-dimensional memory device in different directions to perform in-memory computing. Background Art

[0002] With the advancement of memory technology and the increasing computational power required by artificial intelligence (AI), three-dimensional memory devices with lower per-bit costs have gradually replaced traditional planar memory. Furthermore, to address the significant time and energy required by processors to read data from memory, in-memory computing (IMC) technology has gained increasing attention. IMC allows operations to be performed directly in memory, thereby improving the speed and efficiency of data retrieval.

[0003] The memory array in a three-dimensional memory device has a large number of memory cells, each with a corresponding conductance. In-memory operations are performed by outputting a voltage to the memory array and sensing the resulting current. However, previous in-memory operation methods did not account for voltage drops across the wires within the memory array, resulting in inaccurate calculation results. Larger memory arrays lead to greater calculation errors. To eliminate errors caused by voltage drops across the wires, a method has emerged that uses multiple matrices to perform in-memory operations.

[0004] However, using multiple matrices to perform operations significantly increases the amount of memory required for operations, and the improvement efficiency for the aforementioned phenomenon is still not ideal. Therefore, how to effectively improve the error caused by voltage drop on the wires on memory operations is one of the issues in this field. Summary of the Invention

[0005] The present disclosure provides a three-dimensional memory device comprising a three-dimensional memory array, an encoding circuit, a sensing circuit, and a processing circuit. The three-dimensional memory array comprises a plurality of two-dimensional memory arrays for receiving a plurality of input voltages and outputting a plurality of output currents. Each two-dimensional memory array comprises a plurality of memory cells, and each two-dimensional memory array comprises four array edges. The encoding circuit is coupled to the four array edges for inputting a plurality of input voltages to the plurality of two-dimensional memory arrays. The sensing circuit is coupled to the four array edges for receiving a plurality of output currents from the plurality of two-dimensional memory arrays. The processing circuit is coupled to the encoding circuit and the sensing circuit for performing in-memory operations based on the plurality of input voltages and the plurality of output currents. The four array edges comprise a plurality of array edges, and when one of the plurality of array edges is used to receive a plurality of input voltages, another of the plurality of array edges is used to output a plurality of output currents, and the one of the plurality of array edges and the another are not parallel to each other.

[0006] In some embodiments of a three-dimensional memory device, the encoding circuit includes a first encoding circuit and a second encoding circuit. The first encoding circuit and the second encoding circuit are configured to input a plurality of input voltages to the plurality of two-dimensional memory arrays via a first array side and a second array side, respectively, of a plurality of array sides. The first array side is parallel to and different from the second array side.

[0007] In some embodiments of a three-dimensional memory device, the sensing circuit includes a first sensing circuit and a second sensing circuit. The first sensing circuit and the second sensing circuit are configured to receive a plurality of output currents from a plurality of two-dimensional memory arrays via a first array edge and a second array edge, respectively, of a plurality of array edges. The first array edge is parallel to and different from the second array edge.

[0008] In some embodiments of a three-dimensional memory device, the encoding circuit includes a first encoding circuit and a second encoding circuit, and the sensing circuit includes a first sensing circuit and a second sensing circuit. The first encoding circuit and the second encoding circuit are configured to input a plurality of input voltages to a plurality of two-dimensional memory arrays via a first array side and a second array side, respectively, of a plurality of array sides. The first sensing circuit and the second sensing circuit are configured to receive a plurality of output currents from the plurality of two-dimensional memory arrays via a third array side and a fourth array side, respectively, of the plurality of array sides. The first array side is parallel to and different from the second array side, and the third array side is parallel to and different from the fourth array side.

[0009] In some embodiments of a three-dimensional memory device, the encoding circuit includes a first encoding circuit and a second encoding circuit, and the sensing circuit includes a first sensing circuit and a second sensing circuit. The first encoding circuit is configured to input a plurality of first input voltages to the plurality of two-dimensional memory arrays via a first array edge of the plurality of array edges, and the second encoding circuit is configured to input a plurality of second input voltages to the plurality of two-dimensional memory arrays via a second array edge of the plurality of array edges. The first sensing circuit is configured to receive a plurality of first output currents from the plurality of two-dimensional memory arrays via a third array edge of the plurality of array edges, and the second sensing circuit is configured to receive a plurality of second output currents from the plurality of two-dimensional memory arrays via a fourth array edge of the plurality of array edges. The first array edge is not parallel to the second array edge, the third array edge is not parallel to the fourth array edge, and the plurality of first input voltages are not equal to the plurality of second input voltages.

[0010] In some embodiments of a three-dimensional memory device, the encoding circuit includes four sub-encoding circuits, and the sensing circuit includes four sub-sensing circuits. The four sub-encoding circuits are respectively coupled to multiple array edges of each two-dimensional memory array, and the four sub-sensing circuits are respectively coupled to multiple array edges of each two-dimensional memory array. When one of the four sub-encoding circuits inputs multiple input voltages to the multiple two-dimensional memory arrays, one of the four sub-sensing circuits is configured to receive multiple output currents from the multiple two-dimensional memory arrays. The array edge to which one of the four sub-encoding circuits is coupled is not parallel to the array edge to which one of the four sub-sensing circuits is coupled.

[0011] In some embodiments of the three-dimensional memory device, the processing circuit is further configured to control electrical connection between the one of the four sub-encoding circuits and the one of the four sub-sensing circuits and the three-dimensional memory array, and to control electrical disconnection between the other three of the four sub-encoding circuits and the other three of the four sub-sensing circuits and the three-dimensional memory array.

[0012] The present disclosure provides an arithmetic circuit coupled to a three-dimensional memory array comprising a plurality of two-dimensional memory arrays, each of which comprises four array edges. The arithmetic circuit comprises an encoding circuit, a sensing circuit, and a processing circuit. The encoding circuit is coupled to the four array edges for inputting a plurality of input voltages to the plurality of two-dimensional memory arrays. The sensing circuit is coupled to the four array edges for receiving a plurality of output currents from the plurality of two-dimensional memory arrays. The processing circuit is coupled to the encoding circuit and the sensing circuit for performing in-memory operations based on the plurality of input voltages and the plurality of output currents. The four array edges comprise a plurality of array edges, and when the encoding circuit inputs a plurality of input voltages to one of the plurality of array edges, the sensing circuit receives a plurality of output currents from another of the plurality of array edges, and the one of the plurality of array edges and the other are not parallel to each other.

[0013] In some embodiments of the computing circuit, the encoding circuit includes a first encoding circuit and a second encoding circuit. The first encoding circuit and the second encoding circuit are configured to input a plurality of input voltages to a plurality of two-dimensional memory arrays via a first array side and a second array side, respectively, of a plurality of array sides. The first array side is parallel to and different from the second array side.

[0014] In some embodiments of the computing circuit, the sensing circuit includes a first sensing circuit and a second sensing circuit. The first sensing circuit and the second sensing circuit are configured to receive a plurality of output currents from a plurality of two-dimensional memory arrays via a first array edge and a second array edge, respectively, of a plurality of array edges. The first array edge is parallel to and different from the second array edge.

[0015] In some embodiments of the computing circuit, the encoding circuit includes a first encoding circuit and a second encoding circuit, and the sensing circuit includes a first sensing circuit and a second sensing circuit. The first encoding circuit and the second encoding circuit are configured to input a plurality of input voltages to a plurality of two-dimensional memory arrays via a first array side and a second array side, respectively, of a plurality of array sides. The first sensing circuit and the second sensing circuit are configured to receive a plurality of output currents from the plurality of two-dimensional memory arrays via a third array side and a fourth array side, respectively, of the plurality of array sides. The first array side is parallel to and different from the second array side, and the third array side is parallel to and different from the fourth array side.

[0016] In some embodiments of the computing circuit, the encoding circuit includes a first encoding circuit and a second encoding circuit, and the sensing circuit includes a first sensing circuit and a second sensing circuit. The first encoding circuit is configured to input a plurality of first input voltages to the plurality of two-dimensional memory arrays via a first array edge of the plurality of array edges, and the second encoding circuit is configured to input a plurality of second input voltages to the plurality of two-dimensional memory arrays via a second array edge of the plurality of array edges. The first sensing circuit is configured to receive a plurality of first output currents from the plurality of two-dimensional memory arrays via a third array edge of the plurality of array edges, and the second sensing circuit is configured to receive a plurality of second output currents from the plurality of two-dimensional memory arrays via a fourth array edge of the plurality of array edges. The first array edge is not parallel to the second array edge, the third array edge is not parallel to the fourth array edge, and the plurality of first input voltages are not equal to the plurality of second input voltages.

[0017] In some embodiments of the computing circuit, the encoding circuit includes four sub-encoding circuits, and the sensing circuit includes four sub-sensing circuits. The four sub-encoding circuits are respectively coupled to multiple array edges of each two-dimensional memory array, and the four sub-sensing circuits are respectively coupled to multiple array edges of each two-dimensional memory array. When one of the four sub-encoding circuits inputs multiple input voltages to the multiple two-dimensional memory arrays, one of the four sub-sensing circuits is configured to receive multiple output currents from the multiple two-dimensional memory arrays. The array edge to which one of the four sub-encoding circuits is coupled is not parallel to the array edge to which one of the four sub-sensing circuits is coupled.

[0018] In some embodiments of the computing circuit, the processing circuit is further configured to control electrical connection between one of the four sub-encoding circuits and one of the four sub-sensing circuits and the three-dimensional memory array, and to control electrical disconnection between the other three of the four sub-encoding circuits and the other three of the four sub-sensing circuits and the three-dimensional memory array.

[0019] The present disclosure provides a calculation method applicable to a three-dimensional memory device. The three-dimensional memory device includes a three-dimensional memory array, an encoding circuit, a sensing circuit, and a processing circuit, and the three-dimensional memory array includes multiple two-dimensional memory arrays. The calculation method includes: inputting multiple input voltages to the multiple two-dimensional memory arrays through the encoding circuit; receiving multiple output currents from the multiple two-dimensional memory arrays through the sensing circuit; and performing in-memory calculations based on the multiple input voltages and the multiple output currents through the processing circuit. Each two-dimensional memory array includes four array edges, and the four array edges include multiple array edges. When one of the multiple array edges is used to receive multiple input voltages, another one of the multiple array edges is used to output multiple output currents, and the one of the multiple array edges and the other one are not parallel to each other.

[0020] In some embodiments of the computing method, inputting a plurality of input voltages to a plurality of two-dimensional memory arrays through an encoding circuit includes: inputting the plurality of input voltages to the plurality of two-dimensional memory arrays through a first array side of a plurality of array sides through a first encoding circuit of the encoding circuit; and inputting the plurality of input voltages to the plurality of two-dimensional memory arrays through a second array side of the plurality of array sides through a second encoding circuit of the encoding circuit, wherein the first array side is parallel to and different from the second array side.

[0021] In some embodiments of the computing method, receiving a plurality of output currents from a plurality of two-dimensional memory arrays through a sensing circuit includes: receiving the plurality of output currents from the plurality of two-dimensional memory arrays through a first array side of a plurality of array sides through a first sensing circuit of the sensing circuit; and receiving the plurality of output currents from the plurality of two-dimensional memory arrays through a second array side of the plurality of array sides through a second sensing circuit of the sensing circuit, wherein the first array side is parallel to and different from the second array side.

[0022] In some embodiments of the computing method, inputting multiple input voltages to multiple two-dimensional memory arrays via an encoding circuit includes: inputting the multiple input voltages to the multiple two-dimensional memory arrays via a first array side of multiple array sides via a first encoding circuit of the encoding circuit; and inputting the multiple input voltages to the multiple two-dimensional memory arrays via a second array side of multiple array sides via a second encoding circuit of the encoding circuit. Receiving multiple output currents from the multiple two-dimensional memory arrays via a sensing circuit includes: receiving the multiple output currents from the multiple two-dimensional memory arrays via a third array side of the multiple array sides via a first sensing circuit of the sensing circuit; and receiving the multiple output currents from the multiple two-dimensional memory arrays via a fourth array side of the multiple array sides via a second sensing circuit of the sensing circuit. The first array side is parallel to and different from the second array side, and the third array side is parallel to and different from the fourth array side.

[0023] In some embodiments of the computing method, inputting multiple input voltages to multiple two-dimensional memory arrays via an encoding circuit includes: inputting multiple first input voltages to the multiple two-dimensional memory arrays via a first array edge of multiple array edges via a first encoding circuit of the encoding circuit; and inputting multiple second input voltages to the multiple two-dimensional memory arrays via a second array edge of multiple array edges via a second encoding circuit of the encoding circuit. Receiving multiple output currents from the multiple two-dimensional memory arrays via a sensing circuit includes: receiving multiple first output currents from the multiple two-dimensional memory arrays via a third array edge of the multiple array edges via a first sensing circuit of the sensing circuit; and receiving multiple second output currents from the multiple two-dimensional memory arrays via a fourth array edge of the multiple array edges via a second sensing circuit of the sensing circuit. The first array edge is not parallel to the second array edge, the third array edge is not parallel to the fourth array edge, and the multiple first input voltages are not equal to the multiple second input voltages.

[0024] In some embodiments of the computing method, the encoding circuit includes four sub-encoding circuits respectively coupled to multiple array edges of each two-dimensional memory array, and the sensing circuit includes four sub-sensing circuits respectively coupled to multiple array edges of each two-dimensional memory array. Inputting multiple input voltages to the multiple two-dimensional memory arrays via the encoding circuit includes inputting the multiple input voltages to the multiple two-dimensional memory arrays via one of the four sub-encoding circuits. Receiving multiple output currents from the multiple two-dimensional memory arrays via the sensing circuit includes receiving the multiple output currents from the multiple two-dimensional memory arrays via one of the four sub-sensing circuits. The array edge to which one of the four sub-encoding circuits is coupled is not parallel to the array edge to which one of the four sub-sensing circuits is coupled.

[0025] Through the three-dimensional memory device, operation circuit and operation method of the present disclosure, multiple input voltages and multiple output currents can be used to perform in-memory operations to overcome the impact of voltage drops on the wires inside the memory array on the operations, thereby improving the accuracy of in-memory operations. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] To make the above and other objects, features, advantages and embodiments of the present disclosure more apparent and understandable, the accompanying drawings are described as follows:

[0027] Figure 1 is a schematic perspective view of a three-dimensional memory device according to some embodiments of the present disclosure;

[0028] Figure 2A is a schematic diagram of an encoding circuit, a sensing circuit, and a two-dimensional memory array according to some examples;

[0029] Figure 2B A circuit diagram of a two-dimensional memory array according to some embodiments of the present disclosure is shown;

[0030] Figure 2C A circuit diagram of a two-dimensional memory array according to some other embodiments of the present disclosure;

[0031] Figure 2D is a circuit diagram of a two-dimensional memory array according to some further embodiments of the present disclosure;

[0032] Figure 3 is a schematic diagram illustrating a connection method between a two-dimensional memory array and surrounding circuits according to some embodiments of the present disclosure;

[0033] Figure 4 is a schematic diagram illustrating a connection method between a two-dimensional memory array and surrounding circuits according to some embodiments of the present disclosure;

[0034] Figure 5 is a schematic diagram illustrating a connection method between a two-dimensional memory array and surrounding circuits according to some embodiments of the present disclosure;

[0035] Figure 6A is a schematic diagram illustrating a connection method between a two-dimensional memory array and surrounding circuits according to some embodiments of the present disclosure;

[0036] Figure 6B is a schematic diagram illustrating a connection method between a two-dimensional memory array and surrounding circuits according to some embodiments of the present disclosure;

[0037] Figure 7A schematic diagram illustrating a connection method between a two-dimensional memory array and surrounding circuits according to some embodiments of the present disclosure; and

[0038] Figure 8 The flowchart of the operation method is shown according to some embodiments of the present disclosure.

[0039] Description of reference numerals:

[0040] 100: Three-dimensional memory device

[0041] 110: Three-dimensional memory array

[0042] 111: Two-dimensional memory array

[0043] 120: Encoding circuit

[0044] 120_1~120_4: Sub-coding circuit

[0045] 130: Sensing circuit

[0046] 130_1 to 130_4: Sub-sensing circuit

[0047] 140: Processing circuit

[0048] 800: Calculation method

[0049] S810, S820, S830: Steps

[0050] G11~G13: memory unit

[0051] G21~G23: Memory unit

[0052] G31~G33: Memory unit

[0053] I, I1~I6: output current

[0054] V, V1~V6: input voltage

[0055] X, Y, Z: direction DETAILED DESCRIPTION

[0056] The following will illustrate the embodiments of the present disclosure with reference to the accompanying drawings. In the drawings, the same reference numerals represent the same or similar elements or method flows.

[0057] In this disclosure, when an element is referred to as "connected", it may refer to "electrical connection" or "optical connection", and when an element is referred to as "coupled", it may refer to "electrical coupling" or "optical coupling". "Connected" or "coupled" can also be used to indicate the coordinated operation or interaction between two or more elements. Unless otherwise specified in the text, "one" and "the" may refer to a single or multiple elements. It will be further understood that "comprising", "including", "having" and similar words used herein indicate the features, regions, integers, steps, operations, elements and / or components described therein, but do not exclude the described or additional one or more other features, regions, integers, steps, operations, elements, components and / or groups thereof.

[0058] Figure 1 FIG. 1 is a perspective diagram of a three-dimensional memory device 100 according to some embodiments of the present disclosure. In some embodiments, the three-dimensional memory device 100 includes a three-dimensional memory array 110 , an encoding circuit 120 , a sensing circuit 130 , and a processing circuit 140 .

[0059] The three-dimensional memory array 110 is coupled between the encoding circuit 120 and the sensing circuit 130 to receive an input voltage V from the encoding circuit 120 and transmit an output current I to the sensing circuit 130. In some embodiments, the three-dimensional memory array 110 includes a plurality of two-dimensional memory arrays 111. The planes of these two-dimensional memory arrays 111 are along a planar direction (e.g., Figure 1 The two-dimensional memory arrays 111 extend in a plane direction formed by directions X and Z in the image, and the two-dimensional memory arrays 111 extend in another specific direction (for example, Figure 1 The two members are arranged in the direction Y) to form a three-dimensional structure.

[0060] In some embodiments, the three-dimensional memory array 110 can be implemented by a volatile memory (e.g., dynamic random access memory (DRAM), static random access memory (SRAM)), a non-volatile memory (e.g., magnetoresistive random access memory (MRAM), ferroelectric random access memory (FeRAM)), or a combination thereof.

[0061] In some embodiments, each two-dimensional memory array 111 includes a plurality of memory cells (eg, Figure 1The internal structures of these memory cells will be described in detail in the following paragraphs.

[0062] The encoding circuit 120 is coupled to each 2D memory array 111 in the 3D memory array 110 and the processing circuit 140 to input an input voltage V to each 2D memory array 111 to facilitate the processing circuit 140 to perform in-memory operations.

[0063] The sensing circuit 130 is coupled to each 2D memory array 111 in the 3D memory array 110 and the processing circuit 140 to receive the output current I from each 2D memory array 111 so as to facilitate the processing circuit 140 to perform in-memory operations.

[0064] The processing circuit 140 is coupled to the encoding circuit 120 and the sensing circuit 130 for performing an in-memory operation on the three-dimensional memory array 110 according to the input voltage V and the output current I.

[0065] Since each two-dimensional memory array 111 is coupled to the encoding circuit 120 and the sensing circuit 130 in a similar manner, for the sake of brevity, the connection relationship between one of the two-dimensional memory arrays 111 and the encoding circuit 120 and the sensing circuit 130 is described below. Figure 2A Schematic diagrams of the encoding circuit 120, the sensing circuit 130, and the two-dimensional memory array 111 are shown according to some embodiments. In some embodiments, the two-dimensional memory array 111 includes memory cells G11-G13, G21-G23, and G31-G33, and the memory cells G11-G13, G21-G23, and G31-G33 are arranged in a square array having three rows and three columns. Therefore, the two-dimensional memory array 111 is a square array having four array sides, where the four array sides include multiple array sides. In other words, the two-dimensional memory array 111 includes an array side consisting of memory cells G11-G13, an array side consisting of memory cells G31-G33, an array side consisting of memory cells G11, G21, and G31, and an array side consisting of memory cells G13, G23, and G33.

[0066] It should be noted that for the sake of simplicity of the diagram, the two-dimensional memory array 111 is Figure 2A is depicted as an array of nine memory cells having three rows and three columns. However, Figure 2A The examples are merely illustrative and not intended to limit the present disclosure. Other numbers of memory cells are within the scope of the present disclosure. In some embodiments, the two-dimensional memory array 111 may be an array having 256 rows and 256 columns and consisting of 65,536 memory cells.

[0067] For details on the implementation of memory cells G11 to G13, G21 to G23, and G31 to G33, please refer to Figure 2B to Figure 2D . Figure 2B to Figure 2D FIG. 1 is a circuit diagram of a two-dimensional memory array 111 according to some different embodiments of the present disclosure.

[0068] In some embodiments, the memory cells G11-G13, G21-G23, and G31-G33 can be connected by horizontal and vertical conductive lines to form a cross-point type array. Figure 2B In the embodiment, memory cells G11-G13 and memory cells G21-G23, G31-G33 (not labeled for simplicity) are respectively coupled to adjacent memory cells via lateral and vertical conductive lines (for receiving voltage or outputting current), and each memory cell (i.e., each intersection of the cross-point array) is implemented as a circuit including a resistor.

[0069] In other embodiments, the memory cells G11-G13, G21-G23 and G31-G33 can also be connected by horizontal and vertical conductive lines, and their conduction states can be controlled by word lines to form a logical NOR type array. Figure 2C In the embodiment, memory cells G11-G13 and memory cells G21-G23, G31-G33 (not labeled for simplicity) are coupled to adjacent memory cells via lateral and vertical conductive lines (for receiving voltage or outputting current), and each memory cell is implemented as a circuit including a resistor and a capacitor. Furthermore, the control terminals of memory cells in the same column of the memory array are connected to a word line.

[0070] and Figure 2C Similarly, in Figure 2D In the embodiment, the memory cells G11-G13 and the memory cells G21-G23, G31-G33 also form a logical OR array. The difference is that, Figure 2D Each memory cell in the CMOS is implemented as a circuit including an inductor and a capacitor.

[0071] It should be noted that Figure 2B to Figure 2D The implementations of memory cells G11-G13, G21-G23, and G31-G33 are merely examples and are not intended to limit this disclosure. As long as the circuit structure of the memory cell satisfies the conditions of a cross-point array or a logical-OR array, other memory cell implementations are within the scope of this disclosure.

[0072] Please refer again Figure 2A . Figure 2AThe example shown in FIG is often implemented as a common circuit connection method. Specifically, in the three-dimensional memory device 100, the encoding circuit 120 is connected to one array side of the two-dimensional memory array 111, and the sensing circuit 130 is also connected to the other array side of the two-dimensional memory array 111. Figure 2A For example, the encoding circuit 120 is connected to the left array edge of the two-dimensional memory array 111 to transmit the input voltages V1-V3 to the memory cells G11, G21, and G31, respectively. The sensing circuit 130 is connected to the bottom array edge of the two-dimensional memory array 111 to receive the output currents I1-I3 from the memory cells G31-G33, respectively.

[0073] In operation, when input voltages V1-V3 are input to the two-dimensional memory array 111, the two-dimensional memory array 111 generates a portion of the output current I1 based on the input voltage V1 and the impedance in the path between the memory cells G11, G21, and G31; another portion of the output current I1 based on the input voltage V2 and the impedance in the path between the memory cells G21 and G31; and yet another portion of the output current I1 based on the input voltage V3 and the impedance in the path between the memory cell G31. The sum of these three portions is the output current I1. Similarly, the two-dimensional memory array 111 generates a portion of the output current I2 based on the input voltage V1 and the impedance along the path of the memory cells G11, G12, G22, and G32; generates another portion of the output current I2 based on the input voltage V2 and the impedance along the path of the memory cells G21, G22, and G32; and generates yet another portion of the output current I2 based on the input voltage V3 and the impedance along the path of the memory cells G31 and G32. The sum of these three portions is the output current I2, and so on.

[0074] However, because the encoding circuit 120 and the sensing circuit 130 are each coupled to only one side of the two-dimensional memory array 111, the magnitude of the output currents I1-I3 is solely related to the impedance between the input voltages V1-V3 and the output currents I1-I3. In other words, when the input voltages V1-V3 are input to the two-dimensional memory array 111 from other directions, the output currents I1-I3 output from the two-dimensional memory array 111 may vary due to the different current paths, resulting in inaccurate calculations within the memory.

[0075] In order to improve the aforementioned problems, the present disclosure proposes various embodiments. Figure 3Schematic diagram illustrating the connections between a two-dimensional memory array 111 and surrounding circuits according to some embodiments of the present disclosure. For simplicity, the input voltages V1-V3 input to the array side are collectively referred to as input voltage V, and the output currents I1-I3 output from the array side are collectively referred to as output current I.

[0076] exist Figure 3 In the embodiment, the encoding circuit 120 is coupled to the four array sides of the two-dimensional memory array 111, and the sensing circuit 130 is also coupled to the four array sides of the two-dimensional memory array 111. The two-dimensional memory array 111 can receive an input voltage V from the encoding circuit 120 through one of the four array sides at a time, and output an output current I to the sensing circuit 130 through another of the four array sides.

[0077] It is worth noting that, in order to allow current to flow through the memory cells in the two-dimensional memory array 111, the array side receiving the input voltage V and the array side transmitting the output current I are not parallel to each other. For example, when the input voltage V is input from the left array side of the two-dimensional memory array 111, the output current I can be output from the top array side or the bottom array side of the two-dimensional memory array 111. Therefore, the sensing circuit 130 can obtain the output current I under different current path conditions, thereby enabling the processing circuit 140 to calculate a more objective in-memory operation result (e.g., by calculating the average, median, or other statistical methods) based on the data of multiple input voltages V and multiple output currents I.

[0078] In addition, the encoding circuit 120 and the sensing circuit 130 of the present disclosure can be implemented by multiple sub-circuits to simplify the wiring in the three-dimensional memory array 110. Figures 4 to 7 , Figures 4 to 7 Schematic diagrams illustrating the connection between a two-dimensional memory array 111 and surrounding circuits according to various embodiments of the present disclosure.

[0079] exist Figure 4 In this embodiment, sensing circuit 130 includes sub-sensing circuits 130_1 and 130_2. Sub-sensing circuits 130_1 and 130_2 are disposed on opposite sides of the two-dimensional memory array 111 and connected to two parallel and different array edges. In operation, when encoding circuit 120 inputs input voltages V1-V3 to the left array edge of the two-dimensional memory array 111, sub-sensing circuit 130_1 can receive output currents I1-I3 from the top array edge of the two-dimensional memory array 111, and sub-sensing circuit 130_2 can receive output currents I1-I3 from the bottom array edge of the two-dimensional memory array 111. Therefore, processing circuit 140 can obtain output current data from at least two different current paths.

[0080] exist Figure 5 In this embodiment, encoding circuit 120 includes sub-encoding circuits 120_1 and 120_2. Sub-encoding circuits 120_1 and 120_2 are disposed on opposite sides of a two-dimensional memory array 111 and connected to two parallel and different array edges. In operation, sub-encoding circuit 120_1 can input voltages V1-V3 to the left array edge of the two-dimensional memory array 111, while sub-encoding circuit 120_2 can input voltages V1-V3 to the right array edge of the two-dimensional memory array 111. In this case, sensing circuit 130 receives output currents I1-I3 from the bottom array edge of the two-dimensional memory array 111. Therefore, processing circuit 140 can obtain output current data from at least two different current paths.

[0081] exist Figure 6A In this embodiment, the encoding circuit 120 includes sub-encoding circuits 120_1 and 120_2, and the sensing circuit 130 includes sub-sensing circuits 130_1 and 130_2. The sub-encoding circuits 120_1 and 120_2 are respectively disposed on opposite sides of the two-dimensional memory array 111 and connected to two parallel and different array edges. The sub-sensing circuits 130_1 and 130_2 are respectively disposed on the other opposite sides of the two-dimensional memory array 111 and connected to two other parallel and different array edges. In operation, sub-encoding circuit 120_1 can input voltages V1-V3 to the left side of two-dimensional memory array 111, while sub-encoding circuit 120_2 can input voltages V1-V3 to the right side of two-dimensional memory array 111. In this case, sub-sensing circuit 130_1 can receive output currents I1-I3 from the top side of two-dimensional memory array 111, and sub-sensing circuit 130_2 can receive output currents I1-I3 from the bottom side of two-dimensional memory array 111. Therefore, processing circuit 140 can obtain output current data from at least four different current paths.

[0082] Figure 6B An embodiment similar to Figure 6AThe difference between the embodiments is that sub-encoding circuits 120_1 and 120_2 are respectively disposed on two adjacent sides of the two-dimensional memory array 111 and are respectively connected to two adjacent (i.e., non-parallel) array edges. Furthermore, sub-sensing circuits 130_1 and 130_2 are respectively disposed on two other adjacent sides of the two-dimensional memory array 111 and are respectively connected to two other adjacent (i.e., non-parallel) array edges. In operation, sub-encoding circuit 120_1 can input voltages V1-V3 to the left array edge of the two-dimensional memory array 111, while sub-encoding circuit 120_2 can input voltages V4-V6 to the top array edge of the two-dimensional memory array 111. In this case, sub-sensing circuit 130_1 can receive output currents I1-I3 from the bottom array edge of the two-dimensional memory array 111, and sub-sensing circuit 130_2 can receive output currents I4-I6 from the right array edge of the two-dimensional memory array 111. Therefore, processing circuit 140 can obtain output current data from at least four different current paths.

[0083] It is worth noting that when the sub-encoding circuits 120_1 and 120_2 input the input voltage V to non-opposite (i.e., adjacent) array edges of the two-dimensional memory array 111, since the input voltages are input at the rows and columns of the array, respectively, the equivalent impedances of the current paths will also be different. Therefore, when the sub-encoding circuits 120_1 and 120_2 input the input voltage V to the two-dimensional memory array 111, the input voltages V received by the two circuits will be different (for example, Figure 6B Input voltage V1~V3 and input voltage V4~V6).

[0084] exist Figure 7 In the embodiment of the present invention, the encoding circuit 120 includes sub-encoding circuits 120_1 to 120_4, and the sensing circuit 130 includes sub-sensing circuits 130_1 to 130_4. The sub-encoding circuits 120_1 to 120_4 are respectively disposed on the four sides of the two-dimensional memory array 111 and are respectively connected to the four array edges of the two-dimensional memory array 111. The sub-sensing circuits 130_1 to 130_4 are also respectively disposed on the four sides of the two-dimensional memory array 111 and are respectively connected to the four array edges of the two-dimensional memory array 111. It should be noted that for the sake of simplicity of the figure, Figure 7 The arrows leading to the memory cells G11-G13, G21-G23 and G31-G33 are the input voltage V, and the arrows from the memory cells G11-G13, G21-G23 and G31-G33 are the output currents I. Figure 7 The input voltage V and output current I are omitted.

[0085] In operation, one of the sub-encoding circuits 120_1-120_4 can input an input voltage V to one of the array sides of the two-dimensional memory array 111, while one of the sub-sensing circuits 130_1-130_4 can receive an output current I from another non-opposite (i.e., adjacent) array side. Therefore, the processing circuit 140 can obtain output current data from at least eight different current paths. Furthermore, since sub-encoding circuits and sub-sensing circuits are configured on each side of the two-dimensional memory array 111, the data obtained by the processing circuit 140 can be increased (i.e., the accuracy of in-memory operations is improved), while also simplifying the wiring within the three-dimensional memory array 110.

[0086] Figure 8 FIG8 is a flow chart of a method 800 according to some embodiments of the present disclosure. In some embodiments, the method 800 is applicable to a three-dimensional memory device including a three-dimensional memory array, an encoding circuit, a sensing circuit, and a processing circuit, and includes steps S810, S820, and S830.

[0087] In step S810, a plurality of input voltages are input to a plurality of two-dimensional memory arrays in a three-dimensional memory array via an encoding circuit. In some embodiments, step S810 further includes: inputting a plurality of input voltages to the two-dimensional memory array via a plurality of array edges of the two-dimensional memory array via a plurality of sub-encoding circuits of the encoding circuit. Then, step S820 is executed.

[0088] In step S820, a plurality of output currents are received from a plurality of two-dimensional memory arrays via a sensing circuit. In some embodiments, step S820 further includes receiving a plurality of output currents from a plurality of array edges of the two-dimensional memory array via a plurality of sub-sensing circuits of the sensing circuit. Then, step S830 is executed.

[0089] In step S830, the processing circuit performs an in-memory operation based on the multiple input voltages and the multiple output currents. In some embodiments, performing the in-memory operation based on the multiple input voltages and the multiple output currents may be performed by calculating an average, a median, or other statistical methods.

[0090] It should be noted that the number and order of steps in the operation method 800 of the present disclosure are merely examples and are not intended to limit the present disclosure. Other numbers and orders of steps are within the scope of the present disclosure. In some embodiments, the operation method 800 further includes a step performed after step S830 in which the processing circuit switches the sub-encoding circuit that generates the input voltage, switches the sub-sensing circuit that receives the output current, and then performs step S810 again.

[0091] The three-dimensional memory device 100 and operation method 800 of the present disclosure can perform in-memory operations using multiple input voltages and multiple output currents corresponding to different current paths without significantly complicating the wiring of the three-dimensional memory device 100, thereby improving the problem of inaccurate in-memory operations caused by voltage drops on wires within the memory array.

[0092] The above are merely preferred embodiments of the present disclosure. Various modifications and equivalent variations may be made to the structure of the present disclosure without departing from the scope or spirit of the present disclosure. In summary, all modifications and equivalent variations made to the present disclosure within the scope of the appended claims are encompassed by the present disclosure.

Claims

1. A three-dimensional memory device, comprising: A three-dimensional memory array comprising a plurality of two-dimensional memory arrays for receiving a plurality of input voltages and outputting a plurality of output currents, wherein each two-dimensional memory array comprises a plurality of memory cells, and each two-dimensional memory array comprises four array sides; an encoding circuit coupled to the four array edges for inputting the plurality of input voltages to the plurality of two-dimensional memory arrays; a sensing circuit coupled to the four array edges for receiving the plurality of output currents from the plurality of two-dimensional memory arrays; as well as a processing circuit coupled to the encoding circuit and the sensing circuit, for performing an in-memory operation according to the plurality of input voltages and the plurality of output currents; The four array sides include a plurality of array sides. When one of the plurality of array sides is used to receive the plurality of input voltages, another one of the plurality of array sides is used to output the plurality of output currents. The one and the other of the plurality of array sides are not parallel to each other.

2. The three-dimensional memory device according to claim 1, wherein the encoding circuit comprises a first encoding circuit and a second encoding circuit. wherein the first encoding circuit and the second encoding circuit are used to input the plurality of input voltages to the plurality of two-dimensional memory arrays via a first array edge and a second array edge of the plurality of array edges, respectively; The first array side is parallel to and different from the second array side.

3. The three-dimensional memory device according to claim 1 , wherein the sensing circuit comprises a first sensing circuit and a second sensing circuit. wherein the first sensing circuit and the second sensing circuit are used to receive the plurality of output currents from the plurality of two-dimensional memory arrays via a first array edge and a second array edge of the plurality of array edges, respectively; The first array side is parallel to and different from the second array side.

4. The three-dimensional memory device according to claim 1 , wherein the encoding circuit comprises a first encoding circuit and a second encoding circuit, and the sensing circuit comprises a first sensing circuit and a second sensing circuit. wherein the first encoding circuit and the second encoding circuit are used to input the plurality of input voltages to the plurality of two-dimensional memory arrays via a first array edge and a second array edge of the plurality of array edges respectively; and The first sensing circuit and the second sensing circuit are used to receive the plurality of output currents from the plurality of two-dimensional memory arrays via a third array edge and a fourth array edge of the plurality of array edges, respectively. The first array side is parallel to and different from the second array side, and the third array side is parallel to and different from the fourth array side.

5. The three-dimensional memory device according to claim 1 , wherein the encoding circuit comprises a first encoding circuit and a second encoding circuit, and the sensing circuit comprises a first sensing circuit and a second sensing circuit. wherein the first encoding circuit is used to input a plurality of first input voltages to the plurality of two-dimensional memory arrays via a first array side of the plurality of array sides, and the second encoding circuit is used to input a plurality of second input voltages to the plurality of two-dimensional memory arrays via a second array side of the plurality of array sides, and The first sensing circuit is configured to receive a plurality of first output currents from the plurality of two-dimensional memory arrays via a third array edge of the plurality of array edges, and the second sensing circuit is configured to receive a plurality of second output currents from the plurality of two-dimensional memory arrays via a fourth array edge of the plurality of array edges. The first array side is not parallel to the second array side, the third array side is not parallel to the fourth array side, and the plurality of first input voltages are not equal to the plurality of second input voltages.

6. The three-dimensional memory device according to claim 1 , wherein the encoding circuit comprises a four-sub encoding circuit, and the sensing circuit comprises a four-sub sensing circuit. wherein the four sub-encoding circuits are respectively coupled to the plurality of array edges of each two-dimensional memory array, and the four sub-sensing circuits are respectively coupled to the plurality of array edges of each two-dimensional memory array, When one of the four-sub encoding circuits inputs the multiple input voltages to the multiple two-dimensional memory arrays, one of the four-sub sensing circuits is used to receive the multiple output currents from the multiple two-dimensional memory arrays, wherein the array side to which the one of the four-sub encoding circuits is coupled is not parallel to the array side to which the one of the four-sub sensing circuits is coupled.

7. The three-dimensional memory device of claim 6 , wherein the processing circuit is further configured to control the one of the four-sub encoding circuits and the one of the four-sub sensing circuits to be electrically connected to the three-dimensional memory array, and to control the other three of the four-sub encoding circuits and the other three of the four-sub sensing circuits to be electrically disconnected from the three-dimensional memory array.

8. A computing circuit coupled to a three-dimensional memory array comprising a plurality of two-dimensional memory arrays, each of which comprises four array sides, wherein the computing circuit comprises: an encoding circuit coupled to the four array edges for inputting a plurality of input voltages to the plurality of two-dimensional memory arrays; a sensing circuit coupled to the four array edges for receiving a plurality of output currents from the plurality of two-dimensional memory arrays; as well as a processing circuit coupled to the encoding circuit and the sensing circuit, for performing an in-memory operation according to the plurality of input voltages and the plurality of output currents; The four array sides include a plurality of array sides. When the encoding circuit inputs the plurality of input voltages to one of the plurality of array sides, the sensing circuit receives the plurality of output currents from another of the plurality of array sides. The one of the plurality of array sides and the other of the plurality of array sides are not parallel to each other.

9. The operation circuit according to claim 8, wherein the encoding circuit comprises a first encoding circuit and a second encoding circuit, wherein the first encoding circuit and the second encoding circuit are used to input the plurality of input voltages to the plurality of two-dimensional memory arrays via a first array edge and a second array edge of the plurality of array edges, respectively; The first array side is parallel to and different from the second array side.

10. The computing circuit according to claim 8, wherein the sensing circuit comprises a first sensing circuit and a second sensing circuit. wherein the first sensing circuit and the second sensing circuit are used to receive the plurality of output currents from the plurality of two-dimensional memory arrays via a first array edge and a second array edge of the plurality of array edges, respectively; The first array side is parallel to and different from the second array side.

11. The computing circuit according to claim 8, wherein the encoding circuit comprises a first encoding circuit and a second encoding circuit, and the sensing circuit comprises a first sensing circuit and a second sensing circuit. wherein the first encoding circuit and the second encoding circuit are used to input the plurality of input voltages to the plurality of two-dimensional memory arrays via a first array edge and a second array edge of the plurality of array edges respectively; and The first sensing circuit and the second sensing circuit are used to receive the plurality of output currents from the plurality of two-dimensional memory arrays via a third array edge and a fourth array edge of the plurality of array edges, respectively. The first array side is parallel to and different from the second array side, and the third array side is parallel to and different from the fourth array side.

12. The computing circuit according to claim 8, wherein the encoding circuit comprises a first encoding circuit and a second encoding circuit, and the sensing circuit comprises a first sensing circuit and a second sensing circuit, wherein the first encoding circuit is used to input a plurality of first input voltages to the plurality of two-dimensional memory arrays via a first array side of the plurality of array sides, and the second encoding circuit is used to input a plurality of second input voltages to the plurality of two-dimensional memory arrays via a second array side of the plurality of array sides, and The first sensing circuit is configured to receive a plurality of first output currents from the plurality of two-dimensional memory arrays via a third array edge of the plurality of array edges, and the second sensing circuit is configured to receive a plurality of second output currents from the plurality of two-dimensional memory arrays via a fourth array edge of the plurality of array edges. The first array side is not parallel to the second array side, the third array side is not parallel to the fourth array side, and the plurality of first input voltages are not equal to the plurality of second input voltages.

13. The computing circuit according to claim 8, wherein the encoding circuit comprises a four-sub encoding circuit, and the sensing circuit comprises a four-sub sensing circuit. wherein the four sub-encoding circuits are respectively coupled to the plurality of array edges of each two-dimensional memory array, and the four sub-sensing circuits are respectively coupled to the plurality of array edges of each two-dimensional memory array, When one of the four-sub encoding circuits inputs the multiple input voltages to the multiple two-dimensional memory arrays, one of the four-sub sensing circuits is used to receive the multiple output currents from the multiple two-dimensional memory arrays, wherein the array side to which the one of the four-sub encoding circuits is coupled is not parallel to the array side to which the one of the four-sub sensing circuits is coupled.

14. The arithmetic circuit according to claim 13 , wherein the processing circuit is further configured to control the one of the four-sub encoding circuits and the one of the four-sub sensing circuits to be electrically connected to the three-dimensional memory array, and to control the other three of the four-sub encoding circuits and the other three of the four-sub sensing circuits to be electrically disconnected from the three-dimensional memory array.

15. A computing method, applicable to a three-dimensional memory device, the three-dimensional memory device comprising a three-dimensional memory array, an encoding circuit, a sensing circuit, and a processing circuit, wherein the three-dimensional memory array comprises a plurality of two-dimensional memory arrays, wherein the computing method comprises: Inputting a plurality of input voltages to the plurality of two-dimensional memory arrays through the encoding circuit; receiving a plurality of output currents from the plurality of two-dimensional memory arrays through the sensing circuit; and The processing circuit performs an in-memory operation according to the plurality of input voltages and the plurality of output currents. Each two-dimensional memory array includes four array sides, each of the four array sides includes a plurality of array sides. When one of the plurality of array sides is used to receive the plurality of input voltages, another of the plurality of array sides is used to output the plurality of output currents, and the one of the plurality of array sides and the another are not parallel to each other.

16. The calculation method according to claim 15, wherein inputting the plurality of input voltages to the plurality of two-dimensional memory arrays through the encoding circuit comprises: Inputting the plurality of input voltages to the plurality of two-dimensional memory arrays via a first array edge of the plurality of array edges through a first encoding circuit of the encoding circuit; and The plurality of input voltages are input to the plurality of two-dimensional memory arrays via a second array edge of the plurality of array edges through a second encoding circuit of the encoding circuit, The first array side is parallel to and different from the second array side.

17. The computing method according to claim 15, wherein receiving the plurality of output currents from the plurality of two-dimensional memory arrays through the sensing circuit comprises: receiving the plurality of output currents from the plurality of two-dimensional memory arrays via a first array edge of the plurality of array edges through a first sensing circuit of the sensing circuit; and receiving the plurality of output currents from the plurality of two-dimensional memory arrays via a second array edge of the plurality of array edges through a second sensing circuit of the sensing circuit, The first array side is parallel to and different from the second array side.

18. The calculation method according to claim 15, wherein inputting the plurality of input voltages to the plurality of two-dimensional memory arrays through the encoding circuit comprises: Inputting the plurality of input voltages to the plurality of two-dimensional memory arrays via a first array edge of the plurality of array edges through a first encoding circuit of the encoding circuit; and The plurality of input voltages are input to the plurality of two-dimensional memory arrays via a second array edge of the plurality of array edges through a second encoding circuit of the encoding circuit, and Receiving the plurality of output currents from the plurality of two-dimensional memory arrays by the sensing circuit includes: receiving the plurality of output currents from the plurality of two-dimensional memory arrays via a third array edge of the plurality of array edges through a first sensing circuit of the sensing circuit; and receiving the plurality of output currents from the plurality of two-dimensional memory arrays via a fourth array edge of the plurality of array edges through a second sensing circuit of the sensing circuit, The first array side is parallel to and different from the second array side, and the third array side is parallel to and different from the fourth array side.

19. The calculation method according to claim 15, wherein inputting the plurality of input voltages to the plurality of two-dimensional memory arrays through the encoding circuit comprises: Inputting a plurality of first input voltages to the plurality of two-dimensional memory arrays via a first array edge of the plurality of array edges through a first encoding circuit of the encoding circuit; and A second encoding circuit of the encoding circuit inputs a plurality of second input voltages to the plurality of two-dimensional memory arrays via a second array edge of the plurality of array edges, and Receiving the plurality of output currents from the plurality of two-dimensional memory arrays by the sensing circuit includes: receiving a plurality of first output currents from the plurality of two-dimensional memory arrays via a third array edge of the plurality of array edges through a first sensing circuit of the sensing circuit; and receiving a plurality of second output currents from the plurality of two-dimensional memory arrays via a fourth array edge of the plurality of array edges through a second sensing circuit of the sensing circuit, The first array side is not parallel to the second array side, the third array side is not parallel to the fourth array side, and the plurality of first input voltages are not equal to the plurality of second input voltages.

20. The computing method according to claim 15 , wherein the encoding circuit comprises four encoding circuits respectively coupled to the plurality of array edges of each two-dimensional memory array, and the sensing circuit comprises four sensing circuits respectively coupled to the plurality of array edges of each two-dimensional memory array, wherein inputting the plurality of input voltages to the plurality of two-dimensional memory arrays through the encoding circuit comprises: The plurality of input voltages are input to the plurality of two-dimensional memory arrays through one of the four sub-encoding circuits, and Receiving the plurality of output currents from the plurality of two-dimensional memory arrays by the sensing circuit includes: receiving the plurality of output currents from the plurality of two-dimensional memory arrays through one of the four sub-sensing circuits, The array side to which one of the four sub-encoding circuits is coupled is not parallel to the array side to which one of the four sub-sensing circuits is coupled.

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