Memory with automatic background preprocessing at power-up

Abstract

Memory devices and systems with automatic background pre-processing at power up, and associated methods, are disclosed herein. In one embodiment, a memory device includes a memory array having a plurality of memory cells and a fuse array configured to store pre-processed data. The pre-processing data may identify a portion of the memory array, specify a predetermined pre-processing state, or a combination thereof. When the memory device is powered on, the memory device may be configured to automatically retrieve the pre-processing data from the fuse array and / or write memory cells in the portion of the memory array to the predetermined pre-processing state prior to execution of an access command.

Description

[0001] Information about divisional applications

[0002] This application is a divisional application. Its parent application is an invention patent application filed on August 26, 2020, with application number 202010870091.X, entitled “Memory with Automatic Background Preprocessing at Power-On.”

[0003] CROSS-REFERENCE TO RELATED APPLICATIONS

[0004] This application contains subject matter related to concurrently filed U.S. patent application by Anthony D. Veches et al., entitled "Memory with Automatic Background Preconditioning at Power Up," assigned to Micron Technology, Inc., identified by attorney docket number 010829-9390.US01, the entire contents of which are incorporated herein by reference. Technical Field

[0005] The present disclosure relates to memory systems, devices, and associated methods. In particular, the present disclosure relates to memory devices with automatic background pre-processing at power-up. Background Art

[0006] Memory devices are widely used to store information associated with various electronic devices, such as computers, wireless communication devices, cameras, and digital displays. In computers and other electronic devices, memory devices are typically provided as internal, semiconductor, integrated circuit, and / or external removable devices. There are many different types of memory, including volatile and non-volatile memory. Volatile memory, including static random access memory (SRAM), dynamic random access memory (DRAM), and synchronous dynamic random access memory (SDRAM), may require an applied power source to maintain its data. In contrast, non-volatile memory can retain its stored data even without external power. Non-volatile memory can be used in a variety of technologies, including flash memory (e.g., NAND and NOR), phase change memory (PCM), ferroelectric random access memory (FeRAM), resistive random access memory (RRAM), and magnetic random access memory (MRAM). Improvements to memory devices can generally include increasing memory cell density, increasing read / write speeds or otherwise reducing operation latency, increasing reliability, increasing data retention, reducing power consumption, or reducing manufacturing costs, among other metrics. Summary of the Invention

[0007] In one aspect, the present disclosure relates to a memory device comprising: a memory array including a plurality of memory cells arranged at intersections of memory rows and memory columns, wherein the memory device is configured to write at least a portion of the memory array to a predetermined data state during a power-up operation of the memory device, wherein the predetermined data state comprises a plurality of bits.

[0008] In another aspect, the present disclosure relates to a method comprising: receiving an indication that a memory device is being powered on, the memory device comprising a memory array having a plurality of memory cells arranged at intersections of a plurality of memory rows and a plurality of memory columns; and in response to the indication, prior to executing an access command, writing at least a portion of the memory array to a predetermined data state, wherein the predetermined data state comprises a plurality of bits.

[0009] In a further aspect, the present disclosure relates to a memory device comprising: a memory array having a plurality of memory cells; and a fuse array having a plurality of anti-fuse elements configured to store pre-processed data, wherein the memory device is configured to retrieve the pre-processed data from the fuse array when the memory device is powered on and before executing a command from a host device; and write one or more memory cells of the plurality of memory cells to a predetermined data state, wherein the predetermined data state comprises a plurality of bits, at least one of the plurality of bits having a value different from other bits of the plurality of bits. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Many aspects of the present disclosure may be better understood with reference to the following drawings. The components in the drawings are not necessarily drawn to scale. Instead, emphasis is placed on clearly illustrating the principles of the present disclosure. The drawings should not be construed as limiting the present disclosure to the specific embodiments depicted, but are for purposes of explanation and understanding only.

[0011] Figure 1 is a block diagram schematically illustrating a memory system configured according to various embodiments of the present technology.

[0012] Figure 2 is a flow chart illustrating a background pre-processing routine for a memory device configured in accordance with various embodiments of the present technology.

[0013] Figure 3 is a schematic diagram of a system including a memory device configured according to various embodiments of the present technology. DETAILED DESCRIPTION

[0014] As discussed in more detail below, the technology disclosed herein relates to memory systems and devices (and associated methods) that precondition all or a subset of a memory array to a desired state as part of a background operation that is automatically performed when the memory device is powered on. However, those skilled in the art will appreciate that the technology may have additional embodiments and may be used without reference to the following. Figures 1 to 3 The technology is practiced without having to consider several details of the embodiments described. In the embodiments shown below, memory devices and systems are described primarily in the context of devices incorporating DRAM storage media. However, memory devices configured according to other embodiments of the technology may include other types of memory devices and systems incorporating other types of storage media, including PCM, SRAM, FRAM, RRAM, MRAM, read-only memory (ROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEROM), ferroelectric, magnetoresistive, and other storage media, including non-volatile, flash (e.g., NAND and / or NOR) storage media.

[0015] A host memory system typically includes one or more memory devices for storing information. The host memory system may employ one or more security measures to prevent malicious actors from reading and / or manipulating information while the memory devices are installed in the host memory system. For example, when a malicious actor issues a read request that identifies a memory address corresponding to a restricted portion of a memory array of a memory device, the host memory system may prevent the malicious actor from accessing information stored in the restricted portion of the memory array by returning an error message and / or invalid data in response to the read request. As another example, the host memory system may restrict certain commands (e.g., read, write, or other access commands) to only authorized users.

[0016] When the information is stored on the memory cells of the volatile memory device, the host system is configured to periodically refresh the memory cells to prevent data loss due to charge leakage. When the volatile memory device is powered off or otherwise disconnected from the power source, the memory cells of the volatile memory device are no longer refreshed. In the absence of an intermediate power source, charge leaks from the memory cells until the information stored on the memory cells is corrupted (e.g., can no longer be accurately read). However, this corruption process is not immediate. Therefore, the information may remain accurately readable for a period of time after the volatile memory device is powered off or otherwise disconnected from the power source. As a result, a malicious actor may potentially extract information stored on the conventional memory device by quickly transferring (e.g., hot swapping) the conventional memory device from the host memory system to a hostile memory system that does not employ the above-mentioned security measures or is configured to circumvent such security measures.

[0017] To address this issue, several embodiments of the present technology are directed to memory devices, systems including memory devices, and methods of operating memory devices, in which memory cells in a memory array of the memory device are programmed to a desired (predetermined) state as part of a background operation automatically performed during power-up of the memory device (e.g., before the memory device executes an access or other command received from a user, a memory controller, and / or a host device). In some embodiments, the desired state may be a known state (e.g., a predetermined data string) stored in a fuse array of the memory device. In these and other embodiments, when the memory device is powered on, the memory device may automatically program all or a subset of the memory array to the known state. In these and other embodiments, the desired state may be a random (e.g., corrupted) state, and the memory device may automatically program all or a subset of the memory array to the random state during power-up by stimulating multiple rows of memory cells in the memory array without powering the corresponding sense amplifiers, causing nearby rows of memory cells to overwrite each other with their data and corrupt each other. In either approach, after the memory device is powered off or otherwise disconnected from power, any valid information remaining on the memory cells is automatically overwritten and / or corrupted when the memory device is powered on.

[0018] Figure 1 1 is a block diagram schematically illustrating a memory system 190 configured according to an embodiment of the present technology. The memory system 190 may include a memory device 100, which may be connected to any of a plurality of electronic devices or components thereof that can utilize memory to temporarily or permanently store information. For example, the memory device 100 may be operably connected to a host device 108 and / or a memory controller 101. For example, the host device 108 may be operably connected to the memory device 100, which may be a computing device such as a desktop or portable computer, a server, a handheld device (e.g., a mobile phone, a tablet, a digital reader, a digital media player), or some component thereof (e.g., a central processing unit, a coprocessor, a dedicated memory controller, etc.). The host device 108 may be a networking device (e.g., a switch, a router, etc.) or a recorder of digital images, audio, and / or video, a vehicle, an appliance, a toy, or any of a variety of other products. In one embodiment, host device 108 may be directly connected to memory device 100, although in other embodiments, host device 108 may be indirectly connected to memory device 100 (eg, through a network connection or through an intermediary device, such as through memory controller 101).

[0019] The memory device 100 may employ a plurality of external terminals, including command and address terminals coupled to a command bus and an address bus to receive a command signal CMD and an address signal ADDR, respectively. The memory device may further include a chip select terminal for receiving a chip select signal CS, a clock terminal for receiving clock signals CK and CKF, a data clock terminal for receiving data clock signals WCK and WCKF, data terminals DQ, RDQS, DBI, and DMI, and power supply terminals VDD, VSS, and VDDQ.

[0020] The power supply terminals of the memory device 100 may be supplied with power supply potentials VDD and VSS. These power supply potentials VDD and VSS may be supplied to the internal voltage generator circuit 170. The internal voltage generator circuit 170 may generate various internal potentials VPP, VOD, VARY, VPERI, etc. based on the power supply potentials VDD and VSS. The internal potential VPP may be used in the row decoder 140, the internal potentials VOD and VARY may be used in the sense amplifiers included in the memory array 150 of the memory device 100, and the internal potential VPERI may be used in many other circuit blocks.

[0021] The power supply terminal may also be supplied with a power supply potential VDDQ. The power supply potential VDDQ may be supplied to the input / output (IO) circuit 160 together with the power supply potential VSS. In an embodiment of the present technology, the power supply potential VDDQ may be the same potential as the power supply potential VDD. In another embodiment of the present technology, the power supply potential VDDQ may be a different potential from the power supply potential VDD. However, a dedicated power supply potential VDDQ may be used for the IO circuit 160 so that power supply noise generated by the IO circuit 160 does not propagate to other circuit blocks.

[0022] The clock terminal and the data clock terminal may be supplied with an external clock signal and a complementary external clock signal. The external clock signals CK, CKF, WCK, and WCKF may be supplied to the clock input circuit 120. The CK and CKF signals may be complementary, and the WCK and WCKF signals may also be complementary. The complementary clock signals may have opposite clock levels and simultaneously transition between opposite clock levels. For example, when the clock signal is at a low clock level, the complementary clock signal is at a high clock level, and when the clock signal is at a high clock level, the complementary clock signal is at a low clock level. In addition, when the clock signal transitions from a low clock level to a high clock level, the complementary clock signal transitions from a high clock level to a low clock level, and when the clock signal transitions from a high clock level to a low clock level, the complementary clock signal transitions from a low clock level to a high clock level.

[0023] The input buffer included in the clock input circuit 120 can receive an external clock signal. For example, when enabled by the CKE signal from the command decoder 115, the input buffer can receive the CK and CKF signals and the WCK and WCKF signals. The clock input circuit 120 can receive the external clock signal to generate an internal clock signal ICLK. The internal clock signal ICLK can be supplied to the internal clock circuit 130. The internal clock circuit 130 can provide various phase- and frequency-controlled internal clock signals based on the internal clock signal ICLK and the clock enable signal CKE received from the command decoder 115. For example, the internal clock circuit 130 can include a clock path (not shown) that receives the internal clock signal ICLK and provides various clock signals (not shown) to the command decoder 115. Figure 1 (not shown). The internal clock circuit 130 can further provide an input / output (IO) clock signal. The IO clock signal can be supplied to the IO circuit 160 and can be used as a timing signal for determining the output timing of read data and the input timing of write data. The IO clock signal can be provided at multiple clock frequencies so that data can be output from the memory device 100 and input into the memory device 100 at different data rates. When high memory speed is desired, a higher clock frequency may be desired. When lower power consumption is desired, a lower clock frequency may be desired. The internal clock signal ICLK can also be supplied to the timing generator 135, and thus can generate various internal clock signals that can be used by the command decoder 115, the column decoder 145 and / or other components of the memory device 100.

[0024] Memory device 100 may include an array of memory cells, such as memory array 150. The memory cells of memory array 150 may be arranged in a plurality of memory regions, and each memory region may include a plurality of word lines (WL), a plurality of bit lines (BL), and a plurality of memory cells arranged at the intersections of the word lines and the bit lines. In some embodiments, a memory region may be one or more memory banks, one or more memory rows within a memory bank, or another arrangement of memory cells. In these and other embodiments, the memory regions of memory array 150 may be arranged into one or more groups (e.g., one or more groups of memory banks, one or more logical memory columns or dies, etc.). The memory cells in memory array 150 may include any of a number of different memory media types, including capacitive, magnetoresistive, ferroelectric, phase change, etc. Selection of word lines WL may be performed by row decoder 140, and selection of bit lines BL may be performed by column decoder 145. A sense amplifier (SAMP) may be provided for each bit line BL and connected to at least one corresponding local I / O line pair (LIOT / B), which in turn may be coupled to at least one corresponding master I / O line pair (MIOT / B) via a transmission gate (TG), which may function as a switch. Memory array 150 may also include plate lines and corresponding circuitry for managing their operation.

[0025] The command terminal and the address terminal may be supplied with an address signal and a bank address signal from outside the memory device 100. The address signal and the bank address signal supplied to the address terminal may be transmitted to the address decoder 110 via the command / address input circuit 105. The address decoder 110 may receive the address signal and supply a decoded row address signal (XADD) to the row decoder 140 and a decoded column address signal (YADD) to the column decoder 145. The address decoder 110 may also receive a bank address signal (BADD) and supply the bank address signal to both the row decoder 140 and the column decoder 145.

[0026] The command and address terminals may be supplied with a command signal CMD, an address signal ADDR, and a chip select signal CS (e.g., from the memory controller 101 and / or the host device 108). The command signals may represent various memory commands (e.g., including access commands, which may include read commands and write commands). The select signal CS may be used to select the memory device 100 in response to the command and address provided to the command and address terminals. When a valid CS signal is provided to the memory device 100, the command and address may be decoded and a memory operation may be performed. The command signal CMD may be provided as an internal command signal ICMD to the command decoder 115 via the command / address input circuit 105. The command decoder 115 may include circuitry that decodes the internal command signal ICMD to generate various internal signals and commands for performing memory operations, such as a row command signal for selecting a word line and a column command signal for selecting a bit line. The internal command signals may also include output and input activation commands, such as a clock control command CMDCK (not shown) to the command decoder 115. The command decoder 115 may further include one or more registers 118 for tracking various counts or values (e.g., a count of refresh commands received by the memory device 100 or self-refresh operations performed by the memory device 100; memory regions enabled for refresh operations; memory cells, memory rows, memory columns, memory banks, logical memory banks or dies, and / or other memory regions that were last programmed and / or are to be programmed; etc.).

[0027] When a read command is issued and the row address and column address are supplied with the read command in time, read data can be read from the memory cells in the memory array 150 specified by these row address and column address. The read command can be received by the command decoder 115, and the command decoder 115 can provide an internal command to the IO circuit 160, and the read data is output from the data terminals DQ, RDQS, DBI, and DMI via the read / write (RW) amplifier 155 and the IO circuit 160 according to the RDQS clock signal. The read data can be provided at a time defined by the read latency information RL, which can be, for example, in the mode register ( Figure 1 The memory device 100 (not shown) is programmed. The read latency information RL can be defined based on a clock cycle of the CK clock signal. For example, when providing associated read data, the read latency information RL can be a number of clock cycles of the CK signal after the memory device 100 receives the read command.

[0028] When a write command is issued and the row address and column address are supplied with the command in a timely manner, write data can be supplied to the data terminals DQ, DBI, and DMI according to the WCK and WCKF clock signals. The write command can be received by the command decoder 115, which can provide an internal command to the IO circuit 160, so that the write data can be received by the data receiver in the IO circuit 160 and supplied to the memory array 150 via the IO circuit 160 and the RW amplifier 155. The write data can be written to the memory cell specified by the row address and the column address. The write data can be provided to the data terminal at a time defined by the write wait time WL information. The write wait time WL information can be in the memory device 100, for example, in the mode register ( Figure 1 The write latency information WL may be defined based on a clock cycle of the CK clock signal. For example, when receiving associated write data, the write latency information WL may be a number of clock cycles of the CK signal after the memory device 100 receives a write command.

[0029] As described herein, the memory array 150 can be refreshed or maintained to prevent data loss due to charge leakage or imprinting effects. As described herein, a refresh operation can be initiated by the memory system 190 (e.g., by the host device 108, the memory controller 101, and / or the memory device 100) and can include accessing one or more rows (e.g., WLs) and discharging the cells in the accessed rows to corresponding SAMPs. When the row is opened (e.g., when the accessed WL is activated), the SAMP can compare the voltage generated by the discharged cells to a reference value. The SAMP can then write the logic value (e.g., charge the cell) back to the nominal value for a given logic state. In some cases, this write-back process can increase the charge of the cell to ameliorate the discharge issues described above. In other cases, the write-back process can reverse the data state of the cell (e.g., from high to low or from low to high) to ameliorate hysteresis shift, material depolarization, etc. Other refresh schemes or methods may also be employed.

[0030] In one approach, the memory device 100 can be configured to simultaneously refresh the same row of memory cells in each memory bank of the memory array 150. In another approach, the memory device 100 can be configured to sequentially refresh the same row of memory cells in each memory bank of the memory array 150. In yet another approach, the memory device 100 can further include circuitry (e.g., one or more registers, latches, embedded memories, counters, etc.) configured to track row (e.g., word line) addresses, each row address corresponding to one of the memory banks in the memory array 150. In this approach, the memory device 100 is not limited to refreshing the same row in each memory bank of the memory array 150 before refreshing another row in one of the memory banks.

[0031] Regardless of the refresh method, the memory device 100 can be configured to refresh the memory cells in the memory array 150 within a given refresh rate or time window (e.g., 32 ms, 28 ms, 25 ms, 23 ms, 21 ms, 18 ms, 16 ms, 8 ms, etc.). In these embodiments, the memory system 190 can be configured to supply refresh commands to the memory device 100 according to a specified minimum cadence tREFI. For example, the memory system 190 can be configured to supply one or more refresh commands to the memory device 100 at least every 7.8 μs, such that approximately a minimum of 4,000 refresh commands are supplied to the memory device 100 within the 32 ms time window.

[0032] The memory device 100 may include a fuse array 143. The fuse array 143 may include antifuse elements. An antifuse element is an element that is insulating in its initial state and, when subjected to dielectric breakdown by a connection operation, switches to a conductive state. After the antifuse element switches to the conductive state, it cannot return to the insulating state. Therefore, the antifuse elements of the fuse array 143 can function as nonvolatile and irreversible memory elements. The antifuse elements of the fuse array 143 can be programmed using a conventional antifuse programming circuit (not shown).

[0033] In some embodiments, the antifuse elements of fuse array 143 can be programmed to store pre-conditioning data. For example, the antifuse elements can be programmed with pre-conditioning data that specifies that a portion (e.g., all or a subset) of memory array 150 should be programmed to a known state when the memory device is powered on. For example, the known state can include a predetermined string or sequence of data bits (e.g., all "1s"; all "0s"; alternating "1s" and "0s"; or another string / sequence of data bits) to be programmed into each memory row in the portion of memory array 150. In these and other embodiments, the antifuse elements can be programmed with pre-conditioning data that identifies a portion (e.g., all or a subset) of memory array 150 to be pre-conditioned when the memory device is powered on.

[0034] As described in more detail below, when the memory device 100 is powered on, the memory device 100 can be configured to automatically read pre-processing data from the fuse array 143. In embodiments where the pre-processing data specifies a known state to which a portion of the memory array 150 should be programmed, the known state can be automatically loaded into the I / O circuitry 160 and subsequently (automatically) written to a portion (all or a subset) of the memory array 150. In this way, any valid information remaining in the memory array 150 of the memory device 100 can be automatically overwritten when the memory device 100 is powered on. In these and other embodiments where the pre-processing data identifies a portion of the memory array 150 to be pre-processed, the pre-processing data can be automatically read into the command decoder 115 of the memory device 100. Using the pre-processing data, the command decoder 115 can generate various internal signals and commands for performing pre-processing operations, such as row command signals and column select signals for selecting memory rows and columns, respectively, in the portion of the memory array 150 identified in the pre-processing data. Memory device 100 may then automatically pre-condition the portion of memory array 150 identified in the pre-conditioning data to a desired state (eg, a known or random state).

[0035] To program the portion of memory array 150 to a random state, memory device 100 can be configured to automatically activate multiple memory rows in the portion of memory array 150 without powering corresponding sense amplifiers, causing nearby memory rows to overwrite each other with their data and become corrupted. Thus, when memory device 100 is powered on, any valid information remaining in the portion of memory array 150 can be automatically corrupted. Preconditioning a portion of memory array 150 to a random state is faster and consumes less power than preconditioning a portion of memory array 150 to a known state because memory device 100 does not retrieve the known state and load it into IO circuitry 160 or another component of memory device 100, or power corresponding sense amplifiers, before preconditioning the portion of memory array 150. Thus, memory device 100 can be configured to precondition a portion of memory array 150 to a random state while saving time or power.

[0036] Figure 2 2 is a flow chart illustrating a background pre-processing routine 250 for a memory device configured according to various embodiments of the present technology. In some embodiments, the routine 250 can be performed at least in part by various components of the memory device. For example, all or a subset of the steps of the routine 250 can be performed by a fuse array, a command decoder, an IO circuit, and / or a memory array of the memory device.

[0037] Routine 250 may begin at block 251 by receiving an indication that the memory device is being powered on. In some embodiments, the indication that the memory device is being powered on may be a voltage generator supplied to the memory device and / or one or more potentials generated by the voltage generator of the memory device. In response to the indication, routine 250 may automatically proceed to blocks 252 and / or 253. In this manner, routine 250 may be automatically executed without user intervention as an internal background operation of the memory device. In other words, routine 250 may be automatically executed before the memory device executes an access (e.g., read or write) or other command from a user, a memory controller, and / or a host device of the memory device. In other embodiments, routine 250 may begin at block 251 upon the occurrence of one or more other events. For example, routine 250 may begin at block 251 by receiving an indication that the memory device's RESET pin has been asserted and / or that a user has issued a pre-processed data command or sequence (e.g., a data "self-destruct" command).

[0038] At block 252, routine 250 retrieves pre-processing data. All or a subset of the pre-processing data may be stored in a fuse array and / or another component of the memory device. In some embodiments, the pre-processing data may include instructions for pre-processing a portion of the memory array to a desired state. For example, the pre-processing data may include instructions for pre-processing a portion of the memory array to a known state and / or may specify a predetermined string or sequence of data bits (e.g., all "1s"; all "0s"; alternating "1s" and "0s"; or another string / sequence of data bits) to be programmed into the portion of the memory array. In these and other embodiments, the pre-processing data may include instructions for pre-processing a portion of the memory array to a random or corrupted state. In these and other embodiments, the pre-processing data may identify a portion of the memory array to be pre-processed. For example, the pre-processing data may include instructions for pre-processing the entire memory array to a desired state. In other embodiments, the pre-processing data may include instructions for pre-processing a subset of the memory array (e.g., a specific memory row, a specific memory bank, etc.) to a desired state. After retrieving the pre-processed data, the routine 250 may automatically proceed to block 253 to pre-process a portion of the memory array.

[0039] In some embodiments, the routine 250 can be configured to automatically proceed to block 253 to pre-process a portion of the memory array from block 251 to a desired state without retrieving the pre-processing data at block 252. For example, in some embodiments, the desired state can be a random or corrupted state (as described in more detail below), such that the routine 250 does not retrieve a known state specified in the pre-processing data stored on the memory device. In these and other embodiments, the routine 250 can be configured to pre-process all or a subset of the memory array to a desired state (e.g., by default), such that the routine 250 does not retrieve pre-processing data stored on the memory device that identifies the portion of the memory array.

[0040] At block 253, the routine 250 preconditions a portion of the memory array to a desired state. In embodiments where a portion of the memory array is specified in the preconditioning data retrieved at block 252, the routine 250 may load the preconditioning data into a command decoder, which may issue a row select command to a row decoder and a column select command to a column decoder to precondition the corresponding portion of the memory array to the desired state.

[0041] As discussed above, the desired state can be a known state and / or a random state. In embodiments where the desired state is a known state specified in the pre-processed data retrieved at block 252, routine 250 can pre-process a portion of the memory array (e.g., the portion identified in the pre-processed data) to the desired state by loading the known state into an IO circuit or another component of the memory device. For example, routine 250 can power up the write latches and / or sense amplifiers corresponding to the memory rows in the portion of the memory array to the known state. Routine 250 can then write and / or copy the known state onto the portion of the memory array, such that routine 250 overwrites any valid information that remained in the portion of the memory array prior to execution of routine 250.

[0042] Using a volatile double data rate fourth generation (DDR4) memory device as an example, routine 250 can pre-condition the memory array of the memory device by entering write compression and writing a known desired state to all memory banks in the memory array using an x16 memory device configuration. In other embodiments, routine 250 can use a different memory device configuration (e.g., an x4 and / or x8 memory device configuration). In some embodiments, routine 250 can use a greater amount of compression than standard, allowing routine 250 to write to more than one memory column at a time. In these and other embodiments, routine 250 can enter a test mode of the memory device to enable routine 250 to issue one or more activate commands to the memory banks. To write a known state to the memory array, for each portion of the memory bank, routine 250 can (i) activate the memory row in the portion, (ii) write the corresponding bit of the known state to each memory column in the activated memory row, and (iii) pre-charge the memory row. Assuming that a memory row of a DDR4 memory device contains 2000 bits, routine 250 (in this example) issues 16 write commands to fully program the memory row. Thus, assuming there are 1024 memory rows and 512 sections per section in the memory array, the routine 250 (in this example) can pre-process the entire memory array in approximately 0.05 ms.

[0043] In embodiments where the desired state is a random or corrupted state, the routine 250 can precondition a portion of the memory array (e.g., the portion identified in the preconditioning data retrieved at block 252) to a random state by stepping through the portion of the memory array in a similar manner (e.g., using compression), but by activating multiple memory rows without powering the sense amplifiers corresponding to the memory rows. In this manner, nearby (e.g., adjacent) memory rows overwrite each other with their data and become corrupted, causing the routine 250 to destroy any valid information that remained in the portion of the memory array before the routine 250 was executed. As discussed above, by preconditioning the portion of the memory array to a random state, the routine 250 can save time and power that would be required to precondition the portion of the memory array to a known state.

[0044] Although the steps of routine 250 are discussed and shown in a particular order, Figure 2 The method shown in routine 250 is not limited in this regard. In other embodiments, the method may be performed in a different order. For example, any step of routine 250 may be performed before, during, and / or after any other step of routine 250. Furthermore, one of ordinary skill in the relevant art will readily recognize that the method shown may be varied and still remain within these and other embodiments of the present technology. For example, in some embodiments, steps may be omitted and / or repeated. Figure 2 One or more steps of routine 250 shown in .

[0045] Furthermore, although DDR4 memory devices are used in the above examples, routine 250 in other embodiments can be used to preprocess other memory devices. For example, routine 250 can be used to preprocess a memory array of a non-volatile memory device. In these and other embodiments, routine 250 can be used to preprocess a memory device that uses another generation of DDR (e.g., first generation DDR, second generation DDR, third generation DDR, fifth generation DDR, etc.). In these and other embodiments, routine 250 can be used to preprocess a memory array having a greater or fewer number of memory banks, sectors, sectors per memory bank, memory rows, memory rows per sector, memory columns, and / or memory columns per memory row.

[0046] In some embodiments, routine 250 can be enabled or disabled permanently or temporarily. For example, routine 250 can be enabled (e.g., by the manufacturer, by the terminal, by an intermediary, etc.) as a security feature on the memory device. When enabled, routine 250 automatically executes as a background operation without user intervention when the memory device is powered on (e.g., each time, the next time, at a selected subsequent time, etc.). In these and other embodiments, routine 250 can be disabled so that routine 250 is not executed on one or more subsequent power-ups of the memory device. For example, an authorized user (e.g., a vendor, a service technician, etc.) can disable routine 250 to test the device, save power, and / or save data (e.g., in the event of an error, failure, and / or hang in the host memory system in which the memory device is installed). In these and other embodiments, routine 250 can be disabled only when the memory device was previously powered on (e.g., the most recent power-up).

[0047] In some embodiments, routine 250 can be enabled or disabled using the antifuse elements of the fuse array. For example, when a first antifuse element undergoes dielectric breakdown due to a connection operation, routine 250 can be permanently enabled or disabled when the first antifuse element transitions to a conductive state. In other embodiments, routine 250 can be temporarily enabled or disabled when the first antifuse element transitions to a conductive state (e.g., until a second antifuse element transitions to a conductive state). In these and other embodiments, routine 250 can be toggled between enabled and disabled. For example, routine 250 can be disabled when the first antifuse element transitions to a conductive state, enabled when the second antifuse element subsequently transitions to a conductive state, disabled when the third antifuse element subsequently transitions to a conductive state, and so on.

[0048] Figure 3 is a schematic diagram of a system including a memory device according to an embodiment of the present technology. Figure 1 and 2 Any of the aforementioned memory devices described may be incorporated into any of a myriad of larger and / or more complex systems, a representative example of which is Figure 3 390 is schematically shown in FIG. The system 390 may include a semiconductor device assembly 300, a power supply 392, a driver 394, a processor 396, and / or other subsystems and components 398. The semiconductor device assembly 300 may include a semiconductor device assembly generally similar to the above referenced system. Figure 1 and 2The features of the memory device described above and thus may include various features of automatic background pre-processing after power-up. The resulting system 390 can perform any of a variety of functions, such as memory storage, data processing, and / or other suitable functions. Thus, a representative system 390 may include, but is not limited to, handheld devices (e.g., mobile phones, tablet computers, digital readers, and digital audio players), computers, vehicles, appliances, and other products. The components of system 390 may be housed in a single unit or distributed across multiple interconnected units (e.g., via a communication network). Components of system 390 may also include remote devices and any of a variety of computer-readable media.

[0049] in conclusion

[0050] The above detailed description of the embodiments of the technology is not intended to be exhaustive or to limit the technology to the precise form disclosed above. Although specific embodiments and examples of the technology are described above for illustrative purposes, as those skilled in the relevant art will recognize, various equivalent modifications are possible within the scope of the technology. For example, although the steps are presented and / or discussed in a given order, alternative embodiments may perform the steps in a different order. In addition, the various embodiments described herein may also be combined to provide further embodiments.

[0051] According to the foregoing, it will be understood that, herein, for the purpose of illustration, a specific embodiment of the technology is described, but well-known structures and functions are not shown or described in detail to avoid unnecessarily obscuring the description of the embodiments of the technology. Where the context permits, singular or plural terms may also include plural or singular terms, respectively. In addition, unless the word "or" is explicitly limited to only a single item and does not involve other items in a list of two or more items, the use of "or" in these lists is interpreted as including any single item in (a) the list, (b) all items in the list, or (c) any combination of items in the list. Where the context permits, singular or plural terms may also include plural or singular terms, respectively. In addition, the terms "comprise," "include," "have," and "have" are used throughout the text to include at least the features listed, so as not to exclude any greater number of identical features and / or other types of features. As used herein, the phrase "and / or" in "A and / or B" refers to a single A, a single B, and both A and B.

[0052] Based on the foregoing, it should also be understood that various modifications can be made without departing from the technology. For example, the various components of the technology can be further divided into subcomponents, or the various components and functions of the technology can be combined and / or integrated. In addition, although the advantages associated with certain embodiments of the present technology have been described in the context of those embodiments, other embodiments may also exhibit these advantages, and not all embodiments must exhibit these advantages to fall within the scope of the present technology. Therefore, the present disclosure and associated technology may encompass other embodiments not explicitly shown or described herein.

Claims

1. A method for operating a memory device, comprising: In response to determining that the memory device is powered on and before executing any access command from a host device to a memory array of the memory device, reading information from a storage element indicating that the memory device is to set at least a portion of the memory array to a predetermined data state; as well as In response to reading the information and before executing any access command from the host device to the memory array, the at least a portion of the memory array is set to the predetermined data state.

2. The method of claim 1, wherein the memory array comprises a volatile memory array.

3. The method of claim 2, wherein the memory device is a dynamic random access memory (DRAM) device. 4 . The method of claim 3 , wherein the memory array comprises a plurality of memory cells arranged at intersections of memory rows and memory columns. The method of claim 1 , wherein the predetermined data state is a predetermined sequence of bits.

6. The method of claim 5, wherein at least one bit in the predetermined sequence of digits has a different value than other bits in the predetermined sequence of digits. The method of claim 5 , wherein each bit in the predetermined sequence of bits has the same value.

8. A method for operating a memory device, comprising: responsive to the memory device being powered on, determining that a routine for setting at least a portion of a memory array of the memory device to a predetermined data state is enabled; as well as In response to determining that the routine is enabled and before executing any access command from a host device to the memory array, the at least a portion of the memory array is set to the predetermined data state.

9. The method according to claim 8, further comprising: In response to determining that the routine is enabled, reading pre-processed data from a fuse array, the pre-processed data indicating the portion; as well as The pre-processed data is loaded into a command decoder based on the pre-processed data indicating the portion.

10. The method according to claim 9, further comprising: Based on loading the pre-processed data into the command decoder, one or more commands are issued to a row decoder and one or more commands are issued to a column decoder, wherein each of the row decoder and the column decoder is associated with the portion.

11. The method according to claim 8, further comprising: writing data to the memory array of the memory device; as well as The memory device is powered off after writing the data to the memory array, wherein the memory device is powered on after powering off the memory device.

12. The method according to claim 8, further comprising: activating a memory row in a portion of the memory array, wherein the at least a portion of the memory array is set to the predetermined data state based on activating the memory row; as well as The memory rows in the portion of the memory array are precharged based on setting the at least a portion of the memory array to the predetermined data state.

13. The method of claim 8, wherein the memory array comprises a volatile memory array and the memory devices are dynamic random access memory (DRAM) devices.

14. The method of claim 13, wherein the memory array comprises a plurality of memory cells arranged at intersections of memory rows and memory columns.

15. The method of claim 8, wherein the predetermined data state is a predetermined sequence of bits.

16. The method of claim 15, wherein at least one bit in the predetermined sequence of digits has a different value than other bits in the predetermined sequence of digits. The method of claim 15 , wherein each bit in the predetermined sequence of bits has the same value.

18. A method for operating a memory device, comprising: writing data to a portion of a memory array of the memory device; powering off the memory device after writing the data to the portion of the memory array; In response to powering on the memory device after powering off the memory device, determining that a routine for preconditioning the memory array is enabled; in response to determining that the routine for preconditioning the memory array is enabled, reading preconditioning data from a fuse array, wherein the preconditioning data specifies a predetermined sequence of bits and identifies the portion of the memory array to be programmed with the predetermined sequence of bits; loading the predetermined sequence of bits into input / output circuitry coupled to the memory array based at least in part on reading the pre-processed data; as well as Prior to executing any access commands received after powering up the memory device, programming the portion of the memory array with the predetermined bit sequence based at least in part on loading the predetermined bit sequence into the input / output circuitry, wherein programming the portion of the memory array with the predetermined bit sequence before powering up the memory device overwrites the data written to the portion of the memory array.

19. The method of claim 18, wherein the memory array comprises a volatile memory array and the memory device is a dynamic random access memory (DRAM) device, and wherein the memory array comprises a plurality of memory cells arranged at intersections of memory rows and memory columns.

20. The method of claim 19, further comprising: In response to reading the pre-processed data and based on loading the predetermined bit sequence into the input / output circuit, one or more commands are issued to a row decoder and one or more commands are issued to a column decoder, wherein each of the row decoder and the column decoder is associated with the portion.

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