Fabrication method of package substrate

Abstract

The invention relates to a manufacturing method of a packaging substrate, which comprises the following steps of: combining a plurality of core layers with metal layers into a multi-layer board by virtue of thermal dissociation glue, so as to solve the problem of uneven stress distribution and enable the substrate structure of each layer to be kept in a non-warping state.

Description

Technical Field

[0001] The present invention relates to a semiconductor packaging process, and in particular to a packaging substrate capable of improving reliability and a manufacturing method thereof. Background Art

[0002] With the rapid development of the electronics industry, electronic products are becoming thinner, lighter, and smaller, while their functionality is being developed towards higher performance, greater functionality, and higher speed. Therefore, to meet the demands for high integration and miniaturization of semiconductor devices, packaging substrates with high-density and fine-pitch circuits are often used in the packaging process.

[0003] Flip-Chip Chip Scale Package (FCCSP) packaging substrates are primarily used in consumer electronics and personal computers, such as application processors (APs), Wi-Fi / BT chips, MCUs, AI chips, PMIC chips, and RF chips in mobile phones.

[0004] As end products become thinner and smaller, semiconductor chips are required to have more input / output (I / O) contacts. Consequently, the number of external pads on the package substrates used to carry the semiconductor chips has also increased accordingly. This is to accommodate the shrinking chip area and shorten signal transmission times for thinner end products. Consequently, the development of thinning substrate manufacturing technology has become a critical issue.

[0005] Furthermore, during the manufacturing process of conventional FCCSP package substrates, uneven stress distribution may occur due to the different number of wiring layers in the two-layer structure, causing the package substrate to warp, thereby resulting in poor production yield of the package substrate.

[0006] Therefore, how to overcome the various problems of the above-mentioned prior art has become a topic that needs to be solved urgently. Summary of the Invention

[0007] An object of the present invention is to provide a method for manufacturing a package substrate to solve at least one of the above problems.

[0008] In view of the various defects of the above-mentioned prior art, the present invention provides a method for manufacturing a packaging substrate, comprising: combining a first substrate on opposite sides of a carrier, wherein each first substrate comprises a first core layer and two first metal layers respectively formed on two opposite surfaces of the first core layer; forming a first circuit structure on each first core layer by means of the first metal layer; forming a first build-up layer structure electrically connected to the first circuit structure on each first core layer and the first circuit structure; combining a second substrate on each first build-up layer structure by means of a bonding layer, wherein each second substrate comprises a second core layer and two second metal layers respectively formed on two opposite surfaces of the second core layer; forming a second circuit structure on each second core layer by means of the second metal layer; forming a second build-up layer structure electrically connected to the second circuit structure on each second core layer and the second circuit structure, so as to form the packaging substrate on opposite sides of the carrier. A multi-board assembly including a first circuit structure, a first build-up layer structure, a second circuit structure and a second build-up layer structure is formed on the support; the carrier is removed to separate the two multi-board assemblies; the multi-board assemblies are respectively combined on opposite sides of a support, and the multi-board assembly is combined to the support with its second build-up layer structure to expose the other first metal layer on the first core layer; a first wiring layer electrically connected to the first circuit structure is formed on the first core layer by means of the other first metal layer to form a substrate structure; the combining layer is removed to separate the two substrate structures, and two processing structures with the second core layer are obtained, and the other second metal layer on the second core layer is exposed; a second wiring layer electrically connected to the second circuit structure is formed by means of the other second metal layer on the second core layer of the processing structure to form another substrate structure; and the support is removed to expose the second build-up layer structure.

[0009] In a specific embodiment of the aforementioned manufacturing method, the first circuit structure includes a first circuit layer formed on the first core layer and at least one first conductive via formed in the first core layer, so that the first conductive via electrically connects the first circuit layer and the first wiring layer.

[0010] In a specific embodiment of the aforementioned manufacturing method, the first build-up structure includes an insulating layer formed on the first core layer and the first circuit structure, and a wiring layer formed on the insulating layer and electrically connected to the first circuit structure.

[0011] In a specific embodiment of the aforementioned manufacturing method, the second circuit structure includes a second circuit layer formed on the second core layer and at least one second conductive via formed in the second core layer, so that the second conductive via electrically connects the second circuit layer and the second wiring layer.

[0012] In a specific embodiment of the aforementioned manufacturing method, the second build-up structure includes an insulating layer formed on the second core layer and the second circuit structure, and a wiring layer formed on the insulating layer and electrically connected to the second circuit structure.

[0013] In a specific embodiment of the above-mentioned manufacturing method, the bonding layer is a thermally disintegrating adhesive, a photosensitive disintegrating adhesive, or a temporarily removable adhesive sheet.

[0014] In a specific embodiment of the above-mentioned manufacturing method, the support member is a thermally disintegrating adhesive, a photosensitive disintegrating adhesive, or a temporarily removable adhesive plate with adhesive properties.

[0015] In a specific embodiment of the aforementioned manufacturing method, the bonding layer and the support member are made of the same material.

[0016] In one embodiment of the aforementioned manufacturing method, the bonding layer and the support member are made of different materials. For example, the bonding layer has a dissociation temperature higher than that of the support member.

[0017] As can be seen from the above, the method for manufacturing the packaging substrate of the present invention mainly relies on the application of the bonding layer and the support member to improve the toughness of the multi-board component in the process and improve the problem of uneven stress distribution of the asymmetric substrate type, so that the substrate structure remains in a warping-free state. Therefore, the present invention can avoid the problems of warping, bending or other deformation conditions in the process of manufacturing the first and second build-up layer structures. Therefore, the first and second build-up layer structures can adopt ultra-thin insulating layers to meet the thinning requirements, and the number of production layers of the first and second build-up layer structures can be arbitrarily adjusted according to product requirements.

[0018] Furthermore, the method for manufacturing the packaging substrate of the present invention combines at least two thinner first substrates and second substrates by the bonding layer and the support member to increase the structural thickness required for the process, thereby helping to maintain stability during transportation to avoid board jams, so that the machinability of the ultra-thin asymmetric substrate structure is not limited by equipment performance to achieve the equipment capacity of the minimum board thickness. Therefore, the method of the present invention can be processed using traditional processing equipment without the need for dedicated special equipment, which can not only significantly reduce processing costs but also improve yield.

[0019] In addition, the method for manufacturing the packaging substrate of the present invention combines two first substrates and two second substrates by the bonding layer and the support member, and then performs a circuit process and a layer-adding process to obtain four substrate structures. Therefore, the method of the present invention can process multiple groups of substrates to improve production efficiency and increase production capacity.

[0020] In addition, the method for manufacturing the package substrate of the present invention can manufacture an ultra-thin package substrate, thereby reducing the signal transmission loss of the package substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figures 1A to 1KFIG. 1 is a cross-sectional view of a first embodiment of a method for manufacturing a package substrate according to the present invention.

[0022] Figures 2A to 2D FIG. 1 is a cross-sectional view of a second embodiment of a method for manufacturing a package substrate according to the present invention.

[0023] The reference numerals are as follows:

[0024] 1Package substrate

[0025] 1a, 1b, 1c, 1d substrate structure

[0026] 10 bearing parts

[0027] 11 First Line Structure

[0028] 111 First circuit layer

[0029] 112 first conductive via

[0030] 12 First build-up structure

[0031] 120,140 insulation layer

[0032] 121,141 wiring layers

[0033] 13 Second Line Structure

[0034] 131 Second circuit layer

[0035] 132 second conductive via

[0036] 14 Second layer structure

[0037] 15 Solder mask

[0038] 150 openings

[0039] 16 Surface treatment layer

[0040] 2,7 support parts

[0041] 3 Processing structure

[0042] 5 Multi-board assemblies

[0043] 6 Bonding layer

[0044] 8 Second substrate

[0045] 80 Second Core Layer

[0046] 81 Second metal layer

[0047] 810 Second wiring layer

[0048] 82,92 Metal Covering

[0049] 9. First substrate

[0050] 90 First core layer

[0051] 91 First Metal Layer

[0052] 910 First wiring layer DETAILED DESCRIPTION

[0053] The following describes the implementation of the present invention by means of specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.

[0054] It should be noted that the structures, proportions, sizes, etc. shown in the drawings attached to this specification are only used to match the contents disclosed in the specification for the understanding and reading of those skilled in the art, and are not used to limit the conditions for the implementation of the present invention. Therefore, they have no substantial technical significance. Any modification of the structure, change in the proportional relationship or adjustment of the size should still fall within the scope of the technical content disclosed in the present invention without affecting the efficacy and purpose of the present invention. At the same time, the terms such as "on", "first", "second", "one" and so on quoted in this specification are only for the convenience of description and are not used to limit the scope of the implementation of the present invention. Changes or adjustments in their relative relationships should also be regarded as the scope of the implementation of the present invention without substantially changing the technical content.

[0055] Figures 1A to 1K FIG. 1 is a cross-sectional view of a first embodiment of a method for manufacturing a package substrate 1 according to the present invention.

[0056] like Figure 1A As shown, a first substrate 9 is bonded to opposite sides of a carrier 10, wherein the first substrate 9 includes a first core layer 90, a first metal layer 91 is provided on two opposite surfaces thereof, and a metal covering layer 92 is formed on the first metal layer 91, so that the first substrate 9 is bonded to the carrier 10 with the metal covering layer 92 on one side, while the metal covering layer 92 on the other side is exposed.

[0057] In this embodiment, the first core layer 90 is made of a high-hardness dielectric material, such as bismaleimide triazine (BT), glass, ceramic, SiC, AlO2, or a composite material. The first metal layer 91 is a thin copper layer with a thickness of approximately 3 microns (μm), making the first substrate 9 a copper clad laminate (CCL). For example, the metal cover layer 92 is a thick copper layer, such as copper foil, with a thickness of approximately 18 μm. The combined thickness of the first core layer 90 and the first metal layer 91 is less than or equal to 40 μm, such as 35 μm, 30 μm, 25 μm, or 20 μm.

[0058] Furthermore, the carrier 10 is a dielectric structure, such as ABF film (Ajinomoto build-up film), prepreg (PP) or other dielectric materials.

[0059] like Figure 1B As shown, the metal cover layer 92 is removed to expose the first metal layer 91. Then, a patterning process is performed on the first metal layer 91 to form a first circuit structure 11 on the first core layer 90.

[0060] In this embodiment, each of the first circuit structures 11 includes a first circuit layer 111 formed on the first core layer 90 and a plurality of first conductive vias 112 formed in the first core layer 90, such that the plurality of first conductive vias 112 electrically connect the first circuit layer 111 and the first metal layer 91. For example, a plurality of holes are first formed in the first core layer 90 using a laser, and then copper is electroplated on the first core layer 90 and in the holes to integrally form the first circuit layer 111 and the first conductive vias 112.

[0061] Furthermore, the first circuit layer 111 and the first conductive via 112 adopt a redistribution layer (RDL) specification, and the first conductive via 112 is in a cone-shaped column.

[0062] like Figure 1C As shown, a first build-up layer structure 12 electrically connected to the first circuit structure 11 is formed on each of the first core layers 90 and the first circuit structure 11, wherein each of the first build-up layer structures 12 includes an insulating layer 120 formed on the first core layer 90 and the first circuit layer 111 and a wiring layer 121 formed on the insulating layer 120 and electrically connected to the first circuit layer 111.

[0063] In this embodiment, the wiring layer 121 is a redistribution layer (RDL) and is fabricated using a build-up process by electroplating metal (e.g., copper) or other methods. For example, a plurality of holes are first formed in the insulating layer 120 using a laser, and copper is then electroplated on the insulating layer 120 and in the holes to integrally form the wiring layer 121.

[0064] Furthermore, the insulating layer 120 is ABF film (Ajinomoto build-up film), polybenzoxazole (PBO), polyimide (PI), prepreg (PP) or other dielectric materials.

[0065] It should be understood that by using the build-up method, the number of layers of the build-up structure can be designed according to requirements to produce the required number of wiring layers.

[0066] like Figure 1D As shown, a second substrate 8 is bonded to each of the first build-up layer structures 12 via a bonding layer 6, wherein the second substrate 8 includes a second core layer 80 having a second metal layer 81 on two opposite surfaces, and a metal covering layer 82 is formed on the second metal layer 81, so that the second substrate 8 is bonded to the bonding layer 6 with the metal covering layer 82 on one side, while the metal covering layer 82 on the other side is exposed.

[0067] In this embodiment, each second core layer 80 is made of a high-hardness dielectric material, such as bismaleimide triazine (BT), glass, ceramic, SiC, AlO2, or a composite material. Furthermore, the second metal layer 81 is a thin copper layer with a thickness of approximately 3 microns, making the second substrate 8 a copper clad laminate (CCL). For example, the metal cover layer 82 is a thick copper layer, such as copper foil, with a thickness of approximately 18 microns.

[0068] Furthermore, the bonding layer 6 is a thermally disintegrating adhesive, a photosensitive disintegrating adhesive, or a temporarily removable adhesive sheet with adhesive properties, such as a double-sided thermal release film.

[0069] like Figure 1E As shown, the metal covering layer 82 of the second substrate 8 is removed to expose the second metal layer 81. Then, a patterning process is performed on the second metal layer 81 to form a second circuit structure 13 on the second core layer 80.

[0070] In this embodiment, the second circuit structure 13 includes a second circuit layer 131 formed on the second core layer 80 and a plurality of second conductive vias 132 formed in the second core layer 80, so that the plurality of second conductive vias 132 electrically connect the second circuit layer 131 and the second metal layer 81. For example, a plurality of holes are first formed in the second core layer 80 using a laser, and then copper is electroplated on the second core layer 80 and in the holes to integrally form the second circuit layer 131 and the second conductive vias 132.

[0071] Furthermore, the second circuit layer 131 and the second conductive via 132 adopt a redistribution layer (RDL) specification, and the second conductive via 132 is in a cone-shaped column.

[0072] like Figure 1F As shown, a second build-up layer structure 14 electrically connected to the second circuit structure 13 is formed on each of the second core layer 80 and the second circuit structure 13, so as to form a multi-board component 5 including a first circuit structure 11, a first build-up layer structure 12, a second circuit structure 13 and a second build-up layer structure 14 on opposite sides of the carrier 10, wherein the second build-up layer structure 14 includes an insulating layer 140 formed on the second core layer 80 and the second circuit layer 131 and a wiring layer 141 formed on the insulating layer 140 and electrically connected to the second circuit layer 131.

[0073] In this embodiment, the wiring layer 141 is a redistribution layer (RDL) and is fabricated using a build-up process by electroplating metal (e.g., copper) or other methods. For example, a plurality of holes are first formed in the insulating layer 140 using a laser, and copper is then electroplated on the insulating layer 140 and in the holes to integrally form the wiring layer 141.

[0074] Furthermore, the insulating layer 140 is ABF film (Ajinomoto build-up film), polybenzoxazole (PBO), polyimide (PI), prepreg (PP) or other dielectric materials.

[0075] It should be understood that by using the build-up method, the number of layers of the build-up structure can be designed according to requirements to produce the required number of wiring layers.

[0076] like Figure 1GAs shown, the carrier 10 is removed to separate the two multi-panel assemblies 5. The other metal covering layer 92 of the first substrate 9 of the multi-panel assembly 5 is then removed to expose the other first metal layer 91 on the first core layer 90. Next, the multi-panel assembly 5 is bonded to opposite sides of a support member 7, and the multi-panel assembly 5 is bonded to the support member 7 with its second build-up structure 14, exposing the other first metal layer 91 on the first core layer 90.

[0077] In this embodiment, the support member 7 is a thermally disintegrating adhesive, a photosensitive disintegrating adhesive, or a temporarily removable adhesive plate with adhesive properties, such as a double-sided thermal release film.

[0078] like Figure 1H As shown, a first wiring layer 910 electrically connected to the first conductive via 112 is formed on the first core layer 90 by patterning another first metal layer 91 on the first core layer 90 to form substrate structures 1a, 1b.

[0079] In this embodiment, the first wiring layer 910 adopts a redistribution layer (RDL) specification.

[0080] like Figure 1I As shown, the bonding layer 6 is removed to separate the two substrate structures 1 a and 1 b , and the support member 7 is removed to obtain the two processing structures 3 , thereby exposing the second build-up layer structure 14 .

[0081] In this embodiment, the bonding layer 6 and the support member 7 are made of the same material, and thus are removed simultaneously using the same method. For example, the bonding layer 6 and the support member 7 are heated at the same temperature to separate the two substrate structures 1a, 1b and the two processed structures 3 having the second core layer 80.

[0082] like Figure 1J As shown, the other metal covering layer 92 on the second core layer 80 of the two process structures 3 is removed to expose the other second metal layer 81 on the second core layer 80. Then, a second wiring layer 810 electrically connected to the second conductive via 132 is formed on the second core layer 80 of the process structure 3 by patterning the other second metal layer 81 to form a second wiring layer 810, thereby forming another substrate structure 1c, 1d.

[0083] In this embodiment, the second wiring layer 810 adopts a redistribution layer (RDL) specification.

[0084] like Figure 1KAs shown, a solder mask 15, such as green paint, is formed on opposite sides of the substrate structure 1a, 1b, 1c, and 1d to form a package substrate 1, and a plurality of openings 150 are formed on each solder mask 15 to expose the first wiring layer 910 or the second wiring layer 810 and the wiring layers 121, 141 for combining a surface treatment layer 16 such as nickel / gold.

[0085] In this embodiment, in subsequent processes, multiple solder balls (not shown) can be combined on the exposed surfaces of the first wiring layer 910 or the second wiring layer 810 and the wiring layers 121, 141 for external electronic devices (such as semiconductor chips, passive components, silicon interposers, circuit boards or other components).

[0086] The manufacturing method of the present invention is used to produce an asymmetric packaging substrate 1. It mainly relies on the application of the bonding layer 6 and the support member 7 to improve the toughness of the multi-board component 5 during the process and improve the problem of uneven stress distribution of the asymmetric substrate type, so that the substrate structures 1a, 1b, 1c, and 1d remain in a warping-free state. Therefore, compared with the existing technology, the first build-up layer structure 12 and the second build-up layer structure 14 can avoid the problems of warping, bending or other deformation during the process. Therefore, an ultra-thin dielectric layer can be used as the insulating layer 120, 140 to meet the thinning requirements, and the number of production layers of the first build-up layer structure 12 and the second build-up layer structure 14 can be arbitrarily adjusted according to product requirements.

[0087] Furthermore, by combining at least two thinner first substrates 9 and second substrates 8 with the bonding layer 6 and the support member 7, the structural thickness required for the process is increased, thereby helping to maintain stability during transportation to avoid board jams, so that the machinability of the ultra-thin asymmetric substrate structures 1a, 1b, 1c, 1d is not limited by equipment performance, so as to achieve the equipment capacity of the minimum board thickness (such as the minimum board thickness capacity of pickling before circuit production is 0.06mm). Therefore, the method for manufacturing the packaging substrate 1 of the present invention can be processed using traditional processing equipment without the need for special equipment, which can not only significantly reduce processing costs but also improve yield.

[0088] In addition, two first substrates 9 and two second substrates 8 are combined by the bonding layer 6 and the support member 7, and then a circuit process and a layer-building process are performed to obtain four substrate structures 1a, 1b, 1c, and 1d. Therefore, the method for manufacturing the packaging substrate 1 of the present invention can process multiple groups of substrates to improve production efficiency and increase production capacity by at least four times.

[0089] In addition, the manufacturing method of the present invention can manufacture an ultra-thin packaging substrate 1 , thereby effectively reducing the signal transmission loss of the packaging substrate 1 .

[0090] Figures 2A to 2D1 is a cross-sectional view of a second embodiment of the method for manufacturing the package substrate 1 of the present invention. The difference between this embodiment and the first embodiment lies in the material of the support member 2. The other processes are substantially the same, so the similarities will not be repeated below.

[0091] like Figure 2A As shown, according to Figure 1I The bonding layer 6 is removed to separate the two substrate structures 1a, 1b, while the two processing structures 3 are still bonded to the support member 2, and another metal covering layer 92 on the second core layer 80 of the two processing structures 3 is exposed.

[0092] In this embodiment, the bonding layer 6 and the support member 2 are made of different materials. The dissociation temperature of the support member 2 is higher than the dissociation temperature of the bonding layer 6, so the support member 2 has not been removed. For example, the dissociation temperature of the support member 2 is greater than or equal to 240°C, and the dissociation temperature of the bonding layer 6 is 150°C.

[0093] like Figure 2B As shown, using Figure 1J The metal covering layer 92 on the second core layer 80 of the two processing structures 3 is removed, and the second wiring layer 810 is then manufactured by using the second metal layer 81 to form the substrate structures 1c and 1d.

[0094] like Figure 2C As shown, the support member 2 is removed to obtain the substrate structures 1 c , 1 d , exposing the second build-up layer structure 14 .

[0095] like Figure 2D As shown, using Figure 1K A solder mask layer 15 is formed on opposite sides of the substrate structures 1a, 1b, 1c, and 1d to form a package substrate 1 having a surface treatment layer 16.

[0096] In summary, the method for manufacturing a packaging substrate of the present invention improves the toughness of multi-board components during the process and improves the problem of uneven stress distribution of asymmetric substrate types through the application of bonding layers and support members, so that the substrate structure remains in a warping-free state. Therefore, the present invention can avoid the problems of warping, bending or other deformation conditions during the process of manufacturing the first and second build-up layer structures. Therefore, the first and second build-up layer structures can adopt ultra-thin insulating layers to meet the requirements of thinning, and the number of production layers of the first and second build-up layer structures can be arbitrarily adjusted according to product requirements.

[0097] Furthermore, the method for manufacturing the packaging substrate of the present invention combines at least two thinner first substrates and second substrates by the bonding layer and the support member to increase the structural thickness required for the process, thereby helping to maintain stability during transportation to avoid board jams, so that the machinability of the ultra-thin asymmetric substrate structure is not limited by equipment performance to achieve the equipment capacity of the minimum board thickness. Therefore, the method of the present invention can be processed using traditional processing equipment without the need for dedicated special equipment, which can not only significantly reduce processing costs but also improve yield.

[0098] In addition, the method for manufacturing the packaging substrate of the present invention combines two first substrates and two second substrates by the bonding layer and the support member, and then performs a circuit process and a layer-adding process to obtain four substrate structures. Therefore, the method of the present invention can process multiple groups of substrates to improve production efficiency and increase production capacity.

[0099] In addition, the manufacturing method of the present invention can manufacture an ultra-thin packaging substrate, thereby effectively reducing the signal transmission loss of the packaging substrate.

[0100] The above embodiments are intended to illustrate the principles and effects of the present invention and are not intended to limit the present invention. Those skilled in the art may modify the above embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be as set forth in the claims.

Claims

1. A method for manufacturing a packaging substrate, characterized in that: include: A first substrate is bonded to opposite sides of a carrier, wherein each of the first substrates comprises a first core layer and two first metal layers formed on opposite surfaces of the first core layer; forming a first circuit structure on each of the first core layers by using the first metal layer; forming a first build-up layer structure electrically connected to the first circuit structure on each of the first core layers and the first circuit structure; Bonding a second substrate on each of the first build-up structures via a bonding layer, wherein each of the second substrates comprises a second core layer and two second metal layers formed on two opposite surfaces of the second core layer; forming a second circuit structure on each of the second core layers by using the second metal layer; forming a second build-up structure electrically connected to the second circuit structure on each of the second core layer and the second circuit structure, so as to form a multi-board assembly including the first circuit structure, the first build-up structure, the second circuit structure, and the second build-up structure on opposite sides of the carrier; removing the carrier to separate the two multi-board assemblies; The multi-board assembly is bonded to opposite sides of a support member, and the multi-board assembly is bonded to the support member with its second build-up structure, exposing the other first metal layer on the first core layer; forming a first wiring layer electrically connected to the first circuit structure on the first core layer by another first metal layer to form a substrate structure; removing the bonding layer to separate the two substrate structures and obtain two processed structures having the second core layer, and exposing the other second metal layer on the second core layer; forming a second wiring layer electrically connected to the second circuit structure on the second core layer of the processing structure by another second metal layer to form another substrate structure; and The support member is removed to expose the second build-up layer structure.

2. The method for manufacturing a package substrate according to claim 1, wherein: The first circuit structure includes a first circuit layer formed on the first core layer and at least one first conductive via formed in the first core layer, so that the first conductive via electrically connects the first circuit layer and the first wiring layer.

3. The method for manufacturing a package substrate according to claim 1, wherein: The first build-up structure includes an insulating layer formed on the first core layer and the first circuit structure, and a wiring layer formed on the insulating layer and electrically connected to the first circuit structure.

4. The method for manufacturing a package substrate according to claim 1, wherein: The second circuit structure includes a second circuit layer formed on the second core layer and at least one second conductive via formed in the second core layer, so that the second conductive via electrically connects the second circuit layer and the second wiring layer.

5. The method for manufacturing a package substrate according to claim 1, wherein: The second build-up structure includes an insulating layer formed on the second core layer and the second circuit structure, and a wiring layer formed on the insulating layer and electrically connected to the second circuit structure.

6. The method for manufacturing a package substrate according to claim 1, wherein: The bonding layer is a thermally disintegrating adhesive material, a photosensitive disintegrating adhesive material or a temporarily removable adhesive plate.

7. The method for manufacturing a package substrate according to claim 1, wherein: The supporting member is a thermally dissociated adhesive material, a photosensitive dissociated adhesive material or a temporarily removable adhesive plate.

8. The method for manufacturing a package substrate according to claim 1, wherein: The bonding layer and the supporting member are made of the same material.

9. The method for manufacturing a package substrate according to claim 1, wherein: The bonding layer and the supporting component are made of different materials.

10. The method for manufacturing a package substrate according to claim 9, wherein: The dissociation temperature of the bonding layer is higher than the dissociation temperature of the support member.

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