Method of manufacturing a package substrate

Abstract

A method for manufacturing a packaging substrate includes combining a plurality of core layers having metal layers into a multilayer board by thermal debonding glue to improve uneven stress distribution and maintain a warpage-free state of the substrate structure of each layer.

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor packaging process, and more particularly to a packaging substrate with improved reliability and a manufacturing method thereof. BACKGROUND

[0002] With the rapid development of the electronic industry, electronic products tend to be light, thin, short and small in shape, and high performance, high function and high speed in function. Therefore, to meet the high integration and miniaturization requirements of semiconductor devices, packaging substrates with high density and fine pitch lines are often used in packaging processes.

[0003] Flip-Chip Chip Scale Package (FCCSP) packaging substrates are commonly used in consumer electronics and personal computers, such as application processors (APs), WifiBT chips, MCUs, AI chips, PMIC chips, and RF chips in mobile phones.

[0004] With the increasing functional requirements of terminal products and the development of light, thin, short and small, semiconductor chips need to have more input / output (I / O) contacts, so the number of external pads of the packaging substrate for carrying semiconductor chips also increases accordingly. In order to meet the gradually shrinking chip area to shorten the signal transmission and apply to the thin type of terminal product, the development of thin type substrate manufacturing technology has become an important issue.

[0005] In addition, it is known that the packaging substrate of FCCSP specification is prone to uneven stress distribution during the manufacturing process due to the difference in the number of wiring layers of the two-layer structure, which leads to warping of the packaging substrate, and thus the production yield of the packaging substrate is poor.

[0006] Therefore, how to overcome the various problems of the prior art has become an urgent issue to be solved. SUMMARY

[0007] The present application aims to provide a manufacturing method of a packaging substrate to solve at least one of the above problems.

[0008] In view of the aforementioned drawbacks of the prior art, the present application provides a method for manufacturing a packaging substrate, comprising: bonding a first substrate on opposite sides of a carrier, wherein each of the first substrates comprises a first core layer and two first metal layers respectively formed on opposite surfaces of the first core layer; forming a first circuit structure on each of the first core layers by the first metal layers; forming a first build-up structure on each of the first core layers and the first circuit structure, which electrically connects the first circuit structure; bonding a second substrate on each of the first build-up structures by a bonding layer, wherein each of the second substrates comprises a second core layer and two second metal layers respectively formed on opposite surfaces of the second core layer; forming a second circuit structure on each of the second core layers by the second metal layers; forming a second build-up structure on each of the second core layers and the second circuit structure, which electrically connects the second circuit structure, so as to form a multi-board assembly comprising the first circuit structure, the first build-up structure, the second circuit structure and the second build-up structure on opposite sides of the carrier; removing the carrier to separate two of the multi-board assemblies; bonding the multi-board assemblies on opposite sides of a support, and bonding the multi-board assemblies to the support by the second build-up structures, so as to expose another of the first metal layers on the first core layer; forming a first wiring layer on the first core layer by another of the first metal layers, which electrically connects the first circuit structure, so as to form a substrate structure; removing the bonding layer to separate the two substrate structures, and obtaining two processing structures with the second core layer, and exposing another of the second metal layers on the second core layer; forming a second wiring layer on the second core layer of the processing structure by another of the second metal layers, which electrically connects the second circuit structure, so as to form another substrate structure; and removing the support to expose the second build-up structure.

[0009] In an embodiment of the aforementioned method, the first circuit structure comprises a first circuit layer formed on the first core layer and at least one first conductive via formed in the first core layer, so that the first conductive via electrically connects the first circuit layer and the first wiring layer.

[0010] In an embodiment of the aforementioned method, the first build-up structure comprises an insulating layer formed on the first core layer and the first circuit structure, and a wiring layer formed on the insulating layer and electrically connected to the first circuit structure.

[0011] In an embodiment of the aforementioned method, the second circuit structure comprises a second circuit layer formed on the second core layer and at least one second conductive via formed in the second core layer, so that the second conductive via electrically connects the second circuit layer and the second wiring layer.

[0012] In an embodiment of the aforementioned method, the second build-up structure includes an insulating layer formed on the second core layer and the second circuit structure, and a wiring layer formed on the insulating layer and electrically connected to the second circuit structure.

[0013] In an embodiment of the aforementioned method, the bonding layer is a thermal release adhesive, a photo-sensitive release adhesive, or a temporary adhesive sheet.

[0014] In an embodiment of the aforementioned method, the support member is a thermal release adhesive, a photo-sensitive release adhesive, or a temporary adhesive sheet.

[0015] In an embodiment of the aforementioned method, the bonding layer and the support member are of the same material.

[0016] In an embodiment of the aforementioned method, the bonding layer and the support member are of different materials. For example, the bonding layer has a higher release temperature than the support member.

[0017] As can be seen from the above, the method for manufacturing a packaging substrate of the present application mainly uses the bonding layer and the support member to improve the flexibility of the multi-plate assembly in the process and to solve the problem of uneven stress distribution of the asymmetric substrate type, so that the substrate structure remains in a non-warping state. Therefore, the method of the present application can avoid the problems of warping, bending or other deformation during the process of manufacturing the first and second build-up structures, so that the first and second build-up structures can use ultra-thin insulating layers to meet the thinning requirements, and the production layers of the first and second build-up structures can be adjusted arbitrarily according to product requirements.

[0018] Furthermore, the method for manufacturing a packaging substrate of the present application combines the bonding layer and the support member with at least two thinner first and second substrates to increase the required structural thickness in the process, thereby helping to maintain stability during transportation to avoid plate jamming, making the processability of the ultra-thin asymmetric substrate structure not limited by the performance of the equipment, achieving the equipment capability of the minimum plate thickness, so that the method of the present application can be processed using conventional processing equipment without the need for special equipment. Not only can the processing cost be greatly reduced, but the yield can also be improved.

[0019] In addition, the method for manufacturing a packaging substrate of the present application combines the bonding layer and the support member with two first and two second substrates, and then performs circuit and build-up processes to obtain four substrate structures. Therefore, the method of the present application can process multiple sets of substrates to improve production efficiency and increase production capacity.

[0020] In addition, the method for manufacturing a packaging substrate of the present application can manufacture an ultra-thin packaging substrate, thereby reducing the signal transmission loss of the packaging substrate. BRIEF DESCRIPTION OF DRAWINGS

[0021] Figures 1A-1KCross-sectional view of a first embodiment of a method of manufacturing a package substrate according to the present application.

[0022] Figures 2A-2D Cross-sectional view of a second embodiment of a method of manufacturing a package substrate according to the present application.

[0023] Reference signs are as follows:

[0024] 1 package substrate

[0025] 1a, 1b, 1c, 1d substrate structure

[0026] 10 carrier

[0027] 11 first circuit structure

[0028] 111 first circuit layer

[0029] 112 first conductive via

[0030] 12 first build-up structure

[0031] 120, 140 insulating layer

[0032] 121, 141 wiring layer

[0033] 13 second circuit structure

[0034] 131 second circuit layer

[0035] 132 second conductive via

[0036] 14 second build-up structure

[0037] 15 solder resist layer

[0038] 150 opening

[0039] 16 surface treatment layer

[0040] 2, 7 support

[0041] 3 processing structure

[0042] 5 multi-board assembly

[0043] 6 bonding layer

[0044] 8 second substrate

[0045] 80 second core layer

[0046] 81 second metal layer

[0047] 810 second wiring layer

[0048] 82, 92 metal cap layer

[0049] 9 first substrate

[0050] 90 first core layer

[0051] 91 first metal layer

[0052] 910 first wiring layer DETAILED DESCRIPTION

[0053] Other advantages and effects of the present application can be easily understood by those skilled in the art from the contents disclosed in the present specification.

[0054] It is to be understood that the structures, proportions, sizes, etc. shown in the drawings accompanying the present specification are merely intended to facilitate the understanding of the contents disclosed in the present specification for the understanding and reading of those skilled in the art, and are not intended to limit the conditions under which the present application can be implemented, and therefore do not have technical significance. Any modification of the structure, change of the proportional relationship, or adjustment of the size, without affecting the effects that can be produced by the present application and the purposes that can be achieved, should still fall within the scope of the technical content disclosed by the present application. At the same time, the terms such as "upper", "first", "second", "one", etc. cited in the present specification are only for the convenience of clear description, and are not intended to limit the scope of the present application that can be implemented, and the change or adjustment of the relative relationship without substantially changing the technical content should also be considered as the scope of the present application that can be implemented.

[0055] Figures 1A-1K A cross-sectional schematic view of a first embodiment of a manufacturing method of the package substrate 1 of the present application.

[0056] As shown in Figure 1A a first substrate 9 is combined on the opposite sides of a carrier 10, wherein the first substrate 9 comprises a first core layer 90 having a first metal layer 91 on the opposite surfaces thereof, and a metal cap layer 92 is formed on the first metal layer 91, so that the first substrate 9 is combined to the carrier 10 by the metal cap layer 92 on one side thereof, and the metal cap layer 92 on the other side is exposed.

[0057] In this embodiment, the first core layer 90 is made of high hardness dielectric material, such as bismaleimide triazine (BT), glass, ceramic, SiC, AI02, or composite material, and the first metal layer 91 is thin copper layer with thickness of about 3 micrometers (um), so that the first substrate 9 becomes copper clad laminate (CCL). For example, the metal cap layer 92 is thick copper layer, such as copper foil, with thickness of about 18 micrometers (um), and the total thickness of the first core layer 90 and the first metal layer 91 is less than or equal to 40 um, such as 35 um, 30 um, 25 um, 20 um, etc.

[0058] Further, the carrier 10 is dielectric structure, such as ABF film (Ajinomoto build-up film), Prepreg (PP), or other dielectric material.

[0059] As shown in FIG. 1, the metal cap layer 92 is removed to expose the first metal layer 91. Then, the first metal layer 91 is patterned to form a first circuit structure 11 on the first core layer 90. Figure 1B

[0060] In this embodiment, each of the first circuit structures 11 includes a first circuit layer 111 formed on the first core layer 90 and a plurality of first conductive vias 112 formed in the first core layer 90, so that the first conductive vias 112 electrically connect the first circuit layer 111 and the first metal layer 91. For example, a plurality of holes are formed on the first core layer 90 by laser, and then copper is electroplated on the first core layer 90 and in the holes to integrally form the first circuit layer 111 and the first conductive vias 112.

[0061] Further, the first circuit layer 111 and the first conductive vias 112 are made of redistribution layer (RDL) specification, and the first conductive vias 112 are in the shape of tapered cylinder.

[0062] As shown in FIG. 1, a first build-up structure 12 electrically connected to the first circuit structure 11 is formed on each of the first core layer 90 and the first circuit structure 11, wherein each of the first build-up structures 12 includes an insulating layer 120 formed on the first core layer 90 and the first circuit layer 111, and a wiring layer 121 formed on the insulating layer 120 and electrically connected to the first circuit layer 111. Figure 1C

[0063] ​​In this embodiment, the wiring layer 121 is a redistribution layer (RDL) specification, which is fabricated using a build-up process by electroplating metal (such as copper) or other methods. For example, multiple holes are first formed on the insulating layer 120 using a laser, and then copper is electroplated on the insulating layer 120 and in the holes to integrally form the wiring layer 121.

[0064] Furthermore, the insulating layer 120 is ABF film (Ajinomoto build-up film), polybenzoxazole (PBO), polyimide (PI), prepreg (PP), or other dielectric materials.

[0065] It is understandable that by using the layering method, the number of layers in the layered structure can be designed according to needs to create the required number of wiring layers.

[0066] like Figure 1D As shown, a second substrate 8 is bonded to each of the first add-on structures 12 by a bonding layer 6. The second substrate 8 includes a second core layer 80, which has a second metal layer 81 on its two opposing surfaces, and a metal cover layer 82 is formed on the second metal layer 81, so that the second substrate 8 is bonded to the bonding layer 6 with the metal cover layer 82 on one side, while the metal cover layer 82 on the other side is exposed.

[0067] In this embodiment, each of the second core layers 80 is made of a high-hardness dielectric material, such as bis(maleic)imide triazine (BT), glass, ceramic, SiC, AlO2, or a composite material, and the second metal layer 81 is a thin copper layer with a thickness of approximately 3 micrometers, making the second substrate 8 a copper clad laminate (CCL). For example, the metal capping layer 82 is a thick copper layer, such as copper foil, with a thickness of approximately 18 micrometers (µm).

[0068] Furthermore, the bonding layer 6 is a thermally release adhesive, a photosensitive release adhesive, or a temporarily removable adhesive sheet, such as a double-sided thermally release film.

[0069] like Figure 1E As shown, the metal cover layer 82 of the second substrate 8 is removed, exposing the second metal layer 81. Then, a patterning circuit process is performed on the second metal layer 81 to form a second circuit structure 13 on the second core layer 80.

[0070] In this embodiment, the second circuit structure 13 includes a second circuit layer 131 formed on the second core layer 80 and a plurality of second conductive vias 132 formed in the second core layer 80, so as to electrically connect the second circuit layer 131 and the second metal layer 81 via the second conductive vias 132. For example, a plurality of holes are formed on the second core layer 80 by laser, and then copper is electroplated on the second core layer 80 and in the holes to integrally form the second circuit layer 131 and the second conductive vias 132.

[0071] Further, the second circuit layer 131 and the second conductive vias 132 are of a redistribution layer (RDL) specification, and the second conductive vias 132 are in a conical shape.

[0072] As shown in FIG. 1, a second build-up structure 14 electrically connected to the second circuit structure 13 is formed on each of the second core layer 80 and the second circuit structure 13, so as to form a multi-board assembly 5 including the first circuit structure 11, the first build-up structure 12, the second circuit structure 13, and the second build-up structure 14 on opposite sides of the carrier 10. Figure 1F

[0073] In this embodiment, the wiring layer 141 is of a redistribution layer (RDL) specification, and is made of electroplated metal (such as copper) or other means by a build-up process. For example, a plurality of holes are formed on the insulating layer 140 by laser, and then copper is electroplated on the insulating layer 140 and in the holes to integrally form the wiring layer 141.

[0074] Further, the insulating layer 140 is an ABF film, a polybenzoxazole (PBO), a polyimide (PI), a prepreg (PP), or other dielectric material.

[0075] It should be understood that, by using the build-up process, the number of layers of the build-up structure can be designed as required to make the wiring layer with the required number of layers.

[0076] As shown in FIG. 1, a second build-up structure 14 electrically connected to the second circuit structure 13 is formed on each of the second core layer 80 and the second circuit structure 13, so as to form a multi-board assembly 5 including the first circuit structure 11, the first build-up structure 12, the second circuit structure 13, and the second build-up structure 14 on opposite sides of the carrier 10. Figure 1G ​As shown, the carrier 10 is removed to separate the two multi-plate assemblies 5. Then, another metal cover layer 92 of the first substrate 9 of the multi-plate assembly 5 is removed, exposing another first metal layer 91 on the first core layer 90. Next, the multi-plate assembly 5 is attached to opposite sides of a support member 7, and the multi-plate assembly 5 is attached to the support member 7 by its second layering structure 14, exposing another first metal layer 91 on the first core layer 90.

[0077] In this embodiment, the support member 7 is a thermally release adhesive, a photosensitive release adhesive, or a temporarily removable adhesive sheet, such as a double-sided thermally release film.

[0078] like Figure 1H As shown, a first wiring layer 910 electrically connected to the first conductive via 112 is formed on the first core layer 90 by performing a patterned circuit process on another first metal layer 91 on the first core layer 90, so as to form substrate structures 1a, 1b.

[0079] In this embodiment, the first wiring layer 910 adopts the redistribution layer (RDL) specification.

[0080] like Figure 1I As shown, the bonding layer 6 is removed to separate the two substrate structures 1a and 1b, and the support member 7 is removed to obtain two processing structures 3, thereby exposing the second augmentation structure 14.

[0081] In this embodiment, the bonding layer 6 and the support member 7 are made of the same material, so the bonding layer 6 and the support member 7 are removed simultaneously in the same manner. For example, the bonding layer 6 and the support member 7 are heated at the same temperature to separate the two substrate structures 1a, 1b and the two processing structures 3 with the second core layer 80.

[0082] like Figure 1J As shown, another metal cover layer 92 on the second core layer 80 of the two processing structures 3 is removed to expose another second metal layer 81 on the second core layer 80. Then, a second wiring layer 810 electrically connected to the second conductive via 132 is formed on the second core layer 80 of the processing structure 3 by performing a patterning circuit process on the other second metal layer 81, so as to form another substrate structure 1c, 1d.

[0083] In this embodiment, the second wiring layer 810 adopts the redistribution layer (RDL) specification.

[0084] like Figure 1KAs shown, a solder resist layer 15, such as a green paint, is formed on opposite sides of the substrate structure 1a, 1b, 1c, 1d to form a package substrate 1, and a plurality of openings 150 are formed in the solder resist layer 15 to expose the first wiring layer 910 or the second wiring layer 810 and the wiring layer 121, 141, for bonding a surface treatment layer 16, such as a nickel / gold material.

[0085] In this embodiment, a plurality of solder balls (not shown) are bonded to the exposed surfaces of the first wiring layer 910 or the second wiring layer 810 and the wiring layer 121, 141 in subsequent processes, for connecting external electronic devices, such as semiconductor chips, passive components, silicon interposers, circuit boards or other components.

[0086] The manufacturing method of the present application is used to manufacture an asymmetric package substrate 1, which mainly uses the bonding layer 6 and the support 7 to improve the flexibility of the multi-board assembly 5 in the process and to solve the problem of uneven stress distribution in the asymmetric substrate type, so that the substrate structure 1a, 1b, 1c, 1d remains in a non-warping state. Therefore, compared with the prior art, the first build-up structure 12 and the second build-up structure 14 can avoid the problem of warping, bending or other deformation during the process, so that a super-thin dielectric layer can be used as the insulating layer 120, 140 to meet the thinning requirement, and the production layers of the first build-up structure 12 and the second build-up structure 14 can be adjusted arbitrarily according to product requirements.

[0087] Furthermore, the bonding layer 6 and the support 7 are combined with at least two thinner first substrates 9 and second substrates 8 to increase the required structural thickness in the process, thereby helping to maintain stability during transportation to avoid clamping, so that the processability of the super-thin asymmetric substrate structure 1a, 1b, 1c, 1d is not limited by the performance of the equipment, and the equipment capability of the minimum board thickness (such as the acid pickling capability of the minimum board thickness before circuit manufacturing is 0.06mm) is achieved. Therefore, the manufacturing method of the package substrate 1 of the present application can be processed using conventional processing equipment without the need for special equipment, which not only greatly reduces the processing cost, but also improves the yield.

[0088] In addition, the bonding layer 6 and the support 7 are combined with two first substrates 9 and two second substrates 8, and then the circuit process and the build-up process are performed to obtain four substrate structures 1a, 1b, 1c, 1d. Therefore, the manufacturing method of the package substrate 1 of the present application can process multiple sets of substrates to improve production efficiency and increase production capacity by at least four times.

[0089] In addition, the manufacturing method of the present application can manufacture a super-thin package substrate 1, thereby effectively reducing the signal transmission loss of the package substrate 1.

[0090] Figures 2A-2DThis is a cross-sectional schematic diagram of a second embodiment of the manufacturing method of the packaging substrate 1 of the present invention. The difference between this embodiment and the first embodiment lies in the material of the support member 2; other processes are largely the same, so the similarities will not be repeated below.

[0091] like Figure 2A As shown, according to Figure 1I The process involves removing the bonding layer 6 to separate the two substrate structures 1a and 1b, while the two processing structures 3 remain bonded to the support member 2, and another metal cover layer 92 is exposed on the second core layer 80 of the two processing structures 3.

[0092] In this embodiment, the bonding layer 6 and the support member 2 are made of different materials. The dissociation temperature of the support member 2 is higher than that of the bonding layer 6, so the support member 2 has not been removed. For example, the dissociation temperature of the support member 2 is greater than or equal to 240°C, and the dissociation temperature of the bonding layer 6 is 150°C.

[0093] like Figure 2B As shown, using Figure 1J The process involves removing the metal cover layer 92 on the second core layer 80 of the two processing structures 3, and then using the second metal layer 81 to fabricate the second wiring layer 810 to form the substrate structure 1c, 1d.

[0094] like Figure 2C As shown, the support member 2 is removed to obtain the substrate structure 1c, 1d, thereby exposing the second layer structure 14.

[0095] like Figure 2D As shown, using Figure 1K The process involves forming solder resist layers 15 on opposite sides of the substrate structures 1a, 1b, 1c, and 1d to form a package substrate 1 with a surface treatment layer 16.

[0096] In summary, the method for manufacturing the packaging substrate of the present invention improves the toughness of multi-board assemblies during the process by using bonding layers and support members, thereby improving the problem of uneven stress distribution in asymmetric substrate types and keeping the substrate structure in a warp-free state. Therefore, the present invention can avoid warping, bending or other deformation problems during the manufacturing of the first and second add-on structures. Thus, the first and second add-on structures can use ultra-thin insulating layers to meet the requirements of thinning, and the number of production layers of the first and second add-on structures can be arbitrarily adjusted according to product requirements.

[0097] Furthermore, the manufacturing method of the packaging substrate of the present application combines the bonding layer and the support to combine at least two thinner first substrates and second substrates, so as to increase the structural thickness required by the process, thereby helping to maintain stability during transportation to avoid clamping, making the processability of the ultra-thin asymmetric substrate structure not limited by the performance of the equipment, achieving the equipment capacity of the minimum plate thickness, so that the manufacturing method of the present application can be processed using conventional processing equipment without the need to use special equipment. Not only can the processing cost be greatly reduced, but the yield can also be improved.

[0098] In addition, the manufacturing method of the packaging substrate of the present application combines the bonding layer and the support to combine two first substrates and two second substrates, and then performs a circuit process and a build-up process to obtain four substrate structures, so that the manufacturing method of the present application can process multiple groups of substrates to improve production efficiency and increase production capacity.

[0099] In addition, the manufacturing method of the present application can manufacture ultra-thin packaging substrates, thereby effectively reducing the signal transmission loss of the packaging substrates.

[0100] The above embodiments are used to illustrate the principles and effects of the present application, but are not used to limit the present application. Those skilled in the art can modify the above embodiments without departing from the spirit and scope of the present application. Therefore, the protection scope of the present application should be as listed in the claims.

Claims

1. A method for manufacturing a packaging substrate, characterized in that, include: A first substrate is attached to each of the opposite sides of a carrier, wherein each of the first substrates includes a first core layer and two first metal layers formed on opposite surfaces of the first core layer. A first circuit structure is formed on each of the first core layers by means of the first metal layer; A first add-in structure electrically connected to the first circuit structure is formed on each of the first core layers and the first circuit structure; A second substrate is bonded to each of the first added-layer structures by a bonding layer, wherein each of the second substrates includes a second core layer and two second metal layers respectively formed on opposite surfaces of the second core layer; A second circuit structure is formed on each of the second core layers by means of the second metal layer; A second add-in structure electrically connected to the second circuit structure is formed on each of the second core layers and the second circuit structure, so that a multi-board assembly containing a first circuit structure, a first add-in structure, a second circuit structure and a second add-in structure are formed on opposite sides of the carrier. Remove the carrier to separate the two multi-plate assemblies; The multi-plate assembly is attached to opposite sides of a support member, and the multi-plate assembly is attached to the support member with its second layering structure, exposing another first metal layer on the first core layer. A first wiring layer electrically connected to the first circuit structure is formed on the first core layer by another first metal layer to form a substrate structure; Remove the bonding layer to separate the two substrate structures and obtain two processed structures with the second core layer, and expose another second metal layer on the second core layer. A second wiring layer electrically connected to the second circuit structure is formed on the second core layer of the processing structure via another second metal layer to form another substrate structure; and Remove the support member to expose the second layer structure.

2. The method for manufacturing the packaging substrate as described in claim 1, characterized in that, The first circuit structure includes a first circuit layer formed on the first core layer and at least one first conductive via formed in the first core layer, so that the first conductive via electrically connects the first circuit layer and the first wiring layer.

3. The method for manufacturing the packaging substrate as described in claim 1, characterized in that, The first add-on structure includes an insulating layer formed on the first core layer and the first circuit structure, and a wiring layer formed on the insulating layer and electrically connected to the first circuit structure.

4. The method for manufacturing the packaging substrate as described in claim 1, characterized in that, The second circuit structure includes a second circuit layer formed on the second core layer and at least one second conductive via formed in the second core layer, so that the second conductive via electrically connects the second circuit layer and the second wiring layer.

5. The method for manufacturing the packaging substrate as described in claim 1, characterized in that, The second add-on structure includes an insulating layer formed on the second core layer and the second circuit structure, and a wiring layer formed on the insulating layer and electrically connected to the second circuit structure.

6. The method for manufacturing the packaging substrate as described in claim 1, characterized in that, The bonding layer is a thermally disintegrating adhesive, a photosensitive disintegrating adhesive, or a temporarily removable adhesive sheet.

7. The method for manufacturing the packaging substrate as described in claim 1, characterized in that, The support is made of thermally dissociable adhesive, photosensitive dissociable adhesive, or a temporarily removable adhesive sheet.

8. The method for manufacturing the packaging substrate as described in claim 1, characterized in that, The bonding layer and the support are made of the same material.

9. The method for manufacturing the packaging substrate as described in claim 1, characterized in that, The bonding layer and the support component are made of different materials.

10. The method for manufacturing the packaging substrate as described in claim 9, characterized in that, The dissociation temperature of the bonding layer is higher than that of the support member.

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