Board-level-based CoWoS packaging method and structure

Abstract

The invention discloses a board-level-based CoWoS packaging method, which relates to the technical field of CoWoS packaging, and comprises the following steps of: cutting a silicon intermediate layer into a plurality of rectangular modules, each of which is provided with a complete silicon through hole; all the modules are bonded to a first temporary carrier plate with the Panel-level size; grinding the top of the coated integral structure for the first time; covering and bonding a second temporary support plate on the top of the overall structure after the first grinding; the overall structure covered with the second temporary carrier plate is turned over, and the first temporary carrier plate is removed; performing secondary grinding on the top of the integral structure after the first temporary support plate is removed until the silicon through hole is exposed; and connecting a re-wiring layer to the top of the overall structure after the second grinding. According to the method, the utilization rate of the silicon interposer is improved, the chip packaging and manufacturing cost is reduced, the CoWoS process is completed on the large-size square substrate of 510 * 515 mm, and compared with a wafer level, the method has the outstanding advantages of high productivity, large-size integration, high cost performance and the like.

Description

Technical Field

[0001] The present invention relates to the field of CoWoS packaging technology, and in particular to a board-level CoWoS packaging method and structure. Background Art

[0002] The current CoWoS packages are all manufactured at the wafer level, and all processes are performed on complete wafers. However, the final package of the chip is often square or rectangular, especially for large high-performance chips, such as AI chips and HPC chips, which have a large area. As the size of the package structure becomes larger and larger, since the wafer is circular, the edge area cannot accommodate a complete square large package. As a result, only the middle part of the wafer can be used, and a large amount of silicon interposer area on the edges is wasted. However, the silicon interposer material is expensive, which greatly increases the manufacturing cost. The current 300mm wafer-level packaging solution still has the following pain points: First, the wafer level is limited by the 300mm substrate and circular physical form. When corresponding to large-size products (such as GPUs and FPGAs in high-performance computing, artificial intelligence and other fields), its edge waste is large, the output efficiency is low, and the production capacity is low; secondly, the wafer level adopts a spin coating process, and the effective utilization rate of expensive photosensitive materials such as PI polyimide and PR photoresist is only about 20%-30%. Therefore, the applicant has developed a board-level CoWoS packaging method and structure to solve the above problems. Summary of the Invention

[0003] The present invention proposes a board-level CoWoS packaging method and structure to solve the problems of low silicon interposer utilization, material waste, high cost and low production efficiency in existing CoWoS packaging technology.

[0004] The present invention achieves the above-mentioned purpose through the following technical solutions: The present invention provides a board-level CoWoS packaging method, comprising: Cutting the silicon interposer into a plurality of rectangular modules, each of the modules having a complete through-silicon via; Bonding each of the modules to a first temporary carrier board of panel-level size; Flip-chipping the chip onto the cut silicon interposer and connecting it to the silicon interposer through the through-silicon vias, encapsulating the chip with a potting plastic material, and then performing a first grinding on the top of the encapsulated overall structure; covering and bonding a second temporary carrier plate on top of the first ground integral structure; Turning over the entire structure covered with the second temporary carrier plate and removing the first temporary carrier plate; performing a second grinding on the top of the overall structure after removing the first temporary carrier until the through silicon via is exposed; A redistribution layer is connected on top of the overall structure after the second grinding.

[0005] Furthermore, a copper column is connected on the top of the redistribution layer, and then the second temporary carrier is removed.

[0006] Furthermore, the silicon interposer is cut into several modules according to the size of the chip package required in the end.

[0007] Furthermore, the overall structure after removing the second temporary carrier is cut into a plurality of chip packages as required.

[0008] Furthermore, the single module or package is mounted on a substrate via copper pillars, and solder balls are connected to the substrate to obtain a final package structure.

[0009] Furthermore, each of the modules is bonded to a first temporary carrier board of panel-level size, and the modules completely cover the first temporary carrier board.

[0010] Furthermore, the first temporary carrier plate is a rectangular plate.

[0011] The present invention also provides a board-level CoWoS packaging structure, wherein the board-level CoWoS packaging structure is a packaging structure prepared according to the board-level CoWoS packaging method.

[0012] The beneficial effects of the present invention are: The present invention proposes a board-level CoWoS packaging method and structure, which breaks the wafer size limitation, realizes a rectangular large-area packaging substrate, improves the utilization rate of the silicon interposer, and reduces the chip packaging manufacturing cost. Compared with the wafer level, it has many outstanding advantages such as high production capacity, large-size integration, and high cost performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 This is a flow chart of the board-level CoWoS packaging method of this application. DETAILED DESCRIPTION

[0014] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings of the embodiments of the present invention. It should be understood that the described embodiments are only a portion of the embodiments of the present invention, not all of them. Generally, the components of the embodiments of the present invention described and illustrated in the drawings herein may be arranged and designed in a variety of different configurations.

[0015] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention as claimed, but rather merely represents selected embodiments of the present invention. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without creative effort shall fall within the scope of protection of the present invention.

[0016] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings.

[0017] In the description of the present invention, it should be understood that the terms "upper", "lower", "inside", "outside", "left", "right", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, or are the orientations or positional relationships in which the inventive product is conventionally placed when in use, or are the orientations or positional relationships conventionally understood by those skilled in the art. These are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or component referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.

[0018] Furthermore, the terms “first”, “second”, etc. are merely used for distinguishing descriptions and should not be understood as indicating or implying relative importance.

[0019] In the description of the present invention, it should also be noted that, unless otherwise expressly specified or limited, terms such as "disposed" and "connected" should be understood in a broad sense. For example, "connected" can mean a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can also mean internal communication between two components. Those skilled in the art will be able to understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0020] The specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0021] like Figure 1 As shown, a board-level CoWoS packaging method and structure includes: A board-level CoWoS packaging method, comprising: Cutting the silicon interposer into a plurality of rectangular modules, each of the modules having a complete through-silicon via; Bonding each of the modules to a first temporary carrier board of panel-level size; Flip-chipping the chip onto the cut silicon interposer and connecting it to the silicon interposer through the through-silicon vias, encapsulating the chip with a potting plastic material, and then performing a first grinding on the top of the encapsulated overall structure; covering and bonding a second temporary carrier plate on top of the first ground integral structure; Turning over the entire structure covered with the second temporary carrier plate and removing the first temporary carrier plate; performing a second grinding on the top of the overall structure after removing the first temporary carrier until the through silicon via is exposed; A redistribution layer is connected on top of the overall structure after the second grinding.

[0022] In one embodiment, copper pillars are connected on top of the redistribution layer, and then the second temporary carrier is removed.

[0023] In one embodiment, the silicon interposer is cut into several modules according to the size of the chip package required in the end, thereby further improving the utilization rate of the silicon interposer.

[0024] Figure 1 In the figure, carrier1 represents the first temporary carrier, and carrier2 represents the second temporary carrier.

[0025] In one embodiment, the overall structure after removing the second temporary carrier is cut into a plurality of chip packages as required.

[0026] In one embodiment, the single module or package is mounted on a substrate via copper pillars, and solder balls are connected to the substrate to obtain a final package structure.

[0027] In one embodiment, each of the modules is bonded to a first temporary carrier of panel-level size, and the modules completely cover the first temporary carrier.

[0028] In one embodiment, the first temporary carrier plate is a rectangular plate.

[0029] This embodiment also provides a board-level CoWoS packaging structure, wherein the board-level CoWoS packaging structure is a packaging structure prepared according to the board-level CoWoS packaging method.

[0030] The present invention proposes a board-level CoWoS packaging method and structure. By pre-cutting the silicon interposer and introducing a first temporary carrier for flip-chip and transfer processing, it breaks the wafer size limitation and transitions from the silicon wafer to the panel carrier. The CoWoS process is completed on a 510×515mm large-size square substrate for rectangular large-area packaging substrates, which improves the utilization rate of the silicon interposer and reduces the chip packaging manufacturing cost. Compared with the wafer level, it has many outstanding advantages such as high production capacity, large-size integration, and high cost performance.

[0031] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the technical principles of the present invention. These improvements and modifications should also be regarded as within the scope of protection of the present invention.

Claims

1. A board-level CoWoS packaging method, characterized in that: include: Cutting the silicon interposer into a plurality of rectangular modules, each of the modules having a complete through-silicon via; Bonding each of the modules to a first temporary carrier board of panel-level size; Flip-chipping the chip onto the cut silicon interposer and connecting it to the silicon interposer through the through-silicon vias, encapsulating the chip with a potting plastic material, and then performing a first grinding on the top of the encapsulated overall structure; covering and bonding a second temporary carrier plate on top of the first ground integral structure; Turning over the entire structure covered with the second temporary carrier plate and removing the first temporary carrier plate; performing a second grinding on the top of the overall structure after removing the first temporary carrier until the through silicon via is exposed; A redistribution layer is connected on top of the overall structure after the second grinding.

2. The board-level CoWoS packaging method according to claim 1, wherein: Copper pillars are connected on top of the redistribution layer, and then the second temporary carrier is removed.

3. The board-level CoWoS packaging method according to claim 1, wherein: The silicon interposer is cut into several modules according to the size of the chip package required in the end.

4. The board-level CoWoS packaging method according to claim 1, wherein: The overall structure after removing the second temporary carrier is cut into a plurality of chip packages as required.

5. The board-level CoWoS packaging method according to claim 4, characterized in that: The single module or package is mounted on a substrate via copper pillars, and solder balls are connected to the substrate to obtain a final package structure.

6. The board-level CoWoS packaging method according to claim 1, wherein: Each of the modules is bonded to a first temporary carrier board of panel-level size, and the modules completely cover the first temporary carrier board.

7. The board-level CoWoS packaging method according to claim 1, wherein: The first temporary carrier plate is a rectangular plate.

8. A board-level CoWoS packaging structure, characterized in that: The board-level CoWoS packaging structure is a packaging structure prepared by a board-level CoWoS packaging method according to any one of claims 1-7.

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