Chip, manufacturing method thereof and electronic equipment

Abstract

The embodiment of the invention provides a chip, a manufacturing method thereof and electronic equipment, relates to the technical field of semiconductors, and is used for improving the performance of components under the condition that the miniature size requirement of the components of the electronic equipment is met. The chip comprises a plurality of array structures, and a first isolation retaining wall in each array structure is located between a first transistor column and a second transistor column. Each of the first transistor column and the second transistor column comprises a plurality of vertical channels, a gate dielectric layer and a first signal line. The plurality of vertical channels are arranged on the side wall of the first isolation retaining wall at intervals. The gate dielectric layer and the first signal line wrap the vertical channels on three sides, and the gate dielectric layer and the first signal line continuously cover the plurality of vertical channels and part of the first isolation retaining wall among the plurality of vertical channels. And the gate dielectric layer, the first signal line and the vertical channel wrapped by the first signal line form a vertical transistor. The vertical transistor is only provided with a first signal line serving as a grid on a single side, so that the device miniaturization is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a chip, a manufacturing method thereof, and an electronic device. Background Art

[0002] With the continuous advancement of semiconductor technology, components in electronic devices, such as memory chips, need to be continuously miniaturized to meet user demands for high-performance electronic devices, such as large-capacity and high-bandwidth storage, within the limited layout space of electronic devices. However, the performance and storage density of memory chips are gradually becoming important factors limiting the performance of electronic devices. For example, as storage density continues to increase, the miniaturization of storage cells within memory chips will affect the performance of components within the memory chips, such as transistors, thereby reducing product reliability. Summary of the Invention

[0003] The present application provides a chip and a manufacturing method thereof, and an electronic device, which are used to improve the performance of components while meeting the miniaturization requirements of components of electronic devices.

[0004] To achieve the above objectives, this application adopts the following technical solutions:

[0005] In one aspect of the present application, a chip is provided, comprising a substrate and multiple array structures. The multiple array structures are disposed on the substrate and spaced apart along a first direction. The array structures include a first isolation barrier, a first transistor column, and a second transistor column. The first isolation barrier is located between the first transistor column and the second transistor column. Each of the first and second transistor columns includes multiple vertical channels, a gate dielectric layer, and a first signal line. The multiple vertical channels are spaced apart along a second direction on the sidewalls of the first isolation barrier. The vertical channels are disposed perpendicular to the substrate, with the first and second directions intersecting and parallel to the substrate. The gate dielectric layer is located on the side of the vertical channels facing away from the isolation barrier. The gate dielectric layer wraps around the vertical channels on three sides and continuously covers the multiple vertical channels and the portion of the first isolation barrier between the multiple vertical channels. The first signal line is located on the side of the gate dielectric layer facing away from the first isolation barrier. The first signal line wraps around the vertical channels on three sides and continuously covers the multiple vertical channels and the portion of the first isolation barrier between the multiple vertical channels.

[0006] As can be seen from the above, on the one hand, the first isolation barrier is located between the first transistor column and the second transistor column, and in either of the first transistor column and the second transistor column, the first signal line is arranged on the side of the gate dielectric layer or the vertical channel facing away from the first isolation barrier. Therefore, the vertical channel and the portion of the first signal line that wraps around the vertical channel can constitute a vertical transistor, and the portion of the first signal line that wraps around the vertical channel can serve as the gate of the vertical transistor. Because the side of the vertical channel of the vertical transistor facing the first isolation barrier is located on the sidewall of the first isolation barrier, no gate is provided on the side of the vertical channel facing the first isolation barrier. In this way, along the first direction, the vertical transistor is only provided with a gate on one side, thereby making the chip scalable in the first direction. On the other hand, the vertical channel of the vertical transistor is located on the sidewall of the first isolation barrier, and the first isolation barrier can support the vertical channel, thereby reducing the processing difficulty of reducing the thickness of the vertical channel along the first direction and improving scalability.

[0007] On the other hand, the first signal line wraps around the vertical channel on three sides to provide three-dimensional coverage of the first signal line on three sides, so that the electric field lines of the vertical transistor are more concentrated, which is beneficial to improving the gate control ability and on-state current of the vertical transistor, and achieving the purpose of improving the performance of the vertical transistor, thereby being able to improve the performance of the components while meeting the miniaturization requirements of the components of the electronic device. In addition, the gate dielectric layer and the first signal line can continuously cover the multiple vertical channels and part of the first isolation barrier between the multiple vertical channels. Therefore, along the direction in which the multiple vertical channels are arranged (i.e., the second direction), the gate dielectric layer and the first signal line are both continuous structures. In this way, during the manufacturing process, the multiple vertical channels arranged at intervals can be first formed on both sides of the first isolation barrier, and then the gate dielectric layer and the first signal line can be formed in sequence on the side of any row of multiple vertical channels away from the first isolation barrier.

[0008] In an optional embodiment, the vertical channel includes a first portion and a second portion. The first portion is arranged in a direction perpendicular to the substrate. The second portion is connected to an end of the first portion facing the substrate, and the second portion is arranged along the first direction. The chip also includes a second signal line, which is arranged between the array structure and the substrate, the second signal line extending along the first direction, and the second signal line contacts the second portion. In this way, since the second portion is electrically connected to the second signal line and the second portion is arranged along the first direction, the second portion can increase the contact area between the entire vertical channel and the second signal line, thereby reducing the contact resistance.

[0009] In one optional embodiment, the second portions of two adjacent vertical channels in different array structures are connected, so that the two connected vertical channels form a U-shaped structure. A portion of the U-shaped semiconductor structure is arranged along the first direction and is electrically connected to the second signal line, thereby increasing the contact area between the entire vertical channel and the second signal line and reducing contact resistance.

[0010] In one optional embodiment, the chip includes multiple second signal lines. The chip also includes a third isolation barrier wall, which is disposed between two adjacent second signal lines to isolate the adjacent second signal lines. Furthermore, the third isolation barrier wall is made of a different material than the first isolation barrier wall. This ensures that the structure of the first isolation barrier wall is not affected during wet etching of the third isolation barrier wall.

[0011] In an optional embodiment, two adjacent first signal lines of different array structures are connected to form a conductive integral structure, which is filled between two adjacent rows of vertical channels. The conductive integral structure and the two oppositely positioned vertical channels surrounded on three sides by the conductive integral structure can form a vertical transistor with a dual channel. Compared to a single-channel vertical transistor, the on-state current of this dual-channel vertical transistor can be doubled.

[0012] In an optional embodiment, the chip further includes a second isolation barrier. The second isolation barrier is disposed between two adjacent array structures and is located on the side of the conductive integral structure facing away from the substrate. The second isolation barrier is used to isolate portions of the vertical channels in the two adjacent array structures that are not covered by the conductive integral structure.

[0013] In an optional embodiment, the chip also includes a second isolation barrier. The second isolation barrier is arranged between two adjacent array structures. Two adjacent first signal lines of different array structures are isolated on both sides of the second isolation barrier, and two adjacent vertical channels of different array structures are isolated on both sides of the second isolation barrier. The second isolation barrier can isolate two adjacent first signal lines in different array structures. In addition, the second isolation barrier can also isolate two adjacent vertical channels in different array structures. Among them, the side surface of the first signal line facing away from the first isolation barrier is flush with the side surface of the second part facing away from the first isolation barrier, and the side surface of the gate dielectric layer facing away from the first isolation barrier. In this way, the above-mentioned L-shaped vertical channel, gate dielectric layer and first signal line can be formed simultaneously through this photolithography process.

[0014] In one alternative embodiment, the first signal line covers the surface of the first portion facing away from the first isolation barrier, as well as the surfaces of the first and second portions perpendicular to the first isolation barrier and the substrate. In this case, the portion of the first signal line covering the second portion resembles a horseshoe shape, thereby increasing the coverage area of the first signal line and reducing the resistance of the first signal line.

[0015] In an optional embodiment, the chip further includes a second isolation barrier wall, which is disposed between two adjacent array structures, and two adjacent first signal lines of different array structures are isolated and disposed on both sides of the second isolation barrier wall. The technical effect of the second isolation barrier wall is the same as described above and will not be repeated here. The first signal line covers a portion of the first isolation barrier wall, and has a first groove on the side facing away from the first isolation barrier wall, and a portion of the second isolation barrier wall is located in the first groove. The top-view structure of the second isolation barrier wall located between two adjacent array structures can be similar to the shape of a "N" character.

[0016] In an optional embodiment, the first transistor column and the second transistor column are symmetrically arranged with respect to the first isolation barrier. This allows the chip structure to have a certain regularity. When manufacturing the chip using a patterning process, preparing a patterned structure with the regularity can simplify the manufacturing process.

[0017] In an optional embodiment, the first transistor column and the second transistor column each further include a first electrode and a second electrode. The first electrode is arranged on the side of the vertical channel facing the substrate. The second electrode is arranged on the side of the vertical channel facing away from the substrate. In this case, a voltage can be applied to the first electrode (e.g., source) and the second electrode (e.g., drain) so that a conducting current flows through the vertical channel. At this time, the vertical transistors in the above-mentioned transistor column can be in an on state. Alternatively, when no conducting current flows through the vertical channel, the vertical transistor can be in an off state.

[0018] In an optional embodiment, the chip further includes a capacitor array disposed on a side of the array structure facing away from the substrate. The capacitor array is electrically connected to at least one of the first transistor column or the second transistor column to form a memory array. The chip having this memory array may be a memory chip.

[0019] In an optional implementation, the chip further includes a controller, which is electrically connected to the storage array. The controller is used to control the reading and writing of the storage array to achieve access to the storage array.

[0020] Another aspect of the present application provides a chip comprising a substrate and multiple array structures. The multiple array structures are disposed on the substrate and spaced apart along a first direction. The array structures include a first isolation barrier, a first transistor column, and a second transistor column. The first isolation barrier is located between the first transistor column and the second transistor column. Each of the first and second transistor columns includes multiple vertical channels, a gate dielectric layer, and a first signal line. The multiple vertical channels are spaced apart along a second direction on the sidewalls of the first isolation barrier. The vertical channels are disposed perpendicular to the substrate, with the first and second directions intersecting and parallel to the substrate. The gate dielectric layer is located on the side of the vertical channels facing away from the isolation barrier. The gate dielectric layer wraps around the vertical channels on three sides and continuously covers the multiple vertical channels and the portion of the first isolation barrier between the multiple vertical channels. The first signal line is located on the side of the gate dielectric layer facing away from the first isolation barrier. The first signal line wraps around the vertical channels on three sides and continuously covers the multiple vertical channels and the portion of the first isolation barrier between the multiple vertical channels. The first signal line can be used as the gate of multiple transistors in the first transistor column or the second transistor column. The chip has the same technical effects as the chip provided in the above embodiment, and will not be described in detail here.

[0021] Another aspect of the present application provides an electronic device comprising a circuit board and any of the chips described above. The circuit board is electrically connected to the chip. The electronic device has the same technical effects as the chip provided in the previous embodiment and will not be described in detail here.

[0022] Another aspect of the present application provides a chip fabrication method, comprising: forming a plurality of first isolation barriers arranged at intervals along a first direction on a substrate. Next, forming transistor columns on both sidewalls of the first isolation barriers. Forming transistor columns on both sidewalls of the first isolation barriers includes: forming a plurality of vertical channels arranged at intervals along a second direction on the sidewalls, wherein the vertical channels are perpendicular to the substrate. The first direction intersects with the second direction and are both parallel to the substrate. Next, forming a gate dielectric layer on a side of the plurality of vertical channels facing away from the isolation barriers. The gate dielectric layer wraps around the vertical channels on three sides and continuously covers the plurality of vertical channels, as well as portions of the first isolation barriers between the plurality of vertical channels. Next, forming a first signal line on a side of the gate dielectric layer facing away from the first isolation barriers. The first signal line wraps around the vertical channels on three sides and continuously covers the plurality of vertical channels, as well as portions of the first isolation barriers between the plurality of vertical channels. In this way, the first signal line formed on the gate dielectric layer can conform to the gate dielectric layer.

[0023] In an optional embodiment, forming a plurality of first isolation walls spaced apart along a first direction on a substrate includes: forming a semiconductor material layer on the substrate. Next, forming a plurality of second grooves extending along the first direction on the semiconductor material layer, and forming third isolation walls within the second grooves, wherein the third isolation walls are made of a different material than the first isolation walls. Next, forming a first mask structure on the semiconductor material layer. Next, removing the semiconductor material layer and the third isolation walls exposed by the first mask structure to form a plurality of third grooves spaced apart along the first direction. Next, forming the first isolation walls within the third grooves. The first isolation walls formed by the photolithography and deposition processes have a high degree of precision in terms of size, position, and spacing between the plurality of first isolation walls.

[0024] In an optional embodiment, after forming the first mask structure, forming a plurality of vertical channels spaced apart along the second direction on the sidewalls includes: removing the first mask structure, forming a second mask structure on the sidewalls of the first isolation barrier, and removing the semiconductor material layer and the third isolation barrier exposed by the second mask structure to form the vertical channels. The vertical channels can form vertical transistors together with the first signal line covering the vertical channels.

[0025] In an optional embodiment, after forming the first mask structure, forming a plurality of vertical channels spaced apart along the second direction on the sidewalls includes: removing the first mask structure, forming a second mask structure on the sidewalls of the first isolation barrier, and removing a portion of the semiconductor material layer and the third isolation barrier exposed by the second mask structure to form the plurality of U-shaped vertical channels. The technical effect of the U-shaped vertical channels is the same as described above and will not be further elaborated here.

[0026] In an optional embodiment, after forming the first mask structure, a plurality of vertical channels spaced apart along the second direction are formed on the sidewalls, and the gate dielectric layer and the first signal line are formed, including: removing the first mask structure, and forming a second mask structure on the sidewalls of the first isolation barrier wall, removing a portion of the semiconductor material layer and the third isolation barrier wall exposed by the second mask structure to form a plurality of U-shaped semiconductor structures. Next, a gate dielectric material layer and a second metal material layer are sequentially formed in the U-shaped semiconductor structure, the gate dielectric material layer and the second metal material layer both wrap the plurality of U-shaped semiconductor structures on three sides, and the gate dielectric material layer and the second metal material layer both continuously cover the U-shaped semiconductor structure, and a portion of the first isolation barrier wall between the plurality of U-shaped semiconductor structures. Next, a portion of the bottom of the U-shaped semiconductor structure is removed, and a portion of the gate dielectric material layer and the second metal material layer covering the bottom of the U-shaped semiconductor structure is removed to form an L-shaped vertical channel, a gate dielectric layer, and a first signal line. The technical effect of the L-shaped vertical channel is the same as described above and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application;

[0028] Figure 2 A schematic diagram of a chip structure used in an electronic device according to an embodiment of the present application;

[0029] Figure 3 For the Figure 2 A top view obtained from the A direction in FIG;

[0030] Figure 4 For the Figure 2 Another top view obtained from the A direction in FIG;

[0031] Figure 5 Schematic diagram of the structure of two symmetrically arranged vertical transistors in 2;

[0032] Figure 6 For the Figure 5 A cross-sectional view obtained by cutting along the dotted line O1-O2 in FIG.

[0033] Figure 7 A schematic diagram of another chip structure used in an electronic device according to an embodiment of the present application;

[0034] Figure 8 A schematic diagram of another chip structure used in an electronic device according to an embodiment of the present application;

[0035] Figure 9 A schematic diagram of another chip structure used in an electronic device according to an embodiment of the present application;

[0036] Figure 10 For the Figure 7 A cross-sectional view obtained by cutting along the dotted line O3-O4 in FIG.

[0037] Figure 11 for Figure 9 A structural schematic diagram of a storage array shown;

[0038] Figure 12 A schematic diagram of another chip structure used in an electronic device according to an embodiment of the present application;

[0039] Figure 13 A flow chart of a chip manufacturing method provided in an embodiment of the present application;

[0040] Figure 14 A schematic diagram of a portion of the fabrication process of the chip provided in an embodiment of the present application;

[0041] Figure 15 A schematic diagram of another part of the structure of the chip manufacturing process provided in an embodiment of the present application;

[0042] Figure 16A A schematic diagram of another part of the structure of the chip manufacturing process provided in an embodiment of the present application;

[0043] Figure 16B For the Figure 16A A top view obtained from the B1 direction;

[0044] Figure 17A A schematic diagram of another part of the structure of the chip manufacturing process provided in an embodiment of the present application;

[0045] Figure 17B For the Figure 17A A top view obtained from the B2 direction;

[0046] Figure 18A A schematic diagram of another part of the structure of the chip manufacturing process provided in an embodiment of the present application;

[0047] Figure 18B For the Figure 18A A top view obtained from the B3 direction;

[0048] Figure 19A A schematic diagram of another part of the structure of the chip manufacturing process provided in an embodiment of the present application;

[0049] Figure 19B For the Figure 19A A top view obtained from the B4 direction;

[0050] Figure 20A A schematic diagram of another part of the structure of the chip manufacturing process provided in an embodiment of the present application;

[0051] Figure 20B For the Figure 20A A top view obtained from the B5 direction;

[0052] Figure 21A A schematic diagram of another part of the structure of the chip manufacturing process provided in an embodiment of the present application;

[0053] Figure 21B For the Figure 21A A top view obtained from the B6 direction;

[0054] Figure 22A A schematic diagram of another part of the structure of the chip manufacturing process provided in an embodiment of the present application;

[0055] Figure 22B For the Figure 22A A top view obtained from the B7 direction;

[0056] Figure 23A schematic diagram of another part of the structure of the chip manufacturing process provided in an embodiment of the present application;

[0057] Figure 24A A schematic diagram of another part of the structure of the chip manufacturing process provided in an embodiment of the present application;

[0058] Figure 24B For the Figure 24A A top view obtained from the B8 direction;

[0059] Figure 25A A schematic diagram of another part of the structure of the chip manufacturing process provided in an embodiment of the present application;

[0060] Figure 25B For the Figure 25A A top view obtained from the B9 direction;

[0061] Figure 26A A schematic diagram of another part of the structure of the chip manufacturing process provided in an embodiment of the present application;

[0062] Figure 26B For the Figure 26A A cross-sectional view obtained by cutting along the dotted line O5-O6 in FIG.

[0063] Figure 27 A schematic diagram of another part of the structure of the chip manufacturing process provided in an embodiment of the present application;

[0064] Figure 28A A schematic diagram of another chip structure used in an electronic device according to an embodiment of the present application;

[0065] Figure 28B For the Figure 28A A top view obtained from the C1 direction;

[0066] Figure 29A A schematic diagram of another chip structure used in an electronic device according to an embodiment of the present application;

[0067] Figure 29B For the Figure 29A A cross-sectional view obtained by cutting along the dotted line O7-O8 in FIG.

[0068] Figure 29C For the Figure 29A A top view obtained from the C2 direction;

[0069] Figure 30A A schematic diagram of another chip structure used in an electronic device according to an embodiment of the present application;

[0070] Figure 30B For the Figure 30A A side view obtained from the C3 direction;

[0071] Figure 30C For the Figure 30A A top view obtained from the C4 direction;

[0072] Figure 30D For the Figure 30A A cross-sectional view obtained by cutting along the dotted line P1-P2 in FIG.

[0073] Figure 31 A schematic diagram of a structure of a vertical channel in a chip provided in an embodiment of the present application;

[0074] Figure 32 A schematic diagram of another chip structure used in an electronic device according to an embodiment of the present application;

[0075] Figure 33 A schematic diagram of a partial structure of a chip structure used in an electronic device according to an embodiment of the present application;

[0076] Figure 34A A schematic diagram of another chip structure used in an electronic device according to an embodiment of the present application;

[0077] Figure 34B For the Figure 34A A side view obtained from the D2 direction;

[0078] Figure 34C For the Figure 34A A cross-sectional view obtained by cutting along the dotted line P3-P4 in FIG.

[0079] Figure 35 A schematic diagram of another part of the structure of the chip manufacturing process provided in an embodiment of the present application;

[0080] Figure 36 A schematic diagram of another chip structure used in an electronic device according to an embodiment of the present application;

[0081] Figure 37A A schematic diagram of another chip structure used in an electronic device according to an embodiment of the present application;

[0082] Figure 37B For the Figure 37A A cross-sectional view obtained by cutting along the dotted line P5-P6 in FIG.

[0083] Figure 37C For the Figure 37A A side view obtained from the C3 direction in FIG.

[0084] Reference numerals:

[0085] 01-electronic device; 101-bus; 102-SoC; 103-second RAM; 104-communication chip; 105-power management chip; 112-AP; 122-GPU; 132-first RAM; 20-chip; 21-array structure; 211-first isolation barrier; 221-first transistor column; 222-second transistor column; 200-substrate; 2101-vertical channel; 2102-gate dielectric layer; 2103-first signal line; T1-first vertical transistor; T2-second vertical transistor; 504-fourth groove; a1-first surface; a2-second surface; a3-third surface; a4-fourth surface; 30-storage array; 31-controller; 3 00-storage unit; 311-decoder; 312-driver; 313-timing controller; 314-cache; 315-input and output driver; 41-bottom electrode; 42-dielectric layer; 43-top electrode; 2104-second signal line; 51-first metal material layer; 52-semiconductor material layer; 213-third isolation barrier; 53-first mask structure; 503-third groove; 54-second mask structure; 55-second metal material; 212-second isolation barrier; 501-first groove; 60-metal contact electrode; 400-conductive integrated structure; 21011-first part; 21012-second part; 520-U-shaped semiconductor structure; 56-third mask structure. DETAILED DESCRIPTION

[0086] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments.

[0087] In the following, the terms "first," "second," etc., are used for descriptive convenience only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Thus, a feature specified as "first," "second," etc. may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise specified, "plurality" means two or more.

[0088] In this application, unless otherwise clearly specified and limited, the term "connection" should be understood in a broad sense. For example, "connection" can be a fixed mechanical connection, a detachable mechanical connection, or an integrated connection; or, "connection" can be a direct connection or an indirect connection through an intermediate medium.

[0089] In addition, unless otherwise clearly specified and limited, the term "electrical connection" should be understood in a broad sense. For example, "electrical connection" can be a direct electrical connection, for example, physical contact and electrical conduction between two components. It can also be understood as the electrical connection between different components in the circuit structure through physical lines such as printed circuit board (PCB) copper foil or wires that can transmit electrical signals to transmit electrical signals; or, "electrical connection" can be an indirect electrical connection between two components through an intermediate medium; or, "electrical connection" can be an electrical connection between two components in an air / non-contact manner, for example, two components are electrically connected by capacitive coupling to transmit electrical signals.

[0090] In the embodiments of the present application, the descriptions "vertical" and "parallel" respectively indicate approximately vertical and approximately parallel within a certain error range, and the error range may be a range in which the deviation angle relative to absolute vertical and absolute parallel is less than or equal to 5°, 8° or 10°, respectively, and no specific limitation is made here.

[0091] In the embodiments of the present application, directional terms such as "up", "down", "left" and "right" may be defined including but not limited to the orientation relative to the components schematically placed in the drawings. It should be understood that these directional terms may be relative concepts, which are used for relative description and clarification, and may change accordingly according to changes in the orientation of the components in the drawings.

[0092] In the drawings of the embodiments of the present application, components are represented by guide lines with arrows; parts are represented by guide lines only; openings, holes and the like are represented by guide lines with wavy lines at the ends.

[0093] An embodiment of the present application provides an electronic device. The electronic device can be applied to various communication systems or communication protocols, such as Bluetooth (BT) communication technology, global positioning system (GPS) communication technology, global system of mobile communication (GSM) communication technology, wireless fidelity (WiFi) communication technology, wideband code division multiple access wireless (WCDMA) communication technology, long term evolution (LTE), 5G communication technology, and other future communication technologies.

[0094] The electronic device in the embodiments of the present application may be a mobile phone, a tablet computer (pad), a laptop computer, a smart home, a smart wearable device (e.g., a smart watch, a smart bracelet, smart glasses, a smart helmet), a virtual reality (VR) electronic device, an augmented reality (AR) electronic device, etc. The electronic device may also be a handheld device with wireless communication capabilities, a computing device or other processing device connected to a wireless modem, an in-vehicle device, an electronic device in a 5G network, or an electronic device in a future-evolved public land mobile network (PLMN), etc., and the embodiments of the present application are not limited thereto.

[0095] For example, Figure 1 As shown, the electronic device 01 may include a circuit board (e.g., the PCB) 100, a bus 101 disposed on and electrically connected to the PCB 100, and a processor connected to the bus 101, such as a system on chip (SoC) 102 or a central processing unit (CPU), or a microcontroller unit (MCU). The SoC 102 may be used to process data, such as application data, image data, and cache temporary data.

[0096] In one embodiment, the SoC 102 may include an application processor (AP) 112 for processing application programs, a graphics processing unit (GPU) 122 for processing image data, and a first RAM 132 for caching high-speed data. The first RAM 132 may be a static random access memory (SRAM) or an embedded flash memory (EFlash). The SoC or CPU may be referred to as a logic chip. For example, the first RAM 132 may be integrated with the AP 112 and the GPU 122 into a single chip, or the first RAM 132 may be separately provided in a single memory chip.

[0097] In addition, continue as Figure 1As shown, the electronic device 01 may further include a memory chip connected to the SoC 102 via the bus 101, such as a second RAM 103. The second RAM 103 may be a dynamic random access memory (DRAM). The second RAM 103 may be used to store volatile data, such as temporary data generated by the SoC 102. The storage capacity of the second RAM 103 may generally be greater than that of the first RAM 132, but the reading speed is generally slower than that of the first RAM 132.

[0098] Furthermore, the electronic device 01 may further include a communication chip 104 and a power management chip 105 connected to the SoC 102 via the bus 101. The communication chip 104 may be used for protocol stack processing, or for amplifying and filtering analog RF signals, or for performing the aforementioned functions simultaneously. The power management chip 105 may be used to power other chips. In one embodiment, the SoC 102 and the second RAM 103 may be packaged in a single package structure, such as a 2.5D (dimension) or 3D package, to achieve faster inter-chip data transmission rates.

[0099] The above examples of the chips provided in the embodiments of the present application are logic chips, memory chips or communication chips, and do not constitute a limitation on the chip types. Other types of chips are not described here one by one. In addition, the chip 20 provided in the embodiments of the present application, such as Figure 2 As shown, it may include a substrate 200 and a plurality of array structures 21. Figure 2 The following description uses three array structures 21 as an example, and the present application does not limit the number of array structures 21. The plurality of array structures 21 may be disposed on the substrate 200, and the plurality of array structures 21 may be arranged along the first direction X at intervals.

[0100] The "substrate" mentioned above refers to a structure on which other film layers can be fabricated. The substrate can be patterned or unpatterned, and the film layers fabricated on the substrate can also be patterned or unpatterned. Furthermore, the substrate can include semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can include non-conductive materials such as glass, resin, or sapphire, which is not limited in this application.

[0101] To illustrate the structure of the chip 20, an XYZ coordinate system is established in the accompanying drawings, wherein the first direction X is the arrangement direction of the plurality of array structures 21, and the second direction Y is arranged to intersect (e.g., can be arranged perpendicular to) the first direction X. Both the first direction X and the second direction Y are parallel to the supporting surface of the substrate 200 (the surface for supporting the array structure 21), so the plane formed by the first direction X and the second direction Y can be parallel to the supporting surface of the substrate 200. In addition, the third direction Z is a direction perpendicular to the substrate 200.

[0102] On this basis, continue Figure 2 As shown, each array structure 21 may include a first isolation barrier 211, a first transistor column 221, and a second transistor column 222. The first isolation barrier 211 is located between the first transistor column 221 and the second transistor column 222. Each of the first transistor column 221 and the second transistor column 222 may include a plurality of vertical channels 2101, a gate dielectric layer 2102, and a first signal line 2103. The first isolation barrier 211 may also be referred to as a shallow trench isolation (STI) structure.

[0103] The plurality of vertical channels 2101 can be arranged on the sidewalls of the first isolation barrier 211 at intervals along the second direction Y. Furthermore, the vertical channels 2101 are disposed perpendicularly to the substrate 200. In this case, the vertical channels 2101 can extend in a third direction Z perpendicular to the supporting surface of the substrate 200. The vertical channels 2101 can comprise semiconductor material. The gate dielectric layer 2102 can also be referred to as a gate oxide (Gate-OX) dielectric layer.

[0104] For example, the length of the vertical channel 2101 along the third direction Z can be 30 to 500 nm, the width along the second direction Y can be 10 to 100 nm, and the thickness along the first direction X can be 5 to 50 nm. In this case, the vertical channel 2101 can be a nanowire (NW). In addition, the materials constituting the vertical channel 2101 can include, but are not limited to: single crystal silicon, single crystal germanium, polycrystalline silicon, polycrystalline germanium, oxide semiconductors such as indium gallium zinc oxide (IGZO), indium tungsten oxide (IWO), etc., organic semiconductors (such as pentacene, P3HT, etc.), two-dimensional material semiconductors such as molybdenum disulfide (MoS2), tungsten selenide (WSe2), etc., one-dimensional semiconductors such as carbon nanotubes (CNTs), etc.

[0105] In addition, the gate dielectric layer 2102 may wrap the vertical channel 2101 on three sides, and the gate dielectric layer 2102 continuously covers the plurality of vertical channels 2101 and a portion of the first isolation barrier 211 between the plurality of vertical channels 2101. For example, the gate dielectric layer 2102 may include a dielectric material, such as silicon oxide (e.g., SiO2), silicon nitride (SiN x ), silicon oxynitride, or a high-k dielectric material, such as hafnium dioxide (HfO2) or zirconium dioxide (ZrO2). Furthermore, a first signal line 2103 is located on the side of the gate dielectric layer 2102 facing away from the first isolation barrier 211. The first signal line 2103 can wrap around three sides of the vertical channel 2101 and continuously cover multiple vertical channels 2101, as well as portions of the first isolation barrier 211 between the multiple vertical channels 2101. The first signal line 2103 can be made of metal.

[0106] The following is an example of how the gate dielectric layer 2102 and the first signal line 2103 wrap the vertical channel 2101 on three sides. Figure 3 (along Figure 2 As shown in the top view obtained along the A direction in the figure, the cross-section of the vertical channel 2101 (parallel to the XY plane) can be rectangular. In this case, the gate dielectric layer 2102 and the first signal line 2103 wrapping the vertical channel 2101 on three sides means that along the second direction Y, the gate dielectric layer 2102 and the first signal line 2103 can wrap the first surface a1, the second surface a2 and the third surface a3 connected in sequence in the vertical channel 2101. The first surface a1 and the third surface a3 are arranged opposite to each other and are both arranged perpendicular to the first isolation barrier 211. The second surface a2 is arranged opposite to the fourth surface a4 in the vertical channel 2101 that is in contact with the first isolation barrier 211, and the second surface a2 can be parallel to the sidewall of the first isolation barrier 211.

[0107] The above description uses the example of a rectangular or semicircular cross-section of the vertical channel 2101. For further example, the cross-section of the vertical channel 2101 may also be triangular, trapezoidal, or a polygon with four or more sides, and this application will not elaborate on each of these. As long as the gate dielectric layer 2102 and the first signal line 2103 can wrap around multiple sequentially connected surfaces of the vertical channel 2101 along the second direction Y, the gate dielectric layer 2102 and the first signal line 2103 are protected by the vertical channel 2101 being wrapped around three sides.

[0108] Or, for example, Figure 4 (along Figure 2As shown in the top view taken along the direction A in FIG, the cross-section of the vertical channel 2101 may be semicircular (or semi-elliptical). In this case, the gate dielectric layer 2102 and the first signal line 2103 wrapping around the vertical channel 2101 on three sides means that along the second direction Y, the gate dielectric layer 2102 and the first signal line 2103 may wrap around the curved surface of the vertical channel 2101.

[0109] In addition, the gate dielectric layer 2102 and the first signal line 2103 continuously cover the plurality of vertical channels 2101, and the first isolation barrier 211 between the plurality of vertical channels 2101 is defined as follows: Figure 2 In the Y direction, the gate dielectric layer 2102 and the first signal line 2103 are continuous film layers, that is, the gate dielectric layer 2102 and the first signal line 2103 cover the portion of the vertical channel 2101, and the gate dielectric layer 2102 and the first signal line 2103 cover the portion of the first isolation barrier 211 between two adjacent vertical channels 2101 and are connected.

[0110] Based on this, continue as Figure 2 As described above, in the first transistor column 221, a vertical channel 2101, a portion of the gate dielectric layer 2102 surrounding the vertical channel 2101 on three sides, and the first signal line 2103 can constitute a first vertical transistor T1. Therefore, the first transistor column 221 can include a plurality of first vertical transistors T1 located on one side of the first isolation barrier 211 and arranged at intervals along the second direction Y. Similarly, Figure 2 In the second transistor column 222, a vertical channel 2101, a portion of the gate dielectric layer 2102 that wraps the vertical channel 2101 on three sides, and a first signal line 2103 can constitute a second vertical transistor T2. Therefore, the second transistor column 222 can include a plurality of second vertical transistors T2 located on the other side of the first isolation barrier 211 and arranged at intervals along the second direction Y. The first vertical transistor T1 and the second vertical transistor T2 are respectively arranged on both sides of the first isolation barrier 211. The first vertical transistor T1 and the second vertical transistor T2 can be field effect transistors (FETs). In addition, as can be seen from the above, the vertical channel 2101 is a nanowire, so the first vertical transistor T1 and the second vertical transistor T2 can also be called vertical nanowire transistors (VNWFETs).

[0111] In other embodiments of the present application, Figure 2As shown, a chip 20 is provided. As described above, the chip 20 may include a substrate 200 and a plurality of array structures 21 disposed on the substrate 200. Each array structure 21 includes a first isolation barrier 211, a first transistor column 221, and a second transistor column 222. The first transistor column 221 and the second transistor column 222 may each include a plurality of vertical channels 2101, a gate dielectric layer 2102, and a first signal line 2103. The configuration of the vertical channels 2101, the gate dielectric layer 2102, and the first signal line 2103 is the same as described above and will not be repeated here.

[0112] As can be seen from the above, the first signal line 2103 can wrap around the vertical channel 2101 on three sides, and the first signal line 2103 continuously covers multiple vertical channels 2101, as well as portions of the first isolation barrier 211 between the multiple vertical channels 2101. In the first transistor column 221, a vertical channel 2101, a portion of the gate dielectric layer 2102 wrapping around the vertical channel 2101 on three sides, and the first signal line 2103 can form a first vertical transistor T1. In the second transistor column 222, a vertical channel 2101, a portion of the gate dielectric layer 2102 wrapping around the vertical channel 2101 on three sides, and the first signal line 2103 can form a second vertical transistor T2.

[0113] Based on this, the first signal line 2103 can serve as the gates of multiple transistors in the first transistor column 221 or the second transistor column 222. For example, the first signal line 2103 in the first transistor column 221 can serve as the gates of multiple first vertical transistors T1 in the first transistor column 221. Similarly, the first signal line 2103 in the second transistor column 222 can serve as the gates of multiple second vertical transistors T2 in the second transistor column 222. Specifically, the portion of the first signal line 2103 that surrounds a vertical channel 2101 on three sides serves as the gate of a first vertical transistor T1 or a second vertical transistor T2 having the vertical channel 2101.

[0114] In this case, the vertical channels 2101 of the first vertical transistor T1 and the second vertical transistor T2 are both surrounded on three sides by the first signal line 2103 serving as the gate. Therefore, in the first vertical transistor T1 and the second vertical transistor T2, the first signal line 2103 serving as the gate can be called a tri-gate structure, and the vertical channel 2101 can also be called a gate all around (GAA).

[0115] In some embodiments of the present application, the first transistor column 221 and the second transistor column 222 may be symmetrically arranged with respect to the first isolation barrier 211. In this case, a first vertical transistor T1 in the first transistor column 221 and a second vertical transistor T2 in the second transistor column 222 may be symmetrically arranged with respect to the first isolation barrier 211. This allows the structure of the chip 20 to have a certain regularity. When fabricating the chip 20 using a patterning process, fabricating a patterned structure having this regularity can simplify the manufacturing process.

[0116] In the embodiments of the present application, the patterning process may include a photolithography process, or a photolithography process and an etching step, and may also include other processes such as printing and inkjet printing for forming a predetermined pattern. The photolithography process refers to a process that uses photoresist, a mask, an exposure machine, and the like to form a pattern, including film formation, exposure, and development processes. The corresponding patterning process can be selected based on the structure formed in the present application.

[0117] In addition, if Figure 5 As shown, part of the first signal line 2103 (such as Figure 2 As shown) can serve as the gate (gate, G) of the first vertical transistor T1, and part of the first signal line 2103 (as shown) in the second vertical transistor T1 Figure 2 As shown in FIG. 1 , the gate electrode G of the second vertical transistor T2 may be used as the gate electrode G of the second vertical transistor T2. In addition, any one of the first vertical transistor T1 and the second vertical transistor T2 may further include: Figure 6 (along Figure 5 The first electrode, such as the source (S), and the second electrode, such as the drain (D), are shown in the cross-sectional view (cut along the dotted line O1-O2 in FIG). For convenience of explanation, the following examples are taken as an example in which the first electrode of the transistor is the source S and the second electrode is the drain D. In other embodiments of the present application, the first electrode can be the drain D and the second electrode can be the source S.

[0118] Based on this, continue as Figure 6As shown, the first electrode (e.g., source S) can be arranged on the side of the vertical channel 2101 facing the substrate 200, and the second electrode (e.g., drain D) can be on the side of the vertical channel 2101 facing away from the substrate 200. In this case, a voltage can be applied to the first electrode (e.g., source S) and the second electrode (e.g., drain D) so that a conduction current (or on-state current) flows through the vertical channel 2101. At this time, the first vertical transistor T1 and the second vertical transistor T2 can be in a conduction state (or, an on-state, referred to as an on-state). Alternatively, when no conduction current flows through the vertical channel 2101, the first vertical transistor T1 and the second vertical transistor T2 can be in a cut-off state.

[0119] For example, in the first vertical transistor T1 or the second vertical transistor T2, the first electrode (e.g., source S), the second electrode (e.g., drain D), and the vertical channel 2101 can be connected to form an integrated structure. During the manufacturing process, a columnar intrinsic semiconductor structure can be formed on the sidewalls of the first isolation barrier 211, and ion doping is performed on both ends of the semiconductor structure facing toward and away from the substrate 200 to form the first electrode (e.g., source S) and the second electrode (e.g., drain D). In addition, the undoped portion between the first electrode (e.g., source S) and the second electrode (e.g., drain D) can form the vertical channel 2101.

[0120] In summary, the embodiments of the present application provide Figure 2 In the illustrated chip 20, on one hand, the first isolation barrier 211 is located between the first transistor column 221 and the second transistor column 222, and in either of the first transistor column 221 and the second transistor column 222, the first signal line 2103 is disposed on the side of the gate dielectric layer 2102 or the vertical channel 2101 away from the first isolation barrier 211. Therefore, the vertical channel 2101 and the portion of the first signal line 2103 surrounding the vertical channel 2101 can constitute a vertical transistor (e.g., Figure 5 The portion of the first signal line 2103 that wraps around the vertical channel 2101 can serve as the gate of the vertical transistor. Because the side of the vertical channel 2101 of the vertical transistor facing the first isolation barrier 211 is located on the sidewall of the first isolation barrier 211, no gate is provided on the side of the vertical channel 2101 facing the first isolation barrier 211. This allows the vertical transistor to be provided with a gate only on one side along the first direction X, making the chip 20 scalable in the first direction X.

[0121] On the other hand, continue as Figure 2As shown, the vertical channel 2101 of the vertical transistor can be located on the sidewall of the first isolation barrier 211. The first isolation barrier 211 can support the vertical channel 2101, thereby reducing the processing difficulty of reducing the thickness of the vertical channel 2101 along the first direction X, thereby improving the scalability of the vertical transistor. For example, the size of the vertical transistor can be miniaturized to 45nm or below 40nm, so that the size of the chip 20 having the vertical transistor can be effectively reduced to 6F. 2 ~4F 2 Among them, the minimum processing size of semiconductor is F.

[0122] On the other hand, continue as Figure 2 As shown, the first signal line 2103 wraps around the vertical channel on three sides to provide three-dimensional coverage of the first signal line 2103 on three sides, so that the electric field lines of the vertical transistor are more concentrated, which is beneficial to improving the gate control capability and on-state current of the vertical transistor, thereby achieving the purpose of improving the performance of the vertical transistor, thereby being able to improve the performance of the vertical transistor and the chip 20 while meeting the miniaturization requirements of components of electronic equipment.

[0123] For example, the on-state current of the first vertical transistor T1 or the second vertical transistor T2 may be 100nA to 1000μA. The off-state leakage current of the first vertical transistor T1 or the second vertical transistor T2 may be 0.1fA to 100pA. The gate turn-on voltage of the first vertical transistor T1 or the second vertical transistor T2 may be 1V to 5V. The gate threshold voltage of the first vertical transistor T1 or the second vertical transistor T2 may be -0.5V to 0.7V.

[0124] Furthermore, the gate dielectric layer 2102 and the first signal line 2103 can both continuously cover the plurality of vertical channels 2101 and portions of the first isolation barrier 211 between the plurality of vertical channels 2101. Therefore, along the direction in which the plurality of vertical channels 2101 are arranged (i.e., the second direction Y), the gate dielectric layer 2102 and the first signal line 2103 are both continuous structures. This allows, during the manufacturing process, the plurality of vertical channels 2101, arranged in intervals, to be formed on both sides of the first isolation barrier. Subsequently, the gate dielectric layer 2102 and the first signal line 2103 can be sequentially formed on the side of any row of the plurality of vertical channels 2101 facing away from the first isolation barrier 211, thereby simplifying the manufacturing process.

[0125] In an embodiment of the present application, the first vertical transistor T1 or the second vertical transistor T2 in the chip 20 can be prepared using a front-end of line (FEOL) process or a back-end of line (BEOL) process, which is not limited in this application. For example, when the first vertical transistor T1 or the second vertical transistor T2 is prepared using a front-end process, the substrate 200 of the chip 20 can be a silicon substrate or a sapphire substrate of a wafer. In addition, when the first vertical transistor T1 or the second vertical transistor T2 is prepared using a back-end process, the substrate 200 can be made on a wafer.

[0126] From the above, we can see that Figure 2 The chip 20 in the embodiment may be the aforementioned logic chip. In this case, the first vertical transistor T1 or the second vertical transistor T2 in the chip 20 may be manufactured using the aforementioned front-end process. Alternatively, when Figure 2 When the chip 20 is the above-mentioned memory chip, the first vertical transistor T1 or the second vertical transistor T2 in the chip 20 can be manufactured using either a front-end process or a back-end process.

[0127] Based on this, when the first vertical transistor T1 or the second vertical transistor T2 in the chip 20 is manufactured using the back-end process, the semiconductor material used in the vertical channel 2101 of the vertical transistor is polycrystalline silicon (poly-silicon, Poly-Si), and the mobility is reduced compared to the vertical transistor manufactured using single crystal silicon in the front-end process. However, as can be seen from the above, Figure 2 The vertical transistors in the chip 20 shown have a relatively high gate control capability and on-state current, so even if the vertical transistors are manufactured using a back-end process, a chip 20 with relatively high performance can still be obtained.

[0128] The following is an example of the structure of the memory chip, taking the chip 20 as an example. In this case, the memory chip in the electronic device 01 provided in the embodiment of the present application can be a memory chip, for example Figure 1 The first RAM 132 or the second RAM 103 in the present application does not limit the application scenario of the above-mentioned memory chip. In some embodiments of the present application, such as Figure 7 As shown, the chip 20 may further include a capacitor array 22, which may be disposed on a side of the array structure 21 facing away from the substrate 200. The capacitor array 22 is electrically connected to at least one of the first transistor column 221 or the second transistor column 222 to form a storage array 30. The capacitor array 22 may include a plurality of storage capacitors C arranged in an array.

[0129] Based on this, Figure 8As shown, in the case where the chip 20 is a memory chip, the chip 20 may further include a controller 31 electrically connected to the plurality of memory arrays 30. The controller 31 may be used to control read and write operations of the memory arrays 30 to implement access to the memory arrays 30.

[0130] For example, in the chip 20 described above, the memory array 30 and the controller 31 can be two independent chips. The memory array 30 and the controller 31 can be separately disposed on a carrier board (e.g., a packaged transistor chain or an adapter board), and the memory array 30 and the controller 31 are electrically connected to the carrier board. In this way, the memory array 30 and the controller 31 can achieve signal transmission through metal traces within the carrier board. Based on this, the chip 20 having the memory array 30 described above can be called a stand-alone memory chip.

[0131] Alternatively, as another example, in the above-mentioned chip 20, the storage array 30 and the controller 31 can be two independent chips, and the storage array 30 and the controller 31 are stacked on the above-mentioned carrier board. The storage array 30 and the controller 31 can be electrically connected through silicon vias (TSV) or redistribution layers (RDL), so that the storage array 30 and the controller 31 can transmit signals with the carrier board. Similarly, the chip 20 having the above-mentioned storage array 30 is the above-mentioned independent storage chip. Alternatively, as another example, in the above-mentioned chip 20, the storage array 30 and the controller 31 can be integrated into the same chip, and the integrated chip can be electrically connected to the above-mentioned carrier board. Based on this, the chip 20 having the above-mentioned storage array 30 can be called an embedded storage chip.

[0132] On this basis, if Figure 9 As shown, the memory array 30 may include a plurality of memory cells 300, wherein each memory cell 300 may be used to store 1 bit or multiple bits of data. Figure 7 In the case where the capacitor array 22 and the array structure 21 (including the first transistor column 221 and the second transistor column 222) are formed, Figure 9 The storage unit 300 shown may include Figure 10 The memory cell 300 may include a first vertical transistor T1 and a storage capacitor C electrically connected to the first vertical transistor T1. Figure 10 A second vertical transistor T2 and a storage capacitor C electrically connected to the second vertical transistor T2.

[0133] For example, Figure 7 or Figure 10The storage capacitor C shown is a columnar capacitor, which can be as follows Figure 7 Alternatively, the columnar capacitor may be a cylinder. This application does not limit the shape of the columnar capacitor. Figure 10 As shown, the columnar storage capacitor C may include a bottom electrode (BE) 41, a top electrode (TE) 43, and a dielectric layer 42. At least a portion of the top electrode 43 is disposed within the bottom electrode 41. At least a portion of the dielectric layer 42 is disposed within the bottom electrode 41, and the dielectric layer 42 is located between the bottom electrode 41 and the top electrode 43. In some embodiments of the present application, the material of the bottom electrode 41 or the top electrode 43 may include at least one of tungsten (W), titanium nitride (TiN), and molybdenum (Mo).

[0134] In some embodiments of the present application, the dielectric layer 42 may be a ferroelectric thin film layer, or a ferroelectric insulator layer. In this case, the storage capacitor C may be a ferroelectric capacitor (FeCAP), and the chip 20 having the ferroelectric capacitor may be a ferroelectric random access memory (FeRAM or FRAM).

[0135] Alternatively, in other embodiments of the present application, the dielectric layer 42 may be a resistive switching layer. In this case, the storage capacitor C may be a resistive switching capacitor, and the chip 20 having the resistive switching capacitor may be a resistive random access memory (RRAM). Alternatively, in other embodiments of the present application, the dielectric layer 42 may be a phase change material layer. In this case, the chip 20 may be a phase change memory (PCM).

[0136] In the memory cell 300, the bottom electrode of the storage capacitor C (i.e., bottom electrode 41) can be electrically connected to the second electrode of the first vertical transistor T1 or the second vertical transistor T2, such as the drain D. The top electrodes 43 of different memory cells 300 can be electrically connected through a signal line SL. Figure 10 The storage unit 300 is shown in FIG. Figure 11The 1T1C (one transistor and one capacitor) structure shown is for illustrative purposes only, i.e., one transistor T (e.g., the first vertical transistor T1 or the second vertical transistor T2) and one storage capacitor C. The present embodiment of the present application does not limit the number of transistors and storage capacitors C in the memory cell 300. For example, the memory cell 300 may also have a 2T1C (two transistors and one capacitor) or a 2T0C (two transistors and zero capacitor) structure.

[0137] Continue as Figure 11 As shown above, it can be seen that the control terminal (eg, gate) of the transistor T can be connected to Figure 2 The first signal line 2103 shown is electrically connected to the first signal line 2103, which can serve as a word line (WL). The first electrode (e.g., source S) of the transistor T can be electrically connected to the second signal line, e.g., bit line (BL), and the top electrode 43 (e.g., Figure 10 ) is electrically connected to the signal line SL. One or more of the WL, BL, and SL are used to select a memory cell 300 to be read or written in the memory array 30 by receiving a control level output by the control circuit, thereby changing the polarization direction of the storage capacitor C in the memory cell 300 to implement data read and write operations.

[0138] In some other embodiments of the present application, the storage capacitor C in the storage unit 300 can be replaced with a magnetic tunnel junction (MTJ), and the chip 20 having the MTJ can be a magnetoresistive random access memory (MRAM). Alternatively, in some other embodiments of the present application, the storage capacitor C in the storage unit 300 can be replaced with.

[0139] also, Figure 8 The controller 31 shown may include Figure 9One or more circuit structures are shown in the decoder 311, driver 312, timing controller 313, buffer 314, or input / output driver 315. The decoder 311 is used to decode the address of the storage unit 300. The decoder 311 is used to decode the received address to determine the storage unit 300 to be accessed. The driver 312 is used to control the level of the signal line based on the decoding result generated by the decoder 311, thereby enabling access to the specified storage unit 300. The buffer 314 is used to cache the read data, for example, using a first-in first-out (FIFO) cache. The timing controller 313 is used to control the timing of the buffer 314 and the timing of the driver 312 driving the signal lines in the storage unit 300. The input / output driver 315 is used to drive transmission signals, such as driving received data signals and driving data signals to be transmitted, so that the data signals can be transmitted over long distances. The memory array 30 , decoder 311 , driver 312 , timing controller 313 , buffer 314 and input / output driver 315 may be integrated into one chip or integrated into multiple chips.

[0140] In the case where the chip 20 is a memory chip, Figure 10 The first electrode (eg, source S) of the first vertical transistor T1 or the second vertical transistor T2 may be connected to the Figure 11 Based on this, in some embodiments of the present application, when the chip 20 is prepared using a front-end process, the first vertical transistor T1 or the second vertical transistor T2 can be formed on the substrate 200 first, and then the second signal line, such as BL, is formed.

[0141] Alternatively, in other embodiments of the present application, when the chip 20 is prepared using a back-end process, as shown in FIG. Figure 12 As shown, the second signal line 2104, such as BL, can be prepared on the substrate 200 first, and then the first vertical transistor T1 or the second vertical transistor T2 can be manufactured. Figure 12 The manufacturing method of the chip 20 shown in FIG. 2 is described as an example. The above manufacturing method may include: Figure 13 S101 to S104 shown.

[0142] S101 , forming a plurality of first isolation barriers arranged at intervals along a first direction on a substrate.

[0143] For example, Figure 14 As shown, a first metal material layer 51 and a semiconductor material layer 52 are sequentially formed on the substrate 200. Next, an etching process can be used on the semiconductor material layer 52 to remove Figure 14The portion of the first metal material layer 51 and the portion of the semiconductor material layer 52 shown are used to form Figure 15 The bottom of the second groove 502 can be exposed from the upper surface of the substrate 200. At this time, the portion of the metal material layer between two adjacent second grooves 502 can be used as the second signal line 2104 (for example, Figure 11 BL in ).

[0144] Then, a dielectric material may be filled into the second groove 502 by a deposition process to form a Figure 16A The third isolation barrier 213 shown. At this time, the third isolation barrier 213 can be set between two adjacent second signal lines 2104, so as to isolate the adjacent second signal lines 2104. In addition, the third isolation barrier 213 and Figure 12 The materials of the first isolation barrier 211 can be different. For example, the material of the first isolation barrier 211 can be silicon nitride, and the material of the third isolation barrier 213 can be silicon oxide. Alternatively, the material of the first isolation barrier 211 can be silicon oxide, and the material of the third isolation barrier 213 can be silicon nitride. In this way, the structure of the first isolation barrier 211 will not be affected during the subsequent wet etching of the third isolation barrier 213. Based on this, Figure 16B (along Figure 16A As shown in the top view obtained from the B1 direction in FIG, the semiconductor material layer 52 is separated into a plurality of strip structures by a plurality of third isolation barriers 213 extending along the first direction X.

[0145] Next, if Figure 17A As shown, a first mask structure 53 is formed on the semiconductor material layer 52. Figure 17B (along Figure 17A The hollow portion of the first mask structure 53 can expose a portion of the semiconductor material layer 52 and a portion of the third isolation barrier 213. Then, the film layer below the first mask structure 53 is subjected to a photolithography process using the first mask structure 53 as a mask to remove the semiconductor material layer 52 and the third isolation barrier 213 exposed by the first mask structure 53, thereby forming a film as shown in FIG. Figure 18A As shown, a plurality of third grooves 503 are arranged at intervals along the first direction X. Figure 18B (along Figure 18A As shown in the top view taken along the direction B3 in FIG, the bottom of the third groove 503 may expose a portion of the second signal line 2104 and the third isolation barrier 213 disposed between adjacent second signal lines 2104.

[0146] Next, in Figure 18A The third groove 503 shown can be filled with dielectric material by a deposition process to form a Figure 19A The first isolation retaining wall 211 is shown. Figure 19B (along Figure 19A As shown in the top view obtained in the direction B4 in the figure, the first isolation retaining wall 211 is located in the hollow portion of the first mask structure 53, so that the plurality of first isolation retaining walls 211 are arranged at intervals along the first direction X, and the first isolation retaining walls 211 extend along the second direction Y.

[0147] S102 , forming transistor columns on both sidewalls of the first isolation barrier.

[0148] For example, we can first remove Figure 19A The first mask structure 53 is shown so that Figure 20A As shown, a portion of the first isolation barrier 211 is located within the semiconductor material layer 52 and the third isolation barrier 213, and another portion of the first isolation barrier 211 extends out of the semiconductor material layer 52 and the third isolation barrier 213. Figure 20B (along Figure 20A As shown in the top view obtained from the direction B5 in FIG, a portion of the semiconductor material layer 52 and a portion of the third isolation barrier rib 213 may be exposed between two adjacent first isolation barrier ribs 211.

[0149] Next, if Figure 21A As described above, a second mask structure 54 is formed on the sidewall of the first isolation barrier 211. Figure 19A The first mask structure 53 shown is a mask, which is formed by photolithography and deposition processes. Figure 21A The first isolation walls 211 shown have high precision in size, position, and spacing between the plurality of first isolation walls 211. Based on this, the second mask structure 54 formed on the sidewalls of the first isolation walls 211 can be self-aligned using the first isolation walls 211, thereby forming a second mask structure 54 with high precision in size, position, and spacing.

[0150] In addition, if Figure 21B (along Figure 21A As shown in the top view taken from the direction B6 in FIG, the hollow portion of the second mask structure 54 can expose a portion of the semiconductor material layer 52 and a portion of the third isolation barrier 213. Then, the film layer below the second mask structure 54 is subjected to a photolithography process using the second mask structure 54 as a mask to remove the semiconductor material layer 52 and the third isolation barrier 213 exposed by the second mask structure 54. The remaining portion of the semiconductor material layer 52 can be formed as shown in FIG. Figure 22A The vertical channel 2101 shown is perpendicular to the substrate 200. Based on this, as Figure 22B (along Figure 22AAs shown in the top view obtained from the direction B7 in FIG, a portion of the second signal line 2104 and the third isolation barrier rib 213 may be exposed between two adjacent second mask structures 54.

[0151] As can be seen from the above, the second mask structure 54 formed on the sidewall of the first isolation barrier 211 can be self-aligned with the first isolation barrier 211, thereby obtaining a second mask structure 54 with high precision in size, position, and spacing. In this case, by using the second mask structure 54 with high precision in size, position, and spacing as a mask, the size, position, and spacing of the formed vertical channels 2101 can also be highly precise.

[0152] Next, a chemical mechanical polishing (CMP) process may be used to remove the second mask structure 54 on the top of the vertical trench 2101 and the portion of the first isolation barrier 211 protruding from the vertical trench 2101, so that Figure 23 As shown, the upper surface of the first isolation barrier 211 can be flush with the upper surface of the vertical channel 2101. Next, as can be seen from the above, the first isolation barrier 211 and the third isolation barrier 213 are made of different materials. Therefore, a wet etching process can be used to remove the third isolation barrier 213 between two adjacent vertical channels 2101, so that Figure 24A As shown, there is a gap between two adjacent vertical channels 2101. In addition, in the wet etching process, the third isolation barrier 213 between two adjacent second signal lines 2104 can be retained by controlling relevant parameters of the wet etching process, such as etching time.

[0153] Based on this, Figure 24B (along Figure 24A As shown in the top view taken from the direction B8 in FIG, a plurality of vertical channels 2101 spaced apart and arranged in a row along the second direction Y can be formed on the two opposite side walls of the first isolation barrier 211. Figure 24A The vertical projection of the middle signal line 2104 on the substrate 200 may overlap with the vertical projection of a second signal line 2104 on the substrate 200 .

[0154] On this basis, if Figure 25A As described above, a gate dielectric layer 2102 is formed on one side of the plurality of vertical channels 2101 away from the isolation barrier 211. Figure 25B (along Figure 25A As shown in the top view obtained in the direction B9 in FIG, the gate dielectric layer 2102 wraps the vertical channel 2101 on three sides, and the gate dielectric layer 2102 continuously covers multiple vertical channels 2101 and part of the first isolation barrier 211 between the multiple vertical channels 2101.

[0155] Next, if Figure 26A As shown, a second metal material layer 55 is formed on the side of the gate dielectric layer 2102 away from the first isolation barrier 211. In some embodiments of the present application, as shown in FIG. Figure 26B (along Figure 26A As shown in the cross-sectional view obtained by cutting along the dotted line O5-O6 in FIG, the second metal material layer 55 can cover the gate dielectric layer 2102 with the same thickness at all locations.

[0156] Based on this, it can be seen from the above that Figure 26A The gate dielectric layer 2102 shown wraps around the vertical channels 2101 on three sides, and the gate dielectric layer 2102 continuously covers the multiple vertical channels 2101, as well as portions of the first isolation walls 211 between the multiple vertical channels 2101. Therefore, the second metal material layer 55 formed on the gate dielectric layer 2102 can be conformal to the gate dielectric layer 2102, that is, the second metal material layer 55 can have the same or approximately the same shape as the gate dielectric layer 2102. In this way, the second metal material layer 55 can also wrap around the vertical channels 2101 on three sides, and the gate dielectric layer 2102 continuously covers the multiple vertical channels 2101, as well as portions of the first isolation walls 211 between the multiple vertical channels 2101.

[0157] Next, if Figure 27 As shown, the bottom of the second metal material layer 55 between two adjacent first isolation walls 211 is cut off (bottom open) to form a fourth groove 504. Figure 3 (along Figure 27 As shown in the top view taken along the A direction in FIG, the bottom of the fourth groove 504 may expose a portion of the gate dielectric layer 2102. In this case, Figure 27 The remaining portion of the second metal material layer 55 can be formed Figure 3 Since the second metal material layer 55 is conformal to the gate dielectric layer 2102, the first signal line 2103 can also be conformal to the gate dielectric layer 2102, so that the first signal line 2103 wraps around the vertical channel 2101 on three sides and continuously covers multiple vertical channels 2101 and portions of the first isolation barrier ribs 211 between the multiple vertical channels 2101.

[0158] In this case, if Figure 28AAs shown, a vertical channel 2101 located on one side of the first isolation barrier 211, a portion of the gate dielectric layer 2102 surrounding the vertical channel 2101 on three sides, and a first signal line 2103 can constitute a first vertical transistor T1. The plurality of first vertical transistors T1 are arranged at intervals along the second direction Y to form a first transistor column 221. Furthermore, a vertical channel 2101 located on the other side of the first isolation barrier 211, a portion of the gate dielectric layer 2102 surrounding the vertical channel 2101 on three sides, and a first signal line 2103 can constitute a second transistor column 222. The plurality of second vertical transistors T2 are arranged at intervals along the second direction Y to form a second transistor column 222. The first transistor column 221 and the second transistor column 222 are respectively disposed on either side of the first isolation barrier 211.

[0159] As can be seen from the above, the size, position and spacing of the vertical channel 2101 can also have a high precision. Therefore, the size of the above-mentioned transistor column having the vertical channel 2101, such as the first transistor column 221 and the second transistor column 222, can also have a high precision, which can be beneficial to improving the miniaturization of the transistor column and the chip 20 having the transistor column.

[0160] S103: forming a second retaining wall between the array structures.

[0161] For example, continue as Figure 28A As shown, a second isolation barrier 212 is formed on a substrate 200 having multiple array structures 21. A portion of the isolation barrier 212 covers the surface of the array structure 21 facing away from the substrate 200, and a portion is located between two adjacent array structures 21. Two adjacent first signal lines 2103 belonging to different array structures 21 are isolated and arranged on both sides of the second isolation barrier 212. Two adjacent vertical channels 2101 in different array structures 21 are isolated on both sides of the second isolation barrier 212. The second isolation barrier 212 can isolate two adjacent first signal lines 2103 in different array structures 21. In addition, the second isolation barrier 212 can also isolate two adjacent vertical channels 2101 in different array structures 21.

[0162] As can be seen from the above, the first signal line 2103 continuously covers a portion of the first isolation barrier 211 between the plurality of vertical channels 2101. Figure 28B (along Figure 28A As shown in the top view taken from the direction C1 in FIG, the first signal line 2103 covers part of the first isolation barrier 211 and has a first groove 501 on the side away from the first isolation barrier 211. A part of the second isolation barrier 212 located between two adjacent array structures 21 is located in the first groove 501. In this case, Figure 28BIn the embodiment, the top view structure of the second isolation barrier 212 located between two adjacent array structures 21 may resemble a “N” shape.

[0163] S104 , forming metal contact electrodes on the array structure.

[0164] For example, Figure 29A As described above, first, the first signal line 2103 is etched to reduce its height along the third direction Z. Then, a plurality of metal contact electrodes 60 are formed on the plurality of array structures 21. Each metal contact electrode 60 can be electrically connected to a vertical transistor, such as the first vertical transistor T1 or the second vertical transistor T2. Furthermore, a second isolation barrier 212 is provided between the metal contact electrode 60 and the first signal line 2103.

[0165] For example, Figure 29B (along Figure 29A As shown in the cross-sectional view obtained by cutting along the dotted line O7-O8 in FIG, the second electrode of the first vertical transistor T1 or the second vertical transistor T2, for example, the drain D (eg Figure 10 As shown), it is electrically connected to the metal contact electrode 60. In this case, Figure 29C (along Figure 29A As shown in the top view taken along the C2 direction in FIG, a plurality of metal contact electrodes 60 spaced apart along the second direction Y may be arranged on the sidewall of the first isolation barrier 211.

[0166] From the above, we can see that Figure 26B As shown, the second metal material layer 55 can cover the gate dielectric layer 2102 with the same thickness everywhere. Next, as shown in FIG. Figure 27 As shown, the bottom of the second metal material layer 55 between two adjacent first isolation walls 211 is cut off to form Figure 29B Therefore, two adjacent first signal lines 2103 belonging to different array structures 21 are separated by the second isolation barrier 212 located between the two first signal lines 2103 .

[0167] In some other embodiments of the present application, two adjacent first signal lines 2103 (eg, Figure 29B as shown) are connected as Figure 30A The conductive integral structure 400 shown is filled between two adjacent rows of vertical channels 2101. In this case, Figure 30B (along Figure 30A As shown in the side view obtained from the C3 direction in FIG, a plurality of vertical channels 2101 located in the same row along the second direction Y are covered by the conductive integrated structure 400. Figure 30AAs shown, the second isolation barrier 212 of the chip 20 can be disposed between two adjacent array structures 21, and the second isolation barrier 212 can be located on the side of the conductive integral structure 400 facing away from the substrate 200. The second isolation barrier 212 is used to isolate the portions of the vertical channels 2101 in the two adjacent array structures 21 that are not covered by the conductive integral structure 400.

[0168] In this case, if Figure 30C (along Figure 30A As shown in the top view taken along the direction C4 in FIG, the conductive integral structure 400 and the two oppositely disposed vertical channels 2101 surrounded on three sides by the conductive integral structure 400 can form a vertical transistor T with two channels. Compared to a vertical transistor with a single channel, the on-state current of the vertical transistor T with two channels can be doubled.

[0169] In order to manufacture the conductive integrated structure 400, the following can be done: Figure 30D (along Figure 30A As shown in the cross-sectional view obtained by cutting along the dotted line P1-P2 in the figure, after the gate dielectric layer 2102 is formed, the above-mentioned second metal material layer (the material for forming the conductive integrated structural member 400) is formed on the gate dielectric layer 2102. The second metal material layer does not need to cover the gate dielectric layer 2102 with the same thickness, but is filled between two adjacent first isolation walls 211, and covers the surface of the gate dielectric layer 2102 facing away from the first isolation wall 211 and the substrate 200.

[0170] Next, the second metal material layer is etched back to form the conductive integral structure 400, so that the height of the conductive integral structure 400 along the third direction Z is less than the height of the second electrode of the vertical transistor, such as the drain D. In this way, after the metal contact electrode 60 is formed, the metal contact electrode 60 contacts the second electrode of the vertical transistor, such as the drain D, and the metal contact electrode 60 and the conductive integral structure 400 are separated by the second isolation barrier 212.

[0171] From the above, we can see that Figure 22A In the embodiment, the second mask structure 54 is used as a mask pair to remove the semiconductor material layer 52 and the third isolation barrier 213 exposed by the second mask structure 54. The remaining portion of the semiconductor material layer 52 blocked by the second mask structure 54 can form a vertical channel 2101. Therefore, along the first direction X, the thickness of the second mask structure 54 is the same as the thickness of the vertical channel 2101. The vertical channel 2101 is a cubic structure perpendicular to the substrate 200. The following examples illustrate vertical channels 2101 of other shapes and methods for fabricating the vertical channels 2101.

[0172] In other embodiments of the present application, Figure 31 As shown, the vertical channel 2101 may include a first portion 21011 and a second portion 21012. The first portion 21011 is arranged in a direction perpendicular to the substrate 200, and the second portion 21012 is connected to the end of the first portion 21011 facing the substrate 200. The second portion 21012 is arranged along the first direction X and contacts the second signal line 2104, so that the second portion 21012 can be electrically connected to the second signal line 2104. In this way, since the second portion 21012 is electrically connected to the second signal line 2104 and the second portion 21012 is arranged along the first direction X, the second portion 21012 can increase the contact area between the entire vertical channel 2101 and the second signal line 2104, thereby reducing the contact resistance.

[0173] In this case, continue as Figure 31 As shown, the first portion 21011 and the second portion 21012 in the vertical channel 2101 may form an L-shaped structure. Figure 32 As shown, the gate dielectric layer 2102 that wraps the L-shaped vertical channel 2101 on three sides may expose an end of the second portion 21012 away from the first isolation barrier 211. Figure 33 As shown, the first signal line 2103 covers the surface of the first portion 21011 away from the first isolation barrier 211, and the first signal line 2103 also covers the surface of the first portion 21011 and the second portion 21012 that is perpendicular to the first isolation barrier 211 and the substrate 200. Figure 34A As shown, the portion of the first signal line 2103 covering the second portion 21012 viewed from the direction D1 is shaped like a horseshoe, thereby increasing the coverage area of the first signal line 2103 and reducing the resistance of the first signal line 2103 .

[0174] On this basis, if Figure 34B (along Figure 34A As shown in the top view obtained from the direction D2 in FIG, there is a gap between the two first signal lines 2103 between the adjacent first isolation walls 211, so that Figure 34A The plurality of array structures 21 can be spaced apart along the first direction X. Furthermore, the surface of the first signal line 2103 away from the first isolation barrier 211 is a plane. Figure 34C (along Figure 34A As shown in the cross-sectional view obtained by cutting along the dotted line P3-P4 in the figure, the surface of the first signal line 2103 on one side facing away from the first isolation barrier 211 is flush with the surface of the second portion 21012 of the vertical channel 2101 on one side facing away from the first isolation barrier 211, and the surface of the gate dielectric layer 2102 on one side facing away from the first isolation barrier 211.

[0175] Based on this, when forming the first mask structure 53 (such as Figure 19A After that, Figure 34C The steps of forming a plurality of vertical channels 2101 spaced apart along the second direction Y on the sidewalls of the first isolation barrier 211 and forming a gate dielectric layer 2102 and a first signal line 2103 may include: first, removing the first mask structure 53 (eg, Figure 19A ), and as Figure 21A As shown, a second mask structure 54 is formed on the sidewalls of the first isolation barrier 211 , and a portion of the semiconductor material layer 52 and the third isolation barrier 213 exposed by the second mask structure 54 are removed to form a plurality of U-shaped semiconductor structures.

[0176] The removal of a portion of the semiconductor material layer 52 exposed by the second mask structure 54 means that the semiconductor material layer 52 exposed by the second mask structure 54 does not need to be completely etched, and a portion of the semiconductor material layer 52 at the bottom is retained, so that the unetched semiconductor material layer 52 is Figure 35 The U-shaped semiconductor structure 520 is shown. A portion of the U-shaped semiconductor structure 520 is disposed along the first direction X and is electrically connected to the second signal line 2104, thereby increasing the contact area between the entire vertical channel 2101 and the second signal line 2104 and reducing the contact resistance.

[0177] Next, continue as Figure 35 As shown, a gate dielectric layer 2102 and a second metal material layer 55 are sequentially formed in the U-shaped semiconductor structure 520. As described above, the gate dielectric layer 2102 and the second metal material layer 55 both wrap the multiple U-shaped semiconductor structures 520 on three sides, and the gate dielectric layer 2102 and the second metal material layer 55 both continuously cover the U-shaped semiconductor structure 520, as well as part of the first isolation barrier 211 between the multiple U-shaped semiconductor structures.

[0178] Next, continue as Figure 35 As shown, a third mask structure 56 is formed on the side of the U-shaped semiconductor structure 520 facing away from the substrate 200, and the third mask structure 56 is used as a mask to remove a portion of the bottom of the U-shaped semiconductor structure 520 exposed by the third mask structure 56, and a portion of the gate dielectric layer 2102 and the second metal material layer 55 covering the bottom 520 of the U-shaped semiconductor structure is removed to form Figure 34C The L-shaped vertical channel 2101, the gate dielectric layer 2102 and the first signal line 2103 are shown. In this way, the L-shaped vertical channel 2101, the gate dielectric layer 2102 and the first signal line 2103 can be formed simultaneously by a photolithography process using the third mask structure 56 as a mask.

[0179] On this basis, continue Figure 34CAs shown, a second isolation barrier 212 is formed. Figure 34A Two adjacent first signal lines 2103 are isolated and arranged on both sides of the second isolation barrier 212. Two vertical channels 2101 belonging to different array structures 21 are isolated on both sides of the second isolation barrier 212.

[0180] In other embodiments of the present application, Figure 36 As shown, when the vertical channel 2101 is L-shaped and the second portion of the vertical channel 2101 extending along the first direction X is covered by the gate dielectric layer 2102 on the side away from the first isolation barrier 211, two adjacent first signal lines 2103 (such as Figure 34C as shown) are connected as Figure 36 The conductive integrated structure 400 is shown as filling between two adjacent rows of L-shaped vertical channels 2101. The technical effect of the conductive integrated structure 400 is the same as described above and will not be repeated here.

[0181] In addition, in other embodiments of the present application, Figure 37A As shown, the structure of the vertical channel 2101 is U-shaped. Figure 37B (along Figure 37A As shown in the cross-sectional view obtained by cutting along the dotted line P5-P6 in FIG, the second portions 21012 of two adjacent vertical channels 2101 are connected so that the two connected vertical channels 2101 form a U-shaped structure.

[0182] Based on this, when forming the first mask structure 53 (such as Figure 19A As shown) after that, Figure 37A As shown, forming a plurality of vertical channels 2101 spaced apart along the second direction Y on the sidewall of the first isolation barrier 211 includes: removing the first mask structure 53 (eg, Figure 19A As shown in Figure 21A As shown, a second mask structure 54 is formed on the sidewalls of the first isolation barrier 211 , and a portion of the semiconductor material layer 52 and the third isolation barrier 213 exposed by the second mask structure 54 are removed to form a plurality of U-shaped vertical channels 2101 .

[0183] On this basis, they belong to different array structures 21 (such as Figure 37A shown), Figure 37B Two adjacent first signal lines 2103 are connected to the conductive integral structure 400, and the conductive integral structure 400 is filled between two adjacent rows of L-shaped vertical channels 2101. The technical effect of the conductive integral structure 400 is the same as described above and will not be repeated here.

[0184] In addition, if Figure 37C (along Figure 37A As shown in the side view obtained from the direction D3 in FIG, the first signal line 2103 covers the first portion 21011 (as shown in FIG. Figure 37B The first signal line 2103 also covers the surface of the first portion 21011 and the second portion 21012 that is perpendicular to the first isolation barrier 211 and the substrate 200. Therefore, the portion of the first signal line 2103 covering the second portion 21012 resembles a horseshoe shape. The technical effect of this horseshoe-shaped first signal line 2103 is the same as described above and will not be repeated here.

Claims

1. A chip, characterized in that: include: substrate; A plurality of array structures are provided on the substrate, and the plurality of array structures are arranged at intervals along a first direction; Each of the array structures comprises: First isolation retaining wall; a first transistor column; A second transistor column, wherein the first isolation barrier is located between the first transistor column and the second transistor column; wherein the first transistor column and the second transistor column both include: A plurality of vertical channels are arranged on the sidewalls of the first isolation barrier at intervals along a second direction, and the vertical channels are vertically disposed on the substrate; the first direction intersects with the second direction and are both parallel to the substrate; a gate dielectric layer, wherein the gate dielectric layer wraps the vertical channels on three sides and continuously covers the plurality of vertical channels and a portion of the first isolation barrier wall between the plurality of vertical channels; A first signal line is located on a side of the gate dielectric layer away from the first isolation barrier wall. The first signal line wraps around the vertical channel on three sides and continuously covers the multiple vertical channels and a portion of the first isolation barrier wall between the multiple vertical channels.

2. The chip according to claim 1, characterized in that The vertical channel includes: The first part is arranged in a direction perpendicular to the substrate; a second portion connected to an end of the first portion facing the substrate, the second portion being arranged along the first direction; The chip further includes: A second signal line is provided between the array structure and the substrate, and extends along the first direction; the second signal line contacts the second portion.

3. The chip according to claim 2, characterized in that In different array structures, the second portions of two adjacent vertical channels are connected so that the two connected vertical channels form a U-shaped structure.

4. The chip according to claim 2 or 3, characterized in that: The chip includes a plurality of second signal lines; The chip further includes a third isolation barrier wall, which is disposed between two adjacent second signal lines. The third isolation barrier wall is made of a different material from the first isolation barrier wall.

5. The chip according to any one of claims 1 to 4, characterized in that: In different array structures, two adjacent first signal lines are connected to form a conductive integrated structure, and the conductive integrated structure is filled between two adjacent rows of vertical channels.

6. The chip according to claim 5, characterized in that The chip further includes: A second isolation barrier is provided between two adjacent array structures and is located on a side of the conductive integrated structure facing away from the substrate.

7. The chip according to claim 2, characterized in that The chip further includes: A second isolation barrier is provided between two adjacent array structures; two adjacent first signal lines of different array structures are isolated on both sides of the second isolation barrier; and two adjacent vertical channels of different array structures are isolated on both sides of the second isolation barrier; A surface of the first signal line facing away from the first isolation barrier wall is flush with a surface of the second portion facing away from the first isolation barrier wall and a surface of the gate dielectric layer facing away from the first isolation barrier wall.

8. The chip according to claim 7, characterized in that The first signal line covers a surface of the first portion facing away from the first isolation barrier wall, and surfaces of the first portion and the second portion that are perpendicular to the first isolation barrier wall and the substrate.

9. The chip according to claim 1, characterized in that The chip further includes: A second isolation barrier is provided between two adjacent array structures; two adjacent first signal lines of different array structures are isolated and provided on both sides of the second isolation barrier; The first signal line covers a portion of the first isolation barrier wall and has a first groove on a side away from the first isolation barrier wall; a portion of the second isolation barrier wall is located in the first groove.

10. The chip according to any one of claims 1 to 9, characterized in that: The first transistor column and the second transistor column are symmetrically arranged with respect to the first isolation barrier.

11. The chip according to any one of claims 1 to 9, characterized in that: The first transistor column and the second transistor column each further include: A first electrode is provided on a side of the vertical channel facing the substrate; The second electrode is arranged on a side of the vertical channel away from the substrate.

12. The chip according to any one of claims 1 to 11, characterized in that: The chip further includes: A capacitor array is provided on a side of the array structure facing away from the substrate. The capacitor array is electrically connected to at least one of the first transistor column or the second transistor column to form a storage array.

13. The chip according to claim 12, characterized in that The chip further includes: A controller is electrically connected to the storage array and is used to control the reading and writing of the storage array.

14. An electronic device, characterized in that: include: circuit boards; The chip according to any one of claims 1 to 13, wherein the circuit board is electrically connected to the chip.

15. A method for manufacturing a chip, characterized in that: include: forming a plurality of first isolation barriers arranged at intervals along a first direction on the substrate; Transistor columns are formed on both sidewalls of the first isolation barrier, including: forming a plurality of vertical channels spaced apart along a second direction on the sidewall, wherein the vertical channels are perpendicular to the substrate; The first direction intersects with the second direction, and both are parallel to the substrate; A gate dielectric layer is formed on a side of the plurality of vertical channels away from the isolation barrier wall; the gate dielectric layer wraps around the vertical channels on three sides, and the gate dielectric layer continuously covers the plurality of vertical channels and a portion of the first isolation barrier wall between the plurality of vertical channels; A first signal line is formed on a side of the gate dielectric layer away from the first isolation barrier wall; the first signal line wraps around the vertical channel on three sides, and the first signal line continuously covers the multiple vertical channels and a portion of the first isolation barrier wall between the multiple vertical channels.

16. The method for manufacturing a chip according to claim 15, wherein: The forming of a plurality of first isolation barriers spaced apart along a first direction on the substrate comprises: forming a semiconductor material layer on a substrate; forming a plurality of second grooves extending along the first direction on the semiconductor material layer, and forming third isolation walls in the second grooves, wherein the third isolation walls are made of a different material from the first isolation walls; forming a first mask structure on the semiconductor material layer; removing the semiconductor material layer and the third isolation barrier wall exposed by the first mask structure to form a plurality of third grooves spaced apart along the first direction; The first isolation retaining wall is formed in the third groove.

17. The chip manufacturing method according to claim 16, characterized in that: After forming the first mask structure, forming a plurality of vertical channels spaced apart along the second direction on the sidewall includes: The first mask structure is removed, and a second mask structure is formed on the sidewalls of the first isolation barrier wall. The semiconductor material layer and the third isolation barrier wall exposed by the second mask structure are removed to form the vertical channel.

18. The method for manufacturing a chip according to claim 16, wherein: After forming the first mask structure, forming a plurality of vertical channels spaced apart along the second direction on the sidewall includes: The first mask structure is removed, and a second mask structure is formed on the sidewall of the first isolation barrier wall. A portion of the semiconductor material layer and the third isolation barrier wall exposed by the second mask structure are removed to form a plurality of U-shaped vertical channels.

19. The method for manufacturing a chip according to claim 16, wherein: After forming the first mask structure, forming a plurality of vertical channels spaced apart along the second direction on the sidewall, and forming the gate dielectric layer and the first signal line includes: removing the first mask structure, forming a second mask structure on the sidewalls of the first isolation barrier, and removing a portion of the semiconductor material layer and the third isolation barrier exposed by the second mask structure to form a plurality of U-shaped semiconductor structures; forming a gate dielectric material layer and a second metal material layer in sequence within the U-shaped semiconductor structure, wherein the gate dielectric material layer and the second metal material layer each wrap around the plurality of U-shaped semiconductor structures on three sides, and the gate dielectric material layer and the second metal material layer each continuously cover the U-shaped semiconductor structure and portions of the first isolation barrier between the plurality of U-shaped semiconductor structures; A portion of the bottom of the U-shaped semiconductor structure is removed, and a portion of the gate dielectric material layer and the second metal material layer covering the bottom of the U-shaped semiconductor structure are removed to form the L-shaped vertical channel, the gate dielectric layer and the first signal line.

Images