Semiconductor device and preparation method thereof, mask pattern and storage system

Abstract

The invention discloses a semiconductor device and a preparation method thereof, a mask pattern and a storage system. The semiconductor device comprises a first semiconductor structure and a second semiconductor structure which are connected in a bonding mode, and the first semiconductor structure comprises a first bonding layer and a first contact structure penetrating through the first bonding layer in the first direction. The second semiconductor structure comprises a second bonding layer and a second contact structure penetrating through the second bonding layer in the first direction. The first contact structure comprises a first end in contact with the second contact structure and a second end opposite to the first end in the first direction; and the size of the first contact structure in the second direction is gradually increased from the second end to the first end, and the second direction intersects with the first direction.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor technology, and in particular to semiconductor devices, methods for manufacturing semiconductor devices, mask patterns for manufacturing semiconductor devices, and storage systems. Background Art

[0002] As the integration of semiconductor devices increases, the size of the contact structures in semiconductor devices and the spacing between the contact structures become smaller and smaller, which in turn makes the process of forming contact holes to accommodate the contact structures more difficult. This requires the introduction of more advanced machines, resulting in a significant increase in the preparation cost of semiconductor devices.

[0003] Therefore, how to achieve a stable interconnection process and improve the stability of semiconductor devices without significantly increasing costs is an urgent problem to be solved. Summary of the Invention

[0004] The present application provides a method for manufacturing a semiconductor device, a semiconductor device, a mask pattern, and a storage system that can at least partially solve the above-mentioned problems or other problems in the art.

[0005] On the one hand, the present application provides a semiconductor device, which includes: a first semiconductor structure and a second semiconductor structure bonded together, wherein the first semiconductor structure includes a first bonding layer and a first contact structure extending through the first bonding layer in a first direction, and the second semiconductor structure includes a second bonding layer and a second contact structure extending through the second bonding layer in the first direction, wherein the first contact structure includes a first end in contact with the second contact structure and a second end opposite to the first end in the first direction; and a size of the first contact structure in the second direction gradually increases from the second end to the first end, and the second direction intersects with the first direction.

[0006] In one embodiment of the present application, the size of the first contact structure in the second direction gradually increases from the second end to the first end with a predetermined step length.

[0007] In one embodiment of the present application, the first contact structure further includes a sidewall located between the second end and the first end, wherein a cross-section of the sidewall in a plane parallel to the first direction is tapered.

[0008] In one embodiment of the present application, the first contact structure further includes a sidewall located between the second end and the first end, wherein an inclination angle of the sidewall relative to the first direction is greater than or equal to 20°.

[0009] In one embodiment of the present application, a ratio between a dimension of the first end in the second direction and a dimension of the second end in the second direction is 2 to 3.

[0010] In one embodiment of the present application, a ratio between a size of the first contact structure in the second direction and a size of the first contact structure in the first direction is 1 / 4 to 1.

[0011] In one embodiment of the present application, the first contact structure includes a diffusion barrier layer and a contact conductive layer surrounded by the diffusion barrier layer, wherein the contact conductive layer includes a metal material layer.

[0012] In one embodiment of the present application, the first semiconductor structure further includes a first interconnection layer, wherein the first interconnection layer includes an interconnection path extending along the first direction and an interconnection line extending along the second direction; and the second end of the first contact structure is in contact with the interconnection path or the interconnection line, and at the contact point, the dimension of the second end in the second direction is less than or equal to the width of the interconnection path or the interconnection line.

[0013] In one embodiment of the present application, a dimension of the second end of the first contact structure in the second direction is 100 nm to 150 nm.

[0014] In one embodiment of the present application, the second contact structure includes a third end in contact with the first end of the first contact structure and a fourth end opposite to the third end in the first direction; and the size of the second contact structure in the second direction gradually increases from the fourth end to the third end.

[0015] In one embodiment of the present application, the first semiconductor structure includes a memory array; the second semiconductor structure includes a peripheral circuit, wherein the second end of the first contact structure is connected to the memory array; and the second contact structure includes a third end in contact with the first end of the first contact structure and a fourth end opposite to the third end in the first direction, and the fourth end is connected to the peripheral circuit.

[0016] On the other hand, the present application provides a mask pattern for manufacturing semiconductor devices, the mask pattern comprising: a first area and a second area surrounding the first area, wherein the first area is a completely light-transmitting area; and the second area comprises a completely opaque sub-area and a completely light-transmitting sub-area, the completely opaque sub-area and the completely light-transmitting sub-area being alternately arranged from the inner side of the second area close to the first area to the outer side opposite to the inner side, so that the transmittance of the mask pattern gradually decreases from the inner side to the outer side.

[0017] In one embodiment of the present application, the completely opaque sub-regions and the completely transparent sub-regions are alternately arranged from the inner side to the outer side, so that the transmittance gradually decreases from the inner side to the outer side at a predetermined value.

[0018] In one embodiment of the present application, the completely light-impermeable sub-region includes a boundary defined by a sub-resolution auxiliary pattern having a predetermined size.

[0019] In one embodiment of the present application, the line width of the sub-resolution auxiliary pattern is less than or equal to 100 nm.

[0020] In one embodiment of the present application, the shape of the sub-resolution auxiliary graphic includes at least one of a polygon, an arc, a circle, a ring, and an ellipse.

[0021] On the other hand, the present application provides a method for preparing a semiconductor device, the method comprising: forming a first semiconductor structure, wherein the first semiconductor structure comprises a first bonding layer and a first contact structure penetrating the first bonding layer along a first direction; forming a second semiconductor structure, wherein the second semiconductor structure comprises a second bonding layer and a second contact structure penetrating the second bonding layer along the first direction; and bonding the first semiconductor structure and the second semiconductor structure, wherein the first contact structure comprises a first end in contact with the second contact structure and a second end opposite to the first end in the first direction; and a size of the first contact structure in the second direction gradually increases from the second end to the first end, and the second direction intersects with the first direction.

[0022] In one embodiment of the present application, the method includes forming the first contact structure, and forming the first contact structure includes: forming a first bonding layer; using a mask template pattern to form a through hole in the first bonding layer that passes through the first bonding layer along the first direction; and filling the through hole with a conductive material to form the first contact structure, wherein the through hole includes one end and the other end opposite to each other in the first direction, and the size of the through hole in the second direction gradually increases from the one end to the other end.

[0023] In one embodiment of the present application, forming a through hole in the first bonding layer along the first direction by using a mask pattern includes: covering the first bonding layer with a photoresist layer; transferring the mask pattern to the photoresist layer using a single photolithography process; and removing the portion of the first bonding layer corresponding to the pattern of the photoresist layer using the patterned photoresist layer as a mask to form the through hole.

[0024] In one embodiment of the present application, the mask pattern includes: a first area and a second area surrounding the first area, wherein the first area is a completely light-transmitting area; and the second area includes a completely opaque sub-area and a completely light-transmitting sub-area; and the method also includes changing the transmittance of the mask pattern by adjusting at least one of the size of the first area, the size of the completely opaque sub-area, and the size of the completely light-transmitting sub-area to adjust the size of the through hole in the second direction.

[0025] In one embodiment of the present application, the completely opaque sub-region includes a boundary defined by a sub-resolution auxiliary pattern having a predetermined size; and the method further includes adjusting the size of the through hole in the second direction by adjusting at least one of the line width of the sub-resolution auxiliary pattern, the predetermined size of the sub-resolution auxiliary pattern, and the resolution of the photoresist layer.

[0026] In one embodiment of the present application, the line width of the sub-resolution auxiliary pattern is less than or equal to 100 nm; and the resolution of the photoresist layer is greater than 100 nm.

[0027] In one embodiment of the present application, the shape of the sub-resolution auxiliary graphic includes at least one of a polygon, an arc, a circle, a ring, and an ellipse.

[0028] Another aspect of the present application provides a storage system, including a controller and the semiconductor device described above, wherein the controller is coupled to the semiconductor device and is used to control the semiconductor device to store data.

[0029] According to at least one embodiment of the present application, a semiconductor device, a method for manufacturing a semiconductor device, and a mask pattern for manufacturing a semiconductor device are provided. The semiconductor device includes a first semiconductor structure and a second semiconductor structure bonded together. The first semiconductor structure includes a first bonding layer and a first contact structure extending through the first bonding layer in a first direction. The second semiconductor structure includes a second bonding layer and a second contact structure extending through the second bonding layer in the first direction. The first contact structure includes a first end in contact with the second contact structure and a second end opposite to the first end in the first direction. In a direction intersecting the first direction, the size of the first contact structure gradually increases from the second end to the first end. The first end of the first contact structure has a larger size, which can increase the contact area between the first contact structure and the second contact structure, thereby enabling a reliable and effective connection between the two. In addition, the second end of the first contact structure has a smaller size, thereby facilitating alignment of the second end with other interconnect structures (e.g., interconnect lines) connected to the first semiconductor structure, thereby increasing the stability of the connection. In addition, a through hole accommodating the first contact structure is formed through a single photolithography and etching process, and the size of the first contact structure in a direction intersecting with the first direction gradually increases from the second end to the first end. This can achieve a stable interconnection process, improve the stability of the semiconductor device, and effectively reduce the preparation cost and cycle of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Other features, objects, and advantages of the present application will become more apparent by reading the detailed description of the non-limiting embodiments made with reference to the following drawings. The drawings are provided for a better understanding of the present invention and do not constitute a limitation of the present application. In the drawings:

[0031] Figure 1 is a cross-sectional view of a semiconductor device according to one embodiment of the present application;

[0032] Figure 2 is a partial cross-sectional view of a semiconductor device according to one embodiment of the present application;

[0033] Figure 3 yes Figure 2 An enlarged cross-sectional view of a semiconductor device at point A is shown;

[0034] Figure 4 is a partial cross-sectional view of a semiconductor device according to one embodiment;

[0035] Figure 5 is a top view of a mask pattern for manufacturing a semiconductor device according to one embodiment of the present application;

[0036] Figure 6 is a top view of a mask pattern according to an embodiment;

[0037] Figure 7-Figure 8is an embodiment of the invention Figure 6 A schematic diagram of a process for forming an opening in a mask pattern is shown;

[0038] Figure 9 is a schematic cross-sectional view of a structure formed after forming a patterned photoresist layer according to one embodiment of the present application;

[0039] Figure 10 is a schematic cross-sectional view of a structure formed after forming openings with gradually varying opening sizes according to one embodiment of the present application;

[0040] Figure 11 is a schematic cross-sectional view of a structure formed after forming a bonding layer according to an embodiment;

[0041] Figure 12 is a schematic cross-sectional view of a structure formed after an initial first opening is formed in one embodiment;

[0042] Figure 13 is a schematic cross-sectional view of a structure formed after forming a first opening in one embodiment;

[0043] Figure 14 is a schematic cross-sectional view of a structure formed after an initial second opening is formed in one embodiment;

[0044] Figure 15 is a schematic cross-sectional view of a structure formed after an opening is formed in one embodiment;

[0045] Figure 16 is a schematic cross-sectional view of a structure formed after forming a first filling layer in one embodiment;

[0046] Figure 17 is a flow chart of a method for preparing a semiconductor device according to an exemplary embodiment of the present application;

[0047] Figures 18-21 are schematic process diagrams of a method for preparing a semiconductor structure according to one embodiment of the present application; and

[0048] Figure 22 It is a schematic diagram of the storage system structure according to one embodiment of the present application. DETAILED DESCRIPTION

[0049] For a better understanding of the present application, various aspects of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely descriptions of exemplary embodiments of the present application and are not intended to limit the scope of the present application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0050] It should be noted that in this specification, the expressions first, second, third, etc. are only used to distinguish one feature from another feature area, and do not represent any limitation on the features, and especially do not represent any order of precedence.

[0051] In the accompanying drawings, the thickness, size, and shape of components have been slightly adjusted for ease of illustration. The accompanying drawings are for illustration only and are not drawn strictly to scale. As used herein, the terms "substantially," "approximately," and similar terms are used to indicate approximations, not degrees, and are intended to account for the inherent variations in measurements or calculations that would be recognized by one of ordinary skill in the art.

[0052] It should also be understood that expressions such as "comprises," "including," "having," "includes," and / or "comprising" are open rather than closed expressions in this specification, indicating the presence of the stated features, elements, and / or components, but do not exclude the presence of one or more other features, elements, components, and / or combinations thereof. In addition, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features rather than just the individual elements in the list. In addition, when describing embodiments of the present application, "may" is used to mean "one or more embodiments of the present application." And, the term "exemplary" is intended to refer to an example or illustration.

[0053] Unless otherwise defined, all words used herein (including engineering terms and scientific and technological terms) have the same meaning as commonly understood by those skilled in the art to which this application belongs. It should also be understood that, unless otherwise specified in this application, words defined in commonly used dictionaries should be interpreted as having the same meaning as they do in the context of the relevant technology, and should not be interpreted in an idealized or overly formal sense.

[0054] It should be noted that, unless otherwise specified or inconsistent with the context, the embodiments and features of the embodiments in this application may be combined with each other. Furthermore, unless expressly limited or inconsistent with the context, the specific steps included in the methods described in this application are not necessarily limited to the order in which they are described, but may be performed in any order or in parallel. The present application will be described in detail below with reference to the accompanying drawings and in conjunction with the embodiments.

[0055] In addition, in the present application, the term "layer" refers to a material portion including an area with a thickness. A layer may extend over the entirety of the underlying or upper structure, or may have an extent that is smaller than the extent of the underlying or upper structure. In addition, a layer may be an area of a homogeneous or inhomogeneous continuous structure having a thickness that is smaller than the thickness of the continuous structure. A layer may extend horizontally, vertically and / or along an inclined surface. A layer may include multiple sublayers. In addition, in the present application, when "connected" or "coupled" is used, it may indicate direct contact or indirect contact between the corresponding parts, unless otherwise clearly defined or inferred from the context.

[0056] Some embodiments of the present application provide a semiconductor device. Figure 1 is a cross-sectional view of a semiconductor device 1000 according to one embodiment of the present application. Figure 2 is a partial cross-sectional view of a semiconductor device 1000 according to one embodiment of the present application. Figure 3 yes Figure 2 FIG. 1 shows an enlarged cross-sectional view of a semiconductor device 1000 taken at point A. FIG.

[0057] like Figure 1-Figure 3 As shown, semiconductor device 1000 includes a first semiconductor structure 1000-10-1 and a second semiconductor structure 1000-2 bonded together, wherein the first semiconductor structure 1000-10-1 includes a first bonding layer 110 and a first contact structure 200-1 extending through the first bonding layer 110 along a first direction (z-direction), and the second semiconductor structure 1000-2 includes a second bonding layer 120 and a second contact structure 200-2 extending through the second bonding layer 120 along the z-direction. The first contact structure 200-1 includes a first end 201 in contact with the second contact structure 200-2 and a second end 202 opposite to the first end 201 in the z-direction. The dimension of the first contact structure 200-1 in a second direction (e.g., the x-direction or the y-direction) intersecting the z-direction gradually increases from the second end 202 toward the first end 201.

[0058] The first end of the first contact structure has a larger size, which can increase the contact area between the first contact structure and the second contact structure, so that the two can be reliably and effectively connected. In addition, the second end of the first contact structure has a smaller size, which facilitates the second end to align with other interconnect structures (e.g., interconnect lines, etc.) connected to the first semiconductor structure, thereby increasing the stability of the connection. In addition, a through hole that accommodates the first contact structure is formed through a single photolithography and etching process, and the size of the first contact structure in a direction intersecting the first direction is gradually increased from the second end to the first end. This can achieve a stable interconnection process, improve the stability of the semiconductor device, and effectively reduce the manufacturing cost and cycle of the semiconductor device.

[0059] Optionally, the second contact structure 200-2 may include a third end 203 that contacts the first contact structure 200-2 and a fourth end 204 that opposes the third end 203 in the z-direction. The dimension of the second contact structure 200-2 in a second direction (e.g., the x-direction or the y-direction) intersecting the z-direction gradually increases from the fourth end 204 to the third end 203. In other words, the first and second contact structures may have the same or similar shapes and structures. For example, the third end of the second contact structure that contacts the first contact structure may have a larger dimension, thereby increasing the contact area between the second and first contact structures and achieving a reliable and effective connection. The fourth end of the second contact structure that connects to other interconnect structures may have a smaller dimension, thereby facilitating alignment of the fourth end with the other interconnect structures and increasing the stability of the connection. Similarly, by forming a through hole to accommodate the second contact structure through a single photolithography and etching process, and gradually increasing the dimension of the second contact structure in a direction intersecting the first direction from the fourth end to the third end, a stable interconnection process can be achieved, improving the stability of the semiconductor device while effectively reducing the manufacturing cost and cycle time of the semiconductor device.

[0060] Specifically, in some embodiments of the present application, the size of the first contact structure 200-1 in the second direction (e.g., the x-direction or the y-direction) gradually increases from the second end 202 to the first end 202 in a predetermined step size, wherein the predetermined step size may be, for example, a first predetermined step size, which can be designed according to actual needs and is not limited herein. In other embodiments of the present application, the size of the second contact structure 200-2 in the second direction (e.g., the x-direction or the y-direction) may also gradually increase from the fourth end 204 to the third end 203 in a second predetermined step size, wherein the second predetermined step size can be designed according to actual needs and is not limited herein. Optionally, the first predetermined step size of the first contact structure 200-1 and the second predetermined step size of the second contact structure 200-2 may be different. In some other embodiments of the present application, the size of the first contact structure 200-1 in the second direction (for example, the x direction or the y direction) gradually increases from the second end 202 to the first end 202 with a first predetermined step size; in addition, the size of the second contact structure 200-2 in the second direction (for example, the x direction or the y direction) gradually increases from the fourth end 204 to the third end 203 with a second predetermined step size.

[0061] In addition, in some embodiments of the present application, the first contact structure 200-1 further includes a sidewall 205 located between the second end 202 and the first end 201. The second contact structure 200-2 further includes a sidewall 206 located between the fourth end 204 and the third end 203. As an option, the cross-sectional shape of the sidewall 205 of the first contact structure 200-1 in a plane parallel to the z-direction is a conical shape. As another option, the cross-sectional shape of the sidewall 206 of the second contact structure 200-2 in a plane parallel to the z-direction is a conical shape. Furthermore, as yet another option, the cross-sectional shapes of the sidewall 205 of the first contact structure 200-1 and the sidewall 206 of the second contact structure 200-2 in a plane parallel to the z-direction are conical shapes.

[0062] Furthermore, optionally, the sidewall 205 of the first contact structure 200-1 has an inclination angle α1 greater than or equal to 20° relative to the z-direction. Optionally, the sidewall 206 of the second contact structure 200-2 has an inclination angle α2 greater than or equal to 20° relative to the z-direction. Optionally, the sidewall 205 of the first contact structure 200-1 has an inclination angle α1 greater than or equal to 20° relative to the z-direction, and the sidewall 206 of the second contact structure 200-2 has an inclination angle α2 greater than or equal to 20° relative to the z-direction.

[0063] In addition, in some embodiments of the present application, in the second direction (e.g., the x-direction or the y-direction), the ratio between the dimension D1 of the first end 201 and the dimension D2 of the second end 202 is 2 to 3. In other embodiments of the present application, in the second direction (e.g., the x-direction or the y-direction), the ratio between the dimension D3 of the third end 203 and the dimension D4 of the fourth end 204 is 2 to 3. In still other embodiments of the present application, in the second direction (e.g., the x-direction or the y-direction), the ratio between the dimension D1 of the first end 201 and the dimension D2 of the second end 202 is 2 to 3, and the ratio between the dimension D3 of the third end 203 and the dimension D4 of the fourth end 204 is 2 to 3.

[0064] In some embodiments of the present application, a ratio between a dimension of the first contact structure 200-1 in a second direction (e.g., the x-direction or the y-direction) and a dimension H1 of the first contact structure 200-1 in the z-direction is 1 / 4 to 1. For example, a ratio between a dimension D1 of the first end 201 and its dimension H1 in the z-direction is 1 / 4 to 1; or a ratio between a dimension D2 of the second end 202 and its dimension H1 in the z-direction is 1 / 4 to 1.

[0065] Furthermore, a ratio between a dimension of the second contact structure 200-2 in a second direction (e.g., the x-direction or the y-direction) and a dimension H2 of the second contact structure 200-2 in the z-direction is 1 / 4 to 1. For example, a ratio between a dimension D3 of the third end 203 and its dimension H2 in the z-direction is 1 / 4 to 1; or a ratio between a dimension D2 of the fourth end 204 and its dimension H2 in the z-direction is 1 / 4 to 1.

[0066] Figure 4 is a partial cross-sectional view of a semiconductor device according to one embodiment.

[0067] like Figure 4 As shown, in some embodiments, the semiconductor device may include a bonding layer 1 and a contact structure 2 that penetrates the bonding layer 1 along a first direction (z direction). The contact structure 2 may have a dual damascene structure. Specifically, the contact structure 2 may have two ends opposite to each other in the z direction according to the needs of the semiconductor device, and the two ends have different sizes in a second direction (for example, the x direction or the y direction) that intersects the z direction. For example, the contact structure 2 includes a first end 21 and a second end 22, wherein the size of the first end 21 in the second direction is larger than the size of the second end 22 in the second direction. However, in order to make the size of the first end 21 of the contact structure 2 in the second direction differ sufficiently from the size of the second end 22 in the second direction, so as to increase the contact area of the first end for bonding the contact structures to each other and to align the second end of the contact structure with other interconnect structures, it is usually necessary to form an opening (not shown) to accommodate the contact structure 2 through more than one etching process. For example, a dual damascene process is used to form the opening to accommodate the contact structure 2.

[0068] Specifically, it can be formed first by, for example, a dry etching process or a combination of dry and wet etching processes; in addition, other manufacturing processes, such as patterning processes including photolithography, cleaning, and chemical mechanical polishing, can also be performed to form a first opening (not shown) with a smaller radial size in the bonding layer 1. After filling the first opening, the same process as above can be continued to form a second opening (not shown) that is connected to the first opening and has a larger radial size. The connected first opening and second opening are formed as an opening to accommodate the contact structure 2. The opening to accommodate the contact structure 2 is formed by at least two etching processes and other multiple auxiliary processes, which significantly increases the preparation cost and production cycle of the semiconductor device.

[0069] In order to improve the above situation, at least one embodiment of the present application can form a through hole to accommodate the first contact structure or the second contact structure through a single photolithography and etching process, and make the size of the first contact structure or the second contact structure in the direction intersecting with the first direction gradually increase from one end to the other end, thereby realizing a stable interconnection process and improving the stability of the semiconductor device, while effectively reducing the preparation cost and cycle of the semiconductor device.

[0070] Optionally, in some embodiments of the present application, the first semiconductor structure 1000-1 includes a memory array 400, and the second semiconductor structure 1000-2 includes a peripheral circuit 500, wherein the second end 202 of the first contact structure 200-1 is connected to the memory array 400, the fourth end 204 of the second contact structure 200-2 is connected to the peripheral circuit 500, and the first end 201 of the first contact structure 200-1 and the third end 203 of the second contact structure 200-2 are in contact with each other to realize the connection between the memory array 400 and the peripheral circuit 500.

[0071] Furthermore, in some embodiments of the present application, the first semiconductor structure 1000-1 further includes a first interconnect layer 310 located on one side of the memory array 400 along the z-direction, wherein the first interconnect layer 310 is closer to the peripheral circuit 500 than the memory array 400. Furthermore, the second semiconductor structure 1000-2 further includes a second interconnect layer 320 located on one side of the peripheral circuit 500 along the z-direction, wherein the second interconnect layer 320 is closer to the memory array 400 than the peripheral circuit 500.

[0072] Optionally, the first interconnect layer 310 may include an interconnect via 301 extending along the z-direction and an interconnect line 302 extending along a second direction (e.g., the x-direction or the y-direction). The second end 202 of the first contact structure 200-1 contacts the interconnect via or the interconnect line. At the point of contact, the dimension of the second end 202 in the second direction is less than or equal to the width of the interconnect via or the interconnect line. The first contact structure 200-1 may be connected to the memory array 400 via the first interconnect layer 310.

[0073] Optionally, the second interconnect layer 320 may also include an interconnect via 301 extending along the z-direction and an interconnect line 302 extending along a second direction (e.g., the x-direction or the y-direction). The fourth end 204 of the second contact structure 200-2 contacts the interconnect via or the interconnect line. At the contact point, the dimension of the fourth end 204 in the second direction is less than or equal to the width of the interconnect via or the interconnect line. The second contact structure 200-2 can be connected to the peripheral circuit 500 through the second interconnect layer 320.

[0074] As an option, the second end 202 of the first contact structure 200-1 has a size in the second direction (e.g., the x-direction or the y-direction) of 100 nm to 150 nm. As another option, the fourth end 204 of the second contact structure 200-2 has a size in the second direction (e.g., the x-direction or the y-direction) of 100 nm to 150 nm. As yet another option, the second end 202 of the first contact structure 200-1 has a size in the second direction (e.g., the x-direction or the y-direction) of 100 nm to 150 nm; and the fourth end 204 of the second contact structure 200-2 has a size in the second direction (e.g., the x-direction or the y-direction) of 100 nm to 150 nm.

[0075] In addition, refer again Figure 2 In some embodiments of the present application, the first contact structure 200-1 may include a diffusion barrier layer 220 and a contact conductive layer 210 surrounded by the diffusion barrier layer 220. The contact conductive layer 210 may include any suitable conductive material layer. Alternatively, the contact conductive layer 210 may include any suitable metal material layer. For example, the material of the contact conductive layer 210 may include, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), crystalline silicon, silicide, etc. The diffusion barrier layer 220 may include, but is not limited to, titanium, titanium nitride, tantalum, tantalum nitride, etc. The diffusion barrier layer 220 may be used to prevent the diffusion of metal materials in the contact conductive layer 210.

[0076] Some embodiments of the present application further provide a mask pattern 2000 for manufacturing a semiconductor device. Figure 5 FIG. 1 is a top view of a mask pattern 2000 for manufacturing a semiconductor device according to one embodiment of the present application.

[0077] like Figure 5 As shown, a mask pattern 2000 for manufacturing a semiconductor device includes: a first area S1 and a second area S2 surrounding the first area S1, wherein the first area S1 is a completely light-transmitting area, and the second area S2 includes a completely opaque sub-area S21 and a completely transparent sub-area S22, and the completely opaque sub-area S21 and the completely transparent sub-area S22 are alternately arranged from the inner side R1 of the second area S2 close to the first area S1 to the outer side R2 opposite to the inner side, so that the transmittance (Ratio) of the mask pattern 2000 gradually decreases from the inner side R1 to the outer side R2.

[0078] Specifically, in some embodiments of the present application, the completely opaque sub-region S21 and the completely transparent sub-region S22 are alternately arranged from the inner side R1 to the outer side R2, so that the transmittance gradually decreases from the inside to the outside at a predetermined value, where the predetermined value can be set according to the actual design requirements of the semiconductor device.

[0079] Optionally, the completely opaque sub-region S21 includes a boundary defined by a sub-resolution assistant feature (SRAF) having a predetermined size. In other words, the boundary of the completely opaque sub-region S21 is defined by the sub-resolution assistant feature. By adjusting parameters such as the line width and line length of the sub-resolution assistant feature, the size of the completely opaque sub-region S21 can be defined. By adjusting parameters such as the line spacing and line length of the sub-resolution assistant feature, the size of the completely transparent sub-region S22 located between adjacent completely opaque sub-regions S21 can be defined. As a result, the completely opaque sub-regions S21 and the completely transparent sub-regions S22 are alternately arranged from the inner side R1 to the outer side R2, achieving a gradually decreasing transmittance from the inner side R1 to the outer side R2.

[0080] Alternatively, the sub-resolution assist pattern has a line width less than or equal to 100 nm.

[0081] As an option, the shape of the sub-resolution auxiliary pattern may include at least one of a polygon, an arc, a circle, a ring, and an ellipse.

[0082] Figure 6 FIG. 1 is a top view of a mask pattern 3 according to an embodiment. Figure 7-Figure 8 FIG. 4 is a schematic diagram of a process for forming an opening 41 using a mask pattern 3 according to an embodiment.

[0083] like Figure 6 As shown, the mask pattern 3 only includes a completely light-transmitting area S3 , wherein the completely light-transmitting area S3 is schematically taken as an example of a circular area with a radial size d1 in the figure.

[0084] like Figure 6-Figure 8As shown, forming the opening 41 in the first base layer 4 using a dry etching process or a combination of dry and wet etching processes may include: transferring a mask pattern 3 from a photoresist mask (not shown) to the photoresist layer 5 using a photolithography process. The mask pattern 3 includes a pre-formed pattern for the opening 41, and the shape and size d1 of the completely light-transmitting region S3 are identical to the shape and size of the pre-formed pattern for the opening 41. Therefore, the photolithography process can be used to remove the portion of the photoresist layer 5 opposite the completely light-transmitting region S3, forming the pattern for the opening 41 in the photoresist layer 5, wherein the size d2 of the pattern in the photoresist layer 5 is substantially the same as the size d1 of the completely light-transmitting region S3. Subsequently, using the patterned photoresist layer 5 as a mask, a dry etching process or a combination of dry and wet etching processes is used to form the opening 41 in the first base layer 4. It should be noted that due to process limitations, the top dimension d3 of the opening 41 may be larger than its bottom dimension d4, with the error range between the two being between -10% and 10%. In other words, the top dimension d3 of the opening 41 is approximately the same as the dimension d1 of the completely light-transmitting region S3, while the bottom dimension d2 of the opening 41 is smaller than the dimension d1 of the completely light-transmitting region S3 due to process limitations. However, such a large-top-small-bottom opening cannot meet the technical requirements for an opening to accommodate a contact structure in a semiconductor device.

[0085] Therefore, a relatively complex dual damascene method is usually used to prepare the accommodating contact structure 2 (eg Figure 4 The preparation method will be described in detail below in conjunction with the accompanying drawings.

[0086] Figure 9 It is a schematic cross-sectional view of a structure formed after forming a patterned photoresist layer 5 according to one embodiment of the present application. Figure 10 4 is a schematic cross-sectional view of a structure formed after forming openings 42 with gradually varying opening sizes according to one embodiment of the present application.

[0087] like Figure 5 、 Figure 9 and Figure 10 As shown, in one embodiment of the present application, a mask pattern 2000 is used, and a dry etching process or a combination of dry and wet etching processes is adopted to form an opening 42 (hereinafter referred to as the opening 42) with a gradual opening size in the first base layer 4, wherein the gradual opening size variation can be understood as the opening 42 extending along the z-direction and including a top 42-1 and a bottom 42-2 opposite to each other in the z-direction, and the size of the opening in a direction intersecting with its extension direction (for example, the x-direction or the y-direction) gradually increases from its bottom 42-2 to its top 42-1.

[0088] Specifically, a mask pattern 2000 in a photolithography mask (not shown) is transferred to the photoresist layer 5 using, for example, a photolithography process. The mask pattern 2000 includes a first region S1 and a second region S2 surrounding the first region S1. By alternating completely opaque sub-regions S21 and completely transparent sub-regions S22 from the inner side R1 to the outer side R2, the transmittance can be gradually reduced from the inner side R1 to the outer side R2. As a result, a tapered, gradually changing opening 52 is formed in the photoresist layer 5 through the photolithography process. The maximum dimension of the tapered, gradually changing opening 52 in a direction intersecting its extension direction (e.g., the x-direction or the y-direction) is d7, thereby forming a patterned photoresist layer 5. The patterned photoresist layer 5 includes the tapered, gradually changing opening 52.

[0089] Optionally, by adjusting at least one of the size of the first region S1, the size of the completely opaque sub-region S21, and the size of the completely transparent sub-region S22, the transmittance of the mask pattern 2000 can be changed, thereby adjusting the maximum size d7 of the tapered gradient opening 52 and changing the size and shape of the opening 42 finally formed.

[0090] In addition, by adjusting at least one of the line width of the sub-resolution auxiliary pattern, the predetermined size of the sub-resolution auxiliary pattern, and the resolution of the photoresist layer 5, the transmittance of the mask pattern 2000 can also be changed, thereby adjusting the maximum size d7 of the tapered gradient opening 52 and changing the size and shape of the opening 42 finally formed.

[0091] Then, using the patterned photoresist layer 5 as a mask, a dry etching process or a combination of dry and wet etching processes can be used to form an opening 42 with a gradually varying opening size in the first base layer 4. Optionally, by adjusting the parameters of the etching process, such as the etching rate and etching time, while keeping the parameters of the patterned photoresist layer 5 unchanged, the size and shape of the resulting opening 42 can be adjusted.

[0092] Optionally, the opening 42 has a conical cross-section in a plane parallel to the z-direction. The opening 42 extends along the z-direction and includes a top portion 42-1 and a bottom portion 42-2 that are opposite to each other in the z-direction. The size of the opening in a direction intersecting the direction of its extension (e.g., the x-direction or the y-direction) gradually increases from the bottom portion 42-2 toward the top portion 42-1. The dimension d8 of the top portion 42-1 is the maximum dimension of the opening in the direction intersecting the direction of its extension, and the dimension d9 of the bottom portion 42-2 is the minimum dimension of the opening in the direction intersecting the direction of its extension.

[0093] The opening formed by this embodiment can be used to accommodate the semiconductor device 1000 (such as Figure 1 The first contact structure 200-1 or the second contact structure 200-2 (as shown) Figure 2In other words, a through hole accommodating the first contact structure or the second contact structure can be formed through a single photolithography and etching process, and the size of the first contact structure or the second contact structure in a direction intersecting the first direction gradually increases from one end thereof to the other end thereof opposite thereto. This effectively reduces the manufacturing cost and cycle time of the semiconductor device while achieving a stable interconnection process and improving the stability of the semiconductor device.

[0094] Figure 11 FIG. 1 is a schematic cross-sectional view of a structure formed after forming the bonding layer 1 in an embodiment. Figure 12 FIG. 6 is a cross-sectional schematic diagram of a structure formed after the initial first opening 601 is formed in one embodiment. Figure 13 FIG. 6 is a cross-sectional diagram of a structure formed after forming the first opening 602 in one embodiment. Figure 14 FIG. 1 is a cross-sectional schematic diagram of a structure formed after the initial second opening 603 is formed in one embodiment. Figure 15 FIG. 6 is a schematic cross-sectional view of a structure formed after the opening 605 is formed in one embodiment. Figure 16 FIG. 2 is a schematic cross-sectional view of a structure formed after forming the first filling layer 230 in one embodiment.

[0095] Combine Figure 4 、 Figure 6 、 Figures 11-16 In one embodiment, a dual damascene method can be used to prepare the accommodating contact structure 2 (eg Figure 4 605 as shown).

[0096] Specifically, if Figure 11 As shown, a bonding layer 1 can be formed on the surface of the interconnect layer 310 by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. Optionally, the bonding layer 1 can be a composite structure. For example, the bonding layer 1 can include multiple dielectric layers stacked sequentially along the z-direction. For example, the bonding layer 1 can include a silicon oxide layer, a silicon nitride layer, a polysilicon layer, etc.

[0097] After forming the bonding layer 1, a first mask layer 610 may be formed on the surface of the bonding layer 1 through at least one thin film deposition process. The thin film deposition process includes, but is not limited to, CVD, PVD, ALD, or any combination thereof. The first mask layer 610 may also be a composite structure. For example, the first mask layer 610 may include an amorphous carbon layer, a silicon oxynitride layer, etc.

[0098] like Figure 6 、 Figure 11-12As shown, the first photoresist layer 620 may be formed on the surface of the first mask layer 610 by at least one thin film deposition process, where the thin film deposition process includes but is not limited to CVD, PVD, ALD or any combination thereof.

[0099] Optionally, a photolithography process is used to transfer the mask pattern 3 in a photolithography mask (not shown) to the first photoresist layer 620. The mask pattern 3 includes a pre-formed first opening 602 (e.g., Figure 13 The shape and size d1 of the completely light-transmitting area S3 are exactly the same as the shape and size of the pre-formed pattern of the first opening 602. Therefore, the portion of the first photoresist layer 620 opposite to the completely light-transmitting area S3 can be removed by a photolithography process, and a pattern including an initial first opening 601 is formed in the first photoresist layer 620, wherein the size d5 of the initial first opening 601 in the first photoresist layer 620 is substantially the same as the size d1 of the completely light-transmitting area S3.

[0100] like Figure 12-13 As shown, using the patterned first photoresist layer 620 as a mask, a dry etching process or a combination of dry and wet etching processes is employed to form a first opening 602 in the bonding layer 1. The first opening 602 extends along the z-direction in the bonding layer 1 and extends to the interconnect via 301 or the interconnect line 302 of the interconnect layer 310. Due to process limitations, the top dimension of the first opening 602 is larger than its bottom dimension, with the margin of error between the two dimensions being between -10% and 10%.

[0101] Optionally, the top size of the first opening 602 is equal to the size d1 of the completely light-transmitting area S3 (e.g. Figure 6 shown) are roughly the same.

[0102] like Figure 13-14 As shown, after forming the first opening 602, a sacrificial layer 630 may be used to fill the first opening 602 through at least one thin film deposition process. The thin film deposition process includes, but is not limited to, CVD, PVD, ALD, or any combination thereof. Optionally, the sacrificial layer 630 may be formed of a material with a high deposition rate to facilitate rapid filling of the first opening 602. The sacrificial layer 630 should also be any material with a high dry etching selectivity relative to the bonding layer 1 to facilitate removal in subsequent steps. For example, the sacrificial layer 630 may include a polysilicon layer.

[0103] Optionally, after forming the sacrificial layer 630, the surface of the sacrificial layer 630 may be planarized by any suitable planarization technique, such as grinding and / or chemical mechanical polishing. In addition, a second photoresist layer 640 may be formed on the surface of the sacrificial layer 630 by at least one thin film deposition process, including but not limited to CVD, PVD, ALD, or any combination thereof.

[0104] like Figure 6 、 Figure 13-14 As shown, a photolithography process is used to transfer the mask pattern 3 in the photolithography mask (not shown) to the second photoresist layer 640. The mask pattern 3 includes a pre-formed second opening 604 (e.g., Figure 15 The shape and size d1 of the completely light-transmitting area S3 are consistent with the shape and size d7 of the pattern of the pre-formed second opening 604 (as shown in FIG. Figure 15 Therefore, the portion of the second photoresist layer 640 opposite to the completely light-transmitting area S3 can be removed by a photolithography process, and a pattern including an initial second opening 603 is formed in the second photoresist layer 640, wherein the size d6 of the initial second opening 603 in the second photoresist layer 640 is substantially the same as the size d1 of the completely light-transmitting area S3.

[0105] It should be noted that when the dual damascene method is used to prepare the accommodating contact structure 2 (such as Figure 4 In the process of the opening shown in FIG), although the above two photolithography processes both use Figure 6 The mask pattern of the photolithography mask shown in FIG, but the size d1 of the mask pattern used in the two photolithography processes (eg Figure 6 shown) are not the same.

[0106] like Figure 14-15 As shown, using the patterned second photoresist layer 640 as a mask, a dry etching process or a combination of dry and wet etching processes is adopted to form a second opening 604 in the bonding layer 1. The second opening 604 extends in the z-direction in the bonding layer 1 and extends to the first opening 602, so that the first opening 602 and the second opening 604 are connected to form an opening 605. The opening 605 can be used to accommodate a contact structure formed subsequently.

[0107] like Figure 4 、 Figure 15-16As shown, the opening 605 is filled with a first filling layer 230 through at least one thin film deposition process, wherein the thin film deposition process includes, but is not limited to, CVD, PVD, ALD, or any combination thereof. Optionally, the material of the first filling layer 230 includes, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), crystalline silicon, silicide, etc. The first filling layer 230 is formed, for example, by a dry etching process or a combination of dry and wet etching processes. In addition, other manufacturing processes may also be performed, such as a patterning process including photolithography, cleaning, and chemical mechanical polishing, to remove a portion of the first filling layer 230 to form the contact structure 2.

[0108] In the above embodiment, the opening for accommodating the contact structure 2 is formed through at least two etching processes and other multiple auxiliary processes, which significantly increases the preparation cost and production cycle of the semiconductor device.

[0109] In order to improve the above situation, at least one embodiment of the present application can form a through hole to accommodate the first contact structure or the second contact structure through a single photolithography and etching process, and make the size of the first contact structure or the second contact structure in the direction intersecting with the first direction gradually increase from one end to the other end, thereby realizing a stable interconnection process and improving the stability of the semiconductor device, while effectively reducing the preparation cost and cycle of the semiconductor device.

[0110] Some embodiments of the present application also provide a method 3000 for preparing a semiconductor device.

[0111] Figure 17 is a flow chart of a method 3000 for fabricating a semiconductor device according to an exemplary embodiment of the present application. Figures 18-21 They are respectively process schematic diagrams of a method 3000 for preparing a semiconductor structure according to one embodiment of the present application.

[0112] like Figure 17 As shown, the present application provides a method 3000 for preparing a semiconductor structure, comprising:

[0113] St1, forming a first semiconductor structure, wherein the first semiconductor structure includes a first bonding layer and a first contact structure penetrating the first bonding layer along a first direction, wherein the first contact structure includes a first end in contact with the second contact structure and a second end opposite to the first end in the first direction, the size of the first contact structure in the second direction gradually increases from the second end to the first end, and the second direction intersects with the first direction.

[0114] St2, forming a second semiconductor structure, wherein the second semiconductor structure includes a second bonding layer and a second contact structure penetrating the second bonding layer along the first direction.

[0115] St3, bonding the first semiconductor structure to the second semiconductor structure.

[0116] The following will be combined Figures 17 to 21 The specific process of each step of the above-mentioned preparation method 3000 is described in detail.

[0117] Step 1

[0118] Figure 18 It is a schematic cross-sectional view of a structure formed after forming the first bonding layer 310 according to one embodiment of the present application. Figure 19 FIG. 6 is a cross-sectional diagram of a structure formed after forming the third opening 606 in one embodiment. Figure 20 FIG. 6 is a schematic cross-sectional view of a structure formed after forming a through hole 607 in an embodiment. Figure 21 FIG. 1 is a schematic cross-sectional view of a structure formed after forming the initial contact conductive layer 210 ′ according to an embodiment.

[0119] Specifically, combined Figure 1 and Figure 18 The first semiconductor structure 1000 - 1 includes a memory array 400 , a first interconnection layer 310 located on one side of the memory array 400 along the z direction, and a first bonding layer 110 located on one side of the first interconnection layer 310 along the z direction.

[0120] Optionally, the memory array 400 may include at least one of a non-volatile memory cell and a volatile memory cell. The structure and manufacturing process of the memory cell may adopt existing conventional processes and be manufactured according to actual needs, which will not be described in detail in this application.

[0121] Taking the example of a memory array 400 including a plurality of volatile memory cells, the volatile memory cells may include transistors (not shown) and memory cells (not shown) coupled to the transistors. For example, in some embodiments, the memory cells may include capacitors for storing charge as binary information stored by corresponding DRAM (Dynamic Random Access Memory) cells. Furthermore, in some embodiments, the memory cells may include PCM elements (e.g., comprising a chalcogenide alloy) for storing binary information of corresponding PCM cells based on the different resistivities of the PCM elements in amorphous and crystalline phases. Furthermore, in some embodiments, the memory cells may include ferroelectric capacitors for storing binary information of corresponding FRAM (Ferroelectric Random Access Memory) cells based on the switching of a ferroelectric material between two polarization states under an external electric field.

[0122] Taking the memory array 400 including a plurality of nonvolatile memory cells as an example, the nonvolatile memory cells may include at least one of three-dimensional NAND memory cells and three-dimensional NOR memory cells.

[0123] After forming the memory array 400, a first interconnect layer 310 may be formed on one side of the memory array 400. The first interconnect layer 310 may include interconnect vias 301 extending along the z-direction and interconnect lines 302 extending along a second direction (e.g., the x-direction or the y-direction). The structure and preparation process of the first interconnect layer 310 may be prepared using conventional existing processes according to actual needs, and will not be described in detail herein.

[0124] like Figure 5 、 Figures 18-20 As shown, in some embodiments of the present application, forming a first contact structure may include: forming a first bonding layer 110; using a mask pattern 2000 to form a through hole 607 in the first bonding layer 110 that passes through the first bonding layer 110 along the z direction; and filling the through hole 607 with a conductive material to form a first contact structure 200-1.

[0125] Specifically, if Figure 18 As shown, after forming the first interconnect layer 310, a first bonding layer 110 may be formed on the surface of the first interconnect layer 310 through at least one thin film deposition process. The thin film deposition process includes, but is not limited to, CVD, PVD, ALD, or any combination thereof. Optionally, the first bonding layer 110 may be a composite structure. For example, the first bonding layer 110 may include multiple dielectric layers stacked sequentially along the z-direction. For example, the first bonding layer 110 may include a silicon oxide layer, a silicon nitride layer, a polysilicon layer, etc.

[0126] Optionally, forming a through hole passing through the first bonding layer along the z direction may include: covering the first bonding layer 110 with a photoresist layer 620; using a single photolithography process to transfer the mask pattern 2000 to the photoresist layer 620; and using the patterned photoresist layer 620 as a mask, removing the portion of the first bonding layer 110 corresponding to the pattern of the photoresist layer 620 to form a through hole 607.

[0127] Specifically, if Figure 18 As shown, after forming the first bonding layer 110, a first mask layer 610 may be formed on the surface of the bonding layer 110 through at least one thin film deposition process, including but not limited to CVD, PVD, ALD, or any combination thereof. The first mask layer 610 may also be a composite structure, for example, the first mask layer 610 may include an amorphous carbon layer, a silicon oxynitride layer, etc. Optionally, the first mask layer 610 may also include a dielectric anti-reflective coating.

[0128] like Figure 5 、 Figure 18-19 As shown, after forming the first mask layer 610, a photoresist layer 620 may be formed on the surface of the first mask layer 610 by a process such as smearing. Optionally, the resolution of the photoresist layer 620 may be greater than 100 nm. For example, the material of the photoresist layer 620 may include PI (Polyimide).

[0129] A mask pattern 2000 in a photolithography mask (not shown) is transferred to the photoresist layer 620 using, for example, a photolithography process. The mask pattern 2000 includes a first region S1 and a second region S2 surrounding the first region S1. The completely opaque sub-regions S21 and the completely transparent sub-regions S22 are alternately arranged from the inner side R1 to the outer side R2, so that the transmittance gradually decreases from the inner side R1 to the outer side R2. As a result, a tapered gradually changing opening 606 is formed in the photoresist layer 620 through the photolithography process. The maximum dimension of the tapered gradually changing opening 606 in a direction intersecting its extension direction (e.g., the x-direction or the y-direction) is d10.

[0130] Optionally, by adjusting at least one of the size of the first region S1, the size of the completely opaque sub-region S21, and the size of the completely transparent sub-region S22, the transmittance of the mask pattern 2000 can be changed, thereby adjusting the maximum size d10 of the tapered gradual opening 606 and changing the size of the finally formed through hole 607 (e.g., Figure 20 shown) in size and shape.

[0131] In addition, by adjusting at least one of the line width of the sub-resolution auxiliary pattern, the predetermined size of the sub-resolution auxiliary pattern, and the resolution of the photoresist layer 620, the transmittance of the mask pattern 2000 can be changed, thereby adjusting the maximum size d10 of the tapered gradual opening 606 and changing the size of the finally formed through hole 607 (e.g., Figure 20 shown) in size and shape.

[0132] Alternatively, the line width of the sub-resolution auxiliary pattern may be smaller than the resolution of the photoresist layer 620. For example, the resolution of the photoresist layer 620 may be greater than 100 nm, and the line width of the sub-resolution auxiliary pattern may be less than or equal to 100 nm.

[0133] Optionally, the shape of the sub-resolution auxiliary pattern may include at least one of a polygon, an arc, a circle, a ring, and an ellipse.

[0134] like Figure 19-20As shown, using the patterned photoresist layer 620 as a mask, a dry etching process or a combination of dry and wet etching processes can be used to form a through hole 607 in the first bonding layer 110. Optionally, when the parameters of the patterned photoresist layer 606 remain unchanged, the size and shape of the finally formed through hole 607 can be adjusted by adjusting the parameters of the etching process, such as the etching rate and etching time.

[0135] In addition, when adjusting the parameters of the patterned photoresist layer 606 , the parameters of the etching process, such as etching rate, etching time, etc., may also be adjusted to change the size and shape of the finally formed through hole 607 .

[0136] Optionally, the cross-section of the through hole 607 in a plane parallel to the z-direction is tapered. The through hole 607 extends along the z-direction and includes two opposite ends in the z-direction (e.g., a top end and a bottom end). The size of the through hole in a direction intersecting the direction of its extension (e.g., the x-direction or the y-direction) gradually increases from the bottom end to the top end, wherein the dimension D6 at the top end is the maximum dimension of the through hole in the direction intersecting the direction of its extension, and the dimension D5 at the bottom end is the minimum dimension of the through hole in the direction intersecting the direction of its extension.

[0137] Therefore, the through hole formed by this embodiment can be used to accommodate the semiconductor device 1000 (such as Figure 1 The first contact structure 200-1 (shown as Figure 1 In other words, a through hole accommodating the first contact structure can be formed through a single photolithography and etching process, and the size of the first contact structure in a direction intersecting the first direction gradually increases from one end thereof to the other end thereof opposite thereto. This effectively reduces the manufacturing cost and cycle time of the semiconductor device while achieving a stable interconnection process and improving the stability of the semiconductor device.

[0138] Figure 1 、 Figure 2 and Figure 21 As shown, after forming the through hole 607 , a first contact structure 200 - 1 may be formed in the through hole 607 by at least one thin film deposition process, including but not limited to CVD, PVD, ALD or any combination thereof.

[0139] Optionally, a diffusion barrier layer 220 can be formed on the inner wall of the through hole 607 and an initial contact conductive layer 210' can be formed on the surface of the diffusion barrier layer 220 through at least one thin film deposition process in sequence. The thin film deposition process includes but is not limited to CVD, PVD, ALD or any combination thereof.

[0140] Alternatively, the material of the diffusion barrier layer 220 may include, but is not limited to, titanium, titanium nitride, tantalum, tantalum nitride, and the like. Furthermore, the initial contact conductive layer 210' may include any suitable metal material layer. For example, the material of the initial contact conductive layer 210' may include, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), crystalline silicon, silicide, and the like.

[0141] After forming the initial contact conductive layer 210', a dry etching process or a combination of dry and wet etching processes may be used to form the contact conductive layer 210. Alternatively, other manufacturing processes, such as patterning processes including photolithography, cleaning, and chemical mechanical polishing, may be performed to remove a portion of the initial contact conductive layer 210' to form the contact conductive layer 210. Therefore, the first contact structure 200-1 may include a diffusion barrier layer 220 and the contact conductive layer 210 surrounded by the diffusion barrier layer 220. The diffusion barrier layer 220 may be used to prevent diffusion of metal materials in the contact conductive layer 210.

[0142] Step St2 and Step St3

[0143] like Figure 1 and Figure 17 As shown, the second semiconductor structure 1000-2 includes a peripheral circuit 500 and a second contact structure 200-2. The fourth end 204 of the second contact structure 200-2 is connected to the peripheral circuit 500, and the first end 201 of the first contact structure 200-1 and the third end 203 of the second contact structure 200-2 are in contact with each other to achieve the connection between the memory array 400 and the peripheral circuit 500.

[0144] The peripheral circuit 500 may be understood as a circuit for facilitating the operation of the memory array 400. The peripheral circuit 500 may include any suitable digital, analog, and / or mixed-signal circuit for facilitating the operation of the memory array 400. For example, the peripheral circuit 500 may include one or more of a page buffer, a decoder (e.g., a row decoder and a column decoder), a sensing structure (e.g., a bit line sensing amplifier structure), a driving structure (e.g., a word line driving structure), an input / output circuit, a charge pump, a voltage source or generator, a current or voltage reference, any portion (e.g., a sub-circuit) of the aforementioned functional circuits, or any active or passive component of the circuit (e.g., a transistor, a diode, a resistor, or a capacitor), and the present application is not limited thereto.

[0145] In some embodiments of the present application, the memory array 400 and the peripheral circuit 500 connected to the memory array 400 may be formed in two different chips, such as a memory array chip and a peripheral circuit chip. The memory array chip and the peripheral circuit chip may be combined together by a process such as bonding, and the peripheral circuit 500 and the memory array 400 may be connected together by a connection structure including, for example, a first contact structure 200-1 and a second contact structure 200-2.

[0146] Optionally, the second semiconductor structure 1000 - 2 further includes a second interconnect layer 320 located at one side of the peripheral circuit 500 along the z-direction, wherein the second interconnect layer 320 is closer to the memory array 400 than the peripheral circuit 500 .

[0147] Alternatively, the second interconnect layer 320 may include an interconnect via 301 extending along the z-direction and an interconnect line 302 extending along a second direction (e.g., the x-direction or the y-direction). The fourth end 204 of the second contact structure 200-2 contacts the interconnect via or the interconnect line. At the contact point, the dimension of the fourth end 204 in the second direction is less than or equal to the width of the interconnect via or the interconnect line. The second contact structure 200-2 may be connected to the peripheral circuit 500 via the second interconnect layer 320.

[0148] The structure and preparation process of the peripheral circuit 500 and the second interconnection layer 320 can be prepared according to actual needs using existing conventional processes, and this application will not go into details here. In addition, the bonding process for bonding the first semiconductor structure 1000-1 and the second semiconductor structure 1000-2 can also be formed using existing conventional processes according to actual needs, and therefore, this application will not go into details here. In addition, since the content related to the first contact structure 200-1 described in step St1 above can be fully or partially applicable to the second contact structure 200-2 described here, the content related or similar thereto will not be repeated. However, it can be understood by those skilled in the art that the first contact structure 200-1 and the second contact structure 200-2 can have the same or similar shape and structure, and the characteristics, implementation principles and technical effects achieved of the two structures are similar.

[0149] Figure 22 FIG1 is a block diagram of a system 900 having a semiconductor device according to an embodiment of the present application. The system 900 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a car computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage device located therein. Figure 22As shown in FIG, system 900 may include a host 904 and a memory system 901, wherein the memory system 901 has one or more semiconductor devices 902 and a memory controller 903. The host 904 may be a processor of an electronic device, such as a central processing unit (CPU), or may be a system on a chip (SoC), such as an application processor (AP). The host 904 may be configured to send data to or receive data from the semiconductor device 902.

[0150] The semiconductor device 902 may be any semiconductor device disclosed in this application, for example Figure 1 The semiconductor device shown. According to some embodiments, a memory controller 903 is coupled to the semiconductor device 902 and a host 904 and is configured to control the semiconductor device 902. The memory controller 903 can manage data stored in the semiconductor device 902 and communicate with the host 904. The semiconductor device of the embodiment of the present application includes a first semiconductor structure and a second semiconductor structure bonded together. The first semiconductor structure includes a first bonding layer and a first contact structure extending through the first bonding layer in a first direction. The second semiconductor structure includes a second bonding layer and a second contact structure extending through the second bonding layer in the first direction. The first contact structure includes a first end in contact with the second contact structure and a second end opposite to the first end in the first direction. In a direction intersecting the first direction, the size of the first contact structure gradually increases from the second end to the first end. The first end of the first contact structure has a larger size, which can increase the contact area between the first contact structure and the second contact structure, enabling a reliable and effective connection between the two. In addition, the second end of the first contact structure has a smaller size, thereby facilitating alignment of the second end with other interconnect structures (e.g., interconnect lines) connected to the first semiconductor structure, thereby increasing the stability of the connection. In addition, a through hole accommodating the first contact structure is formed through a single photolithography and etching process, and the size of the first contact structure in a direction intersecting with the first direction gradually increases from the second end to the first end. This can achieve a stable interconnection process, improve the stability of the semiconductor device, and effectively reduce the preparation cost and cycle of the semiconductor device.

[0151] In some embodiments, the memory controller 903 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 903 is designed to operate in a high duty cycle environment, such as an SSD or an embedded multimedia card (eMMC), which is used as a data storage device for mobile devices such as smartphones, tablets, laptops, etc., as well as enterprise storage arrays. The memory controller 903 can be configured to control the operations of the semiconductor device 902, such as read, erase, and program operations. The memory controller 903 can also be configured to manage various functions related to data stored in or to be stored in the semiconductor device 902, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 903 is further configured to process error correction code (ECC) associated with data read from or written to the semiconductor device 902. The memory controller 903 may also perform any other appropriate functions, such as formatting the semiconductor device 902. The memory controller 903 may communicate with an external device (e.g., the host 904) according to a specific communication protocol. For example, the memory controller 903 may communicate with the external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a PCI-Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer mini-interface (SCSI) protocol, an enhanced minidisk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a FireWire protocol, etc.

[0152] The memory controller 903 and the one or more semiconductor devices 902 can be integrated into various types of memory devices, for example, included in the same package (such as a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system 901 can be implemented and packaged into different types of final electronic products. Figure 22 In one example shown, the memory controller 903 and the single semiconductor device 902 may be integrated into a memory card 910. The memory card 910 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, etc.

[0153] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. As an example, the steps described in the present disclosure can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solutions disclosed in this application can be achieved. This is not limited herein.

[0154] The above specific embodiments do not limit the scope of protection of this application. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application shall be included within the scope of protection of this application.

Claims

1. A semiconductor device, characterized in that: include: A first semiconductor structure and a second semiconductor structure bonded together, wherein the first semiconductor structure includes a first bonding layer and a first contact structure extending through the first bonding layer in a first direction, and the second semiconductor structure includes a second bonding layer and a second contact structure extending through the second bonding layer in the first direction. wherein the first contact structure comprises a first end in contact with the second contact structure and a second end opposite to the first end in the first direction; and The size of the first contact structure in the second direction gradually increases from the second end to the first end, and the second direction intersects with the first direction.

2. The semiconductor device according to claim 1, wherein The size of the first contact structure in the second direction gradually increases from the second end to the first end with a predetermined step length.

3. The semiconductor device according to claim 1, wherein The first contact structure further includes a sidewall located between the second end and the first end, Wherein, a cross-section of the side wall in a plane parallel to the first direction is tapered.

4. The semiconductor device according to claim 1, wherein The first contact structure further includes a sidewall located between the second end and the first end, Wherein, the inclination angle of the side wall relative to the first direction is greater than or equal to 20°. The semiconductor device according to claim 1 , wherein A ratio between a dimension of the first end in the second direction and a dimension of the second end in the second direction is 2 to 3. The semiconductor device according to claim 1 , wherein: A ratio between a size of the first contact structure in the second direction and a size of the first contact structure in the first direction is 1 / 4 to 1.

7. The semiconductor device according to claim 1, wherein The first contact structure includes a diffusion barrier layer and a contact conductive layer surrounded by the diffusion barrier layer. Wherein, the contact conductive layer includes a metal material layer.

8. The semiconductor device according to claim 1, wherein The first semiconductor structure further includes a first interconnect layer, wherein the first interconnection layer comprises interconnection vias extending along the first direction and interconnection lines extending along the second direction; and The second end of the first contact structure contacts the interconnection via or the interconnection line. At the contact point, a dimension of the second end in the second direction is smaller than or equal to a width of the interconnection via or the interconnection line.

9. The semiconductor device according to claim 1, wherein A dimension of the second end of the first contact structure in the second direction is 100 nm to 150 nm.

10. The semiconductor device according to any one of claims 1 to 9, wherein: the second contact structure including a third end in contact with the first end of the first contact structure and a fourth end opposite to the third end in the first direction; and A size of the second contact structure in the second direction gradually increases from the fourth end to the third end.

11. The semiconductor device according to any one of claims 1 to 9, wherein: The first semiconductor structure includes a memory array; The second semiconductor structure includes a peripheral circuit, Wherein, the second end of the first contact structure is connected to the memory array; and The second contact structure includes a third end contacting the first end of the first contact structure and a fourth end opposite to the third end in the first direction, wherein the fourth end is connected to the peripheral circuit.

12. A mask pattern for manufacturing a semiconductor device, characterized in that: include: a first area and a second area surrounding the first area, Wherein, the first area is a completely light-transmitting area; as well as The second region includes a completely opaque sub-region and a completely transparent sub-region, and the completely opaque sub-region and the completely transparent sub-region are alternately arranged from the inner side of the second region close to the first region to the outer side opposite to the inner side, so that the transmittance of the mask pattern gradually decreases from the inner side to the outer side.

13. The mask pattern according to claim 12, wherein: The completely opaque sub-regions and the completely transparent sub-regions are alternately arranged from the inner side to the outer side, so that the light transmittance gradually decreases from the inner side to the outer side at a predetermined value.

14. The mask pattern according to claim 12, wherein: The completely light-impermeable sub-region includes a boundary defined by a sub-resolution auxiliary pattern having a predetermined size.

15. The mask pattern according to claim 14, wherein: The line width of the sub-resolution auxiliary pattern is less than or equal to 100 nm.

16. The mask pattern according to claim 14, wherein: The sub-resolution auxiliary graphic has a shape including at least one of a polygon, an arc, a circle, a ring, and an ellipse.

17. A method for preparing a semiconductor device, characterized in that: include: forming a first semiconductor structure, wherein the first semiconductor structure includes a first bonding layer and a first contact structure penetrating the first bonding layer along a first direction; forming a second semiconductor structure, wherein the second semiconductor structure includes a second bonding layer and a second contact structure penetrating the second bonding layer along the first direction; as well as bonding the first semiconductor structure and the second semiconductor structure, wherein the first contact structure comprises a first end in contact with the second contact structure and a second end opposite to the first end in the first direction; and The size of the first contact structure in the second direction gradually increases from the second end to the first end, and the second direction intersects with the first direction.

18. The method according to claim 17, wherein The method includes forming the first contact structure, wherein forming the first contact structure includes: forming a first bonding layer; forming a through hole in the first bonding layer penetrating the first bonding layer along the first direction by using a mask pattern; and Filling the through hole with a conductive material to form the first contact structure, The through hole includes one end and the other end opposite to each other in the first direction, and a size of the through hole in the second direction gradually increases from the one end to the other end.

19. The method according to claim 18, wherein Forming a through hole penetrating the first bonding layer along the first direction in the first bonding layer using a mask pattern includes: covering the first bonding layer with a photoresist layer; Using a single photolithography process, transferring the mask pattern into the photoresist layer; and Using the patterned photoresist layer as a mask, a portion of the first bonding layer corresponding to the pattern of the photoresist layer is removed to form the through hole.

20. The method according to claim 19, wherein The mask pattern includes: a first region and a second region surrounding the first region, wherein the first region is a completely light-transmitting region; and the second region includes a completely light-impermeable sub-region and a completely light-transmitting sub-region; and The method further includes changing the transmittance of the mask pattern by adjusting at least one of the size of the first region, the size of the completely opaque sub-region, and the size of the completely transparent sub-region to adjust the size of the through hole in the second direction.

21. The method according to claim 20, wherein The completely light-impermeable sub-region includes a boundary defined by a sub-resolution auxiliary pattern having a predetermined size; and The method further includes adjusting a size of the through hole in the second direction by adjusting at least one of a line width of the sub-resolution auxiliary pattern, a predetermined size of the sub-resolution auxiliary pattern, and a resolution of the photoresist layer.

22. The method according to claim 21, wherein The line width of the sub-resolution auxiliary pattern is less than or equal to 100 nm; and The resolution of the photoresist layer is greater than 100 nm.

23. The method according to claim 21, wherein The sub-resolution auxiliary graphic has a shape including at least one of a polygon, an arc, a circle, a ring, and an ellipse.

24. A storage system, characterized in that: The storage system includes a controller and the semiconductor device according to any one of claims 1 to 11, wherein the controller is coupled to the semiconductor device and is configured to control the semiconductor device to store data.

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