Semiconductor structure and manufacturing method thereof

Abstract

The invention relates to a semiconductor structure and a manufacturing method thereof, and belongs to the technical field of semiconductors. The technical problem that in the prior art, alignment and load effects exist in photoetching marks mainly based on the morphology of the silicon surface is solved. The semiconductor structure comprises a silicon wafer and a dielectric layer located on the upper surface of the silicon wafer, and the dielectric layer is provided with a groove mark; and the selection ratio of the silicon wafer to the dielectric layer is greater than or equal to 10: 1. According to the semiconductor structure and the dielectric layer, the photoetching mark is protected by using a material with good selection ratio difference, the photoetching mark does not change obviously in subsequent processing, the morphology of the photoetching mark can be kept, and high-quality alignment and overlay marks are formed; moreover, through the coverage of the photoetching mark, the load effect is reduced for subsequent silicon etching, and marks and test patterns at other positions can be kept consistent with the source region, so that the accuracy of quality monitoring is improved, the product quality is improved, and the contrast deviation is reduced.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and in particular relates to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] Photolithography and etching processes are important steps in the semiconductor manufacturing process. This step uses photolithography, development, and etching processes to manufacture geometric structures on silicon wafers. Different geometric structures (i.e., different photolithography layers) need to be aligned between layers through photolithography marks. However, in subsequent processing, the morphology of the photolithography marks will be damaged, and the laser recognition of the photolithography marks will be affected, thereby affecting the photolithography quality. At the same time, since the plasma selects different reaction areas during etching, it will affect the by-products and reaction rate during the reaction, which will also affect the consistency of the product.

[0003] Photolithography marks are visible patterns placed on masks and silicon wafers to determine their position and orientation. Conventional photolithography marks are primarily based on the topography of the silicon surface, relying on this topography to identify and mark the surface, providing a foundation for subsequent photolithography recognition. However, this method has several issues: First, the photolithography marks can undergo significant changes during subsequent processing, such as diffusion and oxidation, which alter their topography. Second, during etching processes with significant loading effects, the photolithography marks can affect the etch rate and topography of the source region, thereby affecting the characteristics of the manufactured device.

[0004] Therefore, in order to solve the above-mentioned problems of alignment and loading effect, it is necessary to research and design a semiconductor structure and a manufacturing method thereof. Summary of the Invention

[0005] In order to solve the above problems, the present invention provides a semiconductor structure and a manufacturing method thereof.

[0006] The technical solutions adopted by the present invention to solve the above technical problems are as follows:

[0007] The present invention provides a semiconductor structure, comprising: a silicon wafer and a dielectric layer located on the upper surface of the silicon wafer, wherein the dielectric layer is provided with groove marks; and the selectivity ratio of the silicon wafer and the dielectric layer is greater than or equal to 10:1.

[0008] Furthermore, the dielectric layer is a single-layer structure, and the material is a thermal oxidation material, electronic grade tetraethyl orthosilicate (TEOS) or silicon nitride;

[0009] Alternatively, the dielectric layer is a multi-layer composite structure, consisting of a plurality of sub-dielectric layers arranged sequentially from bottom to top, wherein the material of the sub-dielectric layer is thermal oxidation material, electronic grade tetraethyl orthosilicate (TEOS) or silicon nitride, and different sub-dielectric layers have different materials.

[0010] Furthermore, the thickness of the dielectric layer satisfies the following formula:

[0011]

[0012] Wherein, D represents the thickness of the dielectric layer, d represents the depth of the trench mark, r represents the selectivity between the silicon wafer and the dielectric layer, and N represents the multiple, where N>3.

[0013] The present invention also provides a method for manufacturing the semiconductor structure, comprising:

[0014] Step 1: growing a dielectric layer on a silicon wafer;

[0015] Step 2: applying photoresist on the dielectric layer, and then exposing and developing the obtained photoresist layer to obtain a mask pattern;

[0016] Step 3: Etching a groove on the dielectric layer according to the mask pattern to obtain a groove mark;

[0017] Step 4: Remove the photoresist layer and use the groove marks as photolithography marks to obtain a semiconductor structure.

[0018] Furthermore, in step 2, the photoresist used is a negative photoresist.

[0019] Furthermore, in step 3, a plasma etching process is used to etch grooves on the dielectric layer.

[0020] Compared with the prior art, the present invention has the following beneficial effects:

[0021] Compared with the existing silicon mark, the dielectric layer of the present invention uses a material with a good selectivity difference to protect the photolithography mark. The photolithography mark will not change significantly during subsequent processing, and the morphology of the photolithography mark can be maintained to form high-quality alignment and overlay marks.

[0022] Compared with existing silicon marks, the present invention reduces the load effect for subsequent silicon etching by covering the photolithography marks, helps other position marks and test patterns to be consistent with the source area, thereby improving the accuracy of quality monitoring, improving product quality, and reducing comparison deviation. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the embodiments of the present invention or the technical solutions of the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0024] Figure 1 is a schematic structural diagram of the semiconductor structure of the present invention;

[0025] Figure 2 is a process flow chart of a method for manufacturing a semiconductor structure of the present invention;

[0026] Figure 3 A schematic structural diagram of a semiconductor structure in the prior art;

[0027] Figure 4 In the figure, (a) is a schematic structural diagram of a monitoring pattern of a semiconductor structure in the prior art, and (b) is a schematic structural diagram of a source region pattern of a semiconductor structure in the prior art;

[0028] Figure 5 In the figure, (a) is a schematic structural diagram of a monitoring pattern of a semiconductor structure in the present invention, and (b) is a schematic structural diagram of a source region pattern of a semiconductor structure in the present invention;

[0029] In the figure: 1. Silicon wafer; 2. Dielectric layer; 3. Mask pattern; 4. Trench mark. DETAILED DESCRIPTION

[0030] In order to enable those skilled in the art to better understand the technical solution of the present invention, the present invention will be further described in detail below in conjunction with specific implementation methods.

[0031] like Figure 1 As shown, the semiconductor structure of the present invention is composed of a silicon wafer 1 and a dielectric layer 2 located on the upper surface of the silicon wafer 1 , wherein a trench mark 4 is formed on the dielectric layer 2 .

[0032] In the semiconductor structure of the present invention, the selection ratio of the silicon wafer 1 and the dielectric layer 2 is greater than or equal to 10:1. The dielectric layer 2 can be a single-layer structure or a multi-layer composite structure. If it is a single-layer structure, the material is a thermal oxidation material, electronic grade ethyl orthosilicate or silicon nitride; if it is a multi-layer composite structure, it is composed of a plurality of sub-dielectric layers arranged in sequence from bottom to top, and the material of the sub-dielectric layer is a thermal oxidation material, electronic grade ethyl orthosilicate or silicon nitride, and the materials of different sub-dielectric layers are different. The specific material is selected according to needs and there is no special restriction. The thickness of the dielectric layer 2 is greater than the depth of the groove mark 4, that is, the upper surface of the silicon wafer 1 does not leak out. The thickness of the dielectric layer 2 preferably satisfies the following formula:

[0033]

[0034] Wherein, D represents the thickness of the dielectric layer 2 , d represents the depth of the trench mark 4 , r represents the selectivity ratio between the silicon wafer 1 and the dielectric layer 2 , and N represents the multiple, where N>3.

[0035] like Figure 2 As shown, the method for manufacturing a semiconductor structure of the present invention includes:

[0036] Step 1: growing a dielectric layer 2 on a silicon wafer 1;

[0037] Step 2: applying a photoresist on the dielectric layer 2, and then exposing and developing the obtained photoresist layer to obtain a mask pattern 3; wherein the photoresist is usually a negative photoresist;

[0038] Step 3: according to the mask pattern 3, a plasma etching process is used to etch a groove on the dielectric layer 2 to obtain a groove mark 4;

[0039] Step 4: Remove the photoresist layer, and use the groove mark 4 as a photolithography mark to obtain a semiconductor structure. Subsequently, semiconductor device manufacturing can be continued based on the photolithography mark.

[0040] In order to enable those skilled in the art to better understand the technical solution of the present invention, the present invention will be further described in detail below with reference to the embodiments.

[0041] In the following examples, various processes and methods not described in detail are conventional methods known in the art. Unless otherwise specified, the materials, reagents, devices, instruments, equipment, etc. used in the following examples can be obtained from commercial sources.

[0042] Example 1

[0043] The semiconductor structure comprises a silicon wafer 1 and a dielectric layer 2 located on the upper surface of the silicon wafer 1. A trench mark 4 is formed in the dielectric layer 2. The dielectric layer 2 is made of 8000Å TEOS, and the trench mark 4 formed in the dielectric layer 2 has a depth of 2000Å.

[0044] The semiconductor structure is further processed using a 2μm dry silicon etching process. Figure 5 As can be seen from (a) and (b), the photolithography mark does not change significantly, and the morphology of the mark is maintained. The silicon etching depth of the monitoring pattern and the source region pattern is consistent, forming a high-quality alignment and overlay mark. Compared with the semiconductor structure using silicon marks in the prior art (the structural diagram is shown in FIG Figure 3 As shown in the figure, in the subsequent processing (2μm dry silicon etching process), the silicon mark will change significantly, resulting in a series of problems such as low lithography accuracy, large registration deviation, and large load effect, which in turn leads to obvious distortion of the monitoring pattern and the source area pattern, and a large difference in the silicon etching depth between the monitoring pattern and the source area pattern (as shown in the figure). Figure 4 (a) and (b) in the figure), which affects the accuracy of monitoring.

[0045] from Figure 4 and Figure 5 It can be seen that compared with the prior art, the present invention reduces the load effect for subsequent silicon etching by covering the photolithography marks, helps other position marks and test patterns to be consistent with the source area, thereby improving the accuracy of quality monitoring, improving product quality, and reducing comparison deviations.

[0046] Obviously, the above embodiments are merely examples for clarity of explanation and are not intended to limit the embodiments. Those skilled in the art will appreciate that other variations or modifications can be made based on the above description. It is not necessary and impossible to enumerate all embodiments here. Obvious variations or modifications arising therefrom remain within the scope of protection of the present invention.

Claims

1. A semiconductor structure, characterized in that include: Semiconductor silicon wafer (1); A dielectric layer (2) located on the upper surface of a semiconductor silicon wafer (1), wherein a groove mark (4) is formed on the dielectric layer (2); The selection ratio between the semiconductor silicon wafer (1) and the dielectric layer (2) is greater than or equal to 10:

1.

2. A semiconductor structure according to claim 1, characterized in that: The dielectric layer (2) is a single-layer structure, and the material is thermal oxidation material, electronic grade tetraethyl orthosilicate or silicon nitride; Alternatively, the dielectric layer (2) is a multi-layer composite structure, consisting of a plurality of sub-dielectric layers arranged sequentially from bottom to top, the material of the sub-dielectric layers is thermal oxidation material, electronic grade tetraethyl orthosilicate or silicon nitride, and the materials of different sub-dielectric layers are different.

3. The semiconductor structure according to claim 1, wherein: The thickness of the dielectric layer (2) satisfies the following formula: In the formula, D represents the thickness of the dielectric layer (2), d represents the depth of the groove mark (4), r represents the selection ratio between the silicon wafer (1) and the dielectric layer (2), and N represents the multiple, N>3.

4. A method for manufacturing a semiconductor structure according to any one of claims 1 to 3, characterized in that: include: Step 1: growing a dielectric layer (2) on a semiconductor silicon wafer (1); Step 2: applying photoresist on the dielectric layer (2), then exposing and developing the obtained photoresist layer to obtain a mask pattern (3); Step 3: etching a groove on the dielectric layer (2) according to the mask pattern (3) to obtain a groove mark (4); Step 4: remove the photoresist layer and use the groove mark (4) as an alignment mark to obtain a semiconductor structure.

5. The method for manufacturing a semiconductor structure according to claim 4, wherein: In step (2), the photoresist used is a negative photoresist.

6. The method for manufacturing a semiconductor structure according to claim 4, wherein: In step (3), a plasma etching process is used to etch grooves on the dielectric layer (2).

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