Power failure protection circuit

Abstract

The invention discloses a power failure protection circuit which is used for an output stage, the output stage comprises a first output tube, the first end of the first output tube is connected with power voltage, and the second end of the first output tube is the first output end of the output stage; the power failure protection circuit comprises a substrate selection unit, a first control unit and an adjusting unit, the substrate selection unit obtains a selection voltage at a second output end of the substrate selection unit based on an output voltage of a first output end and a power supply voltage, and the first control unit is used for generating a control signal based on a state of the power supply voltage. The adjusting unit adjusts the voltage of the control end of the first output tube based on the control signal and the selection voltage. According to the power failure protection circuit, the circuit reliability of the sub-module in the standby state of the system is improved, uncertain behaviors of the circuit are eliminated, and the system can meet more diversified input requirements and wider application scenes.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and in particular relates to a power-off protection circuit. Background Art

[0002] Whether low-voltage or high-voltage nodes, modules often need to be in standby mode when not in use to conserve power and ensure fast response times. Partial power-down shuts down unused circuitry and is primarily used to maintain a system in standby mode. Without brownout protection, when the supply voltage drops to zero, leakage paths to the power rails cannot be cut off, leading to excessive currents flowing through the input and output terminals, potentially damaging the subsystem.

[0003] Figure 1 This diagram shows a circuit without power-off protection. Module 1 operates normally with a first power supply voltage (VCC1) of 5V. Module 2, however, is powered off with a second power supply voltage (VCC2) of 0V. The 5VBus bus connected to module 2 remains active, and the ESD clamping diode from module 2's output to the second power supply voltage (VCC2) conducts forward, providing power to module 2. Without a series resistor to limit the current, the clamping diode could flow tens of milliamperes, potentially damaging the device and raising reliability concerns.

[0004] The information disclosed in this background technology section is only intended to enhance understanding of the overall background of the invention and should not be regarded as an admission or any form of suggestion that the information constitutes the prior art already known to a person skilled in the art. Summary of the Invention

[0005] An object of the present invention is to provide a power-off protection circuit, which can cut off the leakage path leading to the power supply when the power is off.

[0006] To achieve the above object, a specific embodiment of the present invention provides the following technical solution: a power-off protection circuit for an output stage, wherein the output stage includes a first output transistor, a first end of the first output transistor is connected to a power supply voltage, and a second end of the first output transistor is a first output end of the output stage;

[0007] The power-off protection circuit includes a substrate selection unit, a first control unit, and an adjustment unit. The first connection end of the substrate selection unit is connected to the first output end, and the second connection end of the substrate selection unit is connected to the power supply voltage. The substrate selection unit obtains a selection voltage at the second output end of the substrate selection unit based on the output voltage of the first output end and the power supply voltage. The substrate of the first output tube is connected to the second output end of the substrate selection unit. The first control unit is used to generate a control signal based on the state of the power supply voltage. The adjustment unit is connected to the first control unit, the second output end of the substrate selection unit, and the control end of the first output tube to adjust the voltage of the control end of the first output tube based on the control signal and the selection voltage.

[0008] In one or more embodiments of the present invention, the output stage further includes a second output tube, wherein the second end of the second output tube is connected to the control end of the first output tube, and the power-off protection circuit further includes a switch unit and a second control unit, wherein the switch unit is connected between the power supply voltage and the first end of the second output tube, and the second control unit is connected to the first end of the second output tube, the first control unit, and the switch unit to control the switching unit to be turned on or off based on the voltage at the first end of the second output tube and the control signal.

[0009] In one or more embodiments of the present invention, the power-off protection circuit further includes an enhancement unit, the first control unit is powered by a selection voltage, and the enhancement unit is connected to the substrate selection unit and the power supply voltage to enhance the voltage of the second output end of the substrate selection unit based on the power supply voltage when the output stage outputs normally.

[0010] In one or more embodiments of the present invention, the substrate selection unit includes a first transistor and a second transistor, the first end of the first transistor is connected to the first end of the second transistor to form the second output end of the substrate selection unit, the control end of the first transistor is connected to the second end of the second transistor to form the first connection end of the substrate selection unit, and the control end of the second transistor is connected to the second end of the first transistor to form the second connection end of the substrate selection unit.

[0011] In one or more embodiments of the present invention, the first control unit includes an AND gate, a first input terminal of the AND gate is used to receive an enable signal, a second input terminal of the AND gate is used to receive a power-on reset signal, and an output terminal of the AND gate is used to output a control signal.

[0012] In one or more embodiments of the present invention, the regulating unit includes a third transistor, the control end of the third transistor is used to receive a control signal, the first end of the third transistor is used to receive a selection voltage, and the second end of the third transistor is connected to the control end of the first output tube.

[0013] In one or more embodiments of the present invention, the enhancement unit includes a NAND gate, a fourth transistor and a fifth transistor, the first input terminal of the NAND gate is connected to the power supply voltage, the second input terminal of the NAND gate is used to receive an enable signal, the control terminal of the fourth transistor and the control terminal of the fifth transistor are connected to the output terminal of the NAND gate, the first terminal of the fourth transistor and the substrate of the fourth transistor are connected to the power supply voltage, the second terminal of the fourth transistor is connected to the first terminal of the fifth transistor, and the second terminal of the fifth transistor and the substrate of the fifth transistor are connected to the second output terminal of the substrate selection unit.

[0014] In one or more embodiments of the present invention, the substrate selection unit includes a sixth transistor and a seventh transistor, the first end of the sixth transistor is connected to the substrate of the sixth transistor to form the second output end of the substrate selection unit, the second end of the sixth transistor is connected to the first end of the seventh transistor and the enhancement unit, the substrate of the seventh transistor is connected to the second end of the seventh transistor to form the first connection end of the substrate selection unit, and the control end of the sixth transistor is connected to the control end of the seventh transistor to form the second connection end of the substrate selection unit.

[0015] In one or more embodiments of the present invention, the enhancement unit includes an eighth transistor, a ninth transistor, and a tenth transistor, the control end of the eighth transistor is connected to the first end of the resistor and the enable signal, the first end of the eighth transistor is connected to the ground voltage, the second end of the eighth transistor is connected to the control end of the ninth transistor, the control end of the tenth transistor, and the substrate selection unit, the first end of the ninth transistor is connected to the substrate of the ninth transistor and the power supply voltage, the second end of the ninth transistor is connected to the first end of the tenth transistor, and the second end of the tenth transistor is connected to the substrate of the tenth transistor and the second output end of the substrate selection unit.

[0016] In one or more embodiments of the present invention, the second control unit includes an eleventh transistor and a twelfth transistor, the control end of the eleventh transistor and the control end of the twelfth transistor are used to receive a control signal, the first end of the eleventh transistor is connected to the ground voltage, the second end of the eleventh transistor is connected to the first end of the twelfth transistor and the control end of the switch unit, and the second end of the twelfth transistor is connected to the first end of the second output tube.

[0017] Compared with the prior art, the power-off protection circuit of the present invention selects the output voltage of the first output terminal as the selection voltage when power is off through the substrate selection unit, and simultaneously turns off the body diode of the first output tube. The first control unit generates a control signal based on the power-off state, and the adjustment unit adjusts the voltage of the control terminal of the first output tube based on the control signal and the selection voltage to turn off the first output tube, thereby blocking the leakage path between the first output terminal and the power supply voltage, thereby achieving the power-off protection effect. In addition, the normal operation of the output stage is not affected when the power supply voltage is normal.

[0018] The power-off protection circuit of the present invention improves the reliability of the circuit of the submodule in the system standby state, eliminates the uncertain behavior of the circuit, and enables the system to meet more diversified input requirements and a wider range of application scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments recorded in the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0020] Figure 1 This is a system block diagram without a power-off protection circuit in the prior art.

[0021] Figure 2 This is a circuit schematic diagram of the power-off protection circuit in Example 1 of the present invention.

[0022] Figure 3 This is a circuit schematic diagram of the power-off protection circuit in the second embodiment of the present invention.

[0023] Figure 4 This is a circuit schematic diagram of the power-off protection circuit in Example 3 of the present invention. DETAILED DESCRIPTION

[0024] In order to enable those skilled in the art to better understand the technical solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0025] The terms "coupled," "connected," or "connected" as used in this specification encompass both direct and indirect connections. An indirect connection is a connection made through an intermediate medium, such as an electrically conductive medium, which may have parasitic inductance or capacitance. An indirect connection may also include a connection through other active or passive devices, such as switches, follower circuits, or other circuits or components, to achieve the same or similar functional objectives. Furthermore, in the invention, terms such as "first" and "second" are primarily used to distinguish one technical feature from another and do not necessarily require or imply a specific relationship, quantity, or order between these technical features.

[0026] In the detailed description of the specification, reference is made to the accompanying drawings forming a part hereof, wherein like reference numerals designate like parts throughout, and wherein exemplary embodiments that may be implemented are shown by way of example. It should be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present application. Therefore, the following detailed description should not be construed in a limiting sense.

[0027] The various operations in the specification may be described as multiple discrete actions or operations in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be interpreted as implying that these operations must be sequentially related. Specifically, these operations may not be performed in the order presented. The described operations may be performed in an order different from the described embodiments. Various additional operations may be performed and / or the described operations may be omitted in additional embodiments.

[0028] For the purposes of this application, the phrase "A and / or B" means (A), (B), or (A and B). For the purposes of this application, the phrase "A, B and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

[0029] Various components and devices may be referred to or shown in the singular form in this document (for example, "MOS tube", "transistor", "switch", etc.), but this is only for convenience of discussion, and any element referred to in the singular form may include multiple such elements according to the teachings of this document.

[0030] The description uses the phrases "in one embodiment" or "in other embodiments" or "in some embodiments", which can each refer to one or more of the same or different embodiments. In addition, the terms "including", "comprising", "having", etc. used in relation to the embodiments of this application are synonymous.

[0031] Example 1

[0032] like Figure 2As shown, a power-off protection circuit according to one embodiment of the present invention is used in an output stage 100. Output stage 100 can be used to expand an interface driver chip for an IO port (such as an IO port of a microcontroller MCU or a processor). Output stage 100 includes a first output transistor MP1 and a third output transistor MN1 in a push-pull structure. The first end of the first output transistor MP1 is connected to a power supply voltage VCC. The substrate of the third output transistor MN1 is connected to the first end of the third output transistor MN1 and to a ground voltage. The second end of the first output transistor MP1 is connected to the second end of the third output transistor MN1 to form a first output terminal VOUT of output stage 100.

[0033] like Figure 2 As shown, the power-off protection circuit includes a substrate selection unit 10, a first control unit 20, and an adjustment unit 30. The first connection terminal of the substrate selection unit 10 is connected to the first output terminal VOUT, and the second connection terminal of the substrate selection unit 10 is connected to the power supply voltage VCC. The substrate selection unit 10 obtains a selection voltage at the second output terminal NBODY of the substrate selection unit 10 based on the output voltage of the first output terminal VOUT and the power supply voltage VCC. The substrate of the first output transistor MP1 is connected to the second output terminal NBODY of the substrate selection unit 10. The first control unit 20 is configured to generate a control signal CONT based on the state of the power supply voltage VCC. The adjustment unit 30 is connected to the first control unit 20, the second output terminal NBODY of the substrate selection unit 10, and the control terminal of the first output transistor MP1 to adjust the voltage of the control terminal of the first output transistor MP1 based on the control signal CONT and the selection voltage.

[0034] like Figure 2 As shown, output stage 100 further includes a second output transistor MP2 and a fourth output transistor MN2 in a push-pull configuration. The second end of second output transistor MP2 is connected to the second end of fourth output transistor MN2 and the control end of first output transistor MP1. The substrate of second output transistor MP2 is connected to the first end of second output transistor MP2, and the substrate of fourth output transistor MN2 is connected to the first end of fourth output transistor MN2 and to ground. The power-off protection circuit further includes a switch unit 40 and a second control unit 50. Switch unit 40 is connected between power supply voltage VCC and the first end of second output transistor MP2. Second control unit 50 is connected to the first end of second output transistor MP2, first control unit 20, and switch unit 40 to control the on / off state of switch unit 40 based on the voltage at the first end of second output transistor MP2 and control signal CONT.

[0035] In one embodiment, the substrate selection unit 10 includes a first transistor M1 and a second transistor M2, the first end of the first transistor M1 is connected to the first end of the second transistor M2 to form a second output end NBODY of the substrate selection unit 10, the substrate of the first transistor M1 is connected to the first end of the first transistor M1, the substrate of the second transistor M2 is connected to the first end of the second transistor M2, the control end of the first transistor M1 is connected to the second end of the second transistor M2 to form a first connection end of the substrate selection unit 10, and the control end of the second transistor M2 is connected to the second end of the first transistor M1 to form a second connection end of the substrate selection unit 10.

[0036] The first control unit 20 includes an AND gate AND, a first input terminal of the AND gate AND is used to receive an enable signal OE, a second input terminal of the AND gate AND is used to receive a power-on reset signal POC, and an output terminal of the AND gate AND is used to output a control signal CONT.

[0037] The regulating unit 30 includes a third transistor M3, a control terminal of the third transistor M3 is used to receive the control signal CONT, a first terminal of the third transistor M3 is connected to the second output terminal NBODY of the substrate selection unit 10 for receiving the selection voltage, and a second terminal of the third transistor M3 is connected to the control terminal of the first output transistor MP1.

[0038] The switch unit 40 includes a thirteenth transistor M13, the control end of the thirteenth transistor M13 is connected to the first control unit 20 to receive the control signal CONT, the substrate and the first end of the thirteenth transistor M13 are connected to the second output end NBODY of the substrate selection unit 10 for receiving the selection voltage, and the second end of the thirteenth transistor M13 is connected to the control end of the first output transistor MP1.

[0039] The second control unit 50 includes an eleventh transistor M11 and a twelfth transistor M12. The control end of the eleventh transistor M11 and the control end of the twelfth transistor M12 are used to receive a control signal CONT. A first end of the eleventh transistor M11 is connected to a ground voltage. A second end of the eleventh transistor M11 is connected to a first end of the twelfth transistor M12 and a control end of the switch unit 40. A second end of the twelfth transistor M12 is connected to a first end of the second output transistor MP2.

[0040] In one embodiment, the first output tube MP1, the second output tube MP2, the first transistor M1, the second transistor M2, the third transistor M3, the twelfth transistor M12, and the thirteenth transistor M13 are P-channel MOS transistors, and the third output tube MN1, the fourth output tube MN2, and the eleventh transistor M11 are N-channel MOS transistors.

[0041] The first end of the first output tube MP1, the first end of the second output tube MP2, the first end of the first transistor M1, the first end of the second transistor M2, the first end of the third transistor M3, the first end of the twelfth transistor M12, the first end of the thirteenth transistor M13, the first end of the third output tube MN1, the first end of the fourth output tube MN2 and the first end of the eleventh transistor M11 are source electrodes; the second end of the first output tube MP1, the second end of the second output tube MP2, the second end of the first transistor M1, the second end of the second transistor M2, the second end of the third transistor M3, the first end of the twelfth transistor M12, the first end of the thirteenth transistor M13 The second end of the body transistor M12, the second end of the thirteenth transistor M13, the second end of the third output transistor MN1, the second end of the fourth output transistor MN2, and the second end of the eleventh transistor M11 are drains; the control end of the first output transistor MP1, the control end of the second output transistor MP2, the control end of the first transistor M1, the control end of the second transistor M2, the control end of the third transistor M3, the control end of the twelfth transistor M12, the control end of the thirteenth transistor M13, the control end of the third output transistor MN1, the control end of the fourth output transistor MN2, and the control end of the eleventh transistor M11 are gates.

[0042] In one embodiment, the substrate selection unit 10 enables the selection voltage at the second output terminal NBODY to be the higher of the output voltage of the first output terminal VOUT and the power supply voltage VCC. During power-off, the power supply voltage VCC is 0V, and the power-on reset signal POC is also 0V (the state of the power-on reset signal POC represents the state of the power supply voltage VCC). When the output voltage of the first output terminal VOUT exceeds 0V, the selection voltage becomes the output voltage at the first output terminal VOUT, and the substrate of the first output transistor MP1 is also connected to the output voltage at the first output terminal VOUT, causing the body diode of the first output transistor MP1 to turn off. Simultaneously, the third transistor M3 turns on, raising the potential of the control terminal of the first output transistor MP1, turning off the first output transistor MP1, and blocking the path (body diode path and channel path) for the first output terminal VOUT to flow back to the power supply voltage VCC.

[0043] At the same time, the potential of the second end of the twelfth transistor M12 and the first end of the second output transistor MP2 are pulled up by the potential of the control end of the first output transistor MP1 through the body diode of the second output transistor MP2. The twelfth transistor M12 is turned on, pulling up the potential of the control end of the thirteenth transistor M13, and the thirteenth transistor M13 is turned off. At the same time, the substrate of the thirteenth transistor M13 is connected to the second end of the thirteenth transistor M13, and the substrate of the second output transistor MP2 is connected to the first end of the second output transistor MP2. Therefore, the body diode of the thirteenth transistor M13 and the body diode of the second output transistor MP2 are arranged back-to-back, so that the path (body diode path and channel path) for the second end of the second output transistor MP2 to flow back to the power supply voltage VCC is blocked. Therefore, the first output terminal VOUT is a high-impedance node.

[0044] When the power is on and the output is disabled, the enable signal OE is 0, which is consistent with the analysis when the power is off, and the first output terminal VOUT is a high-impedance node.

[0045] When power is applied and output is enabled (when the circuit needs to output normally after power-on is completed, the enable signal OE is 1), the output stage operates normally, the selected voltage on the second output terminal NBODY is the power supply voltage VCC, and at this time, the power-on reset signal POC and the enable signal OE are both 1. The third transistor M3 is turned off, which does not affect the potential of the control terminal of the first output transistor MP1; at the same time, the thirteenth transistor M13 and the eleventh transistor M11 are turned on, and the twelfth transistor M12 is turned off, which does not affect the potential of the first terminal of the second output transistor MP2.

[0046] The present invention also provides a chip including the above-mentioned power-off protection circuit.

[0047] Example 2

[0048] like Figure 3 As shown, based on the first embodiment, the power-off protection circuit further includes an enhancement unit 60. In one embodiment, the first control unit 20 is powered by the selection voltage. The enhancement unit 60 is connected to the substrate selection unit 10 and the power supply voltage VCC to enhance the voltage of the second output terminal NBODY of the substrate selection unit 10 based on the power supply voltage VCC when the output stage 100 outputs normally.

[0049] In one embodiment, the enhancement unit 60 includes a NAND gate, a fourth transistor M4, and a fifth transistor M5. A first input terminal of the NAND gate is connected to a power supply voltage VCC, a second input terminal of the NAND gate is used to receive an enable signal OE, a control terminal of the fourth transistor M4 and a control terminal of the fifth transistor M5 are connected to an output terminal of the NAND gate, a first terminal of the fourth transistor M4 and a substrate of the fourth transistor M4 are connected to the power supply voltage VCC, a second terminal of the fourth transistor M4 is connected to a first terminal of the fifth transistor M5, a second terminal of the fifth transistor M5 and a substrate of the fifth transistor M5 are connected to a second output terminal NBODY of the substrate selection unit 10, and a body diode of the fourth transistor M4 and a body diode of the fifth transistor M5 are arranged back-to-back, thereby blocking a leakage channel between the second output terminal NBODY and the power supply voltage VCC formed by the body diodes of the fourth transistor M4 and the fifth transistor M5.

[0050] In one embodiment, the fourth transistor M4 and the fifth transistor M5 are P-channel MOS transistors, the first end of the fourth transistor M4 and the first end of the fifth transistor M5 are sources, the second end of the fourth transistor M4 and the second end of the fifth transistor M5 are drains, and the control end of the fourth transistor M4 and the control end of the fifth transistor M5 are gates.

[0051] When the power is off, the power supply voltage VCC and the power-on reset signal POC are 0. When the output voltage of the first output terminal VOUT is greater than 0, the selection voltage on the second output terminal NBODY is equal to the output voltage of the first output terminal VOUT, the NAND gate NAND outputs a high potential, the fourth transistor M4 and the fifth transistor M5 are turned off, and the first output terminal VOUT is a high-impedance node.

[0052] When powered on and output is disabled, the enable signal OE is 0, the NAND gate NAND outputs a high potential, the fourth transistor M4 and the fifth transistor M5 are turned off, and the first output terminal VOUT is still a high-resistance node.

[0053] When powered on and the output is enabled, during normal operation, the select voltage at the second output terminal NBODY is equal to the power supply voltage VCC, the power-on reset signal POC and the enable signal OE are 1, the NAND gate NAND output is 0, and the fourth transistor M4 and the fifth transistor M5 are turned on, thereby further raising the select voltage at the second output terminal NBODY and increasing the drive capability of the second output terminal NBODY. Without the enhancement unit 60, the drive capability of the select voltage at the second output terminal NBODY is very limited due to the large number of devices connected to the second output terminal NBODY. If the AND gate AND is designed using TTL logic levels, the operating voltage of the AND gate AND is 5V. When the enable signal OE is an intermediate voltage (such as 1.8V), the AND gate AND outputs 1. At this time, due to the intermediate voltage, the current in the AND gate AND is relatively large, thus requiring a relatively high drive capability of the select voltage at the second output terminal NBODY. To ensure proper circuit function, the select voltage at the second output terminal NBODY needs to be raised. In addition, the enhancement unit 60 has a simple structure and is easy to implement, which solves the problem without causing more complexity in design. The present invention also provides a chip including the above-mentioned power-off protection circuit.

[0054] Example 3

[0055] like Figure 4 As shown, compared with the second embodiment, the circuit structures of the substrate selection unit 10 and the enhancement unit 60 are changed. In one embodiment, the substrate selection unit 10 includes a sixth transistor M6 and a seventh transistor M7. The sixth transistor M6 and the seventh transistor M7 constitute a transmission gate. The first end of the sixth transistor M6 is connected to the substrate of the sixth transistor M6 to form the second output end NBODY of the substrate selection unit 10. The second end of the sixth transistor M6 is connected to the first end of the seventh transistor M7 and the enhancement unit 60. The substrate of the seventh transistor M7 is connected to the second end of the seventh transistor M7 to form the first connection end of the substrate selection unit 10. The control end of the sixth transistor M6 is connected to the control end of the seventh transistor M7 to form the second connection end of the substrate selection unit 10.

[0056] The enhancement unit 60 includes an eighth transistor M8, a ninth transistor M9, and a tenth transistor M10. The control terminal of the eighth transistor M8 is connected to the first terminal of the resistor R and the enable signal OE, and the second terminal of the resistor R is connected to the ground voltage. The resistor R is used to pull down the enable signal OE. The first terminal of the eighth transistor M8 is connected to the ground voltage. The second terminal of the eighth transistor M8 is connected to the control terminal of the ninth transistor M9, the control terminal of the tenth transistor M10, the second terminal of the sixth transistor M6, and the first terminal of the seventh transistor M7 of the substrate selection unit 10. The first terminal of the ninth transistor M9 is connected to the substrate of the ninth transistor M9 and the power supply voltage VCC. The second terminal of the ninth transistor M9 is connected to the first terminal of the tenth transistor M10. The second terminal of the tenth transistor M10 is connected to the substrate of the tenth transistor M10 and the second output terminal NBODY of the substrate selection unit 10.

[0057] In one embodiment, the sixth transistor M6 , the seventh transistor M7 , the ninth transistor M9 , and the tenth transistor M10 are P-channel MOS transistors, and the eighth transistor M8 is an N-channel MOS transistor.

[0058] The first end of the sixth transistor M6, the first end of the seventh transistor M7, the first end of the eighth transistor M8, the first end of the ninth transistor M9 and the first end of the tenth transistor M10 are sources; the second end of the sixth transistor M6, the second end of the seventh transistor M7, the second end of the eighth transistor M8, the second end of the ninth transistor M9 and the second end of the tenth transistor M10 are drains; the control end of the sixth transistor M6, the control end of the seventh transistor M7, the control end of the eighth transistor M8, the control end of the ninth transistor M9 and the control end of the tenth transistor M10 are gates.

[0059] In one embodiment, during power-off, the power supply voltage VCC and the power-on reset signal POC are 0. When the output voltage of the first output terminal VOUT is greater than 0, the sixth transistor M6 and the seventh transistor M7 are turned on, and the selection voltage at the second output terminal NBODY is equal to the output voltage of the first output terminal VOUT. The enable signal OE is weakly pulled down to ground via the resistor R, and the eighth transistor M8 is turned off. Therefore, the potential of the second end of the eighth transistor M8 is high, the ninth transistor M9 and the tenth transistor M10 are turned off, and the selection voltage at the second output terminal NBODY is not enhanced. At the same time, the first output terminal VOUT is a high-impedance node.

[0060] When powered on and output is disabled, the enable signal OE is 0, the eighth transistor M8 is turned off, and the selection voltage on the second output terminal NBODY is not enhanced. Meanwhile, the first output terminal VOUT is a high-resistance node.

[0061] When powered on and output is disabled, when the output voltage of the first output terminal VOUT is greater than the power supply voltage VCC, the selection voltage on the second output terminal NBODY is equal to the output voltage of the first output terminal VOUT, the potential of the second end of the eighth transistor M8 is high, the ninth transistor M9 and the tenth transistor M10 are turned off, the selection voltage on the second output terminal NBODY is not enhanced, and the first output terminal VOUT is a high-impedance node.

[0062] When powered on and output is disabled, when the output voltage of the first output terminal VOUT is lower than the power supply voltage VCC, the second end of the sixth transistor M6 and the first end of the seventh transistor M7 are floating, and the second output terminal NBODY is floating, and no current path from the first output terminal VOUT to the power supply voltage VCC is generated.

[0063] When powered on and output is enabled and in normal operation, the selection voltage on the second output terminal NBODY is equal to the power supply voltage VCC, the enable signal OE is 1, the eighth transistor M8 is turned on, the potential of the second end of the eighth transistor M8 is 0, the ninth transistor M9 and the tenth transistor M10 are turned on, the selection voltage on the second output terminal NBODY is equal to the power supply voltage VCC and has a strong driving capability.

[0064] When the system enable signal OE has the characteristic of being weakly pulled down by the resistor R, the solution of this embodiment is more concise.

[0065] The present invention also provides a chip including the above-mentioned power-off protection circuit.

[0066] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above and that the invention can be embodied in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered in all respects as illustrative and non-restrictive, and the scope of the invention is defined by the appended claims, not the foregoing description, and all variations within the meaning and range of equivalents of the claims are intended to be included therein. Any reference sign in a claim should not be construed as limiting the claim to which it relates.

[0067] In addition, it should be understood that although this specification is described in terms of implementation methods, not every implementation method contains only one independent technical solution. This narrative method of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other implementation methods that can be understood by those skilled in the art.

Claims

1. A power-off protection circuit, characterized in that: Used for an output stage, the output stage includes a first output tube, a first end of the first output tube is connected to the power supply voltage, and a second end of the first output tube is a first output end of the output stage; The power-off protection circuit includes a substrate selection unit, a first control unit, and an adjustment unit. The first connection end of the substrate selection unit is connected to the first output end, and the second connection end of the substrate selection unit is connected to the power supply voltage. The substrate selection unit obtains a selection voltage at the second output end of the substrate selection unit based on the output voltage of the first output end and the power supply voltage. The substrate of the first output tube is connected to the second output end of the substrate selection unit. The first control unit is used to generate a control signal based on the state of the power supply voltage. The adjustment unit is connected to the first control unit, the second output end of the substrate selection unit, and the control end of the first output tube to adjust the voltage of the control end of the first output tube based on the control signal and the selection voltage.

2. The power-off protection circuit according to claim 1, wherein: The output stage further includes a second output tube, the second end of which is connected to the control end of the first output tube. The power-off protection circuit further includes a switch unit and a second control unit. The switch unit is connected between the power supply voltage and the first end of the second output tube. The second control unit is connected to the first end of the second output tube, the first control unit, and the switch unit to control the switching unit to be turned on or off based on the voltage at the first end of the second output tube and the control signal.

3. The power-off protection circuit according to claim 1 or 2, characterized in that: The power-off protection circuit further includes an enhancement unit, the first control unit is powered by a selection voltage, and the enhancement unit is connected to the substrate selection unit and the power supply voltage to enhance the voltage of the second output terminal of the substrate selection unit based on the power supply voltage when the output stage outputs normally.

4. The power-off protection circuit according to claim 1, wherein: The substrate selection unit includes a first transistor and a second transistor, the first end of the first transistor is connected to the first end of the second transistor to form a second output end of the substrate selection unit, the control end of the first transistor is connected to the second end of the second transistor to form a first connection end of the substrate selection unit, and the control end of the second transistor is connected to the second end of the first transistor to form a second connection end of the substrate selection unit.

5. The power-off protection circuit according to claim 1, wherein: The first control unit includes an AND gate, a first input terminal of the AND gate is used to receive an enable signal, a second input terminal of the AND gate is used to receive a power-on reset signal, and an output terminal of the AND gate is used to output a control signal.

6. The power-off protection circuit according to claim 1, characterized in that: The regulating unit includes a third transistor, a control terminal of the third transistor is used to receive a control signal, a first terminal of the third transistor is used to receive a selection voltage, and a second terminal of the third transistor is connected to the control terminal of the first output tube.

7. The power-off protection circuit according to claim 3, characterized in that: The enhancement unit includes a NAND gate, a fourth transistor and a fifth transistor. The first input terminal of the NAND gate is connected to the power supply voltage, the second input terminal of the NAND gate is used to receive an enable signal, the control terminal of the fourth transistor and the control terminal of the fifth transistor are connected to the output terminal of the NAND gate, the first terminal of the fourth transistor and the substrate of the fourth transistor are connected to the power supply voltage, the second terminal of the fourth transistor is connected to the first terminal of the fifth transistor, and the second terminal of the fifth transistor and the substrate of the fifth transistor are connected to the second output terminal of the substrate selection unit.

8. The power-off protection circuit according to claim 3, characterized in that: The substrate selection unit includes a sixth transistor and a seventh transistor, the first end of the sixth transistor is connected to the substrate of the sixth transistor to form the second output end of the substrate selection unit, the second end of the sixth transistor is connected to the first end of the seventh transistor and the enhancement unit, the substrate of the seventh transistor is connected to the second end of the seventh transistor to form the first connection end of the substrate selection unit, and the control end of the sixth transistor is connected to the control end of the seventh transistor to form the second connection end of the substrate selection unit.

9. The power-off protection circuit according to claim 3, characterized in that: The enhancement unit includes an eighth transistor, a ninth transistor, and a tenth transistor, wherein the control end of the eighth transistor is connected to the first end of the resistor and the enable signal, the first end of the eighth transistor is connected to the ground voltage, the second end of the eighth transistor is connected to the control end of the ninth transistor, the control end of the tenth transistor, and the substrate selection unit, the first end of the ninth transistor is connected to the substrate of the ninth transistor and the power supply voltage, the second end of the ninth transistor is connected to the first end of the tenth transistor, and the second end of the tenth transistor is connected to the substrate of the tenth transistor and the second output end of the substrate selection unit.

10. The power-off protection circuit according to claim 2, characterized in that: The second control unit includes an eleventh transistor and a twelfth transistor, the control end of the eleventh transistor and the control end of the twelfth transistor are used to receive a control signal, the first end of the eleventh transistor is connected to the ground voltage, the second end of the eleventh transistor is connected to the first end of the twelfth transistor and the control end of the switch unit, and the second end of the twelfth transistor is connected to the first end of the second output tube.

Images