Small signal acquisition circuit applied to power distribution monitoring terminal

Abstract

The invention discloses a small signal acquisition circuit applied to a power distribution monitoring terminal, which comprises a switch unit and a plurality of sampling units, each sampling unit comprises a plurality of operational amplifiers, a plurality of phase inverters, a plurality of triodes, a plurality of resistors, a gating device, a trigger and a capacitor, the in-phase end of an operational amplifier U1 in the plurality of operational amplifiers is connected with the 21 end, and the in-phase end of the operational amplifier U1 in the plurality of operational amplifiers is connected with the 21 end. The inverting end is connected with the in-phase end of the operational amplifier U5, one end of the resistor R1, one end of the resistor R2 and one end of the capacitor C1, and the output end is connected with the input end of the inverter U2; the inverting end of the operational amplifier U5 is connected with the output end and the first input end of the multiplier U10; the second input end of the multiplier U10 is connected with the end 12, and the output end is connected with the end 13; an O0 pin of the gate U3 is connected with a base electrode of the triode Q2, an O1 pin of the gate U3 is connected with a base electrode of the triode Q1, an A0 pin of the gate U3 is connected with an output end of the phase inverter U4, an A1 pin of the gate U3 is connected with an output end of the phase inverter U2, an input end of the phase inverter U4, an SA pin of the gate U3 is connected with a 1Q pin of the trigger U6, and an SB pin of the gate U3 is connected with a 1Q reverse pin and a 1D pin of the trigger U6.

Description

Technical Field

[0001] The present invention relates to the technical field of power distribution measurement and control, and in particular to a small signal acquisition circuit applied to a power distribution monitoring terminal. Background Art

[0002] The power distribution system is a key link in the power system responsible for distributing electrical energy. Its primary function is to safely and reliably distribute high-voltage electricity transmitted from substations to various electrical devices according to user needs after it is stepped down through transformers. Therefore, to improve power reliability, in addition to real-time monitoring of parameters such as three-phase voltage, current, and zero-sequence voltage during power consumption, various equipment and environmental parameters within the corresponding power supply area must also be monitored. Due to the complexity and diversity of the monitored signals, as well as the varying attenuation characteristics or inherent gain functions of different sensors during signal transmission, the final output signal amplitude can range from multiple orders of magnitude, from μV to V. This requires setting corresponding gain parameters for each signal level during initial system configuration to ensure consistent levels and facilitate centralized monitoring. However, when changes or expansions are required, such as changing the input signal of the original monitoring port to a sensor with a different output level or adding new monitoring points during expansion, this fixed gain configuration requires reprogramming and debugging the system program. Therefore, a small signal acquisition circuit for distribution monitoring terminals is proposed, which facilitates the replacement of signal monitoring types and allows for rapid system configuration during expansion. Summary of the Invention

[0003] In view of the above technical problems, the purpose of the present invention is to provide a small signal acquisition circuit for power distribution monitoring terminals, including a switch unit and a sampling unit, wherein the sampling units are several, and the sampling units include several operational amplifiers, several inverters, several triodes, several resistors, gates, triggers, and capacitors. The operational amplifier U1 in the several operational amplifiers is connected to the 2_1 terminal in the same phase, the inverting terminal is connected to the operational amplifier U5 in the same phase, one end of the resistor R1, one end of the resistor R2, and one end of the capacitor C1, and the output terminal is connected to the input terminal of the inverter U2; the inverting terminal of the operational amplifier U5 is connected to the output terminal and the first input terminal of the multiplier U10; the second input terminal of the multiplier U10 is connected to the 1_2 terminal, and the output terminal is connected to the 2_1 terminal. 1_3 terminal; the O0 pin of the enabler U3 is connected to the base of the transistor Q2, the O1 pin is connected to the base of the transistor Q1, the A0 pin is connected to the output terminal of the inverter U4, the A1 pin is connected to the output terminal of the inverter U2 and the input terminal of the inverter U4, the SA pin is connected to the 1Q pin of the trigger U6, and the SB pin is connected to the 1Q inverse pin and 1D pin of the trigger U6; the 1PR inverse pin, 1CLR inverse pin and the collector of the transistor Q2 are connected to the power supply; the collector of the transistor Q1 is connected to the other end of the resistor R2; the emitter of the transistor Q2 is connected to the other end of the resistor R1; the emitter of the transistor Q1, the B0 pin and B1 pin of the enabler U3, and the other end of the capacitor C1 are grounded.

[0004] Furthermore, the sampling unit also includes a plurality of operational amplifiers, a plurality of transistors, a plurality of diodes, and a plurality of resistors. The operational amplifier U7 among the plurality of operational amplifiers is connected to the emitter of the transistor Q3, one end of the resistor R3, one end of the resistor R4, and one end of the resistor R5 in the same phase, and is connected to the inverting end and I_5 end of the operational amplifier U8 in the opposite phase, and the output is connected to the anode of the diode D2 and the other end of the resistor R5; the operational amplifier U8 is connected to the emitter of the transistor Q4, one end of the resistor R8, one end of the resistor R9, and one end of the resistor R10 in the same phase, and the output is connected to the anode of the diode D1 and the other end of the resistor R10; the operational amplifier U9 is connected to the anode of the diode D3, the anode of the diode D4, and the anode of the resistor R13 in the opposite phase. End, one end of resistor R14, and end 1_6, and the output end is connected to the 1CLK end and 1_4 end of trigger U6; the collector of transistor Q3, the collector of transistor Q4, the other end of resistor R3, the other end of resistor R8, and the other end of resistor R13 are connected to the power supply; the base of transistor Q3 is connected to the output end of inverter U4; the base of transistor Q4 is connected to the output end of inverter U2; the cathode of diode D1 is connected to the cathode of diode D3 and one end of resistor R11; the cathode of diode D2 is connected to the cathode of diode D4 and one end of resistor R12; the other end of resistor R4, the other end of resistor R9, the other end of resistor R11, the other end of resistor R12, and the other end of resistor R14 are grounded.

[0005] Furthermore, one end of the resistor R16 among the plurality of resistors is connected to the power supply, and the other end is connected to the inverting end of the operational amplifier U9 and one end of the resistor R15; the other end of the resistor R15 is grounded.

[0006] Furthermore, one end of the resistor R6 among the plurality of resistors is connected to one end of the resistor R7 and the terminal 1_5; the other end of the resistor R7 is connected to the power supply; and the other end of the resistor R6 is grounded.

[0007] Furthermore, the switch unit includes a rotary switch, the rotary switch is S1, the common terminal is connected to the 1_1 terminal, and the connection terminal is connected to the 2_1 terminal.

[0008] Furthermore, the switch unit includes a plurality of relay switches and corresponding bit decoders, the coils in the plurality of relay switches are connected to the output terminals of the bit decoders, and the input control terminals of the decoders are connected to the upper chip.

[0009] Furthermore, the resistor R16 and the resistor R15 are sliding resistors.

[0010] The beneficial effects of the present invention compared with the prior art are: The present invention can perform rapid configuration when the monitoring type of the power distribution terminal is changed and the monitoring range is expanded, without the need to re-write and debug the program, and the response speed is fast during the configuration process. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, a brief introduction is given below to the prior art and the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0012] Figure 1 This is a circuit structure diagram of the sampling unit provided by the present invention.

[0013] Figure 2 This is a circuit structure diagram of the switch unit provided by the present invention. DETAILED DESCRIPTION

[0014] In order to make the objects and advantages of the present invention more clearly understood, the present invention is described in detail below with reference to the embodiments. It should be understood that the following text is only used to describe one or several specific implementation methods of the present invention and does not strictly limit the scope of protection specifically requested by the present invention.

[0015] The present invention discloses a small signal acquisition circuit for a power distribution monitoring terminal, including a switch unit and a sampling unit. The sampling units are multiple, and the sampling units include multiple operational amplifiers, multiple inverters, multiple triodes, multiple resistors, a gate, a trigger, and a capacitor. The operational amplifier U1 in the multiple operational amplifiers is connected to the 2_1 terminal in the same phase, the inverting terminal is connected to the operational amplifier U5 in the same phase, one end of the resistor R1, one end of the resistor R2, and one end of the capacitor C1, and the output terminal is connected to the input terminal of the inverter U2; the inverting terminal of the operational amplifier U5 is connected to the output terminal and the first input terminal of the multiplier U10; the second input terminal of the multiplier U10 is connected to the 1_2 terminal, and the output terminal is connected to the 1_3 terminal; the gate is connected to the 2_1 terminal. The O0 pin of the pass-through device U3 is connected to the base of the transistor Q2, the O1 pin is connected to the base of the transistor Q1, the A0 pin is connected to the output end of the inverter U4, the A1 pin is connected to the output end of the inverter U2 and the input end of the inverter U4, the SA pin is connected to the 1Q pin of the trigger U6, and the SB pin is connected to the 1Q inverse pin and 1D pin of the trigger U6; the 1PR inverse pin, 1CLR inverse pin and the collector of the transistor Q2 are connected to the power supply; the collector of the transistor Q1 is connected to the other end of the resistor R2; the emitter of the transistor Q2 is connected to the other end of the resistor R1; the emitter of the transistor Q1, the B0 pin and B1 pin of the pass-through device U3 and the other end of the capacitor C1 are grounded.

[0016] Specifically, the sampling unit also includes several operational amplifiers, several transistors, several diodes, and several resistors. The operational amplifier U7 among the several operational amplifiers is connected to the emitter of the transistor Q3, one end of the resistor R3, one end of the resistor R4, and one end of the resistor R5 in the same phase, and is connected to the inverting end and I_5 end of the operational amplifier U8, and the output end is connected to the anode of the diode D2 and the other end of the resistor R5; the operational amplifier U8 is connected to the emitter of the transistor Q4, one end of the resistor R8, one end of the resistor R9, and one end of the resistor R10 in the same phase, and the output end is connected to the anode of the diode D1 and the other end of the resistor R10; the operational amplifier U9 is connected to the anode of the diode D3, the anode of the diode D4, and the anode of the resistor R13 in the same phase. End, one end of resistor R14, and end 1_6, and the output end is connected to the 1CLK end and 1_4 end of trigger U6; the collector of transistor Q3, the collector of transistor Q4, the other end of resistor R3, the other end of resistor R8, and the other end of resistor R13 are connected to the power supply; the base of transistor Q3 is connected to the output end of inverter U4; the base of transistor Q4 is connected to the output end of inverter U2; the cathode of diode D1 is connected to the cathode of diode D3 and one end of resistor R11; the cathode of diode D2 is connected to the cathode of diode D4 and one end of resistor R12; the other end of resistor R4, the other end of resistor R9, the other end of resistor R11, the other end of resistor R12, and the other end of resistor R14 are grounded.

[0017] Specifically, one end of the resistor R16 among the plurality of resistors is connected to the power supply, and the other end is connected to the inverting end of the operational amplifier U9 and one end of the resistor R15; the other end of the resistor R15 is grounded.

[0018] Specifically, one end of the resistor R6 among the plurality of resistors is connected to one end of the resistor R7 and the terminal 1_5; the other end of the resistor R7 is connected to the power supply; and the other end of the resistor R6 is grounded.

[0019] Specifically, the switch unit includes a rotary switch, and the rotary switch is S1, a common terminal of which is connected to terminal 1_1, and a connection terminal of which is connected to terminal 2_1.

[0020] Specifically, the switch unit includes a plurality of relay switches and corresponding bit decoders, the coils in the plurality of relay switches are connected to the output terminals of the bit decoders, and the input control terminals of the decoders are connected to the upper chip.

[0021] Specifically, the resistor R16 and the resistor R15 are sliding resistors.

[0022] In one embodiment, the problem to be solved is the need to re-burn and debug the system program when changing the monitoring type or expanding the number of monitoring. In the scheme, 1_1 is the common gain multiple signal input terminal, 2_1 is the sampling unit gain signal multiple feedback terminal, 1_2 is the gain signal input terminal, 1_3 is the gain output terminal, 1_4 is the start signal input terminal, 1_5 is the reset signal terminal, and 1_6 is another start signal input terminal. In this embodiment, when in use, the monitoring signal output by the corresponding sensor is input to 1_2. After adjusting the 1_1 common gain multiple voltage signal, the switch unit is selected to the sampling unit corresponding to the connection 1_2. The 1_1 voltage can be input by the upper-connected chip or voltage regulation circuit, and then two pulse signals are input to 1_4. After that, the configuration is completed. When the sampling unit is reused for other monitoring types, two pulse signals can be input to 1_4 again. In the specific circuit principle, when the circuit is powered on, the 2_1 signal is input to the in-phase terminal of the operational amplifier U1. After the sampling unit to be regulated is selected through the switch unit, the signal is input to 1_4. When the sampling circuit is initially powered on, it is in the interrupt standby state. After the 1_4 signal is input, the inverting terminal of the operational amplifier U1 will collect the voltage at the connecting terminal of the resistor R2 and the capacitor C1, and then compare it with the in-phase terminal and output the resulting signal to the inverter U2. After inversion, the inverter U2 inputs one path to the A1 pin of the selector U3, and the other path is inverted through the inverter U4 and input to the A0 pin of the selector U3, so that the selector U3 is selected and fed back to the transistors Q1 and Q 2. When the base voltage of C1 and resistor R2 is kept consistent, when the power is initially turned on or in the re-regulation state, the voltage at the connection end of C1 and resistor R2 is less than the 1_1 feedback voltage, the O0 pin of the selector U3 will output a signal to the base of the transistor Q2, and the transistor Q2 will be turned on. The collector voltage of the transistor Q2 will be fed back to the capacitor C1 through the emitter and resistor R1, and its voltage will be pulled up to be synchronized with the voltage of the in-phase terminal of the operational amplifier U1, and then the 1_4 signal will be input again to the 1clk pin of the trigger U6. The 1Q pin and the 1Q inverted pin of the trigger U6 are reversed, the 1Q pin outputs a high potential voltage, and the 1Q inverted pin outputs a low potential voltage. The O0 and O1 pins of the selector U3 output B0 and B1 potential voltages. When the power is initially turned on or in the re-regulation state, it is assumed that the capacitor C1 and the capacitor C1 If the voltage at the connection end of resistor R2 is greater than the feedback voltage of 1_1, the O1 pin of the selector U3 inputs the signal to the base of the transistor Q1, and the voltage at the capacitor C1 passes through the resistor R2, the collector and emitter of the transistor Q1 and the ground loop. The voltage at the capacitor C1 is synchronized with 1_1 and then the 1_4 signal is input to the trigger U6. At the same time, the voltage at the connection end of capacitor C1 and resistor R2 will be followed and output to the multiplier U10 through the operational amplifier U5. After 1_2 is input, it will be gain amplified according to the voltage followed by the operational amplifier U5 and output to 1_3 to complete the gain. When the gain multiples of other sampling units need to be changed again, the 1_1 signal parameters are changed and a pulse signal is input to 1_4 after the switch unit is selected to the corresponding sampling unit. The above process is repeated until all sampling units are controlled.

[0023] In one embodiment, considering the uncertainty of the gain multiple span of the sampling unit before and after regulation, in order to ensure that there is no gain interruption during the automatic regulation process, it is necessary to set the interval period of the two pulse signals 1_4 according to the maximum and minimum values of the time constant curve between the capacitor C1 and the resistor R1 and the capacitor C1 and the resistor R2 each time the gain multiple of the sampling unit is regulated. In the case of multiple sampling units, the response time of the overall regulation will be increased. Therefore, based on the above scheme, a faster response regulation scheme is proposed, in which 1_4 is changed from an external input mode to 1_6 to select the input start signal for the first time, and the second time is self-controlled according to the size of the gain span before and after. In the specific scheme, the inverter U2 and the inverter U4 are first allowed to The output ends are respectively input to the bases of transistors Q4 and Q3. When 1_6 is input for the first time, the op amp U1 outputs a high or low potential voltage signal which is inverted by the inverter U2 and input to the base of the transistor Q4 to turn on, or is inverted by the inverter U4 and input to the base of the transistor Q3 to turn on. Assuming that the output of the selector U3 is first transferred from the O0 pin to the O1 pin output, the transistor Q3 is turned on, and the power supply signal of the collector of the transistor Q3 is fed back to the non-inverting terminal of the op amp U7 through the transistor Q3. When powered on, the non-inverting terminal of the op amp U7 is set with a low potential reference voltage by the resistors R3 and R4, and the inverting terminal of the op amp U7 is set with a high potential reference voltage. After the power is input to the non-inverting terminal of the op amp U7 through the transistor Q3, the op amp U7 outputs a high potential signal which is fed back to the non-inverting terminal through the resistor R5 to close the loop. , pull up the operational amplifier U7 non-inverting terminal potential, and at the same time, the signal passes through the diode D2 and resistor R12 circuit. The diode D4 is reverse biased and cut off during the first signal input of 1_6. The 1_6 signal is routed through the diode D3 and resistor R11 circuit, and the other route passes through the resistor R14 circuit. The potential of the anode connection terminal of the resistor R14 and the diode D3 is greater than the initial state when the operational amplifier U7 outputs a low potential and is less than the reference voltage potential of the inverting terminal of the operational amplifier U9. When the gain multiple is adjusted to switch the O0 and O1 outputs of the selector U3, the outputs of the inverter U2 and the inverter U4 change to turn on the transistor Q4 and turn off the transistor Q3. The operational amplifier U7 is fed back to the non-inverting terminal of the operational amplifier U7 through the resistor R5 to output a high potential in a closed loop, and the collector power supply of the transistor Q4 is reversed by the transistor Q4. Feed to the non-inverting terminal of op amp U8, the non-inverting terminal of op amp U8 is set to a low potential reference voltage, and the inverting terminal of op amp U8 is set to a high potential reference voltage. When transistor Q4 is turned on, the potential of the non-inverting terminal of op amp U8 is greater than the inverting terminal of op amp U8, and the high potential output of op amp U8 is fed back to the non-inverting terminal of op amp U8 through resistor R10 to close the loop. At the same time, the output of op amp U8 is also fed back through diode D1 and resistor R11. Diode D3 is reverse biased and cut off, and then the potential of resistor R13 and diode D3 anode connection terminal is pulled up again and fed back to the non-inverting terminal of op amp U9. The non-inverting terminal of op amp U9 is greater than the input signal voltage of the inverting terminal of op amp U9. The reference voltage parameter of the inverting terminal of op amp U9 is greater than the potential of either diode D4 or diode D3 when biased and less than the potential voltage of diode D4 and diode D3 when biased.Op amp U9 outputs a signal to the 1clk pin of trigger U6 for self-control, and the self-control interval period corresponds to the gain span. Conversely, if selector U3 switches from O1 to O0 output first, transistor Q4 will first turn on during the high-level period of the first input signal of 1_6. When the first signal cycle ends and returns to a low level, the output of op amp U8 is closed-loop fed back to the cathode of diode D3, the pull-up resistor R13, and the voltage potential of the anode of diode D3. Then, the output of op amp U7 is pulled up again, allowing the output of op amp U9 to complete self-control.

[0024] In one embodiment, in addition to the examples in the attached drawings, the first input method of the 1_6 signal can also be input from the inverting terminal of the operational amplifier U9. The connection method is to remove the inverting terminal signal provided by the resistor voltage divider or the power supply to the operational amplifier U9, and enable the pull-up resistor through the upper chip to set the normal voltage of the inverting terminal of the operational amplifier U9 to be greater than the voltage of the resistor R13 and the anode connection terminal of the diode D3 when either the diode D3 or the diode D4 is biased. When starting, the pull-down resistor can be enabled to complete the first input or the resistor R16 and the resistor R15 are set to adjustable resistors, and started by sliding the knob. The upper chip is not shown in the attached drawings. 1_5 is a reset signal. When the sampling unit is controlled, in the second During regulation, a signal is input to 1_5, or during parallel control, a signal is input to 1_5 after the first round of regulation is completed, so that all sampling units re-enter the standby state. During standby, the previous 2_1 signal input parameters are maintained. The high-potential reference voltage set at the inverting terminal of the operational amplifier U7 and the operational amplifier U8 can be set by a power supply or a voltage divider. In addition to the rotary switch S1, the switch unit can also control the conduction of an independent relay switch through decoding. The connection method is to connect the relay switch coil corresponding to each sampling unit to the output terminal of the decoder respectively. According to the number of selected bits, the upper chip controls the coil to be attracted and turned on, and the current 1_1 signal is fed back to 2_1. The relay switch and decoder are not shown in the attached drawings.

[0025] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above and that the invention can be embodied in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered in all respects as illustrative and non-restrictive, and the scope of the invention is defined by the appended claims, not the foregoing description, and all variations within the meaning and range of equivalents of the claims are intended to be encompassed therein. Any reference in a claim should not be construed as limiting the claim to which it relates.

Claims

1. A small signal acquisition circuit applied to a power distribution monitoring terminal, characterized in that: The invention comprises a switch unit and a sampling unit, wherein the sampling unit has several units, and the sampling unit includes several operational amplifiers, several inverters, several transistors, several resistors, a gate, a trigger, and a capacitor. The operational amplifier U1 in the several operational amplifiers has its in-phase terminal connected to the 2_1 terminal, its inverting terminal connected to the in-phase terminal of the operational amplifier U5, one end of the resistor R1, one end of the resistor R2, and one end of the capacitor C1, and its output terminal connected to the input terminal of the inverter U2; the inverting terminal of the operational amplifier U5 is connected to the output terminal and the first input terminal of the multiplier U10; the second input terminal of the multiplier U10 is connected to the 1_2 terminal, and the output terminal is connected to the 1_3 terminal; the O0 pin of the gate U3 is connected to the transistor The base of Q2 and the O1 pin are connected to the base of the transistor Q1, the A0 pin is connected to the output of the inverter U4, the A1 pin is connected to the output of the inverter U2 and the input of the inverter U4, the SA pin is connected to the 1Q pin of the trigger U6, and the SB pin is connected to the 1Q inverse pin and the 1D pin of the trigger U6; the 1PR inverse pin, the 1CLR inverse pin of the trigger U6, and the collector of the transistor Q2 are connected to the power supply; the collector of the transistor Q1 is connected to the other end of the resistor R2; the emitter of the transistor Q2 is connected to the other end of the resistor R1; the emitter of the transistor Q1, the B0 pin and the B1 pin of the selector U3, and the other end of the capacitor C1 are grounded.

2. The small signal acquisition circuit for a power distribution monitoring terminal according to claim 1, characterized in that: The sampling unit also includes a plurality of operational amplifiers, a plurality of transistors, a plurality of diodes, and a plurality of resistors. The operational amplifier U7 among the plurality of operational amplifiers is connected to the emitter of the transistor Q3, one end of the resistor R3, one end of the resistor R4, and one end of the resistor R5 in the same phase, and is connected to the inverting end and I_5 end of the operational amplifier U8 in the opposite phase, and the output end is connected to the anode of the diode D2 and the other end of the resistor R5; the operational amplifier U8 is connected to the emitter of the transistor Q4, one end of the resistor R8, one end of the resistor R9, and one end of the resistor R10 in the same phase, and the output end is connected to the anode of the diode D1 and the other end of the resistor R10; the operational amplifier U9 is connected to the anode of the diode D3, the anode of the diode D4, one end of the resistor R13, One end of resistor R14, the 1_6 end, and the output end are connected to the 1CLK end and the 1_4 end of the trigger U6; the collector of transistor Q3, the collector of transistor Q4, the other end of resistor R3, the other end of resistor R8, and the other end of resistor R13 are connected to the power supply; the base of transistor Q3 is connected to the output end of inverter U4; the base of transistor Q4 is connected to the output end of inverter U2; the cathode of diode D1 is connected to the cathode of diode D3 and one end of resistor R11; the cathode of diode D2 is connected to the cathode of diode D4 and one end of resistor R12; the other end of resistor R4, the other end of resistor R9, the other end of resistor R11, the other end of resistor R12, and the other end of resistor R14 are grounded.

3. The small signal acquisition circuit for a power distribution monitoring terminal according to claim 1, characterized in that: One end of the resistor R16 among the plurality of resistors is connected to the power supply, and the other end is connected to the inverting end of the operational amplifier U9 and one end of the resistor R15; the other end of the resistor R15 is grounded.

4. The small signal acquisition circuit for a power distribution monitoring terminal according to claim 2, characterized in that: One end of the resistor R6 among the plurality of resistors is connected to one end of the resistor R7 and the terminal 1_5; the other end of the resistor R7 is connected to the power supply; and the other end of the resistor R6 is grounded.

5. The small signal acquisition circuit for a power distribution monitoring terminal according to claim 1, characterized in that: The switch unit includes a rotary switch, and the rotary switch is S1, a common terminal of which is connected to terminal 1_1, and a connection terminal of which is connected to terminal 2_1.

6. The small signal acquisition circuit for a power distribution monitoring terminal according to claim 1, characterized in that: The switch unit includes a plurality of relay switches and corresponding bit decoders. The coils in the plurality of relay switches are connected to the output terminals of the bit decoders, and the input control terminals of the decoders are connected to the upper chip.

7. The small signal acquisition circuit for a power distribution monitoring terminal according to claim 3, characterized in that: The resistor R16 and the resistor R15 are sliding resistors.

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