OTP balance protection circuit

Abstract

The invention provides an OTP balance protection circuit, and relates to the field of protection circuits, and the OTP balance protection circuit comprises a flyback topology main circuit, a VCC power supply circuit, an OTP protection pin control circuit, and an OTP balance control circuit. According to the invention, multi-device balance protection is realized through single-point detection, and the circuit complexity and cost are reduced; an OTP protection point is adjusted in a self-adaptive mode, and the reliability under different input voltage and load conditions is ensured; the problem of bridging primary and secondary insulation is avoided, and the design is simplified; the OTP function is closed during light load, so that the false triggering risk is reduced; the circuit not only can reliably protect under different input voltages, but also can reliably protect each power device under different load currents.

Description

Technical Field

[0001] The present application relates to the field of protection circuits, and in particular to an OTP balanced protection circuit. Background Art

[0002] In some low-voltage, high-current DC power supply fields, some loads will change dynamically over a large range, but the load will not continue to work at the highest power. In order to improve the cost-effectiveness and competitiveness of the product, the rated power of the power supply will be lower than the maximum power when the load changes dynamically. In order to improve the reliability of the power supply, it is necessary to install an OTP (over-temperature) protection function on the power supply to prevent it from continuing to work at the maximum power when the load is abnormal, causing damage to the power supply. For low-voltage, high-current power supplies, the input voltage is in the wide range of 100-240Vac. The components with the highest temperature on the power supply are usually: input bridge stack (DB1), MOS (Q1), and output diode (D1). When the input is 100Vac, the temperature of the bridge stack and MOS is very high, and the temperature of the output diode is moderate. When the output load continues to exceed When operating at over-rated current, the temperature of the bridge stack, MOS and output diode will rise sharply, among which the temperature rise of the bridge stack and MOS will be more obvious. It can be seen that OTP detection of the bridge stack or MOS is more appropriate; when the input is 240Vac, the temperature of the bridge stack and MOS is low, and the temperature of the output diode is moderate. However, if the output load continues to exceed the rated current, due to the low voltage and high current, the temperature of the diode will rise sharply, while the temperature rise of the bridge stack and MOS will not be obvious. At this time, if the OTP detects the bridge stack or MOS, the protection effect on the diode is not good. If the diode is detected, the protection effect on the bridge stack and MOS is not good at 100Vac input. In addition, the output diode is in the secondary side, and the OTP circuit must be connected across the primary and secondary sides, making it difficult to strengthen the insulation. Summary of the Invention

[0003] The purpose of the embodiments of the present application is to provide an OTP balancing protection circuit, which can solve the above-mentioned technical problems.

[0004] An embodiment of the present application provides an OTP balancing protection circuit, including a flyback topology main circuit, a VCC power supply circuit, an OTP protection pin control circuit, and an OTP balancing control circuit. The flyback topology main circuit is used to input a voltage of 100-240V; the VCC power supply circuit is used to transform the input voltage of the flyback topology main circuit and then supply power to the OTP protection pin control circuit and the OTP balancing control circuit; the OTP protection pin control circuit is used to monitor temperature or current to trigger a protection mechanism; the OTP balancing control circuit is used to collect current, convert it into a duty value, and dynamically adjust the OTP protection point to achieve balanced protection of the input bridge stack, MOS tube, and output diode under different input voltage and load conditions.

[0005] Preferably, the flyback topology main circuit includes a voltage stabilizing circuit, a rectifier bridge DB1, a processor U1 and a MOS tube Q1, the VCC power supply circuit includes a transformer T1, and the OTP protection pin control circuit includes a reference voltage source for comparing with the current waveform on the MOS tube Q1 to determine whether to trigger the OTP protection; the OTP balance control circuit includes a duty cycle signal processing unit, which collects the current signal of the MOS tube Q1 through a resistor R24, filters out high-frequency interference through an RC filter circuit, and then inputs the current signal into the non-inverting input terminal of the processor U3, compares it with the reference voltage of the inverting input terminal, and outputs a CS_PWM signal reflecting the duty cycle.

[0006] Preferably, the CS_PWM signal is smoothed into a DC voltage signal by an RC filter circuit and then isolated by the processor U3, with an output impedance lower than 50Ω, so as to eliminate interference of external circuits on the duty cycle signal.

[0007] Preferably, the DC voltage signal is weighted to Pin5 of the processor U3 through resistor R37 and compared with Pin6 of the processor U3 after voltage division by the NTC temperature sensor. When the voltage of Pin6 exceeds that of Pin5, the OTP protection action is triggered.

[0008] Preferably, the OTP balance control circuit includes a load judgment module, which is used to capture the peak voltage of the current signal of the MOS tube Q1 based on Pin3 of the processor U3, the diode and the capacitor C9, and set the load judgment benchmark through the voltage divider resistor R29 and the resistor R32. When the load is lower than 60% of the rated value, Pin1 outputs a low level to turn off the OTP function.

[0009] Preferably, the reference voltage of the load judgment module is dynamically coupled with the duty cycle signal (V1) through a resistor R28 to compensate for the influence of load fluctuation on judgment accuracy.

[0010] Preferably, the flyback topology main circuit adopts the OB2362A control chip, enters the continuous conduction mode (CCM) when the output current reaches 2-4A, and the duty cycle range covers 30%-50%.

[0011] Preferably, the VCC power supply circuit provides an independent power supply for the processor U1 and the OTP balance control circuit after rectification and filtering by the auxiliary winding of the transformer.

[0012] Beneficial effects of the present invention:

[0013] The present invention provides an OTP balancing protection circuit, comprising a flyback topology main circuit, a VCC power supply circuit, an OTP protection pin control circuit, and an OTP balancing control circuit. The present invention implements multi-device balanced protection through single-point detection, thereby reducing circuit complexity and cost. The OTP protection point is adaptively adjusted to ensure reliability under different input voltage and load conditions. The problem of bridging primary and secondary insulation is avoided, thereby simplifying the design. The OTP function is disabled under light load, thereby reducing the risk of false triggering. The circuit can reliably protect under different input voltages and can also reliably protect various power devices under different load currents. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0015] Figure 1 It is a circuit principle diagram of the present invention;

[0016] Figure 2 It is a framework diagram of the present invention;

[0017] Figure 3 This is a network node waveform diagram of the present invention. DETAILED DESCRIPTION

[0018] To make the objectives, technical solutions, and advantages of the embodiments of the present application more clear, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Generally, the components of the embodiments of the present application described and shown in the drawings herein can be arranged and designed in various different configurations.

[0019] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for protection, but merely represents selected embodiments of the present application. All other embodiments obtained by persons of ordinary skill in the art based on the embodiments in the present application without creative work are within the scope of protection of the present application.

[0020] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not require further definition or explanation in subsequent drawings.

[0021] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, or are the orientations or positional relationships in which the product of this application is typically placed when in use. These terms are intended only to facilitate the description of this application and simplify the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0022] Furthermore, terms such as "horizontal," "vertical," and "overhanging" do not necessarily imply that a component must be absolutely horizontal or overhanging, but rather that it can be slightly tilted. For example, "horizontal" simply means that its direction is more horizontal than "vertical," and does not mean that the structure must be completely horizontal, but rather that it can be slightly tilted.

[0023] It should also be noted that, in the description of this application, unless otherwise expressly specified or limited, the terms "disposed," "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; and they can refer to internal connections between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0024] like Figure 1-2 As shown, an embodiment of the present application provides an OTP balancing protection circuit, including a flyback topology main circuit, a VCC power supply circuit, an OTP protection pin control circuit and an OTP balancing control circuit. The flyback topology main circuit is used to input a voltage of 100-240V; the VCC power supply circuit is used to transform the input voltage of the flyback topology main circuit and then supply power to the OTP protection pin control circuit and the OTP balancing control circuit; the OTP protection pin control circuit is used to monitor temperature or current to trigger a protection mechanism; the OTP balancing control circuit is used to collect current, convert it into a duty value, and dynamically adjust the OTP protection point to achieve balanced protection of the input bridge stack, MOS tube and output diode under different input voltage and load conditions.

[0025] In this embodiment, the flyback topology main circuit includes a voltage stabilization circuit, a rectifier bridge DB1, a processor U1, and a MOS transistor Q1. The VCC power supply circuit includes a transformer T1. The OTP protection pin control circuit includes a reference voltage source for comparing with the current waveform on the MOS transistor Q1 to determine whether to trigger the OTP protection. The OTP balance control circuit includes a duty cycle signal processing unit. The duty cycle signal processing unit collects the current signal of the MOS transistor Q1 through a resistor R24, filters out high-frequency interference through an RC filter circuit, and then inputs the current signal into the non-inverting input terminal of the processor U3. The signal is compared with the reference voltage at the inverting input terminal and outputs a CS_PWM signal reflecting the duty cycle.

[0026] In this embodiment, the CS_PWM signal is smoothed into a DC voltage signal by the RC filter circuit and then isolated by the processor U3, with the output impedance being lower than 50Ω, so as to eliminate interference of the external circuit on the duty cycle signal.

[0027] In this embodiment, the DC voltage signal is weighted to Pin5 of the processor U3 through the resistor R37 and compared with Pin6 of the processor U3 after voltage division by the NTC temperature sensor. When the voltage of Pin6 exceeds that of Pin5, the OTP protection action is triggered.

[0028] In this embodiment, the OTP balancing control circuit includes a load judgment module. The load judgment module is used to capture the peak voltage of the current signal of the MOS tube Q1 based on Pin3 of the processor U3, the diode and the capacitor C9, and set the load judgment reference through the voltage divider resistor R29 and the resistor R32. When the load is lower than 60% of the rated value, Pin1 outputs a low level to turn off the OTP function.

[0029] In this embodiment, the reference voltage of the load judgment module is dynamically coupled to the duty cycle signal (V1) through the resistor R28 to compensate for the influence of load fluctuation on the judgment accuracy.

[0030] In this embodiment, the flyback topology main circuit adopts the OB2362A control chip, enters the continuous conduction mode (CCM) when the output current reaches 2-4A, and the duty cycle range covers 30%-50%.

[0031] In this embodiment, the VCC power supply circuit provides an independent power supply for the processor U1 and the OTP balance control circuit after rectification and filtering by the auxiliary winding of the transformer.

[0032] When the input voltage is 100Vac, the PWM duty cycle of MOS tube Q1 is about 50%. When the input voltage is 240Vac, the PWM duty cycle of MOS tube Q1 is about 30%. The current on MOS tube Q1 passes through resistor R24 and is converted into a voltage waveform. Then the voltage CS on resistor R24 is removed by resistor R33 and capacitor C11 to remove high-frequency spike interference and then connected to the non-inverting input terminal of Pin12 of processor U3. Pin13 of processor U3 obtains the reference voltage through resistor R31 and resistor R34. It is reasonable. By adjusting the reference voltage (between 0.01V and 0.1V), the duty cycle of the MOS tube Q1 can be restored to the greatest extent. When the output is above half load, the power supply enters the CCM mode. At this time, the duty cycle Don reflects the turn-on time of the MOS tube Q1, and Doff reflects the turn-on time of the secondary diode D1. The duty cycle of the output voltage waveform CS_PWM of Pin14 of the processor U3 restores Don and Doff. After being filtered by resistor R36 and capacitor C12, CS_PWM becomes a smooth DC voltage, which reflects the Don value.

[0033] The voltage of CS_PWM after RC filtering will cause the output impedance to be too large due to the large resistor R36, which is easily affected by other external circuits, resulting in distortion of the Don value. Here, it passes through the Pin10, Pin9, and Pin8 followers of the processor U3 to improve the output impedance so that the Don value is not affected by other circuits. The Pin8 output voltage V1 is weighted to Pin5 through the resistor R37, affecting the benchmark of Pin5. Pin6 is the collected voltage after the NTC temperature sensor and resistor R35 are connected in series and then divided by the resistor R42. When the temperature rises, the resistance of the NTC temperature sensor decreases, and the voltage of Pin6 When the voltage on Pin6 rises and exceeds that on Pin5, the output voltage on Pin7 changes from high to low, which will pull down the voltage on the RT pin of processor U1, causing processor U1 to enter the OTP protection state. When the input voltage becomes high voltage, the CS_PWM duty cycle decreases, and the V1 voltage drops. When the V1 voltage drops, after being weighted to Pin5 through resistor R37, the reference voltage of Pin5 drops, and the voltage on Pin6 is even lower, which can trigger OTP, thereby achieving the purpose of adjusting the OTP point to drop. Therefore, when the input voltage is high, the temperature of MOS tube Q1 is low, and the temperature of output diode D1 is high, reliable protection can still be achieved.

[0034] Pin3 of processor U3 captures the peak voltage on resistor R24 through a diode and capacitor C9, which is not affected by the duty cycle. The voltage peak value will be retained on capacitor C9. Pin2 is a reference obtained by dividing the voltage by resistors R29 and R32, which is used to judge the output load condition. V1 is weighted to Pin2 through capacitor R28 to compensate for the load judgment value, which can more accurately judge whether the output reaches more than 60% of the rated load. When the output load is lower than 60%, Pin1 outputs a low level, pulls down the Pin6 pin, and turns off the OTP function to avoid misjudgment of the OTP point due to duty cycle changes in light-load DCM.

[0035] The OTP detects the position of the MOS transistor Q1. At this time, it can reliably protect the bridge stack, MOS transistor Q1, and output diode at low input voltage. At high input voltage, it confirms the input voltage and load status by detecting the duty cycle of the MOS transistor Q1. After processing, the compensation is given to the OTP balance control circuit. Under high input voltage and heavy load conditions, the OTP protection point is adaptively lowered to protect the reliability of the output diode. This circuit can reliably protect various power devices under different input voltages and load currents.

[0036] like Figure 3 As shown, Pin12 of processor U3 is the non-inverting input terminal, which collects the voltage waveform of resistor R24. This waveform reflects the current waveform on MOS tube Q1, while Pin13 is the inverting input terminal, which collects the reference voltage. After comparison, Pin14 outputs CS_PWM. By reasonably adjusting the Pin13 reference voltage, the duty cycle state of MOS tube Q1 can be restored to the greatest extent; the CS_PWM voltage passes through resistor R36 and capacitor C12, and after RC filtering, it is sent to Pin10 non-inverting input terminal, and forms a follower with Pin9 and Pin8 to improve the output impedance. When it is weighted to Pin5 to adjust the OTP point, it will not be affected by the impedance voltage divider, and precise adjustment can be achieved.

[0037] The above are merely preferred embodiments of the present application and are not intended to limit the present application. Those skilled in the art will readily appreciate that various modifications and variations are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present application shall be included within the scope of protection of the present application.

Claims

1. An OTP balanced protection circuit, characterized in that: It includes a flyback topology main circuit, a VCC power supply circuit, an OTP protection pin control circuit and an OTP balance control circuit. The flyback topology main circuit is used to input a voltage of 100-240V; the VCC power supply circuit is used to transform the input voltage of the flyback topology main circuit and then supply power to the OTP protection pin control circuit and the OTP balance control circuit. The OTP protection pin control circuit is used to monitor temperature or current to trigger the protection mechanism; the OTP balance control circuit is used to collect current, convert it into a duty value, and dynamically adjust the OTP protection point to achieve balanced protection of the input bridge stack, MOS tube and output diode under different input voltage and load conditions.

2. An OTP balanced protection circuit according to claim 1, characterized in that: The flyback topology main circuit includes a voltage stabilization circuit, a rectifier bridge DB1, a processor U1, and a MOS transistor Q1. The VCC power supply circuit includes a transformer T1. The OTP protection pin control circuit includes a reference voltage source for comparing with the current waveform on the MOS transistor Q1 to determine whether to trigger the OTP protection. The OTP balance control circuit includes a duty cycle signal processing unit. The duty cycle signal processing unit collects the current signal of the MOS transistor Q1 through a resistor R24, filters out high-frequency interference through an RC filter circuit, and then inputs the current signal into the non-inverting input terminal of the processor U3. The signal is compared with the reference voltage at the inverting input terminal and outputs a CS_PWM signal reflecting the duty cycle.

3. An OTP balanced protection circuit according to claim 2, characterized in that: The CS_PWM signal is smoothed into a DC voltage signal by the RC filter circuit and then isolated by the processor U3. The output impedance is lower than 50Ω to eliminate interference of the external circuit on the duty cycle signal.

4. An OTP balanced protection circuit according to claim 3, characterized in that: The DC voltage signal is weighted to Pin5 of the processor U3 through the resistor R37 and compared with Pin6 of the processor U3 after voltage division by the NTC temperature sensor. When the voltage of Pin6 exceeds that of Pin5, the OTP protection action is triggered.

5. The OTP balanced protection circuit according to claim 1, wherein: The OTP balance control circuit includes a load judgment module, which is used to capture the peak voltage of the current signal of the MOS tube Q1 based on Pin3 of the processor U3, the diode and the capacitor C9, and set the load judgment benchmark through the voltage divider resistor R29 and the resistor R32. When the load is lower than 60% of the rated value, Pin1 outputs a low level to turn off the OTP function.

6. An OTP balancing protection circuit according to claim 5, characterized in that: The reference voltage of the load judgment module is dynamically coupled with the duty cycle signal (V1) through the resistor R28 to compensate for the influence of load fluctuation on judgment accuracy.

7. An OTP balanced protection circuit according to claim 1, characterized in that: The flyback topology main circuit adopts the OB2362A control chip, enters the continuous conduction mode (CCM) when the output current reaches 2-4A, and the duty cycle range covers 30%-50%.

8. The OTP balanced protection circuit according to claim 1, characterized in that: The VCC power supply circuit provides independent power supply for the processor U1 and the OTP balance control circuit after rectification and filtering by the auxiliary winding of the transformer.

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