Driving circuit of power transistor

Abstract

The invention discloses a driving circuit of a depletion mode power transistor, and relates to the field of power electronics, the driving circuit comprises a depletion mode power transistor, an enhanced power transistor, a first capacitor, a first diode and an under-voltage protection circuit; wherein the first end of the first capacitor is connected with the first end of the under-voltage protection circuit and receives an external PWM driving signal, and the second end of the first capacitor is connected with the second end of the under-voltage protection circuit, the first end of the first diode and the first end of the depletion type power transistor; the second end of the depletion type power transistor is connected to a first external circuit, the third end of the depletion type power transistor is connected with the first end of the enhancement type power transistor, and the second end of the enhancement type power transistor is connected with the third end of the under-voltage protection circuit; the fourth end of the under-voltage protection circuit, the second end of the first diode and the third end of the enhanced power transistor are connected with the driving ground, and the fourth end of the enhanced power transistor is connected to a second external circuit.

Description

Technical Field

[0001] The present application relates to the field of power electronics technology, and in particular to a driving circuit for a depletion-mode power transistor. Background Art

[0002] Power transistor devices, as core components of power conversion, are widely used in many fields such as computer power supplies, AI data center server power supplies, and TV power supplies. Among the many power transistor devices, depletion-mode power transistors have shown significant application advantages due to their lower on-resistance and greater current capacity.

[0003] Depletion-mode power transistors are normally on. Their practical applications typically utilize cascade packaging integration, combining a depletion-mode transistor with a low-voltage SiMOSFET to form a normally closed composite switching device. This composite switching device uses a high-frequency drive signal to control the on / off state of the low-voltage SiMOSFET, thereby controlling the on / off state of the depletion-mode power transistor.

[0004] However, in practical applications, cascade packaged power devices lack effective control and drive for depletion-mode power transistors. Due to the lack of such effective gate drive control, depletion-mode power transistors will produce steep voltage / current change rates during the switching process, which not only significantly increases the dynamic stress of the system but also leads to increased electromagnetic noise interference. Summary of the Invention

[0005] The purpose of this application is to provide a driving circuit for a depletion-mode power transistor.

[0006] To achieve the above objectives, this application provides the following solutions:

[0007] In a first aspect, the present application provides a driving circuit for a depletion-mode power transistor.

[0008] The driving circuit of the depletion-mode power transistor includes a depletion-mode power transistor, an enhancement-mode power transistor, a first capacitor, a first diode and an undervoltage protection circuit; wherein:

[0009] A first end of the first capacitor is connected to a first end of the undervoltage protection circuit and receives an external PWM drive signal, and a second end of the first capacitor is respectively connected to a second end of the undervoltage protection circuit, a first end of the first diode, and a first end of the depletion-mode power transistor;

[0010] The second terminal of the depletion-mode power transistor is connected to the first external circuit, the third terminal of the depletion-mode power transistor is connected to the first terminal of the enhancement-mode power transistor, and the second terminal of the enhancement-mode power transistor is connected to the third terminal of the undervoltage protection circuit;

[0011] The fourth terminal of the undervoltage protection circuit, the second terminal of the first diode, and the third terminal of the enhancement-mode power transistor are connected to a driving ground, and the fourth terminal of the enhancement-mode power transistor is connected to a second external circuit;

[0012] The undervoltage protection circuit is used to monitor the first voltage across the first capacitor. Based on the first voltage, the undervoltage protection circuit outputs an enable / disable signal to control the turning on and off of the enhancement-mode power transistor. When the enhancement-mode power transistor receives the Enable signal and turns on, the external PWM drive signal can control the turning on and off of the depletion-mode power transistor at a high frequency.

[0013] According to the specific embodiments provided in this application, this application discloses the following technical effects:

[0014] The present application provides a driving circuit for a depletion-mode power transistor. The present application monitors a first voltage across a first capacitor through an undervoltage protection circuit, and based on the detection result of the first voltage, sends an enable or disable signal to the enhancement-mode power transistor. When the enhancement-mode power transistor receives the enable signal and turns on, an external PWM drive signal can directly control the on and off of the depletion-mode power transistor at high frequency through the first capacitor, and adjust the on and off speeds of the depletion-mode power transistor through the switching speed adjustment circuit, effectively avoiding the cascade defect problem caused by the cascade method; at the same time, the disable signal sent by the undervoltage protection circuit avoids the risk of false turn-on due to insufficient voltage or energy of the first capacitor, ensuring the reliable turn-off of the depletion-mode power transistor; thereby, the external PWM drive signal can achieve direct, effective and reliable control (turning on and off) of the depletion-mode power transistor Q1. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0016] Figure 1 A schematic diagram of a driving circuit for a depletion-mode power transistor provided in one embodiment of the present application;

[0017] Figure 2 A schematic diagram of a driving circuit for a depletion-mode power transistor provided in another embodiment of the present application;

[0018] Figure 3A schematic diagram of a driving circuit for a depletion-mode power transistor provided in yet another embodiment of the present application;

[0019] Figure 4 A schematic diagram of a driving circuit for a depletion-mode power transistor provided in yet another embodiment of the present application;

[0020] Figure 5 A schematic diagram of a driving circuit for a depletion-mode power transistor provided in another embodiment of the present application;

[0021] Figure 6 A schematic diagram of a driving circuit for a depletion-mode power transistor provided in another embodiment of the present application;

[0022] Figure 7 A schematic diagram of a cascade packaged power device in the related art;

[0023] Figure 8 A schematic diagram of the parasitic inductance introduced by a cascade packaged power device in the related art.

[0024] Reference numerals:

[0025] Q1 - depletion mode power transistor;

[0026] Q2 - Enhancement mode power transistor;

[0027] Q3-first P-type transistor;

[0028] Q4-N type depletion mode transistor;

[0029] Q5-second P-type transistor;

[0030] Q6-first N-type transistor;

[0031] Q7 - the third P-type transistor;

[0032] Q8-second N-type transistor;

[0033] Q9 - first NPN transistor;

[0034] Q10 - second NPN transistor;

[0035] Q11 - third NPN transistor;

[0036] Q12 - first PNP transistor;

[0037] C1-first capacitor;

[0038] C2-second capacitor;

[0039] D1-first diode;

[0040] D2-second diode;

[0041] D3-the third diode;

[0042] D4-fourth diode;

[0043] D5-fifth diode;

[0044] D6-sixth diode;

[0045] Z1-first Zener diode;

[0046] Z2-second Zener diode;

[0047] Z3-the third Zener diode;

[0048] R1-first resistor;

[0049] R2-second resistor;

[0050] R3-the third resistor;

[0051] R4-fourth resistor;

[0052] R5-fifth resistor;

[0053] R6-sixth resistor;

[0054] R7-seventh resistor;

[0055] IC1-first reverse amplifier driver;

[0056] IC2 - Second inverting amplifier driver. DETAILED DESCRIPTION

[0057] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0058] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0059] In an exemplary embodiment, Figure 1 As shown, a driving circuit for a depletion-mode power transistor is provided, wherein the driving circuit for the depletion-mode power transistor includes a depletion-mode power transistor Q1, an enhancement-mode power transistor Q2, a first capacitor C1, a first diode D1 and an undervoltage protection circuit 11; wherein:

[0060] A first end of the first capacitor C1 is connected to a first end of the undervoltage protection circuit and receives an external PWM drive signal, and a second end of the first capacitor C1 is respectively connected to a second end of the undervoltage protection circuit, a first end of the first diode D1, and a first end of the depletion-mode power transistor Q1;

[0061] The second end of the depletion-mode power transistor Q1 is connected to the first external circuit, the third end of the depletion-mode power transistor Q1 is connected to the first end of the enhancement-mode power transistor Q2, and the second end of the enhancement-mode power transistor Q2 is connected to the third end of the undervoltage protection circuit;

[0062] The fourth terminal of the undervoltage protection circuit, the second terminal of the first diode D1, and the third terminal of the enhancement mode power transistor Q2 are connected to a driving ground, and the fourth terminal of the enhancement mode power transistor Q2 is connected to a second external circuit;

[0063] The undervoltage protection circuit is used to monitor the first voltage across the first capacitor. Based on the first voltage, the undervoltage protection circuit outputs an enable / disable signal to control the turning on and off of the enhancement-mode power transistor. When the enhancement-mode power transistor receives the Enable signal and turns on, the external PWM drive signal can control the turning on and off of the depletion-mode power transistor at a high frequency.

[0064] Among them, the PWM (Pulse Width Modulation) drive signal is a digital signal that controls power output by adjusting the pulse width (duty cycle) and is widely used in motor drive, power management and other fields; the undervoltage protection circuit (UVP) is mainly used to detect whether the power supply voltage is lower than the safety threshold, and cut off the circuit or trigger the protection mechanism when the voltage is too low to prevent equipment damage or abnormal operation. The first end of the depletion-mode power transistor Q1 is a gate, the second end is a drain, and the third end is a source. The depletion-mode power transistor Q1 can be a depletion-mode gallium nitride power transistor (D-mode GaN FET) or a silicon carbide junction field-effect power transistor (SiC JFET), and operates in a high-frequency switching state. The first end of the enhancement-mode power transistor Q2 is a drain, the second end is a gate, the third end is a Kelvin source, and the fourth end is a source. The Kelvin source is connected to the driving ground of the external PWM driving signal. The enhancement-mode power transistor Q2 can be a low-voltage N-channel metal-oxide-semiconductor field-effect power transistor (LV N-Channel Metal-Oxide-Semiconductor Field-Effect Power Transistor, LV N-Channel Metal-Oxide-Semiconductor Field-Effect Power Transistor). The first diode D1 may be a diode formed by an NPN transistor (Negative-Positive-Negative Bipolar Junction Transistor), and the first diode D1 may be directly replaced by a diode, wherein the first end of the first diode D1 is a positive electrode and the second end is a negative electrode.

[0065] In an embodiment of the present application, an undervoltage protection circuit monitors a first voltage across a first capacitor, and based on the first voltage detection result, sends an Enable or Disable signal to the enhancement-mode power transistor. When the enhancement-mode power transistor receives the Enable signal and turns on, an external PWM drive signal can directly control the on and off of the depletion-mode power transistor at high frequency through the first capacitor, and adjust the on and off speeds of the depletion-mode power transistor through the switching speed adjustment circuit, effectively avoiding the cascade defect problem caused by the cascade method; at the same time, the disable signal sent by the undervoltage protection circuit avoids the risk of false turn-on due to insufficient voltage or energy of the first capacitor, ensuring the reliable turn-off of the depletion-mode power transistor; thereby, the external PWM drive signal can directly, effectively and reliably control (turn on and off) the depletion-mode power transistor Q1.

[0066] In an exemplary embodiment, the first capacitor is configured to charge and store energy through the first diode when the external PWM drive signal is at a high level;

[0067] the undervoltage protection circuit is configured to monitor a first voltage across the first capacitor and, when detecting that the first voltage is greater than a first set value, output the enable signal to turn on the enhancement-mode power transistor; and when detecting that the first voltage is less than a second set value, output the disable signal to turn off the enhancement-mode power transistor, wherein both the first set value and the second set value are greater than an absolute value of a threshold voltage of the depletion-mode power transistor, and the second set value is not greater than the first set value;

[0068] The first diode is used for, when there is no external PWM drive signal, if an external voltage is applied between the drain of the depletion-mode power transistor and the source of the enhancement-mode power transistor, so that the drain voltage of the enhancement-mode power transistor rises and simultaneously reversely charges the gate-source capacitance of the depletion-mode power transistor and returns to the source of the enhancement-mode power transistor through the conduction of the first diode.

[0069] The first diode is used to, when the external PWM drive signal is present, if the PWM signal is at a high level, turn on when the gate voltage of the depletion-mode power transistor rises to the conduction threshold voltage of the first diode, and clamp the gate voltage of the depletion-mode power transistor; if the PWM signal is at a low level, a first voltage is reversely applied to both ends of the first diode, and the first diode is reversely cut off.

[0070] The capacitance of the first capacitor is at least N times the gate equivalent capacitance of the depletion-mode power transistor in the drive circuit, so that when the external PWM drive signal is at a low level, during the period when the first capacitor reversely charges the gate equivalent capacitance of the depletion-mode power transistor through the turned-on enhancement-mode power transistor, the first voltage is not lower than the absolute value of the threshold voltage of the depletion-mode power transistor, thereby causing the gate-source voltage of the depletion-mode power transistor to drop below the threshold voltage of the depletion-mode power transistor, thereby turning off the depletion-mode power transistor, and N is greater than or equal to 5.

[0071] The gate equivalent capacitance of the depletion-mode power transistor refers to the equivalent capacitance of all devices connected between the gate of the depletion-mode power transistor and the source of the enhancement-mode power transistor, including the gate capacitance of the depletion-mode power transistor, the junction capacitance of the first diode, and the like.

[0072] When the external PWM drive signal is at a high level, the external PWM drive signal flows through the first capacitor C1 and the first diode D1 in sequence to charge and store energy in the first capacitor C1. The undervoltage protection circuit is configured to monitor a first voltage across the first capacitor C1 and, upon detecting that the first voltage is greater than a first set value, output the Enable signal to turn on the enhancement-mode power transistor Q2, so that the external PWM drive signal directly controls the high-frequency switching state of the depletion-mode power transistor Q1 through the first capacitor. The undervoltage protection circuit outputs the Disable signal to turn off the enhancement-mode power transistor Q2 upon detecting that the first voltage is less than a second set value. Both the first set value and the second set value are greater than the absolute value of the threshold voltage of the depletion-mode power transistor Q1, and the second set value is not greater than the first set value.

[0073] In which, the first capacitor C1 is used to store energy to provide energy for the subsequent high-frequency shutdown of the depletion-mode power transistor Q1; the first voltage can be expressed as Vc1; when the external PWM drive signal is applied between the Gate pin and the KelvinSource pin, the external PWM drive signal will flow through the first capacitor C1 and the first diode D1, charging the first capacitor C1 and storing energy in the first capacitor C1.

[0074] Among them, the first set value can be expressed as Vx1, the second set value can be expressed as Vx2, the threshold voltage of the depletion-mode power transistor Q1 can be expressed as Vth, the absolute value of the threshold voltage can be expressed as |Vth| or -Vth, Vx1 and Vx2 are both greater than -Vth, Vx2 is less than or equal to Vx1, the enable signal can be expressed as an Enable signal, and the disable signal can be expressed as a Disable signal; if the first voltage Vc1 detected across the first capacitor C1 is greater than the first set value Vx1, the undervoltage protection circuit will send an Enable signal to turn on the enhancement-mode power transistor Q2, and if the first voltage Vc1 detected across the first capacitor C1 is less than the second set value Vx2, the undervoltage protection circuit will send a Disable signal to turn off the enhancement-mode power transistor Q2. After the enhancement-mode power transistor Q2 is turned on, the external PWM drive signal can control the depletion-mode power transistor Q1 at high frequency through the first capacitor; exemplarily, the first setting value Vx1 is 13 volts (unit: V), the second setting value Vx2 is 12V, the threshold voltage of the depletion-mode power transistor Q1 is -8V, and the absolute value of the threshold voltage of the depletion-mode power transistor Q1 is 8V.

[0075] The external PWM drive signal charges the first capacitor C1 and the gate equivalent capacitance of the depletion-mode power transistor Q1 to increase the gate-source voltage of the depletion-mode power transistor Q1. When the gate-source voltage of the depletion-mode power transistor Q1 rises to the conduction threshold voltage of the first diode D1, the first diode D1 is turned on and clamps the gate-source voltage of the depletion-mode power transistor Q1, so that the depletion-mode power transistor Q1 is fully turned on.

[0076] The gate equivalent capacitance of the depletion-mode power transistor Q1 can be expressed as Cg, the gate-source capacitance of the depletion-mode power transistor Q1 can be expressed as Cgs, and the turn-on threshold voltage of the first diode D1 can be expressed as VD1. Exemplarily, VD1 is 0.7V. When the external PWM drive signal is at a high level, the external PWM drive signal charges the first capacitor C1 and the gate equivalent capacitance Cg of the depletion-mode power transistor Q1. When the voltage of the gate-source capacitance Cgs of the depletion-mode power transistor Q1 rises to 0.7V, the first diode D1 is turned on, and the gate-source voltage across the gate and source of the depletion-mode power transistor Q1 is clamped to the turn-on voltage of the first diode D1, thereby fully turning on the depletion-mode power transistor Q1.

[0077] When the external PWM drive signal is at a low level, the first capacitor C1 reversely charges the gate capacitance of the depletion-mode power transistor Q1 through the turned-on enhancement-mode power transistor Q2, so as to pull down the gate-source voltage of the depletion-mode power transistor Q1 to a level lower than the threshold voltage Vth of the depletion-mode power transistor Q1, thereby turning off the depletion-mode power transistor Q1; the capacitance of the first capacitor C1 is at least N times the gate equivalent capacitance of the depletion-mode power transistor Q1, so that during the period of reverse charging the gate equivalent capacitance of the depletion-mode power transistor, the voltage of the first capacitor is not lower than the absolute value of the threshold voltage of the depletion-mode power transistor, for example, where N may be greater than or equal to 5.

[0078] Among them, when the external PWM drive signal is at a low level, the first capacitor C1 reversely charges the gate capacitance Cg of the depletion-mode power transistor Q1 (the enhancement-mode power transistor Q2 is constantly on), and the first voltage Vc1 across the first capacitor C1 can reach Vc11. Since Vc11 is greater than Vx1, and Vx1 is greater than -Vth, that is, Vc11 is greater than -Vth, since the first capacitor C1 reversely charges the gate equivalent capacitance Cg of the depletion-mode power transistor Q1, at this time, the voltage -Vc11 is applied across the gate-source of the depletion-mode power transistor Q1, -Vc11 Less than Vth; because the capacitance of the first capacitor C1 is much larger than the gate capacitance Cg of the depletion-mode power transistor Q1, the gate-source voltage across the gate of the depletion-mode power transistor Q1 is reversely charged to a voltage approximately equal to the voltage Vc11 across the first capacitor C1. Since Vc11 is greater than the absolute value of the threshold voltage of the depletion-mode power transistor Q1, the depletion-mode power transistor Q1 is turned off when the external PWM drive signal is low. For example, if VC11 is 15V, Vx1 is 13V, Vx1 is 12V, and Vth is -8V, then -VC11 is -15V and -Vth is 8V. When the depletion-mode power transistor Q1 is operating normally at high frequency, the enhancement-mode power transistor Q2 remains in a constant on state.

[0079] The first diode D1 and the enhancement-mode power transistor Q2 are used to effectively turn off the depletion-mode transistor Q1 before the voltage of the first capacitor C1 reaches a set value. When the enhancement-mode power transistor Q2 is enabled and turned on, the depletion-mode power transistor Q1 is turned off by the energy stored in the first capacitor C1. Therefore, the voltage Vc1 across the first capacitor C1 cannot be lower than the absolute value of the threshold voltage of the depletion-mode power transistor Q1 and the energy must be large enough. If Vc1 is lower than -Vth or the energy on the first capacitor C1 is insufficient, even if the enhancement-mode power transistor Q2 is in the on state, the depletion-mode power transistor Q1 cannot be turned off by the energy stored in the first capacitor C1. Shutdown is achieved by means of a PWM drive signal; based on the above situation, the undervoltage circuit becomes the key to ensuring reliable and normal operation of the circuit. Its main function is to promptly shut down the low-voltage enhancement-mode power transistor Q2 when the voltage on the first capacitor C1 is too low or the energy is insufficient, that is, when it is lower than the second set value Vx2, thereby shutting down the depletion-mode power transistor Q1 by shutting down the enhancement-mode power transistor Q2; and when the voltage or energy on the first capacitor C1 is normal, that is, higher than the first set value Vx1, the enhancement-mode power transistor Q2 is turned on, so that the external PWM drive signal can normally drive the depletion-mode power transistor Q1, thereby ensuring stable operation of the drive circuit.

[0080] The present application stores PWM high-level energy through a first capacitor. When the stored energy is large enough (the first voltage is greater than the first set value, and the capacitance of the first capacitor is large enough), the undervoltage protection circuit sends an enable signal to the enhancement-mode power transistor to turn on. The external PWM drive signal directly controls the high-frequency switch of the depletion-mode power transistor through the first capacitor. When the external PWM drive signal is low, the first capacitor reversely charges the gate capacitance of the depletion-mode power transistor through the turned-on enhancement-mode power transistor, forcibly lowering the gate voltage to below the threshold, ensuring the reliable shutdown of the depletion-mode power transistor. When the external PWM drive signal is high, the drive signal charges the first capacitor and the gate equivalent capacitance of the depletion-mode power transistor. During the charging process, the gate-source voltage of the depletion-mode power transistor gradually rises. When the gate-source voltage exceeds the threshold voltage, the depletion-mode power transistor begins to turn on. At this time, the gate-source voltage further rises until the first diode turns on, clamping the gate-source voltage at the turn-on voltage of the first diode. Thus, direct, effective and reliable control (turning on and off) of the depletion-mode transistor Q1 by the external PWM drive signal can be achieved, effectively avoiding the cascade defect problem caused by the cascade connection of the depletion-mode transistor.

[0081] In an exemplary embodiment, Figure 2As shown, the undervoltage protection circuit 11 includes a first P-type transistor Q3, an N-type depletion-type transistor Q4, a second diode D2, a third diode D3, a first Zener diode Z1, a second Zener diode Z2, a first resistor R1 and a second resistor R2; wherein:

[0082] The first end of the first capacitor C1 is commonly connected to the first end of the N-type depletion-mode transistor Q4, the first end of the first resistor R1 and the first end of the first P-type transistor Q3;

[0083] A first end of the first Zener diode Z1 is connected to the second end of the first capacitor C1, and a second end of the first Zener diode Z1 is commonly connected to the second end of the first P-type transistor Q3, the second end of the first resistor R1, and the second end of the N-type depletion transistor Q4;

[0084] The third end of the first P-type transistor Q3 is connected to the first end of the second diode D2, the second end of the second diode D2 is connected to the first end of the second Zener diode Z2, the second end of the second Zener diode Z2 is commonly connected to the first end of the third diode D3, the first end of the second resistor R2, and the second end of the enhancement-mode power transistor Q2, and the second end of the third diode D3 is connected to the third end of the N-type depletion-mode transistor Q4;

[0085] The second end of the second resistor R2 is connected to the driving ground;

[0086] The first P-type transistor is used to turn on when the first voltage is greater than a first set value, thereby sending the Enable signal to turn on the enhancement-mode power transistor; the N-type depletion-mode transistor is used to turn on when the first voltage is less than a second set value, and send the Disable signal to discharge the gate charge of the enhancement-mode power transistor, thereby disabling the enhancement-mode power transistor.

[0087] The second diode is used to prevent the gate charge of the enhancement mode power transistor from being discharged when the external PWM drive signal is at a low level;

[0088] The third diode is used to discharge the gate charge of the enhancement-mode power transistor through the third diode and the N-type depletion-mode transistor when the first voltage is less than the second set value, so as to turn off the enhancement-mode power transistor and prevent the gate of the enhancement-mode power transistor from being charged through the N-type depletion-mode transistor.

[0089] Among them, the first end of the first P-type transistor Q3 is the source, the second end is the gate, and the third end is the drain; the first end of the N-type depletion-mode transistor Q4 is the source, the second end is the gate, and the third end is the drain; the second diode D2 and the third diode D3 are both diodes formed by NPN transistors, by short-circuiting the collector and the base of the NPN transistor, at this time, the collector or the base is the positive electrode and the emitter is the negative electrode, the second diode D2 and the third diode D3 can also be directly replaced by diodes, the first end of the second diode D2 and the third diode D3 are both positive electrodes, and the second end are both negative electrodes; the first Zener diode Z1 and the second Zener diode Z2 are both clamping Zener diodes, the first end of the first Zener diode Z1 is the positive electrode and the second end is the negative electrode, the first end of the second Zener diode Z2 is the negative electrode and the second end is the positive electrode.

[0090] The first end of the undervoltage protection circuit corresponds to the first end of the first capacitor, the second end of the undervoltage protection circuit corresponds to the first end of the first Zener diode, the third end of the undervoltage protection circuit corresponds to the second end of the second Zener diode, and the fourth end of the undervoltage protection circuit corresponds to the second end of the second resistor.

[0091] In an exemplary embodiment, the undervoltage protection circuit is configured to turn off the N-type depletion transistor Q4 when detecting that the first voltage rises to a first difference between a nominal voltage of the first Zener diode Z1 and a threshold voltage of the N-type depletion transistor Q4, wherein the first difference is equal to the second set value;

[0092] In which, the nominal voltage of the first Zener diode Z1 can be expressed as Vz1, the threshold voltage of the N-type depletion-mode transistor Q4 can be expressed as Vth_Q4, and the first difference can be expressed as Vz1-Vth_Q4; when the external PWM drive signal is at a high level, the current charges the first capacitor C1 through the first diode D1 to store energy. Before the voltage Vc1 on the first capacitor C1 reaches a set value, the N-type depletion-mode transistor Q4 is in an on state, the first P-type transistor is in an off state, the gate-source voltage of the enhancement power transistor Q2 is 0, and the enhancement power transistor Q2 is in an off state; once the voltage Vc1 on the first capacitor C1 exceeds Vz1-Vth_Q4, the N-type depletion-mode transistor Q4 is turned off, and at this time the first P-type transistor Q3 is still not turned on.

[0093] When it is detected that the first voltage continues to rise to a second difference between the nominal voltage of the first Zener diode Z1 and the threshold voltage of the first P-type transistor Q3, turning on the first P-type transistor Q3 and outputting an enable signal to turn on the enhancement mode power transistor Q2, and the second difference is equal to the first set value;

[0094] Among them, the threshold voltage of the first P-type transistor Q3 can be expressed as Vth_Q3, and the second difference can be expressed as Vz1-Vth_Q3; once the voltage Vc1 on the first capacitor C1 exceeds Vz1-Vth_Q3, the first P-type transistor Q3 will be turned on and then send an enable signal to the enhancement mode power transistor Q3, thereby turning on the enhancement mode power transistor Q2.

[0095] The second diode D2 is used to prevent the gate charge of the enhancement mode power transistor Q2 from being discharged when the external PWM drive signal is at a low level;

[0096] Among them, thanks to the reverse cutoff characteristics of the second diode D2 and the fact that the N-type depletion-mode transistor Q4 is in the off state at this time, even if the input external PWM drive signal is in a low-level state, the voltage on the gate capacitor of the enhancement-mode power transistor Q2 can be maintained at a high level; and once the enhancement-mode power transistor Q2 is turned on, the input external PWM drive signal can control the on and off of the depletion-mode power transistor Q1.

[0097] When it is detected that the amplitude and / or energy of the external PWM drive signal is insufficient, causing the first voltage to drop to the second difference, the first P-type transistor Q3 is turned off; when it is detected that the amplitude and / or energy of the external PWM drive signal is insufficient, causing the first voltage to drop to the first difference, the N-type depletion-type transistor Q4 is turned back on; the gate charge of the enhancement-mode power transistor Q2 is discharged through the third diode D3 and the N-type depletion-mode transistor Q4, and the enhancement-mode power transistor Q2 is turned off.

[0098] If the energy and amplitude of the input PWM signal are too low, resulting in insufficient energy stored in the first capacitor C1, which in turn causes the first P-type transistor Q3 to turn off and the N-type depletion-mode transistor Q4 to turn on, the energy on the gate of the enhancement-mode power transistor Q2 will be discharged through the third diode D3 and the N-type depletion-mode transistor Q4 when the input PWM signal is at a low level, thereby causing the enhancement-mode power transistor Q2 to enter the off state, and the input external PWM drive signal will be unable to control the on and off of the depletion-mode power transistor Q1. It should be emphasized that the undervoltage protection circuit mentioned herein can adopt a variety of different circuit implementation forms, and these diverse implementation schemes are all included in the protection scope of this application.

[0099] In the embodiment of the present application, the undervoltage protection circuit turns off the enhancement-mode power transistor Q2 when the energy and amplitude of the input PWM signal are too low, which can effectively prevent the depletion-mode power transistor Q1 from failing due to the voltage on the first capacitor C1 being insufficient to turn off the depletion-mode power transistor Q1, thereby ensuring the stable operation of the drive circuit.

[0100] In an exemplary embodiment, Figure 3 As shown, the driving circuit further includes a switching speed regulating circuit 21, and the switching speed regulating circuit is used to regulate the turn-on speed and turn-off speed of the depletion-mode power transistor.

[0101] It should be noted that the switching speed regulation circuit may include a turn-on speed regulation circuit and a turn-off speed regulation circuit connected in parallel, wherein the turn-on speed regulation circuit is used to adjust the turn-on speed of the depletion-type power transistor Q1; and the turn-off speed regulation circuit is used to adjust the turn-off speed of the depletion-type power transistor Q1.

[0102] In an exemplary embodiment, Figure 4 As shown, the switching speed adjustment circuit 21 includes a third resistor R3, a fourth resistor R4 and a fourth diode D4;

[0103] A first end of the third resistor R3 is connected to a first end of the fourth resistor R4 and receives the external PWM drive signal, and a second end of the fourth resistor R4 is connected to a first end of the fourth diode D4;

[0104] The second end of the fourth diode D4 is commonly connected to the second end of the third resistor R3 and the first end of the undervoltage protection circuit.

[0105] The third resistor R3 is used to adjust the turn-on speed of the depletion-mode power transistor Q1;

[0106] The third resistor R3 forms a turn-on speed regulating circuit. Connecting the third resistor R3 in series in the gate drive path limits the charging current, thereby slowing down the turn-on speed of the depletion-mode power transistor Q1.

[0107] The fourth resistor R4 and the fourth diode D4 are used to adjust the turn-off speed of the depletion-mode power transistor Q1 .

[0108] The fourth resistor R4 and the fourth diode D4 form a turn-off speed adjustment circuit, wherein the first end of the fourth diode is a negative electrode and the second end is a positive electrode; the fourth resistor R4 is connected in series in the discharge path to limit the discharge current, thereby slowing down the turn-off speed of the depletion-mode power transistor Q1. When the depletion-mode power transistor Q1 is turned off, the fourth diode D4 is forward-conducted, allowing current to discharge through the fourth resistor R4 to adjust the turn-off speed of the depletion-mode power transistor Q1. When the depletion-mode power transistor Q1 is turned on, the fourth diode D4 is reverse-cut off to prevent the fourth resistor R4 from affecting the turn-on speed of the depletion-mode power transistor Q1, so that the turn-on speed of the depletion-mode power transistor Q1 is controlled only by the third resistor R3.

[0109] In the embodiment of the present application, the switch speed adjustment circuit can adjust the turn-on speed and turn-off speed of the depletion-type power transistor Q1, thereby alleviating the ringing and oscillation phenomena generated by the depletion-type power transistor Q1 when operating at high frequency.

[0110] In an exemplary embodiment, Figure 5 As shown, the driving circuit further includes a limit level conversion circuit 31;

[0111] The first end of the limiter level conversion circuit 31 is connected to the external DC power supply 32, the second end receives the external PWM drive signal, the third end is connected to the first end of the undervoltage protection circuit 11, and the fourth end is connected to the drive ground;

[0112] The amplitude limiting level conversion circuit 31 is used to perform amplitude adjustment and amplitude limiting protection on the external PWM drive signal, and enhance the driving capability of the external PWM drive signal.

[0113] The amplitude of the external DC power supply 32 may be a third amplitude, and when the amplitude of the external PWM drive signal is less than or equal to a preset amplitude threshold, the external PWM drive signal is converted into an output signal with the third amplitude and drive capability;

[0114] The third amplitude can be expressed as VDDH. When the amplitude of the input external PWM drive signal is low, the limit level conversion circuit can convert the input external PWM drive signal into an output signal with an amplitude of approximately VDDH and drive capability.

[0115] When the amplitude of the external PWM drive signal is greater than the preset amplitude threshold, the external PWM drive signal is limited and converted into an output signal with the amplitude of the third amplitude and drive capability.

[0116] When the amplitude of the input external PWM driving signal is too high, the amplitude limiting level conversion circuit 31 will first limit the amplitude of the input external PWM driving signal and then convert it into an output signal with an amplitude approximately equal to VDDH and having driving capability.

[0117] In the embodiment of the present application, regardless of the energy and amplitude of the input PWM drive signal, the first capacitor C1 receives a signal with an amplitude approximately equal to VDDH and capable of driving. This allows for sufficient energy storage, smooth completion of the high-frequency switching function, and effective system drive. This ensures that the drive circuit maintains normal operation when faced with input PWM drive signals of varying amplitudes, guaranteeing stable operation and reliable performance of the system. Even when the input PWM drive signal amplitude is relatively low, the system can operate normally, ensuring stable operation of the system under various conditions of the input external PWM drive signal.

[0118] In an exemplary embodiment, Figure 6 As shown, the amplitude limiting and level conversion circuit 31 includes an amplitude limiting and power supply circuit 311 and a level conversion circuit 312;

[0119] The level conversion circuit 312 includes a second P-type transistor Q5, a third P-type transistor Q7, a first N-type transistor Q6, a second N-type transistor Q8, a first reverse amplifier driver IC1 and a second reverse amplifier driver IC2;

[0120] The limiting and power supply circuit 311 includes a first NPN transistor Q9, a second NPN transistor Q10, a third NPN transistor Q11, a first PNP transistor Q12, a second capacitor C2, a fourth diode D4, a fifth diode D5, a sixth diode D6, a third Zener diode Z3, a fifth resistor R5, a sixth resistor R6 and a seventh resistor R7;

[0121] The first end of the second P-type transistor Q5 is connected to the power supply, the first end of the third P-type transistor Q7, the first end of the second reverse amplifier driver IC2, the first end of the seventh resistor R7, and the first end of the first NPN transistor Q9;

[0122] The second end of the second P-type transistor Q5 is commonly connected to the second end of the third P-type transistor Q7, the second end of the second reverse amplifier driver IC2, and the first end of the first N-type transistor Q6;

[0123] The third end of the second P-type transistor Q5 is commonly connected to the third end of the third P-type transistor Q7 and the first end of the second N-type transistor Q8; the second end of the second N-type transistor Q8 is connected to the first end of the first reverse amplifier driver IC1;

[0124] The second end of the first N-type transistor Q6 is commonly connected to the second end of the first reverse amplifier driver IC1, the first end of the third NPN transistor Q11, and the first end of the first PNP transistor Q12;

[0125] The second end of the third NPN transistor Q11 is commonly connected to the second end of the first PNP transistor Q12, the first end of the sixth resistor R6, and the first end of the sixth diode D6;

[0126] The second end of the sixth resistor R6 receives the external PWM drive signal and is commonly connected to the second end of the sixth diode D6, the first end of the fifth resistor R5, and the first end of the second NPN transistor Q10;

[0127] The second end of the fifth resistor R5 is commonly connected to the second end of the second NPN transistor Q10 and the first end of the fourth diode D4, and the second end of the fourth diode D4 is connected to the first end of the fifth diode D5;

[0128] The second end of the fifth diode D5 is commonly connected to the first end of the third Zener diode Z3, the second end of the first NPN transistor Q9, and the second end of the seventh resistor R7;

[0129] The third terminal of the first NPN transistor Q9 is commonly connected to the third terminal of the second NPN transistor Q10, the first terminal of the second capacitor C2, the third terminal of the third NPN transistor Q11, and the third terminal of the first reverse amplifier driver IC1;

[0130] The second end of the third Zener diode Z3, the second end of the second capacitor C2, the third end of the first PNP transistor Q12, the fourth end of the first reverse amplifier driver IC1, the third end of the first N-type transistor Q6, the third end of the second N-type transistor Q8, and the third end of the second reverse amplifier driver IC2 are commonly connected to the driving ground;

[0131] The fourth terminal of the second inverting amplifier driver IC2 is connected to the first terminal of the undervoltage protection circuit.

[0132] The first end of the second P-type transistor Q5 is a source, the second end is a drain, and the third end is a gate; the first end of the third P-type transistor Q7 is a source, the second end is a gate, and the third end is a drain; the first end of the first N-type transistor Q6 is a drain, the second end is a gate, and the third end is a source; the first end of the second N-type transistor Q8 is a drain, the second end is a gate, and the third end is a source;

[0133] The first end of the first NPN transistor Q9 is a collector, the second end is a base, and the third end is an emitter; the first end of the second NPN transistor Q10 is a collector, the second end is a base, and the third end is an emitter; the first end of the third NPN transistor Q11 is an emitter, the second end is a base, and the third end is a collector; the first end of the first PNP transistor (Positive-Negative-Positive Bipolar Junction Transistor) Q12 is an emitter, the second end is a base, and the third end is a collector; the first end of the fourth diode D4, the fifth diode D5, and the sixth diode D6 are positive electrodes and negative electrodes; the first end of the third Zener diode Z3 is negative electrodes and positive electrodes.

[0134] The first end of the limiting conversion circuit corresponds to the first end of the second P-type transistor, the second end of the limiting conversion circuit corresponds to the second end of the sixth resistor, the third end of the limiting conversion circuit corresponds to the fourth end of the second reverse amplifier driver, and the fourth end of the limiting conversion circuit corresponds to the second end of the third Zener diode.

[0135] In an exemplary embodiment, the fourth diode D4, the fifth diode D5, and the third Zener diode Z3 clamp the output voltages of the first NPN transistor Q9 and the second NPN transistor Q10, so that the voltage on the second capacitor C2 is a low-voltage power supply;

[0136] The energy stored in the second capacitor C2 is used to power the first reverse amplifier driver IC1, and also to power the driving circuit composed of the third NPN transistor Q11 and the first PNP transistor Q12;

[0137] The level conversion circuit is used to convert the external PWM driving signal of a first amplitude received by the first reverse amplifier driver IC1 into an external PWM driving signal of a second amplitude with driving capability output by the second reverse amplifier driver IC2, wherein the first amplitude is smaller than the second amplitude;

[0138] The fifth resistor R5, the sixth resistor R6, and the seventh resistor R7 are current-limiting resistors, and the sixth diode D6 is used to accelerate a turn-off speed.

[0139] Wherein, the first amplitude is low amplitude, and the second amplitude is high amplitude. The level conversion circuit can convert the low amplitude external PWM drive signal received by the first reverse amplifier driver IC1 into a high amplitude external PWM drive signal with driving capability output by the second reverse amplifier driver IC2; the first NPN transistor Q9 takes power from the external power supply VDDH to charge and store energy for the second capacitor C2, and controls and clamps the output of the first NPN transistor Q9 through the third Zener diode Z3; the second NPN transistor Q10 takes power from the input external PWM drive signal to charge and store energy for the second capacitor C2, and controls and clamps the output of the first NPN transistor Q9 through the fourth ...10 through the fourth diode Z3; the second NPN transistor Q10 takes power from the input external PWM drive signal to charge and store energy for the second capacitor C2, and controls and clamps the output of the first NPN transistor Q10 through the fourth diode Z3; the second NPN transistor Q10 takes power from the input external PWM drive signal to charge and store energy for the second capacitor C2 D4, the fifth diode D5, and the third Zener diode Z3 limit and control the output of the second NPN transistor Q10 and clamp it. The energy stored in the second capacitor C2 is used to power the first reverse amplifier driver IC1, and also to power the drive circuit composed of the third NPN transistor Q11 and the first PNP transistor Q12. Since the third NPN transistor Q11 and the first PNP transistor Q12 are powered by the low-amplitude voltage stored on the second capacitor C2, the first reverse amplifier driver IC1 receives a low-amplitude level signal from the drive circuit composed of the third NPN transistor Q11 and the first PNP transistor Q12.

[0140] Because the supply voltage of the first reverse amplifier driver IC1, the third NPN transistor Q11, and the first PNP transistor Q12 is limited to a low amplitude, even if the input PWM signal amplitude is too large, after passing through the sixth resistor R6, the third NPN transistor Q11, and the first PNP transistor Q12, the first reverse amplifier driver IC1 receives a limited low-amplitude PWM signal. The fifth resistor R5, the sixth resistor R6, and the seventh resistor R7 are current-limiting resistors, and the sixth diode D6 is used to accelerate the shutdown speed.

[0141] In an exemplary embodiment, the output clamping voltage of the second NPN transistor Q10 is higher than the output clamping voltage of the first NPN transistor Q9.

[0142] In the embodiment of the present application, to reduce losses, the output clamping voltage of the second NPN transistor Q10 is higher than the output of the first NPN transistor Q9. In this way, the first NPN transistor Q9 charges the second capacitor C2 through the power supply only when the input external PWM drive signal cannot meet the energy demand of the second capacitor C2. Otherwise, only the second NPN transistor Q10 works, thereby avoiding excessive losses in the first NPN transistor Q9 due to excessively high VDDH amplitude.

[0143] It should be noted that all P-type transistors in the above embodiments can be replaced by PNP transistors, such as the first P-type transistor Q3, the second P-type transistor Q5, and the third P-type transistor Q7 can all be replaced by PNP transistors; all N-type transistors can be replaced by NPN transistors, such as the first N-type transistor Q6 and the second N-type transistor Q8 can all be replaced by NPN transistors; similarly, PNP transistors can be replaced by P-type transistors, and NPN transistors can be replaced by N-type transistors; when replacing transistors, corresponding adjustments to the drive circuit can be made as needed, such as increasing the drive resistance, adjusting the bias, etc.

[0144] In related technologies, such as Figure 7 As shown, the depletion-mode transistor (D-MODE transistor) is a normally-on type. In practical applications, a cascade package integration method is usually adopted, that is, the depletion-mode transistor 41 is cascade-packaged with a low-voltage Si MOSFET (Low-Voltage Silicon Metal-Oxide-Semiconductor Field-Effect Transistor, silicon-based metal-oxide semiconductor field-effect transistor) 42 to form a normally-off composite switching device (also known as a cascade package power device); this composite switching device controls the switching of the low-voltage SiMOSFET through a high-frequency driving signal, thereby realizing the control of the switching state of the depletion-mode transistor.

[0145] There are several technical defects in the actual application of cascade packaged power devices (the so-called cascade defects):

[0146] First, the gate drive control mechanism of the depletion-mode transistors within the cascade has inherent flaws. Due to the lack of effective control drive for the depletion-mode transistors, their gates are in a quasi-uncontrolled state. This transient state significantly degrades the system's electromagnetic compatibility (EMI) characteristics, manifesting as an abnormal increase in the high-frequency components of the conducted interference spectrum and excessive radiated interference intensity.

[0147] Second, the cascaded package interconnect structure introduces parasitic parameter coupling. Bonding wires exhibit significant parasitic inductance effects (typically around 3 nanohenries (unit: nH)) under high-frequency conditions. Figure 8 The structure shown (L1 to L6 are all parasitic inductances introduced by the bonding wires during package interconnection). This parasitic parameter causes strong coupling between the two key circuits of the depletion-mode transistor: the drive loop and the main power loop form a common-mode interference path. During the device shutdown transient, the induced electromotive force (L·di / dt) generated by the parasitic inductance directly acts between the gate and source of the depletion-mode transistor, causing the gate potential to abnormally rise above the threshold voltage, thereby triggering false turn-on. Here, L is the parasitic inductance and di / dt is the rate of change of current. This phenomenon is more likely to occur during low-voltage DS (Drain-Source) switching. At low DS voltages, the drive voltage of the upper depletion-mode transistor is lower, closer to the threshold voltage, and therefore more susceptible to the aforementioned interference, which in turn seriously limits system reliability.

[0148] Third, driving cascade depletion-mode devices essentially involves driving the internal cascade low-voltage Silicon MOSFET first, and then driving the depletion-mode transistor. Therefore, there is a lag in the cascade depletion-mode driving process, and there is also an overall reverse recovery charge. These factors will affect and limit higher-frequency applications and application scenarios, resulting in the depletion-mode transistor being unable to fully exert its performance advantages in the cascade architecture.

[0149] The embodiment of the present application directly drives the depletion-mode power transistor Q1 through an external PWM drive signal, and can adjust the switching speed with the help of the external circuit impedance, effectively avoiding the depletion-mode transistor gate being in a quasi-uncontrolled state, thereby significantly improving the electromagnetic compatibility (EMI) characteristics of the system.

[0150] In the embodiment of the present application, the low-voltage enhancement mode transistor (ie, enhancement mode power transistor) Q2 is in the Normal ON state during the high-frequency switching process. Therefore, in this process, the low-voltage enhancement mode transistor Q2 does not suffer from reverse recovery loss.

[0151] In the embodiment of the present application, the turn-off voltage of the depletion-mode power transistor Q1 relies on the energy on the first capacitor C1 to achieve turn-off. Due to the relatively large capacitance of the first capacitor C1, the voltage across the first capacitor C1 remains substantially constant. When the depletion-mode power transistor Q1 is turned off, changes in the DS voltage do not cause changes in the voltage across the first capacitor C1. In other words, the gate-source voltage of the depletion-mode power transistor Q1 does not change with changes in the DS voltage, thus providing strong anti-interference capabilities.

[0152] The level UVP (undervoltage protection) circuit proposed in the embodiment of the present application is a key circuit to ensure the reliable and normal operation of the depletion-mode transistor Q1, and can effectively avoid system failure caused by the external PWM drive signal level being too low; at the same time, the universal driving scheme for driving the depletion-mode transistor proposed in the embodiment of the present application can ensure the normal and stable operation of the system regardless of the input PWM level amplitude.

[0153] It should be noted that the principles described in the embodiments of the present application can be directly applied to application scenarios such as switching power supplies and electric drives, and can also be integrated into power IC devices using the principles described in the embodiments of the application; for example, using Figure 1 Figure 2 The principle of the embodiment described above can be integrated into a 4-pin integrated power chip, whose pin definition is compatible with mainstream power Silicon power transistors / power GaN transistors / power SiC transistor products on the market.

[0154] use Figure 5 The principles of the embodiments described above can be integrated into a 5-pin integrated power device. It is even possible to deeply integrate the principles of the embodiments disclosed in this application with a control IC that generates PWM to construct an integrated power control integrated IC.

[0155] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0156] This document uses specific examples to illustrate the principles and implementation methods of this application. The description of the above examples is only intended to help understand the method and core concept of this application. At the same time, for those skilled in the art, based on the concept of this application, there may be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting this application.

Claims

1. A driving circuit for a depletion-mode power transistor, characterized in that: The driving circuit of the depletion-mode power transistor includes a depletion-mode power transistor, an enhancement-mode power transistor, a first capacitor, a first diode and an undervoltage protection circuit; wherein: A first end of the first capacitor is connected to a first end of the undervoltage protection circuit and receives an external PWM drive signal, and a second end of the first capacitor is respectively connected to a second end of the undervoltage protection circuit, a first end of the first diode, and a first end of the depletion-mode power transistor; The second terminal of the depletion-mode power transistor is connected to the first external circuit, the third terminal of the depletion-mode power transistor is connected to the first terminal of the enhancement-mode power transistor, and the second terminal of the enhancement-mode power transistor is connected to the third terminal of the undervoltage protection circuit; The fourth terminal of the undervoltage protection circuit, the second terminal of the first diode, and the third terminal of the enhancement-mode power transistor are connected to a driving ground, and the fourth terminal of the enhancement-mode power transistor is connected to a second external circuit; The undervoltage protection circuit is used to monitor the first voltage across the first capacitor. Based on the first voltage, the undervoltage protection circuit outputs an enable / disable signal to control the turning on and off of the enhancement-mode power transistor. When the enhancement-mode power transistor receives the Enable signal and turns on, the external PWM drive signal can control the turning on and off of the depletion-mode power transistor at a high frequency.

2. The driving circuit of the depletion-mode power transistor according to claim 1, wherein: The first capacitor is configured to be charged and stored via the first diode when the external PWM drive signal is at a high level; the undervoltage protection circuit is configured to output the Enable signal to turn on the enhancement-mode power transistor when detecting that the first voltage is greater than a first set value, and output the Disable signal to turn off the enhancement-mode power transistor when the first voltage is less than a second set value, wherein both the first set value and the second set value are greater than the absolute value of the threshold voltage of the depletion-mode power transistor, and the second set value is not greater than the first set value; The first diode is used for, when there is no external PWM drive signal, if an external voltage is applied between the drain of the depletion-mode power transistor and the source of the enhancement-mode power transistor, so that the drain voltage of the enhancement-mode power transistor rises and simultaneously reversely charges the gate-source capacitance of the depletion-mode power transistor and returns to the source of the enhancement-mode power transistor through the conduction of the first diode. The first diode is used to, when the external PWM drive signal is present, if the PWM signal is at a high level, turn on when the gate voltage of the depletion-mode power transistor rises to the conduction threshold voltage of the first diode, and clamp the gate voltage of the depletion-mode power transistor; if the PWM signal is at a low level, the first voltage is reversely applied to both ends of the first diode, and the first diode is reversely cut off. The capacitance of the first capacitor is at least N times the gate equivalent capacitance of the depletion-mode power transistor in the drive circuit, so that when the external PWM drive signal is at a low level, during the period when the first capacitor reversely charges the gate equivalent capacitance of the depletion-mode power transistor through the turned-on enhancement-mode power transistor, the first voltage is not lower than the absolute value of the threshold voltage of the depletion-mode power transistor, thereby causing the gate-source voltage of the depletion-mode power transistor to drop below the threshold voltage of the depletion-mode power transistor, thereby turning off the depletion-mode power transistor, and N is greater than or equal to 5.

3. The driving circuit of the depletion-mode power transistor according to claim 1, wherein: The undervoltage protection circuit includes a first P-type transistor, an N-type depletion-type transistor, a second diode, a third diode, a first Zener diode, a second Zener diode, a first resistor, and a second resistor; wherein: The first end of the first capacitor is commonly connected to the first end of the N-type depletion-mode transistor, the first end of the first resistor, and the first end of the first P-type transistor; A first end of the first Zener diode is connected to the second end of the first capacitor, and a second end of the first Zener diode is commonly connected to the second end of the first P-type transistor, the second end of the first resistor, and the second end of the N-type depletion-mode transistor; The third end of the first P-type transistor is connected to the first end of the second diode, the second end of the second diode is connected to the first end of the second Zener diode, the second end of the second Zener diode is commonly connected to the first end of the third diode, the first end of the second resistor, and the second end of the enhancement-mode power transistor, and the second end of the third diode is connected to the third end of the N-type depletion-mode transistor; The second terminal of the second resistor is connected to the driving ground; The first P-type transistor is used to turn on when the first voltage is greater than a first set value, thereby sending the Enable signal to turn on the enhancement-mode power transistor; the N-type depletion-mode transistor is used to turn on when the first voltage is less than a second set value, and send the Disable signal to discharge the gate charge of the enhancement-mode power transistor, thereby disabling the enhancement-mode power transistor. The second diode is used to prevent the gate charge of the enhancement mode power transistor from being discharged when the external PWM drive signal is at a low level; The third diode is used to discharge the gate charge of the enhancement-mode power transistor through the third diode and the N-type depletion-mode transistor when the first voltage is less than the second set value, so as to turn off the enhancement-mode power transistor and prevent the gate of the enhancement-mode power transistor from being charged through the N-type depletion-mode transistor.

4. The driving circuit of the depletion-mode power transistor according to claim 1, wherein: The driving circuit further includes a switching speed regulating circuit, and the switching speed regulating circuit is used to regulate the turn-on speed and turn-off speed of the depletion-mode power transistor.

5. The driving circuit of the depletion-mode power transistor according to claim 4, wherein: The switching speed adjustment circuit includes a third resistor, a fourth resistor and a fourth diode; The first end of the third resistor is connected to the first end of the fourth resistor and receives the external PWM drive signal, and the second end of the fourth resistor is connected to the first end of the fourth diode; The second end of the fourth diode is commonly connected to the second end of the third resistor and the first end of the undervoltage protection circuit; The third resistor is used to adjust the turn-on speed of the depletion-mode power transistor; The fourth resistor and the fourth diode are used to adjust the turn-off speed of the depletion-mode power transistor.

6. The driving circuit of the depletion-mode power transistor according to claim 1, wherein: The driving circuit further includes a limit level conversion circuit; The first end of the limiter level conversion circuit is connected to the external DC power supply, the second end receives the external PWM drive signal, the third end is connected to the first end of the undervoltage protection circuit, and the fourth end is connected to the drive ground; The amplitude limiting level conversion circuit is used to perform amplitude adjustment and amplitude limiting protection on the external PWM drive signal, and enhance the driving capability of the external PWM drive signal.

7. The driving circuit of the depletion-mode power transistor according to claim 6, wherein: The amplitude limiting and level conversion circuit includes an amplitude limiting and power supply circuit, and a level conversion circuit; The level conversion circuit includes a second P-type transistor, a third P-type transistor, a first N-type transistor, a second N-type transistor, a first reverse amplifier driver, and a second reverse amplifier driver; The limiting and power supply circuit includes a first NPN transistor, a second NPN transistor, a third NPN transistor, a first PNP transistor, a second capacitor, a fourth diode, a fifth diode, a sixth diode, a third Zener diode, a fifth resistor, a sixth resistor and a seventh resistor; The first end of the second P-type transistor is connected to the external power supply, the first end of the third P-type transistor, the first end of the second reverse amplifier driver, the first end of the seventh resistor, and the first end of the first NPN transistor; The second end of the second P-type transistor is commonly connected to the second end of the third P-type transistor, the second end of the second reverse amplifier driver, and the first end of the first N-type transistor; The third terminal of the second P-type transistor is commonly connected to the third terminal of the third P-type transistor and the first terminal of the second N-type transistor; the second terminal of the second N-type transistor is connected to the first terminal of the first reverse amplifier driver; The second end of the first N-type transistor is commonly connected to the second end of the first reverse amplifier driver, the first end of the third NPN transistor, and the first end of the first PNP transistor; The second end of the third NPN transistor is commonly connected to the second end of the first PNP transistor, the first end of the sixth resistor, and the first end of the sixth diode; The second end of the sixth resistor receives the external PWM drive signal and is commonly connected to the second end of the sixth diode, the first end of the fifth resistor, and the first end of the second NPN transistor; The second end of the fifth resistor is commonly connected to the second end of the second NPN transistor and the first end of the fourth diode, and the second end of the fourth diode is connected to the first end of the fifth diode; The second end of the fifth diode is commonly connected to the first end of the third Zener diode, the second end of the first NPN transistor, and the second end of the seventh resistor; The third terminal of the first NPN transistor is commonly connected to the third terminal of the second NPN transistor, the first terminal of the second capacitor, the third terminal of the third NPN transistor, and the third terminal of the first inverting amplifier driver; The second end of the third Zener diode, the second end of the second capacitor, the third end of the first PNP transistor, the fourth end of the first reverse amplifier driver, the third end of the first N-type transistor, the third end of the second N-type transistor, and the third end of the second reverse amplifier driver are commonly connected to a driving ground; The fourth terminal of the second inverting amplifier driver is connected to the first terminal of the undervoltage protection circuit.

8. The driving circuit of the depletion-mode power transistor according to claim 7, wherein: The fourth diode, the fifth diode and the third Zener diode are used to clamp the output voltages of the first NPN transistor and the second NPN transistor so that the voltage on the second capacitor is a low-voltage power supply; The energy stored in the second capacitor is used to power the first reverse amplifier driver, and also to power the driving circuit composed of the third NPN transistor and the first PNP transistor; The level conversion circuit is used to convert the external PWM driving signal of a first amplitude received by the first inverting amplifier driver into an external PWM driving signal of a second amplitude with driving capability output by the second inverting amplifier driver, wherein the first amplitude is smaller than the second amplitude; The fifth resistor, the sixth resistor, and the seventh resistor are current-limiting resistors, and the sixth diode is used to speed up the shutdown speed.

9. The driving circuit of the depletion-mode power transistor according to claim 7, wherein: An output clamping voltage of the second NPN transistor is higher than an output clamping voltage of the first NPN transistor.

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