A drive circuit for a power transistor

Abstract

The application discloses a driving circuit of a depletion mode power transistor, and relates to the field of power electronics.The driving circuit comprises a depletion mode power transistor, an enhancement mode power transistor, a first capacitor, a first diode and an under-voltage protection circuit; wherein: a first end of the first capacitor is connected to a first end of the under-voltage protection circuit and receives an external PWM driving signal; a second end of the first capacitor is connected to a second end of the under-voltage protection circuit, a first end of the first diode and a first end of the depletion mode power transistor; a second end of the depletion mode power transistor is connected to a first external circuit; a third end of the depletion mode power transistor is connected to a first end of the enhancement mode power transistor; a second end of the enhancement mode power transistor is connected to a third end of the under-voltage protection circuit; a fourth end of the under-voltage protection circuit, a second end of the first diode and a third end of the enhancement mode power transistor are connected to a driving ground; and a fourth end of the enhancement mode power transistor is connected to a second external circuit.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of power electronics, in particular to a driving circuit of a depletion-mode power transistor. BACKGROUND

[0002] As a core component of power conversion, power transistor devices are widely used in computer power supply, AI data center server power supply, television power supply and many other fields. Among many power transistor devices, depletion-mode power transistors have significant application advantages due to their lower on-resistance and greater current capacity.

[0003] The depletion-mode power transistor is normally open, and its actual application usually adopts a cascaded packaging integrated manner, that is, a depletion-mode transistor is cascaded and packaged with a low-voltage SiMOSFET to form a normally closed composite switching device. This composite switching device controls the switching of the low-voltage SiMOSFET through a high-frequency driving signal, thereby realizing the control of the switching state of the depletion-mode power transistor.

[0004] However, the cascaded packaging power device lacks effective control and driving of the depletion-mode power transistor in actual application. Due to the lack of such effective gate driving control, the depletion-mode power transistor will produce a steep voltage / current change rate during switching, which not only significantly increases the system dynamic stress, but also causes the intensification of electromagnetic noise interference. SUMMARY

[0005] The purpose of the present application is to provide a driving circuit of a depletion-mode power transistor.

[0006] To achieve the above purpose, the present application provides the following solutions:

[0007] In a first aspect, the present application provides a driving circuit of a depletion-mode power transistor,

[0008] The driving circuit of the depletion-mode power transistor includes a depletion-mode power transistor, an enhancement-mode power transistor, a first capacitor, a first diode and an under-voltage protection circuit; wherein:

[0009] The first end of the first capacitor is connected to the first end of the under-voltage protection circuit and receives an external PWM driving signal, and the second end of the first capacitor is respectively connected to the second end of the under-voltage protection circuit, the first end of the first diode and the first end of the depletion-mode power transistor in common;

[0010] The second end of the depletion-mode power transistor is connected to a first external circuit, the third end of the depletion-mode power transistor is connected to the first end of the enhancement-mode power transistor, and the second end of the enhancement-mode power transistor is connected to the third end of the under-voltage protection circuit.

[0011] a fourth terminal of the under-voltage protection circuit, a second terminal of the first diode, and a third terminal of the enhancement-mode power transistor are connected to a driving ground, and a fourth terminal of the enhancement-mode power transistor is connected to a second external circuit;

[0012] The under-voltage protection circuit is configured to monitor a first voltage across the first capacitor, and based on the first voltage, the under-voltage protection circuit outputs an enable / disable signal to control the turn-on and turn-off of the enhancement-mode power transistor. After the enhancement-mode power transistor receives the enable signal to turn on, the external PWM driving signal can control the turn-on and turn-off of the depletion-mode power transistor at a high frequency.

[0013] According to the specific embodiments provided in the present application, the following technical effects are disclosed:

[0014] The present application provides a driving circuit of a depletion-mode power transistor. The under-voltage protection circuit monitors a first voltage across the first capacitor, and based on the detection result of the first voltage, the under-voltage protection circuit outputs an enable / disable signal to the enhancement-mode power transistor. After the enhancement-mode power transistor receives the enable signal to turn on, the external PWM driving signal can directly control the turn-on and turn-off of the depletion-mode power transistor at a high frequency through the first capacitor, and the turn-on and turn-off speed of the depletion-mode power transistor can be adjusted through the switching speed adjustment circuit, thereby effectively avoiding the cascade defect problem caused by the cascade mode. Meanwhile, the disable signal output by the under-voltage protection circuit can avoid the risk of false turn-on caused by insufficient voltage or energy of the first capacitor, and ensure the reliable turn-off of the depletion-mode power transistor. Therefore, the external PWM driving signal can directly, effectively and reliably control (turn on and turn off) the depletion-mode power transistor Q1. BRIEF DESCRIPTION OF DRAWINGS

[0015] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the drawings needed in the embodiments will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0016] Figure 1 A schematic diagram of a driving circuit of a depletion-mode power transistor according to an embodiment of the present application is shown in FIG. 1.

[0017] Figure 2 A schematic diagram of a driving circuit of a depletion-mode power transistor according to another embodiment of the present application is shown in FIG. 2.

[0018] Figure 3A schematic diagram of a drive circuit for a depletion mode power transistor, according to yet another embodiment of the present application;

[0019] Figure 4 A schematic diagram of a drive circuit for a depletion mode power transistor, according to still another embodiment of the present application;

[0020] Figure 5 A schematic diagram of a drive circuit for a depletion mode power transistor, according to yet another embodiment of the present application;

[0021] Figure 6 A schematic diagram of a drive circuit for a depletion mode power transistor, according to still another embodiment of the present application;

[0022] Figure 7 A schematic diagram of a cascaded packaged power device, according to the related art;

[0023] Figure 8 A schematic diagram of a parasitic inductance introduced in a cascaded packaged power device, according to the related art.

[0024] REFERENCE NUMERALS:

[0025] Q1 - depletion mode power transistor;

[0026] Q2 - enhancement mode power transistor;

[0027] Q3 - first P-type transistor;

[0028] Q4 - N-type depletion mode transistor;

[0029] Q5 - second P-type transistor;

[0030] Q6 - first N-type transistor;

[0031] Q7 - third P-type transistor;

[0032] Q8 - second N-type transistor;

[0033] Q9 - first NPN transistor;

[0034] Q10 - second NPN transistor;

[0035] Q11 - third NPN transistor;

[0036] Q12 - first PNP transistor;

[0037] C1 - first capacitor;

[0038] C2 - second capacitor;

[0039] D1 - first diode;

[0040] D2 - second diode;

[0041] D3 - third diode;

[0042] D4 - fourth diode;

[0043] D5 - fifth diode;

[0044] D6 - sixth diode;

[0045] Z1 - first zener diode;

[0046] Z2 - second zener diode;

[0047] Z3 - third zener diode;

[0048] R1 - first resistor;

[0049] R2 - second resistor;

[0050] R3 - third resistor;

[0051] R4 - fourth resistor;

[0052] R5 - fifth resistor;

[0053] R6 - sixth resistor;

[0054] R7 - seventh resistor;

[0055] IC1 - first inverting amplifier driver;

[0056] IC2 - second inverting amplifier driver. DETAILED DESCRIPTION

[0057] The technical solutions in the embodiments of the present application will be described clearly and completely below with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0058] The above purposes, features and advantages of the present application will be more obvious and easy to understand. The present application will be described in further detail below with the drawings and specific embodiments.

[0059] In one exemplary embodiment, as shown in Figure 1 a driving circuit of a depletion mode power transistor is provided, which includes a depletion mode power transistor Q1, an enhancement mode power transistor Q2, a first capacitor C1, a first diode D1 and an under-voltage protection circuit 11; wherein:

[0060] The first end of the first capacitor C1 is connected to the first end of the under-voltage protection circuit and receives an external PWM driving signal, and the second end of the first capacitor C1 is commonly connected to the second end of the under-voltage protection circuit, the first end of the first diode D1 and the first end of the depletion-mode power transistor Q1 respectively;

[0061] The second end of the depletion-mode power transistor Q1 is connected to a first external circuit, the third end of the depletion-mode power transistor Q1 is connected to the first end of the enhancement-mode power transistor Q2, and the second end of the enhancement-mode power transistor Q2 is connected to the third end of the under-voltage protection circuit;

[0062] The fourth end of the under-voltage protection circuit, the second end of the first diode D1 and the third end of the enhancement-mode power transistor Q2 are connected to a driving ground, and the fourth end of the enhancement-mode power transistor Q2 is connected to a second external circuit;

[0063] The under-voltage protection circuit is used to monitor the first voltage across the first capacitor, and based on the first voltage, the under-voltage protection circuit outputs an enable / disable signal to control the turn-on and turn-off of the enhancement-mode power transistor. When the enhancement-mode power transistor receives the enable signal to turn on, the external PWM driving signal can control the turn-on and turn-off of the depletion-mode power transistor at high frequency.

[0064] The PWM (Pulse Width Modulation) drive signal is a digital signal that controls power output by adjusting pulse width (duty cycle) and is widely used in motor drive, power management and other fields. The under voltage protection circuit (UVP) is mainly used to detect whether the power supply voltage is lower than the safety threshold, and cut off the circuit or trigger the protection mechanism when the voltage is too low to prevent equipment damage or abnormal work. The first end of the depletion-mode power transistor Q1 is the gate, the second end is the drain, and the third end is the source. The depletion-mode power transistor Q1 can be a depletion-mode gallium nitride power transistor (D-mode GaN FET) or a silicon carbide junction field-effect power transistor (SiC JFET) working in high-frequency switching state. The first end of the enhancement-mode power transistor Q2 is the drain, the second end is the gate, the third end is the Kelvin source, and the fourth end is the source. The Kelvin source is connected to the driving ground of the external PWM drive signal. The enhancement-mode power transistor Q2 can be a low-voltage N-channel metal-oxide semiconductor field-effect power transistor (LV N-Ch SiMOSFET) or other types of enhancement-mode power transistors, such as low-voltage enhancement-mode gallium nitride devices (LV E-mode GaN). The first diode D1 can be a diode formed by an NPN transistor (Negative-Positive-Negative Bipolar Junction Transistor, NPN-type bipolar junction transistor). By shorting the collector and base of the NPN transistor, the collector or base is positive, and the emitter is negative. The first diode D1 can also be replaced by a diode. The first end of the first diode D1 is positive, and the second end is negative.

[0065] The embodiment of the application monitors the first voltage across the first capacitor through the under-voltage protection circuit, and sends an enable signal or a disable signal to the enhancement-mode power transistor based on the detection result of the first voltage. When the enhancement-mode power transistor receives the enable signal, the external PWM driving signal can directly control the turn-on and turn-off of the depletion-mode power transistor through the first capacitor at high frequency, and the turn-on speed and turn-off speed of the depletion-mode power transistor are adjusted through the switching speed adjustment circuit, effectively avoiding the cascade defect problem caused by the cascade mode. Meanwhile, the disable signal sent by the under-voltage protection circuit avoids the risk of false turn-on caused by insufficient voltage or energy of the first capacitor, ensuring the reliable turn-off of the depletion-mode power transistor. Therefore, the depletion-mode power transistor Q1 can be directly, effectively and reliably controlled (turned on and turned off) by the external PWM driving signal.

[0066] In an exemplary embodiment, the first capacitor is configured to store energy through the first diode when the external PWM driving signal is at a high level.

[0067] The under-voltage protection circuit is configured to monitor the first voltage across the first capacitor, and output the enable signal to turn on the enhancement-mode power transistor when the first voltage is greater than a first set value, and output the disable signal to turn off the enhancement-mode power transistor when the first voltage is less than a second set value. The absolute value of the first set value and the second set value are greater than the threshold voltage of the depletion-mode power transistor, and the second set value is not greater than the first set value.

[0068] The first diode is configured to, when there is no external PWM driving signal, if an external voltage is applied between the drain of the depletion-mode power transistor and the source of the enhancement-mode power transistor, the voltage rise of the drain of the enhancement-mode power transistor will simultaneously reverse charge the gate-source capacitor of the depletion-mode power transistor and return to the source of the enhancement-mode power transistor through the conduction of the first diode.

[0069] The first diode is configured to, when there is the external PWM driving signal, if the PWM signal is at a high level, the gate voltage of the depletion-mode power transistor rises to the conduction threshold voltage of the first diode, the first diode is turned on, and the gate voltage of the depletion-mode power transistor is clamped; if the PWM signal is at a low level, the first voltage is reversely applied across the first diode, and the first diode is reversely cut off.

[0070] The first capacitor has a capacitance of at least N times the gate equivalent capacitance of the depletion-mode power transistor in the driving circuit, so that when the external PWM driving signal is low, the first capacitor is reversely charged through the turned-on enhancement-mode power transistor to the gate equivalent capacitance of the depletion-mode power transistor, the first voltage is not lower than the absolute value of the threshold voltage of the depletion-mode power transistor, and the gate-source voltage of the depletion-mode power transistor is lower than the threshold voltage of the depletion-mode power transistor, so that the depletion-mode power transistor is turned off, and N is greater than or equal to 5.

[0071] The gate equivalent capacitance of the depletion-mode power transistor refers to the equivalent capacitance of all devices connected between the gate of the depletion-mode power transistor and the source of the enhancement-mode power transistor, including the gate capacitance of the depletion-mode power transistor, the junction capacitance of the first diode, and the like.

[0072] When the external PWM driving signal is high, the external PWM driving signal flows through the first capacitor C1 and the first diode D1 in turn to charge and store energy in the first capacitor C1. The under-voltage protection circuit is configured to monitor the first voltage across the first capacitor C1, and output the Enable signal to turn on the enhancement-mode power transistor Q2 when the first voltage is greater than a first set value, so that the external PWM driving signal directly controls the high-frequency switching state of the depletion-mode power transistor Q1 through the first capacitor. When the under-voltage protection circuit detects that the first voltage is less than a second set value, the Disable signal is output to turn off the enhancement-mode power transistor Q2. The first set value and the second set value are both greater than the absolute value of the threshold voltage of the depletion-mode power transistor Q1, and the second set value is not greater than the first set value.

[0073] The first capacitor C1 is configured to store energy to provide energy for subsequent high-frequency turn-off of the depletion-mode power transistor Q1. The first voltage can be represented as Vc1. When the external PWM driving signal is applied between the Gate pin and the KelvinSource pin, the external PWM driving signal flows through the first capacitor C1 and the first diode D1 to charge the first capacitor C1 and store energy on the first capacitor C1.

[0074] Wherein, the first set value can be represented as Vx1, the second set value can be represented as Vx2, the threshold voltage of the depletion mode power transistor Q1 can be represented as Vth, the absolute value of the threshold voltage can be represented as |Vth| or -Vth, Vx1 and Vx2 are both greater than -Vth, Vx2 is less than or equal to Vx1, the enable signal can be represented as the Enable signal, and the disable signal can be represented as the Disable signal; if the first voltage Vc1 detected across the first capacitor C1 is greater than the first set value Vx1, the under-voltage protection circuit will send the Enable signal to turn on the enhancement mode power transistor Q2; if the first voltage Vc1 detected across the first capacitor C1 is less than the second set value Vx2, the under-voltage protection circuit will send the Disable signal to turn off the enhancement mode power transistor Q2. After the enhancement mode power transistor Q2 is turned on, the external PWM drive signal can control the depletion mode power transistor Q1 through the first capacitor at high frequency; for example, the first set value Vx1 is 13 volts (unit: V), the second set value Vx2 is 12V, and the threshold voltage of the depletion mode power transistor Q1 is -8V, and the absolute value of the threshold voltage of the depletion mode power transistor Q1 is 8V.

[0075] The external PWM drive signal charges the first capacitor C1 and the gate equivalent capacitance of the depletion mode power transistor Q1 to raise the gate-source voltage of the depletion mode power transistor Q1; when the gate-source voltage of the depletion mode power transistor Q1 rises to the turn-on threshold voltage of the first diode D1, the first diode D1 is turned on and clamps the gate-source voltage of the depletion mode power transistor Q1, so that the depletion mode power transistor Q1 is fully turned on.

[0076] Wherein, the gate equivalent capacitance of the depletion mode power transistor Q1 can be represented as Cg, the gate-source capacitance of the depletion mode power transistor Q1 can be represented as Cgs, and the turn-on threshold voltage of the first diode D1 can be represented as VD1; for example, the VD1 is 0.7V; when the external PWM drive signal is at a high level, the external PWM drive signal charges the first capacitor C1 and the gate equivalent capacitance Cg of the depletion mode power transistor Q1; when the gate-source capacitance Cgs voltage of the depletion mode power transistor Q1 rises to 0.7V, the first diode D1 is turned on, and the gate-source voltage between the gate and the source of the depletion mode power transistor Q1 is clamped to the turn-on voltage of the first diode D1, so that the depletion mode power transistor Q1 is fully turned on.

[0077] In the case that the external PWM driving signal is low, the first capacitor C1 reversely charges the gate capacitor of the depletion-mode power transistor Q1 through the turned-on enhancement-mode power transistor Q2, so as to pull down the gate-source voltage of the depletion-mode power transistor Q1 to be less than the threshold voltage Vth of the depletion-mode power transistor Q1, and turn off the depletion-mode power transistor Q1; the capacitance of the first capacitor C1 is at least N times of the equivalent gate capacitance of the depletion-mode power transistor Q1, so that the voltage of the first capacitor is not lower than the absolute value of the threshold voltage of the depletion-mode power transistor during the reverse charging of the equivalent gate capacitance of the depletion-mode power transistor, for example, where N can be greater than or equal to 5.

[0078] When the external PWM driving signal is low, the first capacitor C1 reversely charges the gate capacitor Cg of the depletion-mode power transistor Q1 (the enhancement-mode power transistor Q2 is constantly turned on), and the first voltage Vc1 across the first capacitor C1 can reach Vc11. Since Vc11 is greater than Vx1, and Vx1 is greater than -Vth, that is, Vc11 is greater than -Vth, and since the first capacitor C1 reversely charges the equivalent gate capacitance Cg of the depletion-mode power transistor Q1, at this time the voltage -Vc11 is applied across the gate and source of the depletion-mode power transistor Q1, and -Vc11 is less than Vth. Since the capacitance of the first capacitor C1 is much greater than the gate capacitance Cg of the depletion-mode power transistor Q1, the gate-source voltage across the depletion-mode power transistor Q1 is reversely charged to be approximately equal to the voltage Vc11 across the first capacitor C1, and since Vc11 is greater than the absolute value of the threshold voltage of the depletion-mode power transistor Q1, the depletion-mode power transistor Q1 is turned off when the external PWM driving signal is low. For example, VC11 is 15V, Vx1 is 13V, Vx1 is 12V, and Vth is -8V, then -VC11 is -15V, and -Vth is 8V. When the depletion-mode power transistor Q1 normally works at high frequency, the enhancement-mode power transistor Q2 remains constantly turned on;

[0079] The first diode D1 and the enhancement mode power transistor Q2 are used to effectively turn off the depletion mode transistor Q1 before the voltage of the first capacitor C1 is not established to a set value; when the enhancement mode power transistor Q2 is enabled to be turned on, the turn-off of the depletion mode power transistor Q1 is realized depending on the energy stored on the first capacitor C1; in view of this, the voltage Vc1 across the first capacitor C1 cannot be lower than the absolute value of the threshold voltage of the depletion mode power transistor Q1 and the energy must be large enough; if Vc1 is lower than -Vth or the energy on the first capacitor C1 is insufficient, the depletion mode power transistor Q1 cannot be turned off by means of the PWM driving signal even if the enhancement mode power transistor Q2 is in the on state; based on the above, the under-voltage circuit becomes the key to ensuring the reliable and normal operation of the circuit, and its main role is to turn off the enhancement mode power transistor Q2 in time when the voltage on the first capacitor C1 is too low or the energy is insufficient, i.e., lower than the second set value Vx2, so as to turn off the depletion mode power transistor Q1 by turning off the enhancement mode power transistor Q2; and when the voltage on the first capacitor C1 or the energy is normal, i.e., higher than the first set value Vx1, the enhancement mode power transistor Q2 is turned on, so that the external PWM driving signal can normally drive the depletion mode power transistor Q1, thereby ensuring the stable operation of the driving circuit.

[0080] The present application stores the PWM high level energy by means of the first capacitor, and when the stored energy is large enough (the first voltage is greater than the first set value and the capacitance value of the first capacitor is large enough), the under-voltage protection circuit sends an enable signal to the enhancement mode power transistor to turn on, and then the external PWM driving signal directly controls the high frequency switching of the depletion mode power transistor through the first capacitor. When the external PWM driving signal is at a low level, the first capacitor reversely charges the gate capacitance of the depletion mode power transistor through the turned-on enhancement mode power transistor, forcibly pulls down the gate voltage below the threshold value, and ensures the reliable turn-off of the depletion mode power transistor; when the external PWM driving signal is at a high level, the driving signal charges the equivalent capacitance of the first capacitor and the gate of the depletion mode power transistor, and during the charging process, the gate-source voltage of the depletion mode power transistor gradually rises; when the gate-source voltage exceeds the threshold voltage, the depletion mode power transistor starts to turn on. At this time, the gate-source voltage further rises until the first diode is turned on, and the gate-source voltage is clamped at the turn-on voltage of the first diode. Thus, the external PWM driving signal can directly, effectively and reliably control (turn on and turn off) the depletion mode transistor Q1, and the cascading defect problem of the depletion mode transistor caused by the cascading mode is effectively avoided.

[0081] In one exemplary embodiment, as Figure 2As shown, the under-voltage protection circuit 11 comprises a first P-type transistor Q3, an N-type depletion-mode transistor Q4, a second diode D2, a third diode D3, a first Zener diode Z1, a second Zener diode Z2, a first resistor R1 and a second resistor R2; wherein:

[0082] The first end of the first capacitor C1 is commonly connected with the first end of the N-type depletion-mode transistor Q4, the first end of the first resistor R1 and the first end of the first P-type transistor Q3;

[0083] The first end of the first Zener diode Z1 is connected with the second end of the first capacitor C1, and the second end of the first Zener diode Z1 is commonly connected with the second end of the first P-type transistor Q3, the second end of the first resistor R1 and the second end of the N-type depletion-mode transistor Q4;

[0084] The third end of the first P-type transistor Q3 is connected with the first end of the second diode D2, the second end of the second diode D2 is connected with the first end of the second Zener diode Z2, the second end of the second Zener diode Z2 is commonly connected with the first end of the third diode D3, the first end of the second resistor R2 and the second end of the enhancement-mode power transistor Q2, and the second end of the third diode D3 is connected with the third end of the N-type depletion-mode transistor Q4;

[0085] The second end of the second resistor R2 is connected with a driving ground;

[0086] The first P-type transistor is configured to be turned on when the first voltage is greater than a first set value, so as to send the Enable signal to turn on the enhancement-mode power transistor; and the N-type depletion-mode transistor is configured to be turned on when the first voltage is less than a second set value, and send the Disable signal to discharge the gate charge of the enhancement-mode power transistor so as to disable the enhancement-mode power transistor.

[0087] The second diode is configured to prevent the gate charge of the enhancement-mode power transistor from being discharged when the external PWM driving signal is at a low level;

[0088] The third diode is configured to discharge the gate charge of the enhancement-mode power transistor through the third diode and the N-type depletion-mode transistor when the first voltage is less than the second set value, so as to turn off the enhancement-mode power transistor and prevent the gate of the enhancement-mode power transistor from being charged through the N-type depletion-mode transistor.

[0089] The first end of the first P-type transistor Q3 is a source, the second end is a gate, and the third end is a drain. The first end of the N-type depletion-mode transistor Q4 is a source, the second end is a gate, and the third end is a drain. The second diode D2 and the third diode D3 are both diodes formed by NPN transistors, and the collector and the base of the NPN transistor are short-circuited, at this time, the collector or the base is a positive electrode, and the emitter is a negative electrode. The second diode D2 and the third diode D3 can also be directly replaced by diodes. The first end of the second diode D2 is a positive electrode, and the second end is a negative electrode. The first end of the first Zener diode Z1 is a positive electrode, and the second end is a negative electrode. The first end of the second Zener diode Z2 is a negative electrode, and the second end is a positive electrode.

[0090] The first end of the under-voltage protection circuit corresponds to the first end of the first capacitor. The second end of the under-voltage protection circuit corresponds to the first end of the first Zener diode. The third end of the under-voltage protection circuit corresponds to the second end of the second Zener diode. The fourth end of the under-voltage protection circuit corresponds to the second end of the second resistor.

[0091] In an exemplary embodiment, the under-voltage protection circuit is configured to turn off the N-type depletion-mode transistor Q4 when the first voltage rises to a first difference between a nominal voltage of the first Zener diode Z1 and a threshold voltage of the N-type depletion-mode transistor Q4. The first difference is equal to the second set value.

[0092] The nominal voltage of the first Zener diode Z1 can be represented as Vz1, the threshold voltage of the N-type depletion-mode transistor Q4 can be represented as Vth_Q4, and the first difference can be represented as Vz1-Vth_Q4. When the external PWM driving signal is high, the current charges the first capacitor C1 through the first diode D1 to store energy. Before the voltage Vc1 on the first capacitor C1 is established to the set value, the N-type depletion-mode transistor Q4 is in an open state, the first P-type transistor is in a closed state, the gate-source voltage of the enhancement-mode power transistor Q2 is 0, and the enhancement-mode power transistor Q2 is in a closed state. Once the voltage Vc1 on the first capacitor C1 exceeds Vz1-Vth_Q4, the N-type depletion-mode transistor Q4 is turned off, and at this time, the first P-type transistor Q3 is still not turned on.

[0093] In the case that the first voltage continues to rise to a second difference between the nominal voltage of the first Zener diode Z1 and the threshold voltage of the first P-type transistor Q3, the first P-type transistor Q3 is turned on, and an enable signal is output to turn on the enhancement-mode power transistor Q2, and the second difference is equal to the first set value;

[0094] Wherein, the threshold voltage of the first P-type transistor Q3 can be represented as Vth_Q3, and the second difference can be represented as Vz1-Vth_Q3; once the voltage Vc1 on the first capacitor C1 exceeds Vz1-Vth_Q3, the first P-type transistor Q3 will be turned on, and then an enable signal is sent to the enhancement-mode power transistor Q3, thereby turning on the enhancement-mode power transistor Q2.

[0095] The second diode D2 is used to prevent the gate charge of the enhancement-mode power transistor Q2 from being discharged when the external PWM driving signal is at a low level;

[0096] Wherein, thanks to the reverse blocking characteristic of the second diode D2, and the fact that the N-type depletion-mode transistor Q4 is in an off state at this time, the voltage on the gate capacitor of the enhancement-mode power transistor Q2 can be maintained at a high level even if the input external PWM driving signal is at a low level; once the enhancement-mode power transistor Q2 is turned on, the input external PWM driving signal can control the turn-on and turn-off of the depletion-mode power transistor Q1.

[0097] In the case that the first voltage drops to the second difference due to insufficient amplitude and / or energy of the external PWM driving signal, the first P-type transistor Q3 is turned off; in the case that the first voltage drops to the first difference due to insufficient amplitude and / or energy of the external PWM driving signal, the N-type depletion-mode transistor Q4 is turned on again; the gate charge of the enhancement-mode power transistor Q2 is discharged through the third diode D3 and the N-type depletion-mode transistor Q4, and the enhancement-mode power transistor Q2 is turned off.

[0098] If the energy and amplitude of the input PWM signal are too low, the energy stored in the first capacitor C1 is insufficient, which causes the first P-type transistor Q3 to be turned off and the N-type depletion-mode transistor Q4 to be turned on. The energy on the gate of the enhancement-mode power transistor Q2 is discharged through the third diode D3 and the N-type depletion-mode transistor Q4 when the input PWM signal is at a low level, which causes the enhancement-mode power transistor Q2 to be turned off, and the input external PWM driving signal cannot control the turn-on and turn-off of the depletion-mode power transistor Q1. It should be particularly emphasized that the under-voltage protection circuit mentioned herein can be implemented in various forms, and these various implementation schemes are included in the protection scope of the present application.

[0099] In the embodiments of the present application, the under-voltage protection circuit turns off the enhancement-mode power transistor Q2 when the energy and amplitude of the input PWM signal are too low, which can effectively prevent the depletion-mode power transistor Q1 from failing due to insufficient voltage on the first capacitor C1 to turn off the depletion-mode power transistor Q1, and ensure stable operation of the driving circuit.

[0100] In an exemplary embodiment, as shown in Figure 3 The driving circuit further includes a switching speed adjustment circuit 21 for adjusting the turn-on speed and turn-off speed of the depletion-mode power transistor.

[0101] It should be noted that the switching speed adjustment circuit can include a turn-on speed adjustment circuit and a turn-off speed adjustment circuit connected in parallel, the turn-on speed adjustment circuit being configured to adjust the turn-on speed of the depletion-mode power transistor Q1, and the turn-off speed adjustment circuit being configured to adjust the turn-off speed of the depletion-mode power transistor Q1.

[0102] In an exemplary embodiment, as shown in Figure 4 The switching speed adjustment circuit 21 includes a third resistor R3, a fourth resistor R4, and a fourth diode D4.

[0103] The first end of the third resistor R3 is connected to the first end of the fourth resistor R4 and receives the external PWM driving signal, and the second end of the fourth resistor R4 is connected to the first end of the fourth diode D4.

[0104] The second end of the fourth diode D4 is commonly connected to the second end of the third resistor R3 and the first end of the under-voltage protection circuit.

[0105] The third resistor R3 is configured to adjust the turn-on speed of the depletion-mode power transistor Q1.

[0106] The third resistor R3 constitutes an opening speed adjusting circuit. The third resistor R3 is connected in series in the gate drive path, which limits the charging current and slows down the opening speed of the depletion mode power transistor Q1.

[0107] The fourth resistor R4 and the fourth diode D4 are used to adjust the closing speed of the depletion mode power transistor Q1.

[0108] The fourth resistor R4 and the fourth diode D4 constitute a closing speed adjusting circuit. The first end of the fourth diode is negative, and the second end is positive. The fourth resistor R4 is connected in series in the discharge path, which limits the discharge current and slows down the closing speed of the depletion mode power transistor Q1. When the depletion mode power transistor Q1 is closed, the fourth diode D4 is forward biased, allowing current to pass through the fourth resistor R4 to discharge, so as to adjust the closing speed of the depletion mode power transistor Q1. When the depletion mode power transistor Q1 is opened, the fourth diode D4 is reverse blocked, avoiding the influence of the fourth resistor R4 on the opening speed of the depletion mode power transistor Q1, so that the opening speed of the depletion mode power transistor Q1 is only controlled by the third resistor R3.

[0109] In the embodiments of the present application, the opening speed and the closing speed of the depletion mode power transistor Q1 can be adjusted by the switching speed adjusting circuit, which can alleviate the ringing and oscillation phenomenon of the depletion mode power transistor Q1 in high-frequency operation.

[0110] In an exemplary embodiment, as shown in Figure 5 The drive circuit further comprises a limiting amplitude level conversion circuit 31.

[0111] The first end of the limiting amplitude level conversion circuit 31 is connected to an external DC power supply 32, the second end receives the external PWM drive signal, the third end is connected to the first end of the under-voltage protection circuit 11, and the fourth end is connected to the driving ground.

[0112] The limiting amplitude level conversion circuit 31 is used to adjust the amplitude and limit the amplitude of the external PWM drive signal, and enhance the driving ability of the external PWM drive signal.

[0113] The amplitude of the external DC power supply 32 can be a third amplitude. In the case where the amplitude of the external PWM drive signal is less than or equal to a preset amplitude threshold, the external PWM drive signal is converted into an output signal with a third amplitude and a driving ability.

[0114] The third amplitude value can be represented as VDDH. When the amplitude of the input external PWM driving signal is low, the amplitude limiting and level conversion circuit can convert the input external PWM driving signal into an output signal with an amplitude of about VDDH and driving capability.

[0115] In the case where the amplitude of the external PWM driving signal is greater than the preset amplitude threshold value, the external PWM driving signal is subjected to amplitude limiting processing, and is converted into an output signal with an amplitude of the third amplitude value and driving capability.

[0116] When the amplitude of the input external PWM driving signal is too high, the amplitude limiting and level conversion circuit 31 first subjects the input external PWM driving signal to amplitude limiting processing, and then converts the input external PWM driving signal into an output signal with an amplitude of about VDDH and driving capability.

[0117] In the embodiment, no matter the energy and amplitude of the input PWM driving signal, the first capacitor C1 receives a signal with an amplitude of about VDDH and driving capability, so as to sufficiently store energy, successfully complete the high-frequency switching function, and effectively drive the system. The driving circuit can maintain normal operation state when facing input PWM driving signals with different amplitudes, so as to ensure stable operation and reliable performance of the system. Even if the amplitude of the input PWM driving signal is low, the system can also operate normally, so as to ensure that the system can stably work in various states.

[0118] In an exemplary embodiment, as shown in Figure 6 The amplitude limiting and level conversion circuit 31 includes an amplitude limiting and power supply circuit 311 and a level conversion circuit 312.

[0119] The level conversion circuit 312 includes a second P-type transistor Q5, a third P-type transistor Q7, a first N-type transistor Q6, a second N-type transistor Q8, a first inverting amplification driver IC1, and a second inverting amplification driver IC2.

[0120] The amplitude limiting and power supply circuit 311 includes a first NPN transistor Q9, a second NPN transistor Q10, a third NPN transistor Q11, a first PNP transistor Q12, a second capacitor C2, a fourth diode D4, a fifth diode D5, a sixth diode D6, a third Zener diode Z3, a fifth resistor R5, a sixth resistor R6, and a seventh resistor R7.

[0121] The first end of the second P-type transistor Q5 is connected with the power supply, the first end of the third P-type transistor Q7, the first end of the second inverting amplification driver IC2, the first end of the seventh resistor R7, and the first end of the first NPN transistor Q9.

[0122] the second end of the second P-type transistor Q5 is commonly connected with the second end of the third P-type transistor Q7, the second end of the second reverse amplification driver IC2, and the first end of the first N-type transistor Q6;

[0123] the third end of the second P-type transistor Q5 is commonly connected with the third end of the third P-type transistor Q7 and the first end of the second N-type transistor Q8; the second end of the second N-type transistor Q8 is connected with the first end of the first reverse amplification driver IC1;

[0124] the second end of the first N-type transistor Q6 is commonly connected with the second end of the first reverse amplification driver IC1, the first end of the third NPN transistor Q11, and the first end of the first PNP transistor Q12;

[0125] the second end of the third NPN transistor Q11 is commonly connected with the second end of the first PNP transistor Q12, the first end of the sixth resistor R6, and the first end of the sixth diode D6;

[0126] the second end of the sixth resistor R6 receives the external PWM driving signal and is commonly connected with the second end of the sixth diode D6, the first end of the fifth resistor R5, and the first end of the second NPN transistor Q10;

[0127] the second end of the fifth resistor R5 is commonly connected with the second end of the second NPN transistor Q10 and the first end of the fourth diode D4; the second end of the fourth diode D4 is connected with the first end of the fifth diode D5;

[0128] the second end of the fifth diode D5 is commonly connected with the first end of the third Zener diode Z3, the second end of the first NPN transistor Q9, and the second end of the seventh resistor R7;

[0129] the third end of the first NPN transistor Q9 is commonly connected with the third end of the second NPN transistor Q10, the first end of the second capacitor C2, the third end of the third NPN transistor Q11, and the third end of the first reverse amplification driver IC1;

[0130] the second end of the third Zener diode Z3, the second end of the second capacitor C2, the third end of the first PNP transistor Q12, the fourth end of the first reverse amplification driver IC1, the third end of the first N-type transistor Q6, the third end of the second N-type transistor Q8, and the third end of the second reverse amplification driver IC2 are commonly connected with the driving end;

[0131] The fourth end of the second reverse amplification driver IC2 is connected to the first end of the under-voltage protection circuit.

[0132] The first end of the second P-type transistor Q5 is a source, the second end is a drain, and the third end is a gate; the first end of the third P-type transistor Q7 is a source, the second end is a gate, and the third end is a drain; the first end of the first N-type transistor Q6 is a drain, the second end is a gate, and the third end is a source; the first end of the second N-type transistor Q8 is a drain, the second end is a gate, and the third end is a source;

[0133] The first end of the first NPN transistor Q9 is a collector, the second end is a base, and the third end is an emitter; the first end of the second NPN transistor Q10 is a collector, the second end is a base, and the third end is an emitter; the first end of the third NPN transistor Q11 is an emitter, the second end is a base, and the third end is a collector; the first end of the first PNP transistor (Positive-Negative-Positive Bipolar Junction Transistor, PNP bipolar junction transistor) Q12 is an emitter, the second end is a base, and the third end is a collector; the first end of the fourth diode D4, the fifth diode D5, and the sixth diode D6 is a positive electrode, and the second end is a negative electrode; the first end of the third Zener diode Z3 is a negative electrode, and the second end is a positive electrode.

[0134] The first end of the amplitude limiting conversion circuit corresponds to the first end of the second P-type transistor, the second end of the amplitude limiting conversion circuit corresponds to the second end of the sixth resistor, the third end of the amplitude limiting conversion circuit corresponds to the fourth end of the second reverse amplification driver, and the fourth end of the amplitude limiting conversion circuit corresponds to the second end of the third Zener diode.

[0135] In an exemplary embodiment, the fourth diode D4, the fifth diode D5, and the third Zener diode Z3 clamp the output voltage of the first NPN transistor Q9 and the second NPN transistor Q10, so that the voltage on the second capacitor C2 is a low-voltage power supply;

[0136] The energy stored by the second capacitor C2 is used to power the first reverse amplification driver IC1, and also to power the driving circuit composed of the third NPN transistor Q11 and the first PNP transistor Q12;

[0137] The level conversion circuit is used to convert the first amplitude external PWM driving signal received by the first reverse amplification driver IC1 into a second amplitude external PWM driving signal with driving capability output by the second reverse amplification driver IC2, and the first amplitude is less than the second amplitude;

[0138] The fifth resistor R5, the sixth resistor R6 and the seventh resistor R7 are current limiting resistors, and the sixth diode D6 is used to accelerate the turn-off speed.

[0139] Wherein, the first amplitude is a low amplitude, and the second amplitude is a high amplitude, and the level conversion circuit can convert the low amplitude external PWM driving signal received by the first inverting amplifier driver IC1 into the high amplitude external PWM driving signal with driving capability output by the second inverting amplifier driver IC2; the first NPN transistor Q9 charges the second capacitor C2 from the external power supply VDDH, and controls and clamps the output of the first NPN transistor Q9 through the third Zener diode Z3; the second NPN transistor Q10 charges the second capacitor C2 from the input external PWM driving signal, and controls and clamps the output of the second NPN transistor Q10 through the fourth diode D4, the fifth diode D5 and the third Zener diode Z3; the energy stored in the second capacitor C2 is used to power the first inverting amplifier driver IC1, and also powers the driving circuit composed of the third NPN transistor Q11 and the first PNP transistor Q12, and since the third NPN transistor Q11 and the first PNP transistor Q12 are powered by the low amplitude voltage stored in the second capacitor C2, the first inverting amplifier driver IC1 receives a low amplitude level signal from the driving circuit composed of the third NPN transistor Q11 and the first PNP transistor Q12.

[0140] Since the power supply voltage of the first inverting amplifier driver IC1, the third NPN transistor Q11 and the first PNP transistor Q12 is limited to a low amplitude, even if the input PWM signal amplitude is too large, after passing through the sixth resistor R6, the third NPN transistor Q11 and the first PNP transistor Q12, the first inverting amplifier driver IC1 receives a low amplitude PWM signal after limiting.

[0141] In an exemplary embodiment, the output clamping voltage of the second NPN transistor Q10 is higher than the output clamping voltage of the first NPN transistor Q9.

[0142] In the embodiments of the present application, in order to reduce the loss, the output clamping voltage of the second NPN transistor Q10 is higher than that of the first NPN transistor Q9, so that the first NPN transistor Q9 charges the second capacitor C2 through the power supply only when the energy requirement of the second capacitor C2 cannot be met by the input external PWM drive signal, otherwise only the second NPN transistor Q10 works, avoiding excessive loss of the first NPN transistor Q9 due to the excessively high amplitude of VDDH.

[0143] It should be noted that all P-type transistors in the above embodiments can be replaced by PNP transistors, such as the first P-type transistor Q3, the second P-type transistor Q5, and the third P-type transistor Q7, which can be replaced by PNP transistors; all N-type transistors can be replaced by NPN transistors, for example, the first N-type transistor Q6 and the second N-type transistor Q8 can be replaced by NPN transistors; similarly, PNP transistors can be replaced by P-type transistors, and NPN transistors can be replaced by N-type transistors; when replacing the transistors, the corresponding adjustment of the driving circuit can be made as needed, such as increasing the driving resistance and adjusting the bias.

[0144] In the related art, as shown in FIG. 1, a depletion-mode transistor (D-MODE transistor) is normally open, and in practical applications, a cascade packaging integrated manner is usually adopted, that is, a depletion-mode transistor 41 and a low-voltage Si MOSFET (Low-Voltage Silicon Metal-Oxide-Semiconductor Field-Effect Transistor) 42 are cascade packaged to form a normally closed composite switching device (also known as a cascade packaging power device). Figure 7

[0145] There are several technical defects (so-called cascade defects) in the cascade packaging power device in practical applications:

[0146] First, the driving control mechanism of the gate of the depletion-mode transistor inside the cascade has inherent defects. Due to the lack of effective control and driving for the depletion-mode transistor, the gate is in a quasi-uncontrolled state, and the transient process of this quasi-uncontrolled state can significantly deteriorate the electromagnetic compatibility characteristics (EMI (Electromagnetic Interference)) of the system, which is specifically manifested as an abnormal increase in the high-frequency component of the conducted interference spectrum and an excessive radiation interference intensity. ​

[0147] Second, the cascade packaging interconnection structure introduces a parasitic parameter coupling problem. The bonding wire shows a significant parasitic inductance effect (typical value of about 3 nH) under high-frequency working conditions, as shown in the structure (L1 to L6 are parasitic inductances introduced by the bonding wire when the packaging interconnection). Figure 8 The parasitic parameter causes strong coupling of two key circuits of the depletion-mode transistor: the drive loop and the power main loop form a common-mode interference path; during the device off transient, the induced electromotive force (L·di / dt) generated by the parasitic inductance directly acts on the gate-source of the depletion-mode transistor, causing the gate potential to abnormally rise above the threshold voltage, thereby triggering the false turn-on phenomenon, where L is the parasitic inductance and di / dt is the current change rate. And this phenomenon is more likely to occur during the DS (Drain-Source, drain-source) low-voltage switching process, because when the DS voltage is low, the drive voltage of the upper depletion-mode transistor is lower, which is closer to the threshold voltage, so it is more susceptible to the above interference, thereby severely restricting the system reliability.

[0148] Third, the drive cascade depletion-mode device is essentially to first drive the low-voltage Silicon MOSFET inside the cascade, and then drive the depletion-mode transistor, so there is a lag phenomenon in the drive process of the cascade depletion-mode, and there is also reverse recovery charge, which will affect and limit higher frequency applications and application scenarios, resulting in that the depletion-mode transistor cannot fully play its performance advantage in the cascade architecture.

[0149] In the embodiment of the present application, the depletion-mode power transistor Q1 is directly driven by an external PWM drive signal, and the switching speed can be adjusted by means of the size of the external circuit impedance, effectively avoiding the quasi-uncontrolled state of the gate of the depletion-mode transistor, thereby significantly improving the electromagnetic compatibility (EMI) of the system.

[0150] In the embodiment of the present application, the low-voltage enhancement-mode transistor (i.e., enhancement-mode power transistor) Q2 is in a Normal ON state during the high-frequency switching process, so there is no reverse recovery loss in the low-voltage enhancement-mode transistor Q2 during this process.

[0151] In the embodiment of the present application, the turn-off voltage of the depletion-mode power transistor Q1 is realized by relying on the energy on the first capacitor C1, and since the capacitance of the first capacitor C1 is relatively large, the voltage across the first capacitor C1 remains basically constant. When the depletion-mode power transistor Q1 is turned off, the change in the DS voltage will not cause the voltage across the first capacitor C1 to change, that is, the gate-source voltage of the depletion-mode power transistor Q1 will not change with the change in the DS voltage, and has strong anti-interference ability.

[0152] The level UVP (under voltage protection) circuit proposed in the embodiments of the present application is a key circuit for ensuring reliable and normal operation of the depletion mode transistor Q1, which can effectively avoid system failure caused by excessively low external PWM drive signal level; at the same time, the general drive scheme for driving the depletion mode transistor proposed in the embodiments of the present application can ensure normal and stable operation of the system regardless of the size of the input PWM level amplitude.

[0153] It should be noted that the principles described in the embodiments of the present application can be directly applied in switching power supply and electric drive application scenarios, and can also be integrated into a power IC device using the principles described in the embodiments of the present application; for example, the principles described in the embodiments of the present application can be integrated into a 4-pin power chip, and the pin definition of the 4-pin power chip can be compatible with mainstream power Silicon power transistor / power GaN transistor / power SiC transistor products on the market. Figure 1 Figure 2 The principles described in the embodiments can be integrated into a 4-pin power chip, and the pin definition of the 4-pin power chip can be compatible with mainstream power Silicon power transistor / power GaN transistor / power SiC transistor products on the market.

[0154] The principles described in the embodiments can be integrated into a 5-pin power device, and even the principles described in the embodiments of the present application and the control IC for generating PWM can be deeply integrated to construct an integrated power control integrated IC. Figure 5

[0155] The technical features of the above embodiments can be combined in any manner, and to make the description concise, not all possible combinations of the technical features in the above embodiments are described, however, as long as the combinations of the technical features do not exist contradictions, they should be considered as the scope of the present application.

[0156] The principles and implementation modes of the present application are described by using specific examples in the present application, and the above embodiment descriptions are only used to help understand the method and core idea of the present application; at the same time, for those skilled in the art, according to the idea of the present application, the specific implementation mode and application range will be changed. In conclusion, the content of the present application should not be understood as a limitation.​

Claims

1. A drive circuit for a depletion mode power transistor, characterized by The drive circuit of the depletion mode power transistor comprises a depletion mode power transistor, an enhancement mode power transistor, a first capacitor, a first diode and an under-voltage protection circuit; wherein: The first end of the first capacitor is connected to the first end of the under-voltage protection circuit and receives an external PWM drive signal, and the second end of the first capacitor is commonly connected to the second end of the under-voltage protection circuit, the first end of the first diode and the first end of the depletion mode power transistor; The second end of the depletion mode power transistor is connected to a first external circuit, the first end of the enhancement mode power transistor is connected to the third end of the depletion mode power transistor, and the second end of the enhancement mode power transistor is connected to the third end of the under-voltage protection circuit; The fourth end of the under-voltage protection circuit, the second end of the first diode and the third end of the enhancement mode power transistor are connected to a driving ground, and the fourth end of the enhancement mode power transistor is connected to a second external circuit; The under-voltage protection circuit is used to monitor a first voltage across the first capacitor, and based on the first voltage, the under-voltage protection circuit outputs an enable / disable signal to control the turn-on and turn-off of the enhancement mode power transistor, and after the enhancement mode power transistor receives the enable signal to turn on, the external PWM drive signal can control the turn-on and turn-off of the depletion mode power transistor at a high frequency.

2. The drive circuit of the depletion mode power transistor according to claim 1, wherein: The first capacitor is used to charge and store energy through the first diode when the external PWM drive signal is at a high level; The under-voltage protection circuit is used to output the enable signal to turn on the enhancement mode power transistor when the first voltage is detected to be greater than a first set value, and output the disable signal to turn off the enhancement mode power transistor when the first voltage is detected to be less than a second set value, the absolute value of the first set value and the second set value are both greater than the threshold voltage of the depletion mode power transistor, and the second set value is not greater than the first set value; The first diode is used to, when there is no external PWM drive signal, if an external voltage is applied between the drain of the depletion mode power transistor and the source of the enhancement mode power transistor, the voltage rise of the drain of the enhancement mode power transistor will simultaneously reverse charge the gate-source capacitor of the depletion mode power transistor and return to the source of the enhancement mode power transistor through the conduction of the first diode; The first diode is used to, when there is the external PWM drive signal, if the PWM signal is at a high level, the gate voltage of the depletion mode power transistor rises to the conduction threshold voltage of the first diode to turn on, and clamps the gate voltage of the depletion mode power transistor; if the PWM signal is at a low level, the first voltage is reversely applied across the first diode, and the first diode is reversely cut off. The first capacitor has a capacitance of at least N times the gate equivalent capacitance of the depletion-mode power transistor in the drive circuit, so that when the external PWM drive signal is low, the first capacitor, during reverse charging of the gate equivalent capacitance of the depletion-mode power transistor through the turned-on enhancement-mode power transistor, causes the first voltage to be no lower than the absolute value of the threshold voltage of the depletion-mode power transistor, thereby causing the gate-source voltage of the depletion-mode power transistor to drop below the threshold voltage of the depletion-mode power transistor, causing the depletion-mode power transistor to turn off, and N is greater than or equal to 5.

3. The drive circuit for a depletion mode power transistor according to claim 1, wherein The under-voltage protection circuit comprises a first P-type transistor, an N-type depletion-mode transistor, a second diode, a third diode, a first Zener diode, a second Zener diode, a first resistor, and a second resistor. A first end of the first capacitor is connected to a first end of the N-type depletion-mode transistor, a first end of the first resistor, and a first end of the first P-type transistor. A first end of the first Zener diode is connected to a second end of the first capacitor, and a second end of the first Zener diode is connected to a second end of the first P-type transistor, a second end of the first resistor, and a second end of the N-type depletion-mode transistor. A third end of the first P-type transistor is connected to a first end of the second diode, a second end of the second diode is connected to a first end of the second Zener diode, a second end of the second Zener diode is connected to a first end of the third diode, a first end of the second resistor, and a second end of the enhancement-mode power transistor, and a second end of the third diode is connected to a third end of the N-type depletion-mode transistor. A second end of the second resistor is connected to a drive ground. The first P-type transistor is configured to turn on when the first voltage is greater than a first set value, thereby causing the Enable signal to turn on the enhancement-mode power transistor; and the N-type depletion-mode transistor is configured to turn on when the first voltage is less than a second set value, thereby causing the Disable signal to discharge the gate charge of the enhancement-mode power transistor and disable the enhancement-mode power transistor. The second diode is configured to prevent the gate charge of the enhancement-mode power transistor from being discharged when the external PWM drive signal is low. The third diode is configured to discharge the gate charge of the enhancement-mode power transistor through the third diode and the N-type depletion-mode transistor when the first voltage is less than the second set value, thereby turning off the enhancement-mode power transistor and preventing the gate of the enhancement-mode power transistor from being charged through the N-type depletion-mode transistor.

4. The drive circuit for a depletion mode power transistor according to claim 1, wherein The drive circuit further comprises a switching speed adjustment circuit configured to adjust the turn-on speed and turn-off speed of the depletion-mode power transistor.

5. The drive circuit for a depletion mode power transistor according to claim 4, characterized in that, The switching speed adjustment circuit comprises a third resistor, a fourth resistor, and a fourth diode. A first end of the third resistor is connected to a first end of the fourth resistor and configured to receive the external PWM drive signal, and a second end of the fourth resistor is connected to a first end of the fourth diode. The second end of the fourth diode is connected with the second end of the third resistor and the first end of the under-voltage protection circuit; The third resistor is used for adjusting the turn-on speed of the depletion-mode power transistor; The fourth resistor and the fourth diode are used for adjusting the turn-off speed of the depletion-mode power transistor.

6. The drive circuit for a depletion mode power transistor according to claim 1, wherein The driving circuit further comprises a limiting-amplitude level conversion circuit; The first end of the limiting-amplitude level conversion circuit is connected with an external direct-current power supply, the second end receives the external PWM driving signal, the third end is connected with the first end of the under-voltage protection circuit, and the fourth end is connected with a driving ground; The limiting-amplitude level conversion circuit is used for amplitude adjustment and limiting protection of the external PWM driving signal, and enhances the driving capability of the external PWM driving signal.

7. The drive circuit for a depletion mode power transistor according to claim 6, characterized in that, The limiting-amplitude level conversion circuit comprises a limiting-amplitude and power supply circuit and a level conversion circuit; The level conversion circuit comprises a second P-type transistor, a third P-type transistor, a first N-type transistor, a second N-type transistor, a first reverse amplification driver and a second reverse amplification driver; The limiting-amplitude and power supply circuit comprises a first NPN transistor, a second NPN transistor, a third NPN transistor, a first PNP transistor, a second capacitor, a fourth diode, a fifth diode, a sixth diode, a third Zener diode, a fifth resistor, a sixth resistor and a seventh resistor; The first end of the second P-type transistor is connected with the external power supply, the first end of the third P-type transistor, the first end of the second reverse amplification driver, the first end of the seventh resistor and the first end of the first NPN transistor; The second end of the second P-type transistor is connected with the second end of the third P-type transistor, the second end of the second reverse amplification driver and the first end of the first N-type transistor; The third end of the second P-type transistor is connected with the third end of the third P-type transistor and the first end of the second N-type transistor, and the second end of the second N-type transistor is connected with the first end of the first reverse amplification driver; The second end of the first N-type transistor is connected with the second end of the first reverse amplification driver, the first end of the third NPN transistor and the first end of the first PNP transistor; The second end of the third NPN transistor is connected with the second end of the first PNP transistor, the first end of the sixth resistor and the first end of the sixth diode; The second end of the sixth resistor receives the external PWM driving signal and is connected with the second end of the sixth diode, the first end of the fifth resistor and the first end of the second NPN transistor; The second end of the fifth resistor is connected with the second end of the second NPN transistor and the first end of the fourth diode, and the second end of the fourth diode is connected with the first end of the fifth diode; The second end of the fifth diode is connected with the first end of the third Zener diode, the second end of the first NPN transistor and the second end of the seventh resistor. a third terminal of the first NPN transistor is commonly connected with a third terminal of the second NPN transistor, a first terminal of the second capacitor, a third terminal of the third NPN transistor, a third terminal of the first reverse amplification driver; a second terminal of the third Zener diode, a second terminal of the second capacitor, a third terminal of the first PNP transistor, a fourth terminal of the first reverse amplification driver, a third terminal of the first N-type transistor, a third terminal of the second N-type transistor, a third terminal of the second reverse amplification driver are commonly connected; a fourth terminal of the second reverse amplification driver is connected with a first terminal of the under-voltage protection circuit.

8. The driving circuit of the depletion-mode power transistor according to claim 7, wherein, the fourth diode, the fifth diode and the third Zener diode are used to clamp the output voltage of the first NPN transistor and the second NPN transistor, so that the voltage on the second capacitor is a low-voltage power supply; the energy stored by the second capacitor is used to power the first reverse amplification driver, and also to power the driving circuit composed of the third NPN transistor and the first PNP transistor; the level conversion circuit is used to convert the external PWM driving signal of the first amplitude received by the first reverse amplification driver into the external PWM driving signal of the second amplitude with driving capability output by the second reverse amplification driver, the first amplitude being smaller than the second amplitude; the fifth resistor, the sixth resistor and the seventh resistor are current-limiting resistors, and the sixth diode is used to accelerate the turn-off speed.

9. The drive circuit for a depletion mode power transistor according to claim 7, wherein the output clamping voltage of the second NPN transistor is higher than the output clamping voltage of the first NPN transistor.

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