Schmitt shaping circuit and system
Through the improved Smitt shaping circuit, the input signal is hedged by using positive feedback lines and power-off design lines and output standard square waves, solving the problem of poor signal compatibility and anti-interference capability of traditional digital logic circuit chips at the front end, and achieving reduced PCB area and improved reliability.
Patent Information
- Application Number
- CN202510544802.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-28
- Publication Date
- 2025-08-08
AI Technical Summary
Traditional digital logic circuit chips have problems with poor overshoot resistance and reflection capabilities and poor signal compatibility at the front end, resulting in increased PCB area, lower reliability and increased failure rate.
Using an improved Smit shaping circuit, including two sets of positive feedback lines and a power-off design line, the input signal rise and fall process is hedged, standard square waves are output, and polycrystalline resistors are connected in series between connected inverters.
It effectively alleviates the problems of increasing PCB area, low reliability and increased failure rate, and improves signal processing capabilities and anti-interference capabilities of the circuit.
Smart Images
Figure CN120454714A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a Schmitt shaping circuit and system. Background Art
[0002] Currently, traditional digital logic circuit chips generally use ordinary circuit structures with electrostatic protection at the front end. This has problems such as poor overshoot and reflection resistance and poor signal compatibility. Therefore, designers often need to consider signal processing and level compatibility when applying digital logic chips. In particular, when irregular signal waveforms such as triangular waves and sine waves are generated due to long-line transmission or directly output by analog chips after signal acquisition, specialized trigger chips are generally used for shaping. This leads to problems such as increased PCB (Printed Circuit Board) area, lower reliability, and increased failure rate. Summary of the Invention
[0003] In view of this, the purpose of the present invention is to provide a Schmitt shaping circuit and system, which can be used in the front end of a digital logic chip and provide a pulse shaping function to alleviate problems such as increased PCB area, low reliability, and increased failure rate.
[0004] In a first aspect, an embodiment of the present invention provides a Schmitt shaping circuit, comprising an electrically connected improved Schmitt circuit and a power-off design circuit;
[0005] The improved Schmitt circuit includes two sets of positive feedback circuits, which are used to hedge the rising and falling processes of the input signal, so as to cut off the irregular noise in the input signal and output a standard square wave;
[0006] The power-off design circuit includes a plurality of inverters electrically connected in sequence, and a polycrystalline resistor is connected in series between two connected inverters.
[0007] In one embodiment, the two groups of positive feedback lines include a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, and a sixth MOS transistor;
[0008] The first MOS transistor, the second MOS transistor and the third MOS transistor are all NMOS transistors, and the fourth MOS transistor, the fifth MOS transistor and the sixth MOS transistor are all PMOS transistors.
[0009] In one embodiment, the gates of the first MOS transistor, the second MOS transistor, the fourth MOS transistor, and the fifth MOS transistor are connected as input;
[0010] The drain of the fourth MOS transistor is connected in series with the source of the fifth MOS transistor, the source of the fourth MOS transistor is connected to the source of the sixth MOS transistor, and the drain of the fourth MOS transistor is connected to the gate of the sixth MOS transistor, forming a first positive feedback circuit;
[0011] The drain of the first MOS tube is connected in series with the source of the second MOS tube, the source of the second MOS tube is connected to the source of the third MOS tube, and the drain of the second MOS tube is connected to the gate of the third MOS tube, forming a second positive feedback circuit;
[0012] The drain of the second MOS tube and the drain of the fourth MOS tube serve as outputs.
[0013] In one embodiment, the drain of the third MOS transistor and the source of the fifth MOS transistor are both connected to the power supply, and the source of the first MOS transistor and the drain of the sixth MOS transistor are both grounded.
[0014] In one embodiment, the two sets of positive feedback lines further include a first resistor, a second resistor, and a third resistor;
[0015] One end of the first resistor is connected to the source of the fourth MOS transistor, and the other end is connected to the drain of the second MOS transistor and the drain of the fourth MOS transistor;
[0016] One end of the second resistor is connected to the source of the second MOS transistor, and the other end is connected to the drain of the second MOS transistor and the drain of the fourth MOS transistor;
[0017] One end of the third resistor is connected to the drain of the sixth MOS transistor, and the other end is connected to the drain of the second MOS transistor and the drain of the fourth MOS transistor.
[0018] In one embodiment, improving the chip layout of the Schmitt circuit includes:
[0019] The gate directions of the first MOS tube, the second MOS tube, the third MOS tube, the fourth MOS tube, the fifth MOS tube, and the sixth MOS tube are consistent;
[0020] The gate ends of the first MOS transistor, the second MOS transistor, the fourth MOS transistor, and the fifth MOS transistor are opposite to each other, and the gate ends of the third MOS transistor and the sixth MOS transistor are opposite to each other.
[0021] In one embodiment, the first MOS transistor, the second MOS transistor, the third MOS transistor, and the fourth MOS transistor, the fifth MOS transistor, and the sixth MOS transistor are arranged on two sides and are spaced apart by a preset distance.
[0022] In one embodiment, substrates of the fourth MOS transistor, the fifth MOS transistor, and the sixth MOS transistor are all in the same N-well;
[0023] The drain of the fifth MOS transistor and the drain of the fourth MOS transistor share a P active region and have the same size.
[0024] In one embodiment, the number of inverters is two.
[0025] In a second aspect, the present invention further provides a Schmitt shaping system, comprising the Schmitt shaping circuit provided in the first aspect, and a digital logic circuit connected to the Schmitt shaping circuit.
[0026] The present invention provides a Schmitt shaping circuit and system, comprising an electrically connected improved Schmitt circuit and a power-off design circuit. The improved Schmitt circuit includes two sets of positive feedback circuits for offsetting the rising and falling phases of the input signal, thereby eliminating irregular noise within the input signal and outputting a standard square wave. The power-off design circuit includes multiple inverters electrically connected in series, with a polycrystalline resistor connected in series between two connected inverters. This Schmitt shaping circuit can be used in the front end of various digital logic circuits, providing pulse shaping capabilities to alleviate problems such as increased PCB area, low reliability, and increased failure rates.
[0027] Other features and advantages of the present invention will be described in the following description, and in part will become apparent from the description, or understood by practicing the present invention. The purposes and other advantages of the present invention are realized and obtained by the structures particularly pointed out in the description, claims and drawings.
[0028] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS
[0029] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0030] Figure 1 A schematic structural diagram of a Schmitt shaping circuit provided in an embodiment of the present invention;
[0031] Figure 2 A schematic diagram of the specific structure of a Schmitt shaping circuit provided by an embodiment of the present invention;
[0032] Figure 3 A schematic diagram of a chip layout of an improved Schmitt circuit provided by an embodiment of the present invention;
[0033] Figure 4 A schematic diagram of the principle of the Schmidt core function hysteresis process provided by an embodiment of the present invention;
[0034] Figure 5 A traditional plastic surgery effect diagram provided by an embodiment of the present invention;
[0035] Figure 6 This is a diagram showing the shaping effect of a Schmidt shaping circuit provided by an embodiment of the present invention. DETAILED DESCRIPTION
[0036] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions of the present invention will be clearly and completely described below in conjunction with the embodiments. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.
[0037] At present, traditional digital logic chips have problems such as poor anti-interference ability and inability to process irregular signals. This requires adding a dedicated Schmitt trigger chip to the design of digital logic chips. This increases the area of the PCB board and increases the difficulty of design and debugging. At the same time, it has poor reliability and high failure rate.
[0038] Based on this, the present invention provides a Schmitt shaping circuit and system, which can be used in the front end of a digital logic chip and provide a pulse shaping function to alleviate problems such as increased PCB area, low reliability, and increased failure rate.
[0039] To facilitate understanding of this embodiment, a Schmitt shaping circuit disclosed in an embodiment of the present invention is first described in detail. Figure 1 The schematic structural diagram of a Schmitt shaping circuit shown includes an electrically connected improved Schmitt circuit 1 and a power-off design circuit 2 (also known as a high-voltage-allowing or power-off circuit, a buffer circuit).
[0040] In one example, the improved Schmitt circuit 1 can cope with the signal attenuation and deformation problems encountered by digital logic chips and play an anti-interference role. It includes two sets of positive feedback circuits for hedging the rising and falling processes of the input signal to cut off the irregular noise in the input signal and output a standard square wave.
[0041] In one example, the power-off design circuit 2 includes a plurality of inverters electrically connected in sequence, and a polycrystalline resistor is connected in series between two connected inverters. Through this power-off design circuit, effects such as power off and high-voltage input are achieved.
[0042] The Schmitt shaping circuit provided in the embodiment of the present invention can be used in the front end of various digital logic circuits and provide them with a pulse shaping function to alleviate problems such as increased PCB area, low reliability, and increased failure rate.
[0043] For ease of understanding, the embodiment of the present invention provides a specific structure of a Schmitt shaping circuit, see Figure 2 A schematic diagram of the specific structure of a Schmitt shaping circuit is shown.
[0044] Figure 2 As shown, the two sets of positive feedback lines include a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, and a sixth MOS transistor. The first MOS transistor, the second MOS transistor, and the third MOS transistor are all NMOS transistors, denoted as NMOS transistor M1, NMOS transistor M2, and NMOS transistor M3; the fourth MOS transistor, the fifth MOS transistor, and the sixth MOS transistor are all PMOS transistors, denoted as PMOS transistor M4, PMOS transistor M5, and PMOS transistor M6.
[0045] Furthermore, the gates of the NMOS transistor M1 , the NMOS transistor M2 , the PMOS transistor M4 and the PMOS transistor M5 are connected to serve as inputs of the irregular waveform; the drains of the NMOS transistor M2 and the PMOS transistor M4 serve as square wave outputs.
[0046] Furthermore, the drain of the PMOS transistor M4 is connected in series with the source of the PMOS transistor M5 , the source of the PMOS transistor M4 is connected to the source of the PMOS transistor M6 , and the drain of the PMOS transistor M4 is connected to the gate of the PMOS transistor M6 , forming a first positive feedback circuit.
[0047] Furthermore, the drain of the NMOS transistor M1 is connected in series with the source of the NMOS transistor M2, the source of the NMOS transistor M2 is connected to the source of the NMOS transistor M3, and the drain of the NMOS transistor M2 is connected to the gate of the NMOS transistor M3, forming a second positive feedback circuit.
[0048] In the above two sets of positive feedback circuits, the drain of the NMOS transistor M3 and the source of the PMOS transistor M5 are both connected to the power supply, and the source of the NMOS transistor M1 and the drain of the PMOS transistor M6 are both grounded.
[0049] For further information, please see Figure 2The two sets of positive feedback lines also include a first resistor R1, a second resistor R2, and a third resistor R3. In one example, the first resistor R1 and the second resistor R2 are added between the two sets of positive feedback lines, and the third resistor R3 is pulled down at the Schmitt output. Specifically, one end of the first resistor R1 is connected to the source of the PMOS transistor M4, and the other end is connected to the drain of the NMOS transistor M2 and the drain of the PMOS transistor M4; one end of the second resistor R2 is connected to the source of the NMOS transistor M2, and the other end is connected to the drain of the NMOS transistor M2 and the drain of the PMOS transistor M4; one end of the third resistor R3 is connected to the drain of the PMOS transistor M6, and the other end is connected to the drain of the NMOS transistor M2 and the drain of the PMOS transistor M4.
[0050] Please continue to see Figure 2 In the embodiment of the present invention, the number of inverters is two, that is, two inverters are added after the output of the Schmidt circuit is improved, and a polycrystalline resistor is connected in the middle to serve as a buffer circuit.
[0051] Furthermore, an embodiment of the present invention provides a chip layout for improving the Schmitt circuit, which realizes the IP of the chip layout and reduces the design area. At the same time, the layout of each MOS tube can achieve good isolation, so that the irregular waveform of the input cannot be transmitted to the output and affect the square wave output.
[0052] See also Figure 3 The schematic diagram of the chip layout of an improved Schmitt circuit is shown, which includes six MOS transistors. Among them, the NMOS transistor M1 adopts three transistors in parallel with a width-to-length ratio of 60-100, which can facilitate the adjustment when the threshold needs to be adjusted. The NMOS transistor M2, PMOS transistor M4, PMOS transistor M5, and PMOS transistor M6 adopt two transistors in parallel with width-to-length ratios of 60-100, 50-80, 50-80, and 70-120, respectively. The NMOS transistor M3 adopts a single transistor with a width-to-length ratio of 10-30, which can effectively reduce the gate parasitic resistance.
[0053] Furthermore, the gates of all MOS transistors are in the same direction, that is, the gates of the NMOS transistor M1 , the NMOS transistor M2 , the NMOS transistor M3 , the PMOS transistor M4 , the PMOS transistor M5 , and the PMOS transistor M6 are in the same direction.
[0054] Furthermore, the gate ends of the NMOS transistor M1 , the NMOS transistor M2 , the PMOS transistor M4 , and the PMOS transistor M5 are opposite to each other, and the gate ends of the NMOS transistor M3 and the PMOS transistor M6 are opposite to each other.
[0055] Furthermore, the NMOS and PMOS transistors are arranged on opposite sides, and to prevent latch-up, a certain distance is maintained between the NMOS and PMOS transistors. That is, the NMOS transistors M1, M2, and M3 are arranged on opposite sides of the PMOS transistors M4, M5, and M6, and are spaced apart by a predetermined distance.
[0056] Furthermore, the substrates of all the PMOS transistors (including the PMOS transistor M4 , the PMOS transistor M5 , and the PMOS transistor M6 ) are in the same N-well and connected to VDD.
[0057] Furthermore, the source terminal of the PMOS transistor M5 is connected to VDD, and the drain terminal is connected to the source terminal of the PMOS transistor M4.
[0058] Furthermore, the drain of the PMOS transistor M5 and the drain of the PMOS transistor M4 share a P active region and have the same size.
[0059] Furthermore, the gate terminals of the multi-MOS tube parallel device extend out of the active area by a certain distance, ensuring that the source and drain metals of the device can be connected from the left and right.
[0060] Furthermore, the layout IP is based on the P-substrate N-well CMOS process, and the gate length L takes the minimum process size, which can reduce both the layout area and the parasitic resistance and capacitance.
[0061] Based on the above-mentioned Schmitt shaping circuit and the corresponding chip layout IP, the working principle of the embodiment of the present invention is explained as follows:
[0062] When a Schmitt shaping circuit is used for pulse shaping, it typically occurs in circuits with oscillating waveforms or long-distance transmission. When the output waveform exhibits noise, reflections, overshoot, or slowed rise and fall times, the Schmitt shaping circuit's most important characteristic is its ability to transform slowly varying input signals, noise, reflections, and overshoot into square wave pulses with sharp edges. Furthermore, the Schmitt shaping circuit can utilize its hysteresis voltage to improve the circuit's anti-interference capability.
[0063] The biggest difference between the Schmitt shaping circuit and the buffer is that the rising and falling flip thresholds of the Schmitt shaping circuit are different, and there is hysteresis. Hysteresis means that if the input noise, overshoot, emission, etc. are within the hysteresis range, the output will not flip, such as Figure 4 A schematic diagram of the principle of the Schmidt core function hysteresis process is shown.
[0064] Traditional shaping circuits, for example, a comparator has only one threshold voltage for comparison. If noise at the input crosses the threshold voltage multiple times, the output will be disturbed, and its positive and negative states will switch abnormally, such as Figure 5 A traditional plastic surgery effect diagram is shown.
[0065] The Schmitt shaping circuit provided in this embodiment of the present invention primarily implements hysteresis, which is achieved using PMOS transistor M6 and NMOS transistor M3. When the output is high, NMOS transistor M3 turns on, PMOS transistors M4 and M5 turn on, and PMOS transistor M6 turns off, providing a path from VDD to the output. When the output is low, PMOS transistor M6 turns on, NMOS transistors M1 and M2 turn on, and NMOS transistor M3 turns off, providing a path from the output to ground. The first and second resistors R1 and R2 provide acceleration feedback.
[0066] The Schmidt shaping circuit provided in an embodiment of the present invention has two flip thresholds. When the input rises from a low level to a high level, the output switches from a high level to a low level. This threshold is called the positive flip threshold VT+. When the input rises from a high level to a low level, the output switches from a low level to a high level. This threshold is called the negative flip threshold VT-. The difference between the two is the hysteresis interval.
[0067] First, let's explain the process of a positive input conversion. When the input is 0 and the output is high, NMOS transistors M1 and M2 are off, while NMOS transistor M3 is on. The voltage at point A is equal to the source voltage of NMOS transistor M3, i.e., VA = VDD - Vth3. As the input Vin increases from 0 to VDD, VA remains at VDD - Vth3 until Vin falls below the threshold voltage Vth1 of NMOS transistor M1. When Vin increases above Vth1, NMOS transistor M1 turns on, and the voltage at point A begins to decrease due to the conduction of NMOS transistor M1. Since the voltage at the source of NMOS transistor M2, i.e., point A, is not 0V, NMOS transistor M2 turns on after NMOS transistor M1, which is the source of hysteresis. When Vin increases until Vin-VA=Vth2, NMOS tube M2 is turned on. Once NMOS tube M2 is turned on, the output begins to decrease, causing NMOS tube M3 to slowly turn off, causing point A to further drop, and the voltage at point A to drop. At the same time, the input Vin increases, causing NMOS tube M2 to turn on faster, the output to drop faster, causing NMOS tube M3 to turn off faster, and finally NMOS tube M1 and NMOS tube M2 to be fully turned on. This is a positive feedback process.
[0068] The Vin at which the NMOS tube M2 starts to conduct is defined as the positive flip voltage VT+:
[0069] VT + =V A +Vth2 (1)
[0070] When the NMOS tube M2 is turned on, the currents of the NMOS tubes M1 and M3 are equal, and we get:
[0071]
[0072] Where: Un is the electron migration rate. Cox is the gate oxide capacitance per unit area. W / L is the oxide layer width-to-length ratio.
[0073] Since the source terminals of NMOS transistors M2 and M3 are short-circuited, the body terminals of NMOS transistors M2 and M3 are both grounded, so Vth2 = Vth3. Substituting (1) into (2), we get:
[0074]
[0075] Since the source and body terminals of the NMOS transistor M1 are short-circuited, the NMOS transistor M1 has no body effect, while the NMOS transistors M2 and M3 have body effects, so Vth1 is smaller than Vth2 and Vth3.
[0076] The process of negative conversion of input is similar.
[0077] The embodiment of the present invention provides a Schmitt shaping circuit. In summary, it is necessary to give a VT+ and VT- according to the design indicators. According to the above formula, the size ratio of the NMOS tube M1, the PMOS tube M5 and the NMOS tube M3, the PMOS tube M6 can be obtained. The size of the NMOS tube M2 and the PMOS tube M4 is larger than the size of the NMOS tube M1, the PMOS tube M5 and the NMOS tube M3, the PMOS tube M6. This is because the NMOS tube M2 and the PMOS tube M4 are used as a switch. If it is faster in the positive feedback loop, it will be beneficial to positive feedback. On this basis, the embodiment of the present invention provides the following: Figure 6 The shaping effect diagram of a Schmitt shaping circuit shown in FIG. 1 shows that the Schmitt shaping circuit provided by the embodiment of the present invention has a good shaping effect.
[0078] For the Schmitt shaping circuit provided by the embodiment of the present invention, L does not need to be particularly small for low-frequency circuit chips, and W / L cannot be too large for low-power circuits, otherwise the power consumption will not meet the parameters.
[0079] The above fully explains the design principle of the positive and negative flip threshold voltage and the size design basis of each tube. According to the circuit requirements, you can design the tube size by giving VT+ and VT- yourself, and obtain different VT+ and VT- by changing the tube size.
[0080] Based on the above-mentioned embodiments, an embodiment of the present invention provides a Schmitt shaping system, including the above-mentioned Schmitt shaping circuit and a digital logic circuit connected to the Schmitt shaping circuit. The Schmitt shaping circuit can be used at the front end of various digital logic circuits and provide them with a pulse shaping function to alleviate problems such as increased PCB area, low reliability, and increased failure rate.
[0081] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working process of the Schmidt shaping system described above can refer to the corresponding process in the aforementioned embodiment and will not be repeated here.
[0082] In the description of the embodiments of the present invention, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; mechanical connections or electrical connections; direct connections or indirect connections through an intermediate medium; and internal connections between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on the specific circumstances.
[0083] In the description of the present invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate and simplify the description of the present invention. They are not intended to indicate or imply that the devices or components referred to must have, be constructed, or operate in a specific orientation, and therefore should not be construed as limitations on the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0084] Finally, it should be noted that the above-described embodiments are only specific implementation methods of the present invention, which are used to illustrate the technical solutions of the present invention, rather than to limit them. The scope of protection of the present invention is not limited thereto. Although the present invention has been described in detail with reference to the above-described embodiments, those skilled in the art should understand that any person skilled in the art can modify or easily conceive of changes to the technical solutions described in the above-described embodiments within the technical scope disclosed by the present invention, or replace some of the technical features therein with equivalents. Such modifications, changes, or replacements do not deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be subject to the scope of protection of the claims.
Claims
1. A Schmitt shaping circuit, characterized in that: Including improved Schmitt circuit and power-off design circuit with electrical connection; The improved Schmitt circuit includes two sets of positive feedback circuits for performing hedging processing on the rising process and the falling process of the input signal to cut off the irregular noise in the input signal and output a standard square wave; The power-off design circuit includes a plurality of inverters electrically connected in sequence, and a polycrystalline resistor is connected in series between two connected inverters.
2. The Schmidt shaping circuit according to claim 1, wherein: The two groups of positive feedback lines include a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, and a sixth MOS transistor; The first MOS transistor, the second MOS transistor and the third MOS transistor are all NMOS transistors, and the fourth MOS transistor, the fifth MOS transistor and the sixth MOS transistor are all PMOS transistors.
3. The Schmidt shaping circuit according to claim 2, wherein: The gates of the first MOS transistor, the second MOS transistor, the fourth MOS transistor and the fifth MOS transistor are connected as input; The drain of the fourth MOS transistor is connected in series with the source of the fifth MOS transistor, the source of the fourth MOS transistor is connected to the source of the sixth MOS transistor, and the drain of the fourth MOS transistor is connected to the gate of the sixth MOS transistor, forming a first positive feedback circuit; The drain of the first MOS transistor is connected in series with the source of the second MOS transistor, the source of the second MOS transistor is connected to the source of the third MOS transistor, and the drain of the second MOS transistor is connected to the gate of the third MOS transistor, forming a second positive feedback circuit; The drain of the second MOS transistor and the drain of the fourth MOS transistor serve as outputs.
4. The Schmidt shaping circuit according to claim 2, wherein: The drain of the third MOS transistor and the source of the fifth MOS transistor are both connected to a power supply, and the source of the first MOS transistor and the drain of the sixth MOS transistor are both grounded.
5. The Schmitt shaping circuit according to claim 2, wherein: The two groups of positive feedback lines further include a first resistor, a second resistor and a third resistor; One end of the first resistor is connected to the source of the fourth MOS transistor, and the other end is connected to the drain of the second MOS transistor and the drain of the fourth MOS transistor; One end of the second resistor is connected to the source of the second MOS transistor, and the other end is connected to the drain of the second MOS transistor and the drain of the fourth MOS transistor; One end of the third resistor is connected to the drain of the sixth MOS transistor, and the other end is connected to the drain of the second MOS transistor and the drain of the fourth MOS transistor.
6. The Schmitt shaping circuit according to claim 2, wherein: The chip layout of the improved Schmitt circuit includes: The gate directions of the first MOS transistor, the second MOS transistor, the third MOS transistor, the fourth MOS transistor, the fifth MOS transistor, and the sixth MOS transistor are consistent; The gate ends of the first MOS transistor, the second MOS transistor, the fourth MOS transistor, and the fifth MOS transistor are opposite to each other, and the gate ends of the third MOS transistor and the sixth MOS transistor are opposite to each other.
7. The Schmidt shaping circuit according to claim 6, wherein: The first MOS transistor, the second MOS transistor, the third MOS transistor, and the fourth MOS transistor, the fifth MOS transistor, and the sixth MOS transistor are arranged on two sides and are spaced apart by a preset distance.
8. The Schmitt shaping circuit according to claim 6, wherein: The substrates of the fourth MOS transistor, the fifth MOS transistor, and the sixth MOS transistor are all in the same N-well; The drain of the fifth MOS transistor and the drain of the fourth MOS transistor share a P active region and have the same size.
9. The Schmitt shaping circuit according to claim 1, wherein: The number of the inverters is two.
10. A Schmidt shaping system, characterized in that: The device comprises the Schmitt shaping circuit according to any one of claims 1 to 9, and a digital logic circuit connected to the Schmitt shaping circuit.