High-speed ADC clock jitter measurement method and device

Abstract

The invention provides a high-speed ADC clock jitter measurement method and device, and relates to the technical field of high-speed and high-precision analog-digital conversion. Comprising the following steps: setting coprime coherence of an input sinusoidal signal and a sampling clock signal, and determining a sampling sequence according to the frequency and clock jitter of the input sinusoidal signal; according to the gain mismatch, the phase offset and the detuning mismatch, separating an output sequence of the sub-channel from the sampling sequence, and determining an output sequence amplitude according to the amplitude and the gain mismatch; determining a sub-channel jitter error sequence according to the output sequence of the sub-channel, and calculating an autocorrelation function of the sub-channel jitter error sequence according to a mean value of the sub-channel jitter error sequence; according to the autocorrelation function of the sub-channel jitter error sequence, the standard deviation of additive white noise and the excitation of time delay, the total cyclic spectral density is determined through Fourier transform; and determining the standard deviation of clock jitter according to the total cyclic spectral density, the output sequence amplitude and the frequency of the input sinusoidal signal. Therefore, the test precision of the clock jitter is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of high-speed and high-precision analog-to-digital conversion, and in particular to a method and device for measuring clock jitter of a high-speed analog-to-digital converter (ADC). Background Art

[0002] Time-interleaved analog-to-digital converters (TIADCs), by virtue of their ability to overcome the limitations of the Nyquist sampling theorem, have become a key technology for achieving GHz-level sampling rates. TIADC systems convert high-speed signals in the time dimension into multiple, lower-speed signals through alternating sampling of parallel sub-channels. However, clock jitter is a significant factor affecting TIADC performance, especially at very high sampling frequencies. Clock jitter can lead to sampling uncertainty, reducing the signal-to-noise ratio (SNR) and spurious-free dynamic range (SFDR), ultimately impacting overall system performance. Figure 1 The effect of clock jitter on ADC sampling is shown schematically. Figure 1 As shown in Figure 2, the ideal clock signal edges should be equally spaced, but in practice, due to jitter, the sampling times are scattered within a time range, which directly leads to the deviation between the quantized value and the actual analog signal. Figure 1 As shown in the figure, the two curves are low-frequency and high-frequency signals, respectively. Taking both low-frequency and high-frequency signals as input signals, the higher the input signal frequency, the more obvious the deviation between the quantized value and the actual analog signal. Therefore, in applications where high-frequency signal sampling is required, the impact of clock jitter is particularly prominent. Figure 2 The effect of clock jitter on ADC signal-to-noise ratio is shown schematically. Figure 2 The following figure shows four traces of SNR degradation caused by jitter, with jitter durations of 50, 100, 200, and 500 femtoseconds, respectively. When the input frequency increases from 10 MHz to 100 MHz, the SNR drops by 20 dB due to a jitter duration of 100 femtoseconds. In practice, the most common type of clock jitter is random jitter (RJ), which follows a Gaussian distribution. Therefore, measuring the standard deviation of random jitter is particularly important.

[0003] Currently, random jitter standard deviation can be measured using a method that utilizes cyclostationary random variance. This method is primarily targeted at single-channel ADCs and requires sorting the output sampling sequence by phase magnitude while accurately estimating the signal's phase offset. However, additive white noise, such as thermal noise, can affect measurement results. Applying this method to multichannel ADCs can also lead to interference between channel mismatches, such as clock deviation and offset mismatch, between different channels of the TIADC. This can interfere with jitter calculations, resulting in lower clock jitter test accuracy. Summary of the Invention

[0004] The purpose of the embodiments of the present invention is to provide a method and device for measuring clock jitter of a high-speed ADC, so as to solve the problem of low test accuracy of clock jitter.

[0005] To solve the above technical problems, the embodiments of the present invention provide the following technical solutions:

[0006] A first aspect of the present invention provides a high-speed ADC clock jitter measurement method, comprising:

[0007] The input sinusoidal signal and the sampling clock signal are set to be mutually prime and coherent to obtain the frequency of the input sinusoidal signal, and the sampling sequence is determined according to the frequency of the input sinusoidal signal, the amplitude of the input sinusoidal signal, the sampling time, the clock jitter and the initial phase of the input sinusoidal signal;

[0008] Separating the output sequence of the sub-channel from the sampling sequence according to the gain mismatch caused by the sub-channel, the phase offset caused by the clock deviation of the sub-channel, and the offset mismatch caused by the sub-channel, and determining the amplitude of the output sequence under the influence of the gain mismatch of the sub-channel according to the amplitude and the gain mismatch;

[0009] Determine a sub-channel jitter error sequence according to the output sequence of the sub-channel, and calculate an autocorrelation function of the sub-channel jitter error sequence according to a mean value of the sub-channel jitter error sequence;

[0010] Determine the total cyclic spectral density of the sub-channel jitter error sequence using Fourier transform based on the autocorrelation function of the sub-channel jitter error sequence, the standard deviation of the additive white noise, and the delayed excitation;

[0011] The standard deviation of the clock jitter is determined based on the total cyclic spectral density, the output sequence amplitude, and the frequency of the input sinusoidal signal. The standard deviation of the clock jitter is used to evaluate and optimize the analog-to-digital conversion system.

[0012] A second aspect of the present invention provides a high-speed ADC clock jitter measurement device, comprising:

[0013] A setting module is used to set the input sinusoidal signal and the sampling clock signal to be mutually prime and coherent, obtain the frequency of the input sinusoidal signal, and determine the sampling sequence according to the frequency of the input sinusoidal signal, the amplitude of the input sinusoidal signal, the sampling time, the clock jitter and the initial phase of the input sinusoidal signal;

[0014] a separation module, configured to separate an output sequence of the sub-channel from the sampling sequence according to a gain mismatch caused by the sub-channel, a phase offset caused by a clock deviation of the sub-channel, and an offset mismatch caused by the sub-channel, and determine an amplitude of the output sequence under the influence of the gain mismatch of the sub-channel according to the amplitude and the gain mismatch;

[0015] a calculation module, configured to determine a sub-channel jitter error sequence according to an output sequence of the sub-channel, and calculate an autocorrelation function of the sub-channel jitter error sequence according to a mean value of the sub-channel jitter error sequence;

[0016] A first determining module is configured to determine a total cyclic spectral density of the sub-channel jitter error sequence by using Fourier transform according to an autocorrelation function of the sub-channel jitter error sequence, a standard deviation of additive white noise, and a delayed excitation;

[0017] The second determination module is used to determine the standard deviation of the clock jitter according to the total cyclic spectral density, the output sequence amplitude and the frequency of the input sinusoidal signal. The standard deviation of the clock jitter is used to evaluate and optimize the analog-to-digital conversion system.

[0018] Compared with the prior art, the high-speed ADC clock jitter measurement method and device provided by the present invention set the input sinusoidal signal and the sampling clock signal to be mutually prime and coherent, obtain the frequency of the input sinusoidal signal, and determine the sampling sequence according to the frequency of the input sinusoidal signal, the amplitude of the input sinusoidal signal, the sampling time, the clock jitter and the initial phase of the input sinusoidal signal; separate the output sequence of the sub-channel from the sampling sequence according to the gain mismatch caused by the sub-channel, the phase offset caused by the clock deviation of the sub-channel and the offset mismatch caused by the sub-channel, and determine the gain of the sub-channel according to the amplitude and gain mismatch. The output sequence amplitude under the influence of gain mismatch is determined; the sub-channel jitter error sequence is determined based on the output sequence of the sub-channel, and the autocorrelation function of the sub-channel jitter error sequence is calculated based on the mean of the sub-channel jitter error sequence; the total cyclic spectral density of the sub-channel jitter error sequence is determined using Fourier transform based on the autocorrelation function of the sub-channel jitter error sequence, the standard deviation of the additive white noise, and the delayed excitation; the standard deviation of the clock jitter is determined based on the total cyclic spectral density, the output sequence amplitude, and the frequency of the input sinusoidal signal. The standard deviation of the clock jitter is used to evaluate and optimize the analog-to-digital conversion system. In this way, the output sequence of the sub-channel can be separated from the sampling sequence based on the gain mismatch caused by the sub-channel, the phase offset caused by the clock deviation of the sub-channel, and the offset mismatch caused by the sub-channel. This can prevent the interference of inter-channel mismatches such as clock deviation and offset mismatch between different sub-channels of the TIADC on the standard deviation calculation result of the clock jitter, thereby improving the test accuracy of the clock jitter. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The above and other objects, features and advantages of the exemplary embodiments of the present invention will become readily understood by reading the detailed description below with reference to the accompanying drawings. In the accompanying drawings, several embodiments of the present invention are shown in an exemplary and non-limiting manner, and the same or corresponding reference numerals represent the same or corresponding parts, wherein:

[0020] Figure 1 The figure schematically shows the effect of clock jitter on ADC sampling.

[0021] Figure 2 The effect of clock jitter on ADC signal-to-noise ratio is schematically shown;

[0022] Figure 3 The flowchart of the high-speed ADC clock jitter measurement method is schematically shown;

[0023] Figure 4 The figure schematically shows a physical device for measuring high-speed ADC clock jitter;

[0024] Figure 5 Schematically shows a schematic diagram of the total cyclic spectral density of the sub-channel jitter error sequence;

[0025] Figure 6 The structure of a high-speed ADC clock jitter measurement device is schematically shown. DETAILED DESCRIPTION

[0026] Exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of the present invention and to fully convey the scope of the present invention to those skilled in the art.

[0027] It should be noted that, unless otherwise specified, the technical or scientific terms used in the present invention should have the common meanings understood by those skilled in the art to which the present invention belongs.

[0028] The method in the embodiment of the present invention is described in detail below.

[0029] Figure 3 The flowchart of the method for measuring clock jitter of a high-speed ADC in an embodiment of the present invention is schematically shown. Figure 3 As shown, the high-speed ADC clock jitter measurement method may include:

[0030] S301: Set the input sinusoidal signal and the sampling clock signal to be mutually prime and coherent, obtain the frequency of the input sinusoidal signal, and determine the sampling sequence according to the frequency of the input sinusoidal signal, the amplitude of the input sinusoidal signal, the sampling time, the clock jitter and the initial phase of the input sinusoidal signal.

[0031] Figure 4 The schematic diagram of the physical device for measuring high-speed ADC clock jitter shows a clock generator connected to an arbitrary waveform generator, providing it with an external reference clock signal. The clock generator is also connected to the clock input port of the TIADC under test, providing a sampling clock signal. This ensures that the output of the arbitrary waveform generator and the external reference clock signal provided by the clock generator use the same frequency source. The signal output port of the arbitrary waveform generator is connected to the signal input port of the TIADC under test, providing an input sinusoidal signal. Finally, the output port of the TIADC under test is connected to a computer via the JESD204B high-speed serial data transmission interface, transmitting the output data of the TIADC under test to the computer.

[0032] Specifically, step S301 includes:

[0033] Step A1: Based on the number of phase points in each sampling period, use the Nyquist sampling theorem to determine the coprime numbers of the phase points.

[0034] Total sampling N periods cycles, each sampling cycle has Nphase =M phase points, the total sampling time is t s ·N phase ·N periods , where t s is the sampling time interval.

[0035] In the case of satisfying the Nyquist sampling theorem, a number that is relatively prime to the number M of phase points in each sampling period is selected, that is, a number J that is relatively prime to the number M of phase points in each sampling period.

[0036] Step A2: Determine the frequency of the input sinusoidal signal according to the number of phase points, the coprime number of the phase points, and the frequency of the sampling clock signal.

[0037] The frequency of the input sinusoidal signal is expressed as:

[0038]

[0039] Among them, f in is the frequency of the input sinusoidal signal, J is the coprime number of the phase points in each sampling period, M is the phase points in each sampling period, f s is the frequency of the sampling clock signal.

[0040] Step A3: Determine the angular frequency of the input sinusoidal signal according to the frequency of the input sinusoidal signal.

[0041] The angular frequency of the input sinusoidal signal is ω = 2πf in , where ω is the angular frequency of the input sinusoidal signal, f in is the frequency of the input sinusoidal signal.

[0042] Step A4: Determine a sampling sequence according to the angular frequency, the amplitude of the input sinusoidal signal, the sampling time, the clock jitter, and the initial phase of the input sinusoidal signal.

[0043] Modeling and analysis of the sampling sequence under the influence of clock jitter, where ω = 2πf in . Clock jitter t j′ The mean is 0 and the variance is σ 2 Normally distributed random jitter, clock jitter t j′ The order of magnitude is ps or even fs, so cosωt j′ ≈1, sinωt j′ ≈ωt j′ Therefore, the sampling sequence S can be divided into the sampling signal S0 and the error part caused by jitter, namely the jitter error sequence S j′ .

[0044] The expression of the sampling sequence is:

[0045]

[0046] Where S is the sampling sequence, A0 is the amplitude of the input sinusoidal signal, ω is the angular frequency, t is the sampling time, t j′ is the clock jitter, is the initial phase of the input sinusoidal signal, S0 is the sampling signal, S j′ is the jitter error sequence.

[0047] S302. Separate the output sequence of the sub-channel from the sampling sequence based on the gain mismatch caused by the sub-channel, the phase offset caused by the clock deviation of the sub-channel, and the offset mismatch caused by the sub-channel, and determine the amplitude of the output sequence under the influence of the gain mismatch of the sub-channel based on the amplitude and the gain mismatch.

[0048] Specifically, the gain mismatch G caused by the mismatch between TIADC sub-channels i , Phase offset caused by clock deviation of sub-channel Mismatch caused by subchannel O i The expression of the output sequence of the sub-channel is:

[0049]

[0050] S i =S 0i +S j′i +O i ;

[0051] Among them, S i is the output sequence of the ith subchannel, A0 is the amplitude of the input sinusoidal signal, G i is the gain mismatch caused by the i-th sub-channel, ω is the angular frequency, t is the sampling time, is the initial phase of the input sinusoidal signal, is the phase offset caused by the clock deviation of the i-th sub-channel, t j′ is the clock jitter, O i is the offset mismatch caused by the i-th sub-channel; S 0i is the sampling signal of the i-th sub-channel, S j′i is the jitter error sequence of the i-th sub-channel, is the sum of the phase offset caused by the clock deviation of the i-th sub-channel and the initial phase.

[0052] The output sequence amplitude under the influence of gain mismatch is estimated using fast Fourier transform. The expression of the output sequence amplitude is:

[0053] A=A0G i ;

[0054] Among them, A is the amplitude of the output sequence, A0 is the amplitude of the input sinusoidal signal, G i is the gain mismatch caused by the i-th sub-channel.

[0055] S303: Determine a sub-channel jitter error sequence according to the output sequence of the sub-channel, and calculate an autocorrelation function of the sub-channel jitter error sequence according to the mean value of the sub-channel jitter error sequence.

[0056] The sub-channel jitter error sequence includes a sub-channel jitter error sequence at a first time and a sub-channel jitter error sequence at a second time.

[0057] Specifically, determining the sub-channel jitter error sequence according to the sub-channel output sequence includes:

[0058] Step B1: According to the number of phase points in each sampling period and the number of sampling periods, the output sequence of the sub-channel is converted into a corresponding matrix, and the matrix is transposed to obtain a transposed matrix. Each row of the transposed matrix is each sampling period, and each column is a sampling output sequence with the same phase corresponding to the sampling moment.

[0059] Convert the output sequence of the i-th subchannel into the corresponding The matrix, where is the number of phase points per sampling period in the channel, With N phase The relationship is: The number of sub-channels. Each row of the transposed matrix represents each complete sampling period, and each column represents the sampled output sequence of the same phase corresponding to a certain sampling moment.

[0060] Step B2: Calculate the average value of all elements in each column of the transposed matrix to obtain the average value of the sampling signal corresponding to each phase.

[0061] The average value of the sampled signal can be expressed as

[0062] Step B3: Determine the sub-channel jitter error sequence according to the difference between the sub-channel output sequence and the average value of the sampling signal.

[0063] Average value of sampled signal The result contains S 0i +O i , so we can pass To get the sub-channel jitter error sequence S j′i , S j′i The expression is Among them, t j′ The mean is 0 and the variance is σ 2 Normally distributed random jitter with angular frequency ω in radians per second.

[0064] S j′i The expression for the mean of is:

[0065]

[0066] Among them, E(S j′i ) is the mean value of the sub-channel jitter error sequence, S j′i is the sub-channel jitter error sequence, E(t j′ ) is the mean value of clock jitter, t j′ is the clock jitter, A is the output sequence amplitude, ω is the angular frequency, t is the sampling time, is the sum of the phase offset caused by the clock deviation of the i-th sub-channel and the initial phase.

[0067] Specifically, calculating the autocorrelation function of the sub-channel jitter error sequence according to the mean value of the sub-channel jitter error sequence includes:

[0068] Step C1: Determine the average value of the product of the sub-channel jitter error sequence at the first time and the sub-channel jitter error sequence at the second time.

[0069] The mean value of the product of the sub-channel jitter error sequence at the first time and the sub-channel jitter error sequence at the second time is expressed as E(S j′1 ·S j′2 ), where S j′1 is the first time sub-channel jitter error sequence, S j′2 is the sub-channel jitter error sequence at the second time, and E(·) is the mean value.

[0070] Step C2: Determine the mean as the autocorrelation function of the first time and the second time.

[0071] The expressions of the autocorrelation functions of the first time and the second time are:

[0072]

[0073] Among them, R(t1, t2) is the autocorrelation function of the first time and the second time, t1 is the first time, t2 is the second time, S j′1 is the first time sub-channel jitter error sequence, S j′2 is the sub-channel jitter error sequence at the second time, A is the output sequence amplitude, ω is the angular frequency, t j′1 is the random jitter sample at the first time t1, is the sum of the phase offset caused by the clock deviation of the i-th sub-channel and the initial phase, t j′2 is the random jitter sample at the second time t2, E(·) is the mean, δ(·) is the impulse function, t j′1 , tj′2 To satisfy the mean of 0 and the variance of σ 2 , and the samples at different times are unrelated.

[0074] Step C3: Replace the first time in the autocorrelation function of the first time and the second time with the sampling time, and replace the difference between the second time and the first time in the autocorrelation function of the first time and the second time with the delay to obtain the autocorrelation function of the sub-channel jitter error sequence.

[0075] The autocorrelation function R(t1, t2) of the first time and the second time is converted into the form of sampling time t and delay τ, that is, let t1 = t, t2-t1 = τ, and the expression of the autocorrelation function of the sub-channel jitter error sequence can be obtained as follows:

[0076]

[0077] Where R(t,τ) is the autocorrelation function of the sub-channel jitter error sequence, A is the output sequence amplitude, ω is the angular frequency, σ is the standard deviation of the clock jitter, t is the sampling time, and τ is the delay. is the sum of the phase offset caused by the clock deviation of the i-th subchannel and the initial phase. δ(·) is the impulse function. When τ is 0, the value of δ(·) is 1. Except for the case where τ is 0, the value of δ(·) is 0.

[0078] According to the definition of cyclostationary random process, if the mean and autocorrelation function of the random process are periodic functions with time T as the period, then the random process is generalized cyclostationary, and it can be seen that the sub-channel jitter error sequence S j′i is cyclostationary, and its period is Therefore, we can deeply analyze the cyclostationary characteristics of the sub-channel jitter error sequence, solve the total cyclic autocorrelation function and total cyclic spectral density of the sub-channel jitter error sequence, observe the relationship between the clock jitter standard deviation σ and the cyclic spectral density, and then reversely infer σ.

[0079] S304 : Determine the total cyclic spectral density of the sub-channel jitter error sequence by Fourier transform according to the autocorrelation function of the sub-channel jitter error sequence, the standard deviation of the additive white noise, and the delayed excitation.

[0080] The subchannel jitter error sequence is a cyclostationary random sequence. The autocorrelation function R(t,τ) of the subchannel jitter error sequence is a function of the sampling time t and the delay τ, and has periodicity (period T) with respect to the sampling time t.

[0081] Specifically, the total cyclic spectral density of the sub-channel jitter error sequence is determined using Fourier transform according to the autocorrelation function of the sub-channel jitter error sequence, the standard deviation of the additive white noise, and the delayed excitation, including:

[0082] Step D1: Determine the autocorrelation function of the additive white noise based on the standard deviation of the additive white noise and the delayed excitation.

[0083] In practice, the output sequence S of the subchannel i It is also affected by the additive white noise S ni (S ni The mean is 0 and the variance is The influence of the normal distribution) and S ni With S j′i Output sequence S of the subchannel i The influence of is independent, since additive white noise is a stationary process, the expression of the autocorrelation function of additive white noise is:

[0084]

[0085] Among them, R noise (τ) is the autocorrelation function of additive white noise, σ a is the standard deviation of the additive white noise, τ is the delay, and δ(·) is the impulse function.

[0086] Step D2: Determine a total autocorrelation function based on the autocorrelation function of the sub-channel jitter error sequence and the autocorrelation function of the additive white noise.

[0087] S j′i With S ni To S i The error term caused by is analyzed together, and the expression of the total autocorrelation function is:

[0088] R total (t,τ)=R noise (τ)+R(t,τ);

[0089] Among them, R total (t,τ) is the total autocorrelation function, R noise (τ) is the autocorrelation function of the additive white noise, and R(t,τ) is the autocorrelation function of the sub-channel jitter error sequence.

[0090] Step D3: Decompose the total autocorrelation function using a Fourier series expression to obtain a total cyclic autocorrelation function.

[0091] The expression of the total cyclic autocorrelation function is:

[0092]

[0093] in, is the total cyclic autocorrelation function, T is the period, R total (t,τ) is the total autocorrelation function, α is the cycle frequency, and k is the coefficient, which is an integer.

[0094] The total cyclic autocorrelation function R total Substitute (t,τ) into the total cyclic autocorrelation function The expression of the total cyclic autocorrelation function is solved as follows:

[0095]

[0096] in, is the total cyclic autocorrelation function, A is the output sequence amplitude, ω is the angular frequency, σ is the standard deviation of the clock jitter, τ is the delay, δ(·) is the impulse function, σ a is the standard deviation of the additive white noise, δ(α) is the impulse function of the cyclic frequency, and j is the imaginary unit.

[0097] Step D4: Perform Fourier transform on the total cyclic autocorrelation function to obtain the total cyclic spectral density of the sub-channel jitter error sequence.

[0098] The total cyclic spectral density is the Fourier transform of the total cyclic autocorrelation function with respect to the time delay τ. The expression of the total cyclic spectral density is:

[0099]

[0100] in, is the total cyclic spectral density of the sub-channel jitter error sequence, is the total cyclic autocorrelation function, and f is the frequency variable.

[0101] The total cyclic autocorrelation function Substitute the total cyclic spectral density of the sub-channel jitter error sequence into Solving the expression of , we can get the expression of the total cyclic spectral density of the sub-channel jitter error sequence:

[0102]

[0103] in, is the total cyclic spectral density of the sub-channel jitter error sequence, A is the output sequence amplitude, ω is the angular frequency, σ is the standard deviation of the clock jitter, σ a is the standard deviation of additive white noise, α is the cycle frequency, f in is the frequency of the input sinusoidal signal, is the sum of the phase offset caused by the clock deviation of the i-th sub-channel and the initial phase, and j is an imaginary unit.

[0104] So far we can see that due to Therefore, the offset mismatch and clock deviation caused by the TIADC inter-channel mismatch do not affect the amplitude of the cyclic spectrum. However, the output sequence amplitude A under the influence of the gain mismatch can be estimated using Fourier transform in step S102. In addition, because additive white noise is a stationary process, its cyclic spectrum is non-zero only at α = 0.

[0105] Figure 5 The total cyclic spectral density of the sub-channel jitter error sequence is schematically shown, see Figure 5 As shown in the figure, the horizontal axis is the cyclic frequency, and the vertical axis is the cyclic spectral density amplitude of the sub-channel jitter error sequence. The total cyclic spectral density of the jitter sequence output by a certain channel of the TIADC with and without the influence of additive white noise is respectively shown. It can be seen that the sub-channel jitter error sequence is a cyclostationary random sequence, and its cyclic spectrum exhibits specific frequency components in the cyclic frequency domain. The non-zero cyclic frequency describes the cyclostationary characteristics of the sub-channel jitter error sequence, and the zero cyclic frequency corresponds to the stationary part of the sub-channel jitter error sequence. The additive white noise is a stationary random sequence, and its cyclic spectrum has only one component at the zero cyclic frequency in the cyclic frequency domain, that is, when the cyclic frequency is 0, it contains the stationary part of the sub-channel jitter error sequence and the frequency component of the additive white noise, a stationary random sequence. Only the jitter sequence with a non-zero cyclic frequency exhibits a specific frequency component in the cyclic frequency domain.

[0106] S305 , determining a standard deviation of the clock jitter according to the total cyclic spectral density, the output sequence amplitude, and the frequency of the input sinusoidal signal. The standard deviation of the clock jitter is used to evaluate and optimize the analog-to-digital conversion system.

[0107] Additive white noise does not affect the results at non-zero cyclic frequencies, so the calculation of the standard deviation of clock jitter can directly calculate the cyclic frequency as 2f in The amplitude of the total cyclic spectral density at is used to calculate the standard deviation of the clock jitter using the following formula.

[0108] Specifically, the expression for the standard deviation of clock jitter is:

[0109]

[0110] Where σ is the standard deviation of clock jitter, is the total cyclic spectral density of the sub-channel jitter error sequence, f is the frequency variable, A is the output sequence amplitude, f in is the frequency of the input sinusoidal signal, and α is the cycle frequency.

[0111] The clock jitter standard deviation calculated by the present invention is a key metric for evaluating and optimizing the performance of analog-to-digital conversion systems. It directly reflects the impact of the clock signal's timing accuracy on ADC sampling quality. Using this quantified parameter, the signal-to-noise ratio (SNR) dynamic range upper limit at the input signal frequency can be predicted using a signal-to-noise ratio (SNR) prediction model. This provides a benchmark for effective number of bits (ENR) calibration and guides the identification and optimization of noise sources in high-speed ADC design. In practical applications, this clock jitter standard deviation is not only used to verify whether a chip meets the ADC jitter requirements specified in the IEEE 1241-2010 standard, supporting chip reliability certification and aging monitoring, but also guides clock tree design and parameter optimization of digital post-compensation algorithms for high-speed sampling systems. For example, in high-frequency applications such as 5G communications or radar, an excessively large clock jitter standard deviation can indicate the need to improve the clock source or adjust the PCB layout. For time-interleaved ADC systems, differential analysis of the jitter standard deviations of each subchannel helps identify and resolve inter-channel timing mismatches. Therefore, the clock jitter standard deviation provided by the present invention not only has theoretical analytical value but also serves as an indispensable engineering decision-making basis throughout the entire lifecycle of high-speed ADCs, from design and testing to maintenance.

[0112] The concept of the present invention is that the sub-channel jitter error sequence is a cyclostationary random sequence, and the cyclic spectrum of the cyclostationary random sequence is used to express specific frequency components in the cyclic frequency domain. The cyclic frequency reflects the periodic characteristics of the signal in time, the non-zero cyclic frequency describes the cyclostationary characteristics of the signal, and the zero cyclic frequency corresponds to the stationary part of the signal. By modeling and analyzing the TIADC sampling sequence under the influence of clock jitter, it is modeled as a cyclostationary random process, and the output sequence of each sub-channel is separated. The total cyclic spectral density of the sub-channel jitter error sequence is solved, and the value of the cyclic spectrum corresponding to the non-zero cyclic frequency is extracted. Finally, the standard deviation of the clock jitter is calculated.

[0113] Starting from the characteristics of cyclostationary random sequences, the present invention can ignore the influence of stationary noise such as white noise on the standard deviation calculation results of clock jitter. By solving and extracting the cyclic spectrum amplitude, it can also be immune to the influence of clock deviation and offset mismatch in different sub-channels of TIADC. In addition, the measuring device is simple, requiring only general instruments (i.e., arbitrary waveform generator, clock generator, high-speed serial data transmission interface and computer), without the need for special jitter analysis equipment, and has low cost. The advantages of low computational complexity and high result accuracy of the present invention are not only suitable for TIADC sub-channel clock jitter testing, but can also be widely used in the measurement scenario of single-channel analog-to-digital converter clock jitter, and have broad application prospects. The present invention exhibits a high degree of anti-interference characteristics, which can effectively suppress the influence of additive white noise such as thermal noise on the test results, and ensure the stability and reliability of the test process.

[0114] Based on the above Figure 1 As can be seen from the implementation method, the embodiment of the present invention sets the input sinusoidal signal and the sampling clock signal to be mutually prime and coherent to obtain the frequency of the input sinusoidal signal, and determines the sampling sequence based on the frequency of the input sinusoidal signal, the amplitude of the input sinusoidal signal, the sampling time, the clock jitter, and the initial phase of the input sinusoidal signal. The output sequence of the subchannel is separated from the sampling sequence based on the gain mismatch caused by the subchannel, the phase offset caused by the clock deviation of the subchannel, and the offset mismatch caused by the subchannel. The amplitude of the output sequence under the influence of the subchannel gain mismatch is determined based on the amplitude and gain mismatch. The subchannel jitter error sequence is determined based on the subchannel output sequence, and the autocorrelation function of the subchannel jitter error sequence is calculated based on the mean of the subchannel jitter error sequence. The total cyclic spectral density of the subchannel jitter error sequence is determined using Fourier transform based on the autocorrelation function of the subchannel jitter error sequence, the standard deviation of additive white noise, and the delayed excitation. The standard deviation of the clock jitter is determined based on the total cyclic spectral density, the output sequence amplitude, and the frequency of the input sinusoidal signal. The standard deviation of the clock jitter is used to evaluate and optimize the analog-to-digital conversion system. In this way, the output sequence of the sub-channel can be separated from the sampling sequence based on the gain mismatch caused by the sub-channel, the phase offset caused by the clock deviation of the sub-channel, and the offset mismatch caused by the sub-channel. This can make the interference of the inter-channel mismatches such as clock deviation and offset mismatch between different sub-channels of TIADC on the standard deviation calculation results of the clock jitter immune, thereby improving the test accuracy of the clock jitter.

[0115] Based on the same inventive concept, as an implementation of the above-mentioned high-speed ADC clock jitter measurement method, an embodiment of the present invention further provides a high-speed ADC clock jitter measurement device. Figure 6 is a structural diagram of the device in the embodiment of the present invention, see Figure 6 As shown, the device may include:

[0116] A setting module 601 is used to set the input sinusoidal signal and the sampling clock signal to be mutually prime and coherent, obtain the frequency of the input sinusoidal signal, and determine the sampling sequence according to the frequency of the input sinusoidal signal, the amplitude of the input sinusoidal signal, the sampling time, the clock jitter, and the initial phase of the input sinusoidal signal;

[0117] a separation module 602 for separating the output sequence of the subchannel from the sampling sequence based on the gain mismatch caused by the subchannel, the phase offset caused by the clock deviation of the subchannel, and the offset mismatch caused by the subchannel, and determining the amplitude of the output sequence under the influence of the gain mismatch of the subchannel based on the amplitude and the gain mismatch;

[0118] A calculation module 603 is configured to determine a sub-channel jitter error sequence according to an output sequence of the sub-channel, and calculate an autocorrelation function of the sub-channel jitter error sequence according to a mean value of the sub-channel jitter error sequence;

[0119] A first determining module 604 is configured to determine a total cyclic spectral density of the sub-channel jitter error sequence by Fourier transform based on an autocorrelation function of the sub-channel jitter error sequence, a standard deviation of additive white noise, and a delayed excitation;

[0120] The second determination module 605 is configured to determine a standard deviation of the clock jitter according to the total cyclic spectral density, the output sequence amplitude, and the frequency of the input sinusoidal signal. The standard deviation of the clock jitter is used to evaluate and optimize the analog-to-digital conversion system.

[0121] The setting module 601 is specifically used to determine the coprime number of the phase points according to the number of phase points in each sampling period using the Nyquist sampling theorem; determine the frequency of the input sinusoidal signal according to the number of phase points, the coprime number of the phase points, and the frequency of the sampling clock signal; determine the angular frequency of the input sinusoidal signal according to the frequency of the input sinusoidal signal; and determine the sampling sequence according to the angular frequency, the amplitude of the input sinusoidal signal, the sampling time, the clock jitter, and the initial phase of the input sinusoidal signal.

[0122] The calculation module 603 determines a subchannel jitter error sequence based on the subchannel output sequence, including: converting the subchannel output sequence into a corresponding matrix according to the number of phase points in each sampling period and the number of sampling periods, and transposing the matrix to obtain a transposed matrix, where each row of the transposed matrix represents each sampling period, and each column represents a sampled output sequence of the same phase corresponding to a sampling moment; calculating an average value of all elements in each column of the transposed matrix to obtain an average value of a sampled signal corresponding to each phase; and determining the subchannel jitter error sequence based on a difference between the subchannel output sequence and the average value of the sampled signal.

[0123] The calculation module 603 calculates the autocorrelation function of the sub-channel jitter error sequence based on the mean of the sub-channel jitter error sequence, including: determining the mean of the product of the sub-channel jitter error sequence at a first time and the sub-channel jitter error sequence at a second time; determining the mean as the autocorrelation function of the first time and the second time; replacing the first time in the autocorrelation function of the first time and the second time with the sampling time, and replacing the difference between the second time and the first time in the autocorrelation function of the first time and the second time with the delay, to obtain the autocorrelation function of the sub-channel jitter error sequence, where the sub-channel jitter error sequence includes the sub-channel jitter error sequence at the first time and the sub-channel jitter error sequence at the second time.

[0124] The first determination module 604 is specifically configured to determine an autocorrelation function of the additive white noise based on a standard deviation of the additive white noise and a delayed excitation; determine a total autocorrelation function based on the autocorrelation function of the sub-channel jitter error sequence and the autocorrelation function of the additive white noise; decompose the total autocorrelation function using a Fourier series expression to obtain a total cyclic autocorrelation function; and perform a Fourier transform on the total cyclic autocorrelation function to obtain a total cyclic spectral density of the sub-channel jitter error sequence.

[0125] It should be noted that the above description of the embodiment of the high-speed ADC clock jitter measurement apparatus is similar to the description of the embodiment of the high-speed ADC clock jitter measurement method described above, and has similar beneficial effects as the embodiment of the high-speed ADC clock jitter measurement method. For technical details not disclosed in the embodiment of the high-speed ADC clock jitter measurement apparatus according to the present invention, please refer to the description of the embodiment of the high-speed ADC clock jitter measurement method according to the present invention.

[0126] The above are merely specific embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any modifications or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. A high-speed ADC clock jitter measurement method, characterized in that: include: Setting the input sinusoidal signal and the sampling clock signal to be mutually prime and coherent, obtaining the frequency of the input sinusoidal signal, and determining a sampling sequence according to the frequency of the input sinusoidal signal, the amplitude of the input sinusoidal signal, the sampling time, the clock jitter, and the initial phase of the input sinusoidal signal; Separating an output sequence of the subchannel from the sampling sequence based on a gain mismatch caused by the subchannel, a phase offset caused by a clock deviation of the subchannel, and an offset mismatch caused by the subchannel, and determining an amplitude of the output sequence under the influence of the gain mismatch of the subchannel based on the amplitude and the gain mismatch; determining a sub-channel jitter error sequence according to the output sequence of the sub-channel, and calculating an autocorrelation function of the sub-channel jitter error sequence according to a mean value of the sub-channel jitter error sequence; Determine the total cyclic spectral density of the sub-channel jitter error sequence by Fourier transform according to the autocorrelation function of the sub-channel jitter error sequence, the standard deviation of the additive white noise, and the delayed excitation; A standard deviation of clock jitter is determined according to the total cyclic spectral density, the output sequence amplitude and the frequency of the input sinusoidal signal. The standard deviation of clock jitter is used to evaluate and optimize an analog-to-digital conversion system.

2. The high-speed ADC clock jitter measurement method according to claim 1, wherein: The step of setting the input sinusoidal signal and the sampling clock signal to be mutually prime and coherent, obtaining the frequency of the input sinusoidal signal, and determining the sampling sequence according to the frequency of the input sinusoidal signal, the amplitude of the input sinusoidal signal, the sampling time, the clock jitter, and the initial phase of the input sinusoidal signal, includes: According to the number of phase points in each sampling period, using the Nyquist sampling theorem, determining the coprime numbers of the phase points; Determining the frequency of the input sinusoidal signal according to the number of phase points, the coprime numbers of the phase points, and the frequency of the sampling clock signal; Determining the angular frequency of the input sinusoidal signal according to the frequency of the input sinusoidal signal; The sampling sequence is determined according to the angular frequency, the amplitude of the input sinusoidal signal, the sampling time, the clock jitter and the initial phase of the input sinusoidal signal.

3. The high-speed ADC clock jitter measurement method according to claim 2, wherein: The expression of the output sequence of the subchannel is: Wherein, Si is the output sequence of the i-th sub-channel, A0 is the amplitude of the input sinusoidal signal, Gi is the gain mismatch caused by the i-th sub-channel, ω is the angular frequency, t is the sampling time, is the initial phase of the input sinusoidal signal, is the phase offset caused by the clock deviation of the i-th sub-channel, tj ′ is the clock jitter, Oi is the offset mismatch caused by the i-th sub-channel; The expression of the output sequence amplitude is: A=A0Gi; Wherein, A is the amplitude of the output sequence, A0 is the amplitude of the input sinusoidal signal, and Gi is the gain mismatch caused by the i-th sub-channel.

4. The high-speed ADC clock jitter measurement method according to claim 1, wherein: The determining the sub-channel jitter error sequence according to the output sequence of the sub-channel includes: Converting the output sequence of the subchannel into a corresponding matrix according to the number of phase points in each sampling period and the number of sampling periods, and transposing the matrix to obtain a transposed matrix, wherein each row of the transposed matrix is each sampling period, and each column is a sampling output sequence with the same phase corresponding to the sampling moment; Calculating the average value of all elements in each column of the transposed matrix to obtain the average value of the sampling signal corresponding to each phase; The sub-channel jitter error sequence is determined according to a difference between the sub-channel output sequence and the average value of the sampling signal.

5. The high-speed ADC clock jitter measurement method according to claim 3, wherein: The sub-channel jitter error sequence includes a sub-channel jitter error sequence at a first time and a sub-channel jitter error sequence at a second time, and calculating the autocorrelation function of the sub-channel jitter error sequence according to the mean value of the sub-channel jitter error sequence includes: determining a mean value of a product of a sub-channel jitter error sequence at the first time and a sub-channel jitter error sequence at the second time; determining the mean as an autocorrelation function of the first time and the second time; The first time in the autocorrelation function of the first time and the second time is replaced by the sampling time, and the difference between the second time and the first time in the autocorrelation function of the first time and the second time is replaced by the delay to obtain the autocorrelation function of the sub-channel jitter error sequence.

6. The high-speed ADC clock jitter measurement method according to claim 5, wherein: The expression of the autocorrelation function of the sub-channel jitter error sequence is: Wherein, R(t,τ) is the autocorrelation function of the sub-channel jitter error sequence, A is the output sequence amplitude, ω is the angular frequency, σ is the standard deviation of the clock jitter, t is the sampling time, and τ is the delay. is the sum of the phase offset caused by the clock deviation of the i-th sub-channel and the initial phase, and δ(·) is the impulse function.

7. The high-speed ADC clock jitter measurement method according to claim 6, wherein: Determining the total cyclic spectral density of the sub-channel jitter error sequence by Fourier transform according to the autocorrelation function of the sub-channel jitter error sequence, the standard deviation of the additive white noise, and the delayed excitation includes: determining an autocorrelation function of the additive white noise based on a standard deviation of the additive white noise and the delayed excitation; determining a total autocorrelation function according to the autocorrelation function of the sub-channel jitter error sequence and the autocorrelation function of the additive white noise; Decomposing the total autocorrelation function using a Fourier series expression to obtain a total cyclic autocorrelation function; Performing Fourier transform on the total cyclic autocorrelation function to obtain the total cyclic spectral density of the sub-channel jitter error sequence.

8. The high-speed ADC clock jitter measurement method according to claim 7, wherein: The expression of the total cyclic spectral density of the sub-channel jitter error sequence is: in, is the total cyclic spectral density of the sub-channel jitter error sequence, A is the output sequence amplitude, ω is the angular frequency, σ is the standard deviation of the clock jitter, σa is the standard deviation of the additive white noise, α is the cyclic frequency, fin is the frequency of the input sinusoidal signal, is the sum of the phase offset caused by the clock deviation of the i-th sub-channel and the initial phase, and j is an imaginary unit.

9. The high-speed ADC clock jitter measurement method according to claim 1, wherein: The expression of the standard deviation of the clock jitter is: Where σ is the standard deviation of the clock jitter, is the total cyclic spectral density of the sub-channel jitter error sequence, f is the frequency variable, A is the output sequence amplitude, fin is the frequency of the input sinusoidal signal, and α is the cyclic frequency.

10. A high-speed ADC clock jitter measurement device, characterized in that: include: a setting module, configured to set the input sinusoidal signal and the sampling clock signal to be mutually prime and coherent, obtain the frequency of the input sinusoidal signal, and determine a sampling sequence according to the frequency of the input sinusoidal signal, the amplitude of the input sinusoidal signal, the sampling time, the clock jitter, and the initial phase of the input sinusoidal signal; a separation module, configured to separate an output sequence of the subchannel from the sampling sequence according to a gain mismatch caused by the subchannel, a phase offset caused by a clock deviation of the subchannel, and an offset mismatch caused by the subchannel, and determine an amplitude of the output sequence under the influence of the gain mismatch of the subchannel according to the amplitude and the gain mismatch; a calculation module, configured to determine a sub-channel jitter error sequence according to an output sequence of the sub-channel, and calculate an autocorrelation function of the sub-channel jitter error sequence according to a mean value of the sub-channel jitter error sequence; A first determining module is configured to determine a total cyclic spectral density of the sub-channel jitter error sequence by using Fourier transform according to an autocorrelation function of the sub-channel jitter error sequence, a standard deviation of additive white noise, and a delayed excitation; The second determination module is configured to determine a standard deviation of clock jitter according to the total cyclic spectral density, the output sequence amplitude, and the frequency of the input sinusoidal signal, wherein the standard deviation of clock jitter is used to evaluate and optimize an analog-to-digital conversion system.

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