Arbitrary waveform sampling rate seamless transformation method based on FPGA (Field Programmable Gate Array) processing

Abstract

The invention belongs to the technical field of test and measurement, and relates to an arbitrary waveform sampling rate seamless transformation method based on FPGA processing. The method comprises the following steps of: dynamically generating the number of original sampling points needing to be read every time and the time offset of each new sampling moment relative to an original sampling point according to an original sampling rate and a target sampling rate under the driving of an FPGA (Field Programmable Gate Array) processing clock, and calculating and generating a new sampling value according to the original sampling points and the time offset. According to the random waveform sampling rate seamless transformation method based on FPGA processing, no matter how much the sampling rate in a user waveform file is, only original waveform sampling point data needs to be loaded, software does not need to carry out any processing on an original sampling point, the loading time is not influenced, the length of the original sampling point can reach the maximum storage depth, and the sampling rate is greatly improved. And the problem of waveform tail distortion does not exist.

Description

Technical Field

[0001] The invention belongs to the technical field of test and measurement, and relates to a method for seamless conversion of arbitrary waveform sampling rate based on FPGA processing. Background Art

[0002] The arbitrary waveform generator is a general-purpose basic test instrument with a wide range of applications. Its sampling rate conversion function is a basic function that allows the arbitrary waveform generator to load user waveform files with different sampling rates to better adapt to the user's application scenarios. Users can edit and generate waveform files with specified sampling rates by themselves, or directly use the oscilloscope to collect and export waveform files. The sampling rates of these waveform files do not necessarily match the highest sampling rate of the arbitrary waveform used. When using these waveform files, the arbitrary waveform needs to convert the sampling rate according to the sampling rate specified in the arbitrary waveform file during the waveform file loading process, and then output the converted waveform data to the DAC, thereby realizing the loading and playback output of waveform files with different sampling rates, such as Figure 1 shown.

[0003] In the practical application of arbitrary waveform generators, user-provided waveform files vary widely, and their specified sampling rates also vary. How to efficiently achieve seamless sampling rate conversion without introducing distortion has always been a design challenge for arbitrary waveform generators. There are two common methods for achieving seamless sampling rate conversion: the first is through software, where the software recalculates the original waveform data, resamples the original waveform data at the specified sampling rate according to the highest sampling rate, calculates new sample points, and then loads the new sample point data into the FPGA for playback output, achieving the conversion from the specified sampling rate to the target maximum sampling rate. The second is to achieve this by changing the DAC clock, where the DAC sampling clock is changed according to the sampling rate specified in the waveform file. The original waveform data is still loaded, and the FPGA does not need to calculate the original sample points, achieving the specified sampling rate at the DAC output.

[0004] The existing method of achieving sampling rate conversion through software requires additional time to calculate and generate sample data through software algorithms. When the amount of data in the waveform file is large, the required calculation time is very long. Typically, it takes 5 minutes to convert 4G sample points from a 1GSa / s sampling rate to a 10GSa / s sampling rate. The user needs to wait for a long time to get the required output signal. When the difference between the specified sampling rate and the maximum sampling rate is large, the amount of newly generated sample data increases dramatically, and the storage depth of the arbitrary waveform generator is limited, resulting in a sharp decrease in the length of the supported original sample data. For example, when the sampling rate is converted from 100GSa / s to 10GSa / s, the length of the original sample data is greatly reduced. s sampling rate, the length of the newly generated sample data is 100000000 times the length of the original data. If the storage depth is 4G samples, the maximum length of the original data supported at the 100Sa sampling rate can only be 40 samples, which is obviously limited in use. In addition, since the software algorithm must inevitably use a data filtering algorithm when recalculating and generating samples, and the data filtering algorithm has a hysteresis effect, it requires a certain length of original samples to comprehensively calculate the new sample, that is, the new sample value is related to a certain length of the original sample value. However, since the software does not know the subsequent output waveform data in advance when loading, a certain length of original sample data will be missing at the end of the waveform data, resulting in sample distortion.

[0005] The existing sampling rate conversion method by changing the DAC sampling clock requires corresponding changes to the related processing clocks in the FPGA. The entire clock system is difficult to implement. When it comes to seamless clock conversion, modern clock generation chips cannot achieve seamless clock output conversion. Moreover, when the sampling rate is low enough, the DAC generally does not support a sampling clock that is too low. Therefore, this sampling rate conversion method by changing the DAC sampling clock is very limited in use and is generally only used for sampling rate conversion within a small range. Summary of the Invention

[0006] The purpose of the present invention is to solve the problems existing in the prior art. By using digital signal processing technology in FPGA, the original waveform data loaded and stored by the user is subjected to real-time sampling rate conversion. The original sample data of any sampling rate within the range can be converted to the target highest sampling rate sample data, and then output to the DAC, thereby realizing seamless switching of the sampling rate.

[0007] The technical solution adopted by the present invention is: a method for seamless conversion of arbitrary waveform sampling rate based on FPGA processing, comprising the following steps: first, based on the original sampling rate and the target sampling rate, under the drive of the FPGA processing clock, dynamically generating the number of original sample points to be read each time, and the time offset of each new sampling moment relative to the original sampling point, and then calculating and generating new sampling values based on the original sample points and the time offset.

[0008] Preferably, the dynamic generation of the number of original sample points to be read each time is specifically as follows: the step size of the original sampling rate and the step size of the FPGA processing clock are quantified according to the original sampling rate being proportional to the frequency of the FPGA processing clock, and then they are accumulated respectively starting from the same zero moment, and then the number of original sample points to be read is calculated based on these two accumulated values.

[0009] Preferably, the method for calculating the number of original samples to be read is: within each step accumulation interval of the original sampling rate, calculate the number of FPGA processing clock accumulation values falling within the interval, and this number is the number of original samples to be read.

[0010] Preferably, the method for dynamically generating the time offset of each new sampling moment relative to the original sampling point is specifically as follows: the step amount of the original sampling rate and the step amount of the target sampling rate are quantified in direct proportion to the reciprocal of the original sampling rate and the reciprocal of the target maximum sampling rate, and then they are accumulated separately starting from time zero, and then the time offset of the new sampling moment relative to the original sampling point is calculated based on these two accumulated values.

[0011] Preferably, the accumulated quantized value of each new sampling moment is subtracted from the quantized value of the adjacent original sampling point on its left, which is the time offset of the new sampling moment relative to the original sampling point. A fixed number of offset values is dynamically generated under the drive of each FPGA processing clock. The fixed number is the ratio of the DAC sampling rate to the FPGA processing clock.

[0012] Preferably, the method for generating new sampling values is: firstly, generating an original sampling sequence based on the original sampling points, and then using a general polyphase filtering interpolation algorithm to calculate and generate new sampling values based on a section of sampling values adjacent to the left of each new sampling moment and a time offset.

[0013] The present invention provides a seamless FPGA-based arbitrary waveform sampling rate conversion method. Regardless of the sampling rate in the user waveform file, only the original waveform sample data needs to be loaded. No software processing of the original samples is required, which does not affect loading time. The original sample length can reach the maximum storage depth, and waveform tail distortion is eliminated. Software configuration is also very simple, requiring only the original sample rate to be specified. The DAC sampling clock does not need to be changed, and the highest sampling clock can be maintained. This method is very convenient to use and is applicable to all arbitrary waveform generator FPGA processing. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 This is a schematic diagram of sampling rate conversion for an arbitrary waveform generator; Figure 2 This is a principle block diagram of a method for seamless conversion of arbitrary waveform sampling rate based on FPGA processing provided in an embodiment of the present invention; Figure 3 A schematic diagram of the principle of dynamically generating the number of sample points N; Figure 4 A schematic diagram of the principle of generating interpolation offset information; Figure 5 A schematic diagram of calculating new sample points using a segment of original sample points and offset information. DETAILED DESCRIPTION

[0015] In order to enable those skilled in the art to more clearly understand the technical solution of the present invention, the technical solution of the present invention will be described in detail below with reference to specific embodiments. It should be understood that the following detailed description is exemplary and is intended to provide further explanation of the present invention. Unless otherwise specified, all technical and scientific terms used in the present invention have the same meaning as commonly understood by those of ordinary skill in the art to which the present invention belongs.

[0016] The present invention provides a method for seamless conversion of arbitrary waveform sampling rate based on FPGA processing, the principle of which is as follows: Figure 2 As shown, the specific steps and implementation process are as follows: 1. Load the raw sample data in the waveform file into the DDR memory without performing any processing on the raw data. Set the sampling rate of the raw sample data to Fs_user.

[0017] 2. The FPGA performs sampling rate conversion driven by the processing clock Frun. Since the FPGA processing clock generally does not exceed 350MHz, and the DAC sampling clock (set to Fs_max) is generally much larger than Frun, M-channel parallel processing is required within the FPGA. Each Frun clock outputs M samples to the DAC, where Frun = Fs_max / M.

[0018] 3. Within the FPGA, the number of raw samples to be read, N, is dynamically generated based on Frun, Fs_user, and Fs_max. Each Frun processing clock generates a new N value, and consecutive N values may not be identical. For example, when Frun = 250 MHz, Fs_user = 1 GSa / s, and Fs_max = 10 GSa / s, M = 40 and N = 4. When Fs_user = 1 GSa / s and is set to 3 GSa / s, N = 3, 3, 3, 4, 3, ...

[0019] Assume that one clock cycle corresponding to the original sampling rate Fs_user of the original sample is Tuser, and one clock cycle corresponding to the FPGA processing clock Frun is Trun. Theoretically, each Frun clock cycle needs to extract N_ (N_=Trun / Tuser) original sample points. The value of N_ can be an integer or a decimal. However, the FPGA cannot read a decimal number of sample points within one Frun processing clock. Therefore, the present invention uses dynamic generation technology to generate N (N is always an integer). Its principle is as follows Figure 3 As shown, within the FPGA, Tuser and Trun are quantized to integers. For example, when Fs_user = 333.33333333 MSa / s and Frun = 100 MSa / s, Tuser and Trun are proportionally quantized to 333 and 100, respectively. On the X-axis, both sampling rates run from zero, corresponding to the first sampling point. Tuser increments by 333 and Trun increments by 100. Within each Tuser interval, the number of Truns is N, corresponding to the number of raw samples N required for each Frun processing clock. As Frun continues running, N is dynamically and continuously output. In actual operation, to further improve frequency resolution, Tuser and Trun can be quantized to larger integers, such as 33333333 and 10000000.

[0020] 4. Within the FPGA, offset information Oft[M] corresponding to N is also generated. The number of Oft information is always M. This offset information is the time offset of the new sampling moment relative to the original sampling point, and is used for subsequent interpolation to generate new sample points.

[0021] The offset information Oft is calculated by quantizing the original sampling rate step and the target sampling rate step in direct proportion to the reciprocal of the original sampling rate and the reciprocal of the target maximum sampling rate. These steps are then accumulated starting from time zero. The time offset of the new sampling moment relative to the original sampling point is then dynamically calculated based on these two accumulated values. For example, the time offset of the new sampling moment relative to the original sampling point is calculated by subtracting the quantized value of the adjacent original sampling point to its left from the accumulated quantized value of each new sampling moment. A fixed number of offset values is dynamically generated under each FPGA processing clock, where the fixed number is equal to the ratio of the DAC sampling rate to the FPGA processing clock.

[0022] The principle of calculating Oft[M] in the present invention is as follows Figure 4As shown in the figure, assuming Fs_user = 333.33333333 MSa / s, Frun = 100 MSa / s, and Fs_max = 1000 MSa / s, then M = Fs_max / Frun = 10. This means that each Frun processing clock requires the calculation and generation of 10 new sample values. Tuser and Tmax are quantized to 300 and 100, respectively, proportional to the reciprocals of Fs_user and Fs_max. The first group, Oft[M], is 100, 200, 300, 100, 200, 300, 100, 200, 300, 100; the second group, Oft[N], is 200, 300, 100, 100, 200, 300, 100, 200, 300, 100, and so on. The calculations of N and Oft[M] can be performed using addition and subtraction, making them easy to implement in an FPGA.

[0023] 5. The FPGA controls the reading of N original sample data points (data[N]) from the DDR and outputs them to the subsequent interpolation unit to generate new samples. Within a Trun, N original sample points are read. Based on these N sample points and the previously read original sample points, M new sample values are calculated. To correctly calculate the M new sample values, the offset of each of these M sample points relative to the original sample point to the left (Oft[M]) must be recorded and passed on for later use.

[0024] 6. The interpolation unit uses the interpolation algorithm to calculate and generate M new sample data at each processing clock Frun based on Oft[M] and the read data[N].

[0025] The original sample points and offset information are used in the polyphase interpolation filter as follows: Figure 5 Each new sample point is based on Figure 5 The principle calculation is shown in the figure. Each Frun processing clock will get M new sample points. The sampling rate of these M sample points is Fs_max, which is then output to the DAC to complete the sampling rate conversion.

[0026] 7. M new sample data points are continuously output to the DAC to generate the signal required by the user.

Claims

1. A method for seamless conversion of arbitrary waveform sampling rate based on FPGA processing, characterized by: First, based on the original sampling rate and the target sampling rate, driven by the FPGA processing clock, the number of original sample points that need to be read each time and the time offset of each new sampling moment relative to the original sampling point are dynamically generated. Then, new sampling values are calculated based on the original sample points and the time offset.

2. The method for seamless conversion of arbitrary waveform sampling rate based on FPGA processing according to claim 1, characterized in that: The dynamic generation of the number of original sample points that need to be read each time is specifically as follows: the step size of the original sampling rate and the step size of the FPGA processing clock are quantified according to the direct proportion between the original sampling rate and the frequency of the FPGA processing clock, and then they are accumulated respectively starting from the same zero time, and then the number of original sample points that need to be read is calculated based on these two accumulated values.

3. The method for seamless conversion of arbitrary waveform sampling rate based on FPGA processing according to claim 2, characterized in that: The method for calculating the number of raw sample points that need to be read is: within each step accumulation interval of the original sampling rate, calculate the number of FPGA processing clock accumulation values that fall within the interval. This number is the number of raw sample points that need to be read.

4. The method for seamless conversion of arbitrary waveform sampling rate based on FPGA processing according to claim 1, characterized in that: The method for dynamically generating the time offset of each new sampling moment relative to the original sampling point is as follows: the step amount of the original sampling rate and the step amount of the target sampling rate are quantified in direct proportion to the reciprocal of the original sampling rate and the reciprocal of the target maximum sampling rate, and then they are accumulated separately starting from time zero, and the time offset of the new sampling moment relative to the original sampling point is calculated based on these two accumulated values.

5. The method for seamless conversion of arbitrary waveform sampling rate based on FPGA processing according to claim 4, characterized in that: The accumulated quantized value of each new sampling moment is subtracted from the quantized value of the adjacent original sampling point on its left, which is the time offset of the new sampling moment relative to the original sampling point. A fixed number of offset values is dynamically generated under the drive of each FPGA processing clock. The fixed number is the ratio of the DAC sampling rate to the FPGA processing clock.

6. The method for seamless conversion of arbitrary waveform sampling rate based on FPGA processing according to claim 1, characterized in that: The method for generating new sampling values is as follows: first, an original sampling sequence is generated based on the original sampling points, and new sampling values are calculated using a general polyphase filtering interpolation algorithm based on a segment of sampling values adjacent to the left of each new sampling moment and a time offset.

Images