LVDS receiving circuit and LVDS transmitting circuit for cross-BANK transmission

Abstract

The invention discloses an LVDS (Low Voltage Differential Signaling) receiving circuit and an LVDS transmitting circuit for cross-BANK transmission. The LVDS receiving circuit for cross-BANK transmission comprises a clock channel and a plurality of data channels, the clock channel and the data channels are distributed in at least two BANKs, and the clock channel and at least one of the data channels are located in the same BANK; the programmable phase-locked loop is used for receiving a single-ended clock signal generated by the clock channel, and the first global clock buffer and the second global clock buffer are respectively used for buffering a first clock and a second clock and then outputting the first clock and the second clock; each of the clock channel and the data channel comprises a differential-to-single-ended module, a delay module and a serial-to-parallel conversion module. The programmable phase-locked loop and the global clock buffer are introduced, the clock channels and the data channels are distributed in the at least two BANKs, it is guaranteed that part of the data channels and the clock channels are located in the same BANK, and a flexible and efficient LVDS transmission architecture for cross-BANK transmission is achieved.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to an LVDS receiving circuit and an LVDS transmitting circuit for cross-BANK transmission. Background Art

[0002] LVDS (Low Voltage Differential Signaling) transmission systems are widely used for high-speed data transmission due to their low power consumption, low noise, and high speed. However, as data transmission demands continue to grow, the limitations of existing LVDS transmission systems are becoming increasingly apparent. Traditional LVDS designs have significant shortcomings in supporting inter-bank transmissions, resulting in limited transmission rates and an inability to effectively increase the number of LVDS channels in a single transmission. This significantly restricts overall system performance and flexibility. Summary of the Invention

[0003] In view of the above problems, the present application provides an LVDS receiving circuit and an LVDS transmitting circuit for cross-BANK transmission to solve the above technical problems.

[0004] In a first aspect, the present application provides an LVDS receiving circuit for inter-BANK transmission, comprising:

[0005] A clock channel and a plurality of data channels, wherein the clock channel and each of the data channels are distributed in at least two banks, and the clock channel and at least one of the plurality of data channels are located in the same bank;

[0006] A programmable phase-locked loop, configured to receive a single-ended clock signal generated by the clock channel and generate a high-speed first clock and a low-speed second clock;

[0007] a first global clock buffer and a second global clock buffer, wherein the first global clock buffer is used to output the first clock after buffering processing, and the second global clock buffer is used to output the second clock after buffering processing;

[0008] The clock channel and each of the data channels include:

[0009] A differential-to-single-ended module, configured to receive a serial LVDS differential signal and convert the LVDS differential signal into a single-ended signal for output. For the clock channel, the LVDS differential signal is a clock signal; for the data channel, the LVDS differential signal is a data signal.

[0010] A delay module, configured to receive the single-ended signal, perform delay processing on the single-ended signal, and then output a delay adjustment signal;

[0011] a serial-to-parallel conversion module, configured to sample the delay adjustment signal according to the first clock, and convert the delay adjustment signal into a parallel signal output according to the second clock;

[0012] The differential-to-single-ended module in the clock channel is further configured to output the single-ended signal as the single-ended clock signal to the programmable phase-locked loop.

[0013] In a second aspect, the present application provides an LVDS transmission circuit for inter-BANK transmission, comprising:

[0014] A clock channel and a plurality of data channels, wherein the clock channel and the plurality of data channels are configured such that: the clock channel and each of the data channels are distributed in at least two banks, and the clock channel and at least one of the plurality of data channels are located in the same bank;

[0015] A programmable phase-locked loop, configured to receive a preset reference clock and generate a high-speed third clock and a low-speed fourth clock;

[0016] a third global clock buffer and a fourth global clock buffer, wherein the third global clock buffer is used to output the third clock after buffering processing, and the fourth global clock buffer is used to output the fourth clock after buffering processing;

[0017] The clock channel and each of the data channels include:

[0018] a parallel-to-serial conversion module, configured to sample a preset serial signal according to the fourth clock, and convert the serial signal into a parallel signal for output according to the third clock;

[0019] A delay module, configured to receive the parallel signal, perform delay processing on the parallel signal, and then output a delay adjustment signal;

[0020] The single-ended to differential conversion module is used to receive the delay adjustment signal and convert the delay adjustment signal into an LVDS differential signal.

[0021] The present application provides an LVDS receiving circuit and transmitting circuit for cross-BANK transmission. The LVDS receiving circuit for cross-BANK transmission solves the problem that the LVDS transmission system is difficult to achieve efficient cross-BANK transmission by introducing a programmable phase-locked loop and a global clock buffer, and combining the distribution design of clock channels and data channels in multiple BANKs. Specifically, the programmable phase-locked loop receives the single-ended signal generated by the clock channel, generates a high-speed first clock and a low-speed second clock, and provides a time reference for subsequent data sampling and serial-to-parallel conversion; the global clock buffer further optimizes the distribution and stability of the clock signal to ensure synchronization between multiple BANKs. At the same time, the present application realizes a flexible and efficient LVDS transmission architecture for cross-BANK transmission by distributing the clock channel and the data channel in at least two BANKs and ensuring that some data channels and clock channels are located in the same BANK.

[0022] These and other aspects of the present application will become more readily apparent from the description of the following embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0024] Figure 1 A schematic diagram of an LVDS receiving circuit for cross-BANK transmission provided by an embodiment of the present application is shown.

[0025] Figure 2 Another schematic diagram of an LVDS receiving circuit for cross-BANK transmission provided by an embodiment of the present application is shown.

[0026] Figure 3 Another schematic diagram of an LVDS receiving circuit for cross-BANK transmission provided by an embodiment of the present application is shown.

[0027] Figure 4 Another schematic diagram of an LVDS receiving circuit for cross-BANK transmission provided by an embodiment of the present application is shown.

[0028] Figure 5 A schematic diagram of an LVDS transmitting circuit for cross-BANK transmission provided by an embodiment of the present application is shown.

[0029] Figure 6 A schematic diagram of an LVDS transmitting circuit for cross-BANK transmission provided by an embodiment of the present application is shown.

[0030] Figure 7Another schematic diagram of an LVDS transmitting circuit for cross-BANK transmission provided by an embodiment of the present application is shown.

[0031] Figure 8 An application scenario of an embodiment of the present application is shown.

[0032] Figure 9 Another application scenario provided by an embodiment of the present application is shown.

[0033] Figure 10 A schematic diagram of a chip provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0034] In order to enable those skilled in the art to better understand the solutions of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0035] In the embodiments of the present application, it should be noted that, in this document, relational terms such as first and second, etc., are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

[0036] In addition, in the embodiments of the present application, "plurality" refers to two or more. In view of this, in the embodiments of the present application, "plurality" can also be understood as "at least two". "At least one" can be understood as one or more, for example, one, two, or more. For example, "including at least one" means including one, two, or more, and does not limit which ones are included. For example, "including at least one of A, B, and C" means including A, B, C, A and B, A and C, B and C, or A, B, and C.

[0037] It should be noted that in the embodiments of the present application, "connection" can be understood as electrical connection, and the connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be either a direct connection between A and B or an indirect connection between A and B through one or more other electrical components.

[0038] Traditional LVDS transmission systems typically centralize clock and data channels within the same bank. While this layout simplifies the design, it struggles to increase transmission speeds and support cross-bank operations. Due to the lack of effective clock management and signal synchronization mechanisms, traditional LVDS designs struggle to ensure stability and reliability at high data rates, especially when performing cross-bank data transmission.

[0039] In view of the above problems, an embodiment of the present application provides an LVDS receiving circuit for cross-BANK transmission. Figure 1 FIG. 1 shows a schematic diagram of an LVDS receiving circuit for cross-BANK transmission provided by an embodiment of the present application, as shown in FIG. Figure 1 As shown, the circuit includes:

[0040] The clock channel and multiple data channels are distributed in at least two banks, and the clock channel and at least one of the multiple data channels are located in the same bank. Optionally, in an integrated circuit, a bank refers to a group of storage units or I / O (input / output) units with the same electrical characteristics and functions. For example, the I / O pins of an FPGA (Field Programmable Gate Array) chip are classified into groups, each group is called a bank, and each bank is independently powered to adapt to different voltage standards, thereby enhancing the flexibility of the I / O design. It should be clear that Figure 1 It is only used to illustrate the solution provided in the embodiment of the present application. It shows a schematic diagram in which the clock channel and multiple data channels are distributed in BANK0 and BANK1, but it does not mean that the LVDS receiving circuit provided in the embodiment of the present application only supports transmission across two BANKs.

[0041] The programmable phase-locked loop is used to receive a single-ended clock signal generated by a clock channel, generate a high-speed first clock and a low-speed second clock, and thus provide clocks for subsequent circuits.

[0042] The first global clock buffer and the second global clock buffer are both connected to a programmable phase-locked loop. The first global clock buffer is used to output the first clock after buffering processing, and the second global clock buffer is used to output the second clock after buffering processing.

[0043] The clock channel and each data channel include:

[0044] The differential-to-single-ended module is used to receive serial LVDS differential signals and convert the LVDS differential signals into single-ended signals for output. For the clock channel, the LVDS differential signal received by the internal differential-to-single-ended module is the clock signal. For each data channel, the LVDS differential signal received by the internal differential-to-single-ended module is the data signal. The differential-to-single-ended module in the clock channel is also used to output the single-ended signal as a single-ended clock signal to the programmable phase-locked loop.

[0045] The delay module is connected to the differential-to-single-ended module and is used to receive single-ended signals, delay the single-ended signals, and output delay adjustment signals. The delay adjustment signals are the delayed single-ended signals. The purpose of the delay unit is to statically delay or dynamically delay the single-ended signals, so that the serial-to-parallel conversion module can accurately sample at the stable position of the single-ended signal, ensuring that the serial-to-parallel conversion module can collect accurate single-ended data each time it samples. Among them, static delay refers to the fixed delay value determined in the LVDS design stage, and dynamic delay allows the signal delay time to be adjusted in real time according to the actual operation of the LVDS system.

[0046] The serial-to-parallel conversion module is connected to the delay module, the first global clock buffer and the second global clock buffer respectively, and is used to sample the delay adjustment signal according to the high-speed first clock and convert the delay adjustment signal into a parallel signal output according to the low-speed second clock.

[0047] It should be clear that in the embodiments of the present application, there is no restriction on the specific structure of the differential to single-ended module, the delay module and the serial-to-parallel conversion module, and any implementation method in the prior art can be adopted, or a customized design can be performed according to actual needs. The functional implementation of these modules mainly depends on the support and cooperation of the overall circuit architecture, rather than the limitation of the specific structure. Therefore, no matter what specific form is adopted, as long as the functional logic described in this application can be realized, it should be regarded as the protection scope of this application. For example, in an FPGA chip, these modules can be flexibly configured and implemented based on existing logic resources. The differential to single-ended module can be implemented using the high-speed input and output (I / O) module inside the FPGA to convert the received LVDS differential signal into a single-ended signal suitable for internal processing. The delay module can achieve accurate signal delay adjustment through the programmable delay element or phase-locked loop (PLL) in the FPGA to ensure signal synchronization and stability. The serial-to-parallel conversion module can be implemented with the help of the logic unit and storage resources inside the FPGA.

[0048] The LVDS receiving circuit for cross-BANK transmission provided in the embodiment of the present application solves the problem that the LVDS transmission system is difficult to achieve efficient cross-BANK transmission by introducing a programmable phase-locked loop and a global clock buffer, and combining the distribution design of clock channels and data channels in multiple BANKs. Specifically, the programmable phase-locked loop receives the single-ended signal generated by the clock channel, generates a high-speed first clock and a low-speed second clock, and provides a time reference for subsequent data sampling and serial-to-parallel conversion; the global clock buffer further optimizes the distribution and stability of the clock signal to ensure synchronization between multiple BANKs. In addition, at the same time, the present application realizes a flexible and efficient LVDS transmission architecture for cross-BANK transmission by distributing the clock channel and the data channel in at least two BANKs and ensuring that some data channels and clock channels are located in the same BANK.

[0049] As a preferred embodiment, in the LVDS receiving circuit for cross-BANK transmission provided in an embodiment of the present application, the clock channel and multiple data channels are configured as follows: the clock channel and each data channel are distributed in two BANKs, and the clock channel and at least one of the multiple data channels are located in the same BANK.

[0050] In some embodiments, Figure 2 Another schematic diagram of the LVDS receiving circuit for cross-BANK transmission provided by an embodiment of the present application is shown, Figure 2 As shown, the circuit also includes:

[0051] The delay control module is connected to the first global clock buffer, the serial-to-parallel conversion module of the clock channel, and the delay modules of the clock channel and each data channel. It is used to compare the parallel signal output by the clock channel according to the second clock sampling, with the correct data preset within the clock channel, and generate a control signal to control the delay modules of the clock channel and each data channel to delay the single-ended signal, thereby dynamically adjusting the delay of the delay module. Optionally, the delay control module is preset with the expected correct data. After sampling the parallel signal, the delay control module compares the sampled parallel data with the correct data to detect whether there is a bit error or sampling time deviation. If the parallel data has a sampling time deviation, a control signal is generated to increase or decrease the delay of the delay module, thereby eliminating the sampling time deviation.

[0052] It is understood that the specific structure of the delay control module is not limited in the embodiments of the present application, and it can be implemented in a variety of ways to achieve the purpose of dynamically adjusting the delay. For example, in an FPGA chip, the delay control module can be flexibly configured based on the FPGA's programmable logic resources and internal memory.

[0053] In some embodiments, Figure 3Another schematic diagram of the LVDS receiving circuit for cross-BANK transmission provided by the embodiment of the present application is shown, Figure 3 As shown, the circuit also includes:

[0054] The byte alignment module is respectively connected to the first global clock buffer, the clock channel and the serial-to-parallel conversion module of each data channel, and is used to sample the parallel signal output by each data channel according to the second clock, compare it with the characteristic data preset inside, and generate a shift signal to control the serial-to-parallel conversion module of the clock channel and each data channel to shift the parallel signal generated inside. Optionally, the byte alignment module is preset with characteristic data. After the byte alignment module samples the parallel signal, it compares the sampled parallel data with the characteristic data to determine whether the parallel data is in the correct byte alignment position. If the parallel data is not aligned, a shift signal is generated to control the serial-to-parallel conversion module to shift the parallel data. If the data is ahead, it shifts backward, and if the data lags, it shifts forward. It should be clear that the embodiment of the present application does not limit the specific data format of the characteristic data. For example, the characteristic data can be a part of the parallel data, so that the byte alignment module can determine whether the parallel data is aligned by comparing the characteristic data with the parallel data.

[0055] It is understood that in the embodiments of the present application, the specific structure of the byte alignment module is not limited, and it can be implemented in a variety of ways to achieve the purpose of byte alignment. For example, in an FPGA chip, the byte alignment module can be flexibly configured based on the programmable logic resources and internal memory of the FPGA.

[0056] In some embodiments, Figure 4 Another schematic diagram of the LVDS receiving circuit for cross-BANK transmission provided by the embodiment of the present application is shown, Figure 4 As shown, the circuit also includes:

[0057] A clock control module is connected to a programmable phase-locked loop (PLL) and is configured to generate and output a clock control signal to the programmable phase-locked loop (PLL) to control the first clock to lag behind the second clock output. Optionally, in an embodiment of the present application, the low-speed clock is output before the high-speed clock to support system power-on initialization and back-end module preparation. The high-speed clock, through the clock control signal, ensures safe startup after the back-end module is ready, thereby preventing the LVDS system from collecting unnecessary data.

[0058] It is understandable that the embodiments of the present application do not limit the specific structure of the clock control module. For example, in an FPGA chip, the clock control module can be implemented using its internal dedicated clock management resources.

[0059] In some embodiments, in the LVDS receiving circuit for cross-BANK transmission provided in the embodiment of the present application, the BANK type where the clock channel and multiple data channels are located is HP BANK IOB (High Performance BANK Input / Output Block). Optionally, HP BANK IOB is a high-performance input / output block (Input / Output Block) in the FPGA, which is used to further increase the transmission rate of the LVDS receiving circuit. Optionally, in the embodiment of the present application, when HP BANK IOB is applied, the transmission rate of the LVDS receiving circuit reaches up to 1.5 Gbps.

[0060] The embodiment of the present application also provides an LVDS transmission circuit for cross-BANK transmission. Figure 5 FIG. 1 shows a schematic diagram of an LVDS transmission circuit for cross-BANK transmission provided by an embodiment of the present application, as shown in FIG. Figure 5 As shown, the circuit includes:

[0061] The clock channel and multiple data channels are configured as follows: the clock channel and each data channel are distributed in at least two banks, and the clock channel and at least one of the multiple data channels are located in the same bank. It should be clear that Figure 5 It is only used to illustrate the solution provided in the embodiment of the present application. It shows a schematic diagram in which the clock channel and multiple data channels are distributed in BANK0 and BANK1, but it does not mean that the LVDS transmitting circuit provided in the embodiment of the present application only supports transmission across two BANKs.

[0062] The programmable phase-locked loop is used to receive a preset reference clock and generate a high-speed third clock and a low-speed fourth clock.

[0063] The third global clock buffer and the fourth global clock buffer are both connected to a programmable phase-locked loop and are used for buffering and processing the third clock and the fourth clock respectively and then outputting them.

[0064] The clock channel and each data channel include:

[0065] The parallel-to-serial conversion module is connected to the third global clock buffer and the fourth global clock buffer respectively, and is used to sample a preset serial signal according to the low-speed fourth clock, and convert the serial signal into a parallel signal output according to the high-speed third clock. For the clock channel, the serial signal received by the internal parallel-to-serial conversion module is the clock signal. For each data channel, the serial signal received by the internal parallel-to-serial conversion module is the data signal.

[0066] The delay module is connected to the parallel-serial conversion module, and is used to receive the parallel signal, perform delay processing on the parallel signal, and then output a delay adjustment signal, where the delay adjustment signal is the delayed parallel signal.

[0067] The single-ended to differential module is used to receive the delay adjustment signal and convert the delay adjustment signal into an LVDS differential signal.

[0068] It should be clear that in the embodiments of the present application, there is no restriction on the specific structure of the parallel-to-serial conversion module, the delay module and the single-ended differential conversion module, and any implementation method in the prior art can be adopted, or a customized design can be performed according to actual needs. The functional implementation of these modules mainly depends on the support and cooperation of the overall circuit architecture, rather than the limitation of the specific structure. Therefore, no matter what specific form is adopted, as long as the functional logic described in this application can be realized, it should be regarded as the protection scope of this application. For example, in an FPGA chip, these modules can be flexibly configured and implemented based on existing logic resources, and the parallel-to-serial conversion module can be implemented with the help of the logic unit and storage resources inside the FPGA. The delay module can realize accurate signal delay adjustment through the programmable delay element or phase-locked loop (PLL) in the FPGA to ensure signal synchronization and stability. The single-ended differential conversion module can be implemented using the high-speed input and output (I / O) module inside the FPGA to convert the received delay adjustment signal into an LVDS differential signal suitable for internal processing.

[0069] The LVDS transmission circuit for cross-BANK transmission provided in the embodiment of the present application solves the problem that the LVDS transmission system is difficult to achieve efficient cross-BANK transmission by introducing a programmable phase-locked loop and a global clock buffer, and combining the distribution design of clock channels and data channels in multiple banks. Specifically, the programmable phase-locked loop receives a preset reference clock, generates a high-speed third clock and a low-speed fourth clock, and provides a time reference for subsequent data sampling and parallel-serial conversion; the global clock buffer further optimizes the distribution and stability of the clock signal to ensure synchronization between multiple banks. In addition, at the same time, the present application realizes a flexible and efficient LVDS transmission architecture for cross-BANK transmission by distributing the clock channel and the data channel in at least two banks and ensuring that some data channels and clock channels are located in the same bank.

[0070] As a preferred embodiment, in the LVDS transmitting circuit for cross-BANK transmission provided in an embodiment of the present application, the clock channel and multiple data channels are configured as follows: the clock channel and each data channel are distributed in two BANKs, and the clock channel and at least one of the multiple data channels are located in the same BANK.

[0071] In some embodiments, Figure 6FIG. 1 shows a schematic diagram of an LVDS transmission circuit for cross-BANK transmission provided by an embodiment of the present application, as shown in FIG. Figure 6 As shown, the circuit also includes:

[0072] The data generation module is connected to the parallel-to-serial conversion module in each data channel to generate a data signal and transmit the data signal as a serial signal to the parallel-to-serial conversion module in each data channel. Optionally, the embodiment of the present application can configure the data generation module to generate different types of data signals and provide them to the parallel-to-serial conversion module.

[0073] The clock generation module is connected to the parallel-to-serial conversion module in the clock channel and is used to generate a clock signal and transmit the clock signal as a serial signal to the parallel-to-serial conversion module in the clock channel.

[0074] As an implementation manner, the data generation module and the clock generation module are further connected to a fourth global clock buffer for receiving a fourth clock, so as to use the low-speed fourth clock as its system clock.

[0075] It is understood that in the embodiments of the present application, the specific structures of the data generation module and the clock generation module are not limited, and they can be implemented in various ways. For example, in an FPGA chip, the data generation module and the clock generation module can be flexibly configured based on the FPGA's programmable logic resources and internal memory.

[0076] In some embodiments, Figure 7 Another schematic diagram of the LVDS transmission circuit for cross-BANK transmission provided by an embodiment of the present application is shown. Figure 7 As shown, the circuit also includes:

[0077] The clock control module is connected to the programmable phase-locked loop and is used to generate and output a clock control signal to the programmable phase-locked loop to control the third clock to lag behind the fourth clock output. Optionally, in an embodiment of the present application, the low-speed clock is output before the high-speed clock to support system power-on initialization and back-end module preparation. The high-speed clock ensures safe startup after the back-end module is ready through the clock control signal, thereby preventing the LVDS system from collecting unnecessary data.

[0078] In some embodiments, in the LVDS transmitting circuit for cross-BANK transmission provided in the embodiment of the present application, the BANK type where the clock channel and multiple data channels are located is HP BANK IOB (High Performance BANK Input / Output Block). Optionally, HP BANK IOB is a high-performance input / output block (Input / Output Block) in the FPGA, which is used to further increase the transmission rate of the LVDS receiving circuit. Optionally, in the embodiment of the present application, when HP BANK IOB is applied, the transmission rate of the LVDS receiving circuit reaches up to 1.5 Gbps.

[0079] The LVDS transmission architecture provided in the embodiment of the present application supports high-speed cross-BANK transmission. For example, Figure 8 An application scenario of the embodiment of the present application is shown. Figure 8 As shown, the LVDS transmission architecture provided in the embodiment of the present application can drive high-speed data transmission between the FPGA chip and the high-definition LCD screen of 1920*1080@60 / 1920*1200@60 / 2560*1440@60 / 3840*2160@30 / 3840*2160@60, where the number after @ is the refresh rate and the number before @ is the resolution, such as 1920*1080@60 represents a high-definition LCD screen with a resolution of 1920*1080 and a refresh rate of 60HZ. For example, Figure 9 Another application scenario provided by the embodiment of the present application is shown. Figure 9 As shown, the LVDS transmission architecture provided by this application can drive high-speed data transmission between the FPGA chip and the CPU.

[0080] The embodiment of the present application further provides a chip 100, Figure 10 A schematic diagram of a chip provided in an embodiment of the present application is shown in FIG. Figure 10 As shown, the chip 100 includes the aforementioned LVDS receiving circuit for inter-bank transmission and the LVDS transmitting circuit for inter-bank transmission. An integrated circuit (IC) is also called an integrated circuit. Such chips include, but are not limited to, SOC (System on Chip), SIP (System in Package), and FPGA (Field-Programmable Gate Array). FPGAs, as programmable logic devices, can implement user-customized logic functions using hardware description languages and are widely used in communications, industry, data centers, and other fields.

[0081] The above content is a further detailed description of the present application in conjunction with specific implementation methods, and the specific implementation of the present application cannot be considered to be limited to these descriptions. For ordinary technicians in the technical field to which the present application belongs, they can make several simple deductions or substitutions without departing from the concept of the present application, which should be considered as the scope of protection of the present application.

Claims

1. An LVDS receiving circuit for cross-BANK transmission, characterized in that: include: A clock channel and a plurality of data channels, wherein the clock channel and each of the data channels are distributed in at least two banks, and the clock channel and at least one of the plurality of data channels are located in the same bank; A programmable phase-locked loop, configured to receive a single-ended clock signal generated by the clock channel and generate a high-speed first clock and a low-speed second clock; a first global clock buffer and a second global clock buffer, wherein the first global clock buffer is used to output the first clock after buffering processing, and the second global clock buffer is used to output the second clock after buffering processing; The clock channel and each of the data channels include: A differential-to-single-ended module, configured to receive a serial LVDS differential signal and convert the LVDS differential signal into a single-ended signal for output. For the clock channel, the LVDS differential signal is a clock signal; for the data channel, the LVDS differential signal is a data signal. A delay module, configured to receive the single-ended signal, perform delay processing on the single-ended signal, and then output a delay adjustment signal; a serial-to-parallel conversion module, configured to sample the delay adjustment signal according to the first clock, and convert the delay adjustment signal into a parallel signal output according to the second clock; The differential-to-single-ended module in the clock channel is further configured to output the single-ended signal as the single-ended clock signal to the programmable phase-locked loop.

2. The LVDS receiving circuit for inter-BANK transmission according to claim 1, wherein: The LVDS receiving circuit for cross-BANK transmission further includes: The delay control module is used to sample the parallel signal output by the clock channel according to the second clock, compare it with the correct data preset inside it, and generate a control signal to control the delay modules of the clock channel and each of the data channels to delay the single-ended signal.

3. The LVDS receiving circuit for inter-BANK transmission according to claim 1, wherein: The LVDS receiving circuit for cross-BANK transmission further includes: The byte alignment module is used to sample the parallel signals output by each of the data channels according to the second clock, compare them with the internally preset characteristic data, and generate a shift signal to control the serial-to-parallel conversion modules of the clock channel and each of the data channels to perform a shift operation on the parallel signals generated internally.

4. The LVDS receiving circuit for inter-BANK transmission according to claim 1, wherein: The LVDS receiving circuit for cross-BANK transmission further includes: The clock control module is used to generate a clock control signal and output it to the programmable phase-locked loop to control the first clock to lag behind the second clock output.

5. The LVDS receiving circuit for inter-BANK transmission according to claim 1, wherein: The bank is HP BANKIOB.

6. An LVDS transmission circuit for cross-BANK transmission, characterized in that: include: A clock channel and a plurality of data channels, wherein the clock channel and each of the data channels are distributed in at least two banks, and the clock channel and at least one of the plurality of data channels are located in the same bank; A programmable phase-locked loop, configured to receive a preset reference clock and generate a high-speed third clock and a low-speed fourth clock; a third global clock buffer and a fourth global clock buffer, wherein the third global clock buffer is used to output the third clock after buffering processing, and the fourth global clock buffer is used to output the fourth clock after buffering processing; The clock channel and each of the data channels include: a parallel-to-serial conversion module, configured to sample a preset serial signal according to the fourth clock, and convert the serial signal into a parallel signal for output according to the third clock, wherein for the clock channel, the serial signal is a clock signal, and for the data channel, the serial signal is a data signal; A delay module, configured to receive the parallel signal, perform delay processing on the parallel signal, and then output a delay adjustment signal; The single-ended to differential conversion module is used to receive the delay adjustment signal and convert the delay adjustment signal into an LVDS differential signal.

7. The LVDS transmitting circuit for inter-BANK transmission according to claim 6, wherein: The LVDS transmitting circuit for cross-BANK transmission further includes: a data generation module, configured to generate a data signal and transmit the data signal as the serial signal to the parallel-to-serial conversion module of each data channel; The clock generation module is used to generate a clock signal and transmit the clock signal as the serial signal to the parallel-serial conversion module of the clock channel.

8. The LVDS transmitting circuit for inter-BANK transmission according to claim 6, wherein: The LVDS transmitting circuit for cross-BANK transmission further includes: The clock control module is used to generate a clock control signal and output it to the programmable phase-locked loop, so as to control the third clock to lag behind the fourth clock output.

9. The LVDS transmitting circuit for inter-BANK transmission according to claim 6, wherein: The bank is HP BANKIOB.

10. A chip, characterized in that: The invention comprises the LVDS receiving circuit for inter-BANK transmission according to any one of claims 1 to 5 and the LVDS transmitting circuit for inter-BANK transmission according to any one of claims 6 to 9.

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