Self-adaptive equalization circuit and method of decision feedback equalizer

Abstract

The invention relates to the technical field of communication, and provides a self-adaptive equalization circuit and method of a decision feedback equalizer, the circuit comprises a decision feedback equalizer circuit, a self-adaptive algorithm circuit and a digital-to-analog converter circuit which are connected in sequence, the output end of the digital-to-analog converter circuit is connected with the decision feedback equalizer circuit, and the output end of the digital-to-analog converter circuit is connected with the decision feedback equalizer circuit. The decision feedback equalizer circuit decides an original data signal to obtain a decision result and outputs sampling data and error data based on the decision result, and the adaptive algorithm circuit processes the sampling data and the error data by using a minimum root mean square algorithm to obtain a control code word; the digital-to-analog converter circuit converts the control code word into a control voltage and outputs the control voltage to the decision feedback equalizer circuit, so that the decision feedback equalizer circuit adjusts a feedback coefficient based on the control voltage. According to the adaptive equalization circuit provided by the invention, the symbol minimum root-mean-square algorithm is matched with the decision feedback equalizer circuit, various channel losses can be dynamically compensated, and the adaptive equalization circuit has a faster and more stable convergence characteristic.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to an adaptive equalization circuit and method for a decision feedback equalizer. Background Art

[0002] As serial signal transmission rates continue to increase, channel loss can lead to a series of signal integrity issues, such as intersymbol interference and crosstalk. To overcome these issues, a feedforward equalizer (FFE) is typically used at the transmitter end, and a decision feedback equalizer (DFE) and continuous-time linear equalizer (CTLE) are used at the receiver end to compensate for channel loss in high-speed interface circuit design systems. Regardless of the equalizer used, appropriate equalization coefficients must be set to offset channel attenuation and crosstalk. This is especially true when the channel is unknown and severely affected by the channel environment. The equalizer must adaptively change the tap coefficients in real time, utilizing an adaptive equalization algorithm to achieve this goal.

[0003] In high-speed interface circuit design, the zero-forcing method is often used as the adaptive equalization algorithm for the decision feedback equalizer. However, in situations where high-speed transmission and time-varying channels cause large inter-symbol interference (ISI), the zero-forcing method ignores channel noise and time-varying factors, often only obtaining the optimal solution at a specific moment and is not suitable for long-term channel environments. Summary of the Invention

[0004] In response to the above-mentioned shortcomings of the existing technology, the present invention provides an adaptive equalization circuit and method for a decision feedback equalizer, which solves the technical problem that the solution obtained by the adaptive equalization algorithm of the decision feedback equalizer in the existing technology has limitations and cannot be applied to long-term working channel environments.

[0005] In one aspect, the present invention provides an adaptive equalization circuit of a decision feedback equalizer, comprising: a decision feedback equalizer circuit, an adaptive algorithm circuit, and a digital-to-analog converter circuit;

[0006] The first input end of the decision feedback equalizer circuit receives the original data signal, the output end of the decision feedback equalizer circuit is connected to the input end of the adaptive algorithm circuit, the decision feedback equalizer circuit is used to make a decision on the original data signal to obtain a decision result, and output sampled data and error data to the adaptive algorithm circuit based on the decision result;

[0007] The output end of the adaptive algorithm circuit is connected to the input end of the digital-to-analog converter circuit, and the adaptive algorithm circuit processes the sampled data and the error data using a least mean square algorithm to obtain a control codeword and outputs the control codeword to the digital-to-analog converter circuit;

[0008] The output end of the digital-to-analog converter circuit is connected to the second input end of the decision feedback equalizer circuit. The digital-to-analog converter circuit converts the control codeword into a control voltage and outputs it to the decision feedback equalizer circuit. The decision feedback equalizer circuit adjusts the feedback coefficient of the decision feedback equalizer circuit based on the control voltage.

[0009] Preferably, the decision feedback equalizer circuit includes a five-tap decision feedback equalizer, a first multiplexer, and a second multiplexer;

[0010] An input end of the five-tap decision feedback equalizer receives an original data signal, a first output end of the five-tap decision feedback equalizer is connected to an input end of the first multiplexer, and a second output end of the five-tap decision feedback equalizer is connected to an input end of the second multiplexer. The five-tap decision feedback equalizer performs a decision on the original data signal to obtain a decision result, generates a first quantity of sampled data and a second quantity of error data based on the decision result, outputs the first quantity of sampled data to the first multiplexer, and simultaneously outputs the second quantity of error data to the second multiplexer.

[0011] The output terminal of the first multiplexer is connected to the first input terminal of the adaptive algorithm circuit, and the first multiplexer decomposes the first amount of sampled data into a third amount of sampled data based on a first preset ratio and outputs the third amount of sampled data to the adaptive algorithm circuit;

[0012] The output terminal of the second multiplexer is connected to the second input terminal of the adaptive algorithm circuit. The second multiplexer decomposes the second amount of error data into a fourth amount of error data based on a second preset ratio and outputs the fourth amount of error data to the adaptive algorithm circuit.

[0013] Preferably, the adaptive algorithm circuit includes a least mean square logic circuit, a voting circuit and an accumulation circuit;

[0014] The input end of the minimum mean square logic circuit is connected to the output end of the decision feedback equalizer circuit, and the output end of the minimum mean square logic circuit is connected to the input end of the voting circuit. The minimum mean square logic circuit is used to perform adaptive logic processing on the sampled data and the error data to obtain a tap coefficient increase signal and a tap coefficient decrease signal and output them to the voting circuit;

[0015] The output end of the voting circuit is connected to the input end of the accumulating circuit, and the voting circuit is used to calculate the tap coefficient increase signal and the tap coefficient decrease signal to obtain the tap coefficient output result step size and output it to the accumulating circuit;

[0016] The output end of the accumulation circuit is connected to the input end of the digital-to-analog converter circuit. The accumulation circuit accumulates the tap coefficient output result step size based on a preset accumulation value to obtain an accumulation result, and generates a control code word according to the accumulation result, and outputs the control code word to the digital-to-analog converter circuit.

[0017] Preferably, the expression of the tap coefficient reduction signal is:

[0018]

[0019] The expression of the tap coefficient increase signal is:

[0020]

[0021] Among them, Tap_Increase k Represents the kth feedback tap coefficient increase signal output by the least mean square logic circuit, Tap_Decrease k Represents the reduction signal of the kth feedback tap coefficient output by the least mean square logic circuit, e i Represents the error data at the current moment, d i-k Represents the first k bits of sampled data, d i Represents the sample data of the current bit.

[0022] Preferably, the step size of the tap coefficient output result is equal to the difference between the tap coefficient increase signal and the tap coefficient decrease signal;

[0023] When the step size of the tap coefficient output result is 0, the feedback tap coefficient remains unchanged;

[0024] When the step size of the tap coefficient output result is greater than 0, the feedback tap coefficient needs to be increased;

[0025] When the step size of the tap coefficient output result is less than 0, the feedback tap coefficient needs to be reduced.

[0026] Preferably, the accumulation circuit performs a summation operation on the step size of the tap coefficient output result based on a preset accumulation value to obtain a summation result, and performs a right shift operation on the summation result to obtain and output a control codeword, wherein the number of bits of the control codeword is equal to the number of bits of the digital-to-analog converter circuit.

[0027] Preferably, the digital-to-analog converter circuit includes a reference current source, a transmission gate switch, an NMOS tail current source, a PMOS current mirror, and a first NMOS field-effect transistor, wherein the number of the transmission gate switch and the NMOS tail current source is equal to the number of bits of the control codeword;

[0028] The output end of the reference current source is respectively connected to the input end of the plurality of transmission gate switches, the output end of each transmission gate switch is correspondingly connected to the input end of an NMOS tail current source, the output ends of the plurality of NMOS tail current sources are respectively connected to the input end of the PMOS current mirror, the output end of the PMOS current mirror is connected to the input end of the first NMOS field effect transistor, and the output end of the first NMOS field effect transistor is connected to the second input end of the decision feedback equalizer circuit;

[0029] The signal control end of the transmission gate switch receives the control code word and controls the on / off state of the transmission gate switch based on the control code word;

[0030] When the transmission gate switch is in the on state, the NMOS tail current source is in the on state, the output current of the reference current source passes through at least one NMOS tail current source in the on state, flows through the PMOS current mirror, and outputs a control voltage through the output end of the first NMOS field-effect transistor.

[0031] Preferably, the NMOS tail current source includes a second NMOS field effect transistor and a third NMOS field effect transistor, and the transmission gate switch includes a first signal control terminal and a second signal control terminal;

[0032] The second signal control terminal of the transmission gate switch is connected to the gate of the second NMOS field effect transistor, the source of the second NMOS field effect transistor is connected to the ground terminal, and the drain of the second NMOS field effect transistor is connected to the output terminal of the transmission gate switch;

[0033] The output end of the transmission gate switch is also connected to the gate of the third NMOS field effect transistor, the source of the third NMOS field effect transistor is connected to the ground end, and the drain of the third NMOS field effect transistor is connected to the input end of the PMOS current mirror;

[0034] The first signal control terminal and the second signal control terminal of the transmission gate switch are respectively connected to the output terminal of the adaptive algorithm circuit, the first signal control terminal of the transmission gate switch receives a first control signal based on the control codeword, and the second signal control terminal of the transmission gate switch receives a second control signal based on the control codeword;

[0035] When the first control signal is a high level signal and the second control signal is a low level signal, the transmission gate switch is in an on state;

[0036] When the first control signal is a low level signal and the second control signal is a high level signal, the transmission gate switch is in an off state.

[0037] Another aspect of the present invention provides an adaptive equalization method for a decision feedback equalizer, which is applied to the adaptive equalization circuit of any of the above-mentioned decision feedback equalizers, and includes:

[0038] The decision feedback equalizer circuit receives an original data signal, makes a decision on the original data signal to obtain a decision result, and outputs sampled data and error data based on the decision result;

[0039] The adaptive algorithm circuit receives the sampled data and the error data, processes the sampled data and the error data using a least mean square algorithm, and outputs a control codeword;

[0040] The digital-to-analog converter circuit receives the control code word, converts the control code word into a control voltage and outputs the control voltage;

[0041] The decision feedback equalizer circuit receives the control voltage and adjusts a feedback coefficient based on the control voltage.

[0042] Preferably, the adaptive algorithm circuit includes a minimum mean square (LMS) logic circuit, a voting circuit, and an accumulation circuit; the adaptive algorithm circuit receives the sampled data and the error data, processes the sampled data and the error data using a minimum mean square (LMS) algorithm, and outputs a control codeword, including:

[0043] The least mean square logic circuit performs adaptive logic processing on the sampled data and the error data to obtain a tap coefficient increase signal and a tap coefficient decrease signal and outputs them;

[0044] The voting circuit calculates the tap coefficient increase signal and the tap coefficient decrease signal to obtain a tap coefficient output result step length and outputs the result;

[0045] The accumulation circuit accumulates the tap coefficient output result step size to obtain an accumulation result, and performs a right shift operation on the accumulation result to obtain a control codeword and output it.

[0046] The present invention provides an adaptive equalization circuit and method for a decision feedback equalizer. The decision feedback equalizer circuit compensates the original data signal according to the decision result to minimize errors in transmission, thereby helping to reduce signal noise and distortion and improve the accuracy of data transmission. The adaptive algorithm circuit uses the least mean square (LMS) algorithm to process the sampled data and error data to obtain the optimal control codeword, thereby automatically adjusting the feedback coefficient and optimizing it according to the actual signal conditions, thereby improving system performance. The digital-to-analog converter circuit converts the control codeword into a control voltage. By adjusting the control voltage, the feedback coefficient of the decision feedback equalizer circuit can be accurately adjusted, further optimizing the signal transmission quality. In this application, the adaptive algorithm circuit adopts the least mean square (LMS) algorithm as the adaptive algorithm. The LMS algorithm is specifically a signed LMMS algorithm, which uses symbols instead of numerical values. It has the advantages of easy circuit implementation, low computational complexity, and smooth convergence. The signed LMMS algorithm is combined with the decision feedback equalizer circuit to achieve dynamic compensation for various channel losses and has faster and more stable convergence characteristics.

[0047] Other features and advantages of the present invention will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present invention. The purposes and other advantages of the present invention can be realized and obtained by the structures particularly pointed out in the written description, claims, and drawings.

[0048] The technical solution of the present invention is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings:

[0050] Figure 1 A schematic diagram of the structure of an adaptive equalization circuit of a decision feedback equalizer in one embodiment of the present application;

[0051] Figure 2 A schematic structural diagram of a decision feedback equalizer circuit in an adaptive equalization circuit of a decision feedback equalizer in one embodiment of the present application;

[0052] Figure 3 A schematic diagram of the structure of an adaptive algorithm circuit in an adaptive equalization circuit of a decision feedback equalizer in an embodiment provided by the present application;

[0053] Figure 4 A schematic diagram of the structure of a minimum mean square logic circuit in an adaptive algorithm circuit in an adaptive equalization circuit of a decision feedback equalizer in one embodiment of the present application;

[0054] Figure 5 A schematic diagram of the structure of a voting circuit and an accumulation circuit in an adaptive algorithm circuit in an adaptive equalization circuit of a decision feedback equalizer provided in an embodiment of the present application;

[0055] Figure 6 A schematic structural diagram of a digital-to-analog converter circuit in an adaptive equalization circuit of a decision feedback equalizer in one embodiment of the present application;

[0056] Figure 7 A schematic diagram of the current output of a digital-to-analog converter circuit in an adaptive equalization circuit of a decision feedback equalizer in one embodiment of the present application;

[0057] Figure 8 A schematic diagram of loop convergence of an adaptive equalization circuit of a decision feedback equalizer in one embodiment of the present application;

[0058] Figure 9 A flowchart of an adaptive equalization method of a decision feedback equalizer in an embodiment provided in this application is provided.

[0059] In the picture:

[0060] DATA_IN, raw data signal; 5-tap DFE, five-tap decision feedback equalizer; DACS, digital-to-analog converter circuit; Tapcode, control codeword; Vpost, control voltage; Tap_Decrease k , tap coefficient reduction signal; Tap_Increase k , the tap coefficient increases the signal;

[0061] D<>, the first signal control terminal of the transmission gate switch; DB<>, the second signal control terminal of the transmission gate switch; I REF , reference current source;

[0062] Q1, a first NMOS field effect transistor; Q2, a second NMOS field effect transistor; Q3, a third NMOS field effect transistor; Q4, a PMOS current mirror. DETAILED DESCRIPTION

[0063] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like to indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0064] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature identified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined.

[0065] In the present invention, unless otherwise expressly specified or limited, the terms "mounted," "connected," "connect," "fixed," etc. should be understood broadly. For example, they may refer to fixed, detachable, or integral connections; mechanical or electrical connections; direct or indirect connections through an intermediary; or internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0066] On one hand, the present invention provides an adaptive equalization circuit of a decision feedback equalizer, such as Figure 1 As shown, the circuit includes: a decision feedback equalizer circuit, an adaptive algorithm circuit and a digital-to-analog converter circuit, wherein the first input end of the decision feedback equalizer circuit receives the original data signal, the output end of the decision feedback equalizer circuit is connected to the input end of the adaptive algorithm circuit, the decision feedback equalizer circuit is used to make a decision on the original data signal to obtain a decision result, and output sampled data and error data to the adaptive algorithm circuit based on the decision result, the output end of the adaptive algorithm circuit is connected to the input end of the digital-to-analog converter circuit, the adaptive algorithm circuit uses a minimum mean square algorithm to process the sampled data and error data, obtains a control codeword and outputs it to the digital-to-analog converter circuit, the output end of the digital-to-analog converter circuit is connected to the second input end of the decision feedback equalizer circuit, the digital-to-analog converter circuit converts the control codeword into a control voltage and outputs it to the decision feedback equalizer circuit, and the decision feedback equalizer circuit adjusts the feedback coefficient of the decision feedback equalizer circuit based on the control voltage.

[0067] The adaptive equalization circuit of the decision feedback equalizer provided by the present invention compensates the original data signal according to the decision result to minimize the error in transmission, helps to reduce signal noise and distortion, and improves the accuracy of data transmission; the adaptive algorithm circuit uses the least mean square algorithm to process the sampled data and error data to obtain the optimal control codeword, and then automatically adjusts the feedback coefficient and optimizes it according to the actual signal conditions, thereby improving the system performance; the digital-to-analog converter circuit converts the control codeword into a control voltage, and by adjusting the control voltage, the feedback coefficient of the decision feedback equalizer circuit can be accurately adjusted to further optimize the signal transmission quality. In this application, the adaptive algorithm circuit adopts the least mean square algorithm as the adaptive algorithm. The least mean square algorithm is specifically a signed least mean square algorithm, that is, using symbols instead of numerical values. It has the advantages of easy circuit implementation, low computational complexity and smooth convergence. The signed least mean square algorithm is combined with the decision feedback equalizer circuit to achieve dynamic compensation for various channel losses and has faster and more stable convergence characteristics.

[0068] Specifically, the least mean square algorithm is an algorithm commonly used in optimization and estimation. It can obtain better parameter estimation or system optimization results. By adjusting parameters or control variables, the system performance can be optimized. At the same time, the least mean square algorithm has adaptive characteristics and can automatically adjust parameters or control variables according to actual input and feedback data to adapt to different environments and system conditions, thereby helping to improve the stability and adaptability of the system. The least mean square algorithm is very effective for processing signals containing noise. By minimizing the mean square error, the impact of noise on the signal can be reduced, and the quality and clarity of the signal can be improved. At the same time, the least mean square algorithm has good robustness to outliers or outliers. It is optimized through statistical characteristics rather than relying on the specific value of a single data point. Therefore, it has a certain resistance to outliers in the data and can obtain more robust results.

[0069] Specifically, in the above embodiment, the decision feedback equalizer circuit includes a five-tap decision feedback equalizer, a first multiplexer, and a second multiplexer, wherein the input end of the five-tap decision feedback equalizer receives the original data signal, the first output end of the five-tap decision feedback equalizer is connected to the input end of the first multiplexer, and the second output end of the five-tap decision feedback equalizer is connected to the input end of the second multiplexer. The five-tap decision feedback equalizer judges the original data signal to obtain a judgment result, and generates a first number of sampled data and a second number of error data based on the judgment result, outputs the first number of sampled data to the first multiplexer, and outputs the second number of error data to the second multiplexer at the same time; the output end of the first multiplexer is connected to the first input end of the adaptive algorithm circuit, the first multiplexer decomposes the first number of sampled data into a third number of sampled data based on a first preset ratio and outputs the third number of sampled data to the adaptive algorithm circuit; the output end of the second multiplexer is connected to the second input end of the adaptive algorithm circuit, the second multiplexer decomposes the second number of error data into a fourth number of error data based on a second preset ratio and outputs the fourth number of error data to the adaptive algorithm circuit.

[0070] Specifically, the five-tap decision feedback equalizer (DFEQ) is a commonly used equalizer in digital communication systems. Its equalization technology is used to eliminate time-domain distortion during signal transmission. In digital communications, signals may be subject to various interferences during transmission, such as multipath and clock skew, which can cause signal distortion. The goal of the DFEQ is to minimize distortion by introducing noise and distortion estimates at the receiving end and calculating corresponding correction coefficients. A five-tap DFEQ uses five delay elements or filters in the equalizer's feedback path. These delay elements or filters are used to store and process previously received signal samples to make appropriate corrections.

[0071] In this embodiment, the decision feedback equalizer circuit structure is as follows: Figure 2 As shown, the five-tap decision feedback equalizer receives the original data signal input from the outside and attenuated by the channel, obtains a decision result by judging the original data signal, and outputs 4 channels of sampled data and 2 channels of error data, wherein the 4 channels of sampled data are passed to the first multiplexer, which is a 4:16 multiplexer, and the 4 channels of sampled data are decomposed into 16 channels of sampled data; at the same time, the 2 channels of error data are passed to the second multiplexer, which is a 2:8 multiplexer, to obtain 8 channels of error data, and finally the 16 channels of sampled data and 8 channels of error data are output to the adaptive algorithm circuit.

[0072] Specifically, in the above embodiment, Figure 3As shown, the adaptive algorithm circuit includes a minimum mean square logic circuit, a voting circuit and an accumulation circuit, wherein the input end of the minimum mean square logic circuit is connected to the output end of the decision feedback equalizer circuit, the output end of the minimum mean square logic circuit is connected to the input end of the voting circuit, the minimum mean square logic circuit is used to perform adaptive logic processing on the sampling data and the error data, obtain the tap coefficient increase signal and the tap coefficient decrease signal and output them to the voting circuit, the output end of the voting circuit is connected to the input end of the accumulation circuit, the voting circuit is used to calculate the tap coefficient increase signal and the tap coefficient decrease signal, obtain the tap coefficient output result step length and output it to the accumulation circuit, the output end of the accumulation circuit is connected to the input end of the digital-to-analog converter circuit, the accumulation circuit accumulates the tap coefficient output result step length based on a preset accumulation value to obtain an accumulation result, generates a control codeword according to the accumulation result, and outputs the control codeword to the digital-to-analog converter circuit.

[0073] In this embodiment, the adaptive algorithm circuit is refined according to its specific function, and then the adaptive algorithm circuit structure is split into a minimum mean square logic circuit, a voting circuit and an accumulation circuit. Specifically, the minimum mean square logic circuit is used to perform adaptive logic processing on the sampling data and error data output by the decision feedback equalizer circuit. The voting circuit determines whether the feedback tap coefficient of the decision feedback equalizer circuit is increased or decreased based on the result output by the minimum mean square logic circuit of the previous level symbol. The accumulation circuit is used to determine the range of increase or decrease of the coefficient based on the result of the previous level voting circuit. Specifically, the minimum mean square logic circuit performs adaptive logic processing on the sampling data and error data, and can dynamically adjust the size of the feedback tap coefficient increase signal and the feedback tap coefficient decrease signal according to the actual input data and error conditions to minimize the error and improve the system performance; the voting circuit calculates the feedback tap coefficient increase signal and the feedback tap coefficient decrease signal, and obtains different feedback tap coefficients through the voting mechanism combined with multiple adaptive processing, so as to obtain a more robust and accurate tap coefficient output result step size; the accumulation circuit accumulates and calculates the feedback tap coefficient output result step size based on the preset accumulation value, and thus effectively adjusts the change rate of the tap coefficient so that the system optimization is carried out gradually to avoid too fast or too slow adjustments; the accumulation result is used as input, and a control code word is generated according to the accumulation result, and it is output to the digital-to-analog converter circuit, allowing the generation of appropriate control code words to adjust the control voltage of the decision feedback equalizer circuit according to the size and direction of the accumulation result, thereby realizing the adjustment of the feedback coefficient.

[0074] Furthermore, the expression of the tap coefficient reduction signal is:

[0075]

[0076] The expression of the tap coefficient increase signal is:

[0077]

[0078] Among them, Tap_Increase k Represents the kth feedback tap coefficient increase signal output by the least mean square logic circuit, Tap_Decrease k Represents the reduction signal of the kth feedback tap coefficient output by the least mean square logic circuit, e i Represents the error data at the current moment, d i-k Represents the first k bits of sampled data, d i Represents the sample data of the current bit.

[0079] In this embodiment, since there are only high level 1 and low level 0 in the digital circuit, the e in the symbolic least mean square algorithm iteration formula is i ×d i-k There are two output results: ±1. In this algorithm, use Tap_Increase k and Tap_Decrease k To replace the changes in the two directions of +1 and -1. At the same time, only the current bit sampling data d i is 1, It can be set to 1, and the correct error data can be selected according to the code type of the current bit to ensure the stability of convergence.

[0080] Specifically, the structure of the least mean square logic circuit is as follows: Figure 4 As shown, Tap_Decrease1 is obtained by performing an XOR operation between e[i] and d[i-1], and performing an AND operation on the result obtained by performing an XOR operation between e[i] and d[i-1], and performing an AND operation on the result obtained by performing an XOR operation between e[i] and d[i-1]. In the figure, Tap_Increase1, Tap_Increase2, Tap_Increase3, Tap_Increase4, and Tap_Increase5 respectively represent the increase signals of the first, second, third, fourth, and fifth feedback tap coefficients output by the minimum mean square logic circuit, and Tap_Decrease1, Tap_Decrease2, Tap_Decrease3, Tap_Decrease4, and Tap_Decrease5 represent the decrease signals of the first, second, third, fourth, and fifth feedback tap coefficients output by the minimum mean square logic circuit. e i Represents the error signal at the current moment, d i-1 d i-2 d i-3 d i-4d i-5 Represents the sampling data of the first, second, third, fourth, and fifth digits, d i Represents the sampling data of the current bit. The specific expressions are:

[0081]

[0082]

[0083]

[0084]

[0085]

[0086]

[0087]

[0088]

[0089]

[0090]

[0091] Furthermore, the step size of the tap coefficient output result is equal to the difference between the tap coefficient increase signal and the tap coefficient decrease signal; when the step size of the tap coefficient output result is 0, the feedback tap coefficient remains unchanged; when the step size of the tap coefficient output result is greater than 0, the feedback tap coefficient needs to be increased; when the step size of the tap coefficient output result is less than 0, the feedback tap coefficient needs to be reduced.

[0092] In this embodiment, the voting circuit receives the Tap_Increase and Tap_decrease signals output by the least mean square logic circuit and performs the following processing on the Tap_Increase and Tap_decrease signals:

[0093] The specific formula is:

[0094] STEP k =Tap_Increase k -Tap_Decrease k

[0095] Among them STEP k Represents the step size of the kth feedback tap coefficient output result.

[0096] Based on the Tap_Increase and Tap_decrease signals output by the minimum mean square logic circuit obtained in the previous step, the following is calculated:

[0097] STEP1=Tap_Increase1-Tap_Decrease1

[0098] STEP2=Tap_Increase2-Tap_Decrease2

[0099] STEP3=Tap_Increase3-Tap_Decrease3

[0100] STEP4=Tap_Increase4-Tap_Decrease4

[0101] STEP5=Tap_Increase5-Tap-Decrease5

[0102] Among them, STEP1, STEP2, STEP3, STEP4, and STEP5 represent the first, second, third, fourth, and fifth feedback tap coefficient output result step sizes, respectively. When STEP is 0, it means that the feedback tap coefficient does not increase or decrease; when STEP is greater than 0, it means that the corresponding feedback tap coefficient needs to increase; when STEP is less than 0, it means that the corresponding feedback tap coefficient needs to decrease.

[0103] Furthermore, the accumulation circuit performs a summation operation on the step size of the tap coefficient output result based on a preset accumulation value to obtain a summation result, and performs a right shift operation on the summation result to obtain and output a control codeword, wherein the number of bits of the control codeword is equal to the number of bits of the digital-to-analog converter circuit.

[0104] In this embodiment, the circuit diagram of the voting circuit combined with the accumulation circuit is as follows: Figure 5 As shown, the generated step value is input to the accumulation circuit for accumulation, and the input coefficient change value is summed with the preset accumulation value at the low bit. Because the subsequent digital-to-analog converter circuit has only 5 bits, the output result of the accumulation circuit can only take the value of the upper five bits, that is, the output of the accumulation circuit needs to be right-shifted. Only when the low-bit data overflows will the upper five-bit data change, thereby effectively avoiding the influence of interference signals such as noise on the overall adaptive algorithm and ensuring the stable convergence characteristics of the overall adaptive algorithm.

[0105] Specifically, in the above embodiment, the digital-to-analog converter circuit includes a reference current source, a transmission gate switch, an NMOS tail current source, a PMOS current mirror, and a first NMOS field-effect transistor, wherein the number of transmission gate switches and NMOS tail current sources is equal to the number of bits of the control codeword; the output end of the reference current source is respectively connected to the input ends of multiple transmission gate switches, the output end of each transmission gate switch is correspondingly connected to the input end of an NMOS tail current source, the output ends of the multiple NMOS tail current sources are respectively connected to the input ends of the PMOS current mirror, the output end of the PMOS current mirror is connected to the input end of the first NMOS field-effect transistor, and the output end of the first NMOS field-effect transistor is connected to the second input end of the decision feedback equalizer circuit; the signal control end of the transmission gate switch receives the control codeword and controls the conduction state of the transmission gate switch based on the control codeword; when the transmission gate switch is in the conduction state, the NMOS tail current source is in the conduction state, the output current of the reference current source passes through at least one NMOS tail current source in the conduction state, flows through the PMOS current mirror, and outputs the control voltage through the output end of the first NMOS field-effect transistor.

[0106] In this embodiment, the reference current source provides a high-precision reference current for the digital-to-analog converter circuit; the coordinated use of the transmission gate switch and the control codeword can achieve precise control of the transmission gate switch. By controlling the conduction state of the transmission gate switch through the control codeword, it can be accurately determined whether the reference current source flows through the NMOS tail current source through the PMOS current mirror to achieve the purpose of accurately outputting the control voltage; the NMOS tail current source is in the on or off state under the control of the control codeword. By timely switching the NMOS tail current source, it can be turned off when the output control voltage is not needed, and the low-power design helps save energy and extend battery life; the first NMOS field-effect transistor receives the current from the PMOS current mirror and outputs the control voltage according to the conduction state controlled by the reference current source, which helps to provide accurate and stable output, ensuring the accuracy and stability of the digital-to-analog converter.

[0107] Furthermore, the NMOS tail current source includes a second NMOS field-effect transistor and a third NMOS field-effect transistor, and the transmission gate switch includes a first signal control end and a second signal control end; the second signal control end of the transmission gate switch is connected to the gate of the second NMOS field-effect transistor, the source of the second NMOS field-effect transistor is connected to the ground end, and the drain of the second NMOS field-effect transistor is connected to the output end of the transmission gate switch; the output end of the transmission gate switch is also connected to the gate of the third NMOS field-effect transistor, the source of the third NMOS field-effect transistor is connected to the ground end, and the drain of the third NMOS field-effect transistor is connected to the input end of the PMOS current mirror; the first signal control end and the second signal control end of the transmission gate switch are respectively connected to the output end of the adaptive algorithm circuit, the first signal control end of the transmission gate switch receives a first control signal based on the control code word, and the second signal control end of the transmission gate switch receives a second control signal based on the control code word; when the first control signal is a high-level signal and the second control signal is a low-level signal, the transmission gate switch is in an on state; when the first control signal is a low-level signal and the second control signal is a high-level signal, the transmission gate switch is in an off state.

[0108] In this embodiment, the transmission gate switch can accurately control the conduction state of the transmission gate switch according to the input of the control code word and the control signal. By adjusting the levels of the first control signal and the second control signal, the transmission gate switch can be placed in the on or off state, ensuring that the NMOS tail current source is in the on state when needed to achieve the required current flow path; by adjusting the control signal of the transmission gate switch, the conduction and off states of the NMOS tail current source can be adjusted. When the transmission gate switch is in the on state, the second NMOS field-effect transistor is turned on, so that the output current of the reference current source flows through the NMOS tail current source through the PMOS current mirror, and then the current output of the tail current source is adjusted according to actual needs; through the combination of the transmission gate switch and the third NMOS field-effect transistor, the control voltage can be accurately transmitted to the PMOS current mirror. The conduction state of the transmission gate switch controls the third NMOS field-effect transistor, thereby affecting the transmission path of the control voltage, and ultimately achieving accurate and stable control of the PMOS current mirror.

[0109] Specifically, the overall structure of the digital-to-analog converter circuit is as follows: Figure 6 As shown in the figure, the size of the NMOS tail current source of each bit in the digital-to-analog converter circuit increases from low to high. The transmission gate switch controls the shutdown of the NMOS tail current source. When D is high and DB is low, the transmission gate switch is turned on and the NMOS tail current source is turned on; when D is low and DB is high, the transmission gate switch is turned off and the NMOS tail current source is turned off. The total current I is output through the NMOS tail current source in the on state. outAfter being copied by the PMOS current mirror, the control voltage V is generated by the first NMOS field effect transistor connected to the gate and drain below. out .

[0110] The specific experimental results of the adaptive equalization circuit of the decision feedback equalizer provided in this application are as follows:

[0111] like Figure 7 As shown in the figure, the output current of the DAC circuit is increased from 0 to the maximum value. From the simulation, it can be seen that the output result of the DAC circuit meets the requirements, but a large leakage current will be generated when different control codes are switched. Since the control code will remain stable after a period of time in the entire adaptive loop, the influence of leakage current can be ignored when the code word is stable. Figure 8 The figure shows the convergence of the adaptive equalization circuit loop of the entire decision feedback equalizer. The adaptive algorithm circuit generates a control code corresponding to the feedback tap coefficient based on the decision feedback equalizer circuit. The control code corresponding to the feedback tap coefficient is output to the digital-to-analog converter circuit, which generates a corresponding control voltage and feeds it back to the decision feedback equalizer circuit. After 1.5us, the control voltage begins to stabilize, indicating that the entire loop has reached convergence.

[0112] Another aspect of the present invention provides an adaptive equalization method for a decision feedback equalizer, which is applied to the adaptive equalization circuit of the decision feedback equalizer, such as Figure 9 As shown, the decision feedback equalizer circuit receives the original data signal, makes a decision on the original data signal to obtain a decision result, and outputs sampled data and error data based on the decision result; the adaptive algorithm circuit receives the sampled data and error data, processes the sampled data and error data using the least mean square algorithm, and outputs a control codeword; the digital-to-analog converter circuit receives the control codeword, converts the control codeword into a control voltage and outputs it; the decision feedback equalizer circuit receives the control voltage and adjusts the feedback coefficient based on the control voltage.

[0113] The above method is applied to the adaptive equalization circuit of the decision feedback equalizer, and the least mean square algorithm is used as the adaptive algorithm. The least mean square algorithm is combined with the decision feedback equalizer circuit to achieve dynamic compensation for various channel losses and has a faster and more stable convergence characteristic.

[0114] Specifically, in the above embodiment, the adaptive algorithm circuit includes a minimum mean square logic circuit, a voting circuit and an accumulation circuit; the adaptive algorithm circuit receives sampling data and error data, processes the sampling data and error data using the minimum mean square algorithm, and outputs a control codeword, including: first, the minimum mean square logic circuit performs adaptive logic processing on the sampling data and error data to obtain a tap coefficient increase signal and a tap coefficient decrease signal and outputs them, then the voting circuit calculates the tap coefficient increase signal and the tap coefficient decrease signal to obtain a tap coefficient output result step length and outputs it, finally, the accumulation circuit accumulates the tap coefficient output result step length to obtain an accumulated result, and performs a right shift operation on the accumulated result to obtain a control codeword and output it.

[0115] In this embodiment, the adaptive algorithm circuit realizes dynamic adjustment of tap coefficients and optimization of signal processing through adaptive logic processing, voting calculation, accumulation operation and control codeword generation, which helps to improve the robustness, adaptability and performance of the system, thereby achieving better signal processing effects.

[0116] Obviously, those skilled in the art may make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if such changes and modifications fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. An adaptive equalization circuit for a decision feedback equalizer, characterized in that: include: Decision feedback equalizer circuit, adaptive algorithm circuit and digital-to-analog converter circuit; The first input end of the decision feedback equalizer circuit receives the original data signal, the output end of the decision feedback equalizer circuit is connected to the input end of the adaptive algorithm circuit, the decision feedback equalizer circuit is used to make a decision on the original data signal to obtain a decision result, and output sampled data and error data to the adaptive algorithm circuit based on the decision result; The output end of the adaptive algorithm circuit is connected to the input end of the digital-to-analog converter circuit, and the adaptive algorithm circuit processes the sampled data and the error data using a least mean square algorithm to obtain a control codeword and outputs the control codeword to the digital-to-analog converter circuit; The output end of the digital-to-analog converter circuit is connected to the second input end of the decision feedback equalizer circuit. The digital-to-analog converter circuit converts the control codeword into a control voltage and outputs it to the decision feedback equalizer circuit. The decision feedback equalizer circuit adjusts the feedback coefficient of the decision feedback equalizer circuit based on the control voltage.

2. The adaptive equalization circuit of the decision feedback equalizer according to claim 1, wherein: The decision feedback equalizer circuit includes a five-tap decision feedback equalizer, a first multiplexer and a second multiplexer; An input end of the five-tap decision feedback equalizer receives an original data signal, a first output end of the five-tap decision feedback equalizer is connected to an input end of the first multiplexer, and a second output end of the five-tap decision feedback equalizer is connected to an input end of the second multiplexer. The five-tap decision feedback equalizer performs a decision on the original data signal to obtain a decision result, generates a first quantity of sampled data and a second quantity of error data based on the decision result, outputs the first quantity of sampled data to the first multiplexer, and simultaneously outputs the second quantity of error data to the second multiplexer. The output terminal of the first multiplexer is connected to the first input terminal of the adaptive algorithm circuit, and the first multiplexer decomposes the first amount of sampled data into a third amount of sampled data based on a first preset ratio and outputs the third amount of sampled data to the adaptive algorithm circuit; The output terminal of the second multiplexer is connected to the second input terminal of the adaptive algorithm circuit. The second multiplexer decomposes the second amount of error data into a fourth amount of error data based on a second preset ratio and outputs the fourth amount of error data to the adaptive algorithm circuit.

3. The adaptive equalization circuit of the decision feedback equalizer according to claim 1, wherein: The adaptive algorithm circuit includes a minimum mean square logic circuit, a voting circuit and an accumulation circuit; The input end of the minimum mean square logic circuit is connected to the output end of the decision feedback equalizer circuit, and the output end of the minimum mean square logic circuit is connected to the input end of the voting circuit. The minimum mean square logic circuit is used to perform adaptive logic processing on the sampled data and the error data to obtain a tap coefficient increase signal and a tap coefficient decrease signal and output them to the voting circuit; The output end of the voting circuit is connected to the input end of the accumulating circuit, and the voting circuit is used to calculate the tap coefficient increase signal and the tap coefficient decrease signal to obtain the tap coefficient output result step size and output it to the accumulating circuit; The output end of the accumulation circuit is connected to the input end of the digital-to-analog converter circuit. The accumulation circuit accumulates the tap coefficient output result step size based on a preset accumulation value to obtain an accumulation result, and generates a control code word according to the accumulation result, and outputs the control code word to the digital-to-analog converter circuit.

4. The adaptive equalization circuit of the decision feedback equalizer according to claim 3, wherein: The expression of the tap coefficient reduction signal is: The expression of the tap coefficient increase signal is: Among them, Tap_Increase k Represents the kth feedback tap coefficient increase signal output by the least mean square logic circuit, Tap_Decreast k Represents the reduction signal of the kth feedback tap coefficient output by the least mean square logic circuit, e i Represents the error data at the current moment, d i-k Represents the first k bits of sampled data, d i Represents the sample data of the current bit.

5. The adaptive equalization circuit of the decision feedback equalizer according to claim 4, characterized in that: The step size of the tap coefficient output result is equal to the difference between the tap coefficient increase signal and the tap coefficient decrease signal; When the step size of the tap coefficient output result is 0, the feedback tap coefficient remains unchanged; When the step size of the tap coefficient output result is greater than 0, the feedback tap coefficient needs to be increased; When the step size of the tap coefficient output result is less than 0, the feedback tap coefficient needs to be reduced.

6. The adaptive equalization circuit of the decision feedback equalizer according to claim 4, characterized in that: The accumulation circuit performs a summation operation on the step size of the tap coefficient output result based on a preset accumulation value to obtain a summation result, and performs a right shift operation on the summation result to obtain and output a control codeword, wherein the number of bits of the control codeword is equal to the number of bits of the digital-to-analog converter circuit.

7. The adaptive equalization circuit of the decision feedback equalizer according to claim 1, wherein: The digital-to-analog converter circuit includes a reference current source, a transmission gate switch, an NMOS tail current source, a PMOS current mirror, and a first NMOS field-effect transistor, wherein the number of the transmission gate switch and the NMOS tail current source is equal to the number of bits of the control codeword; The output end of the reference current source is respectively connected to the input end of the plurality of transmission gate switches, the output end of each transmission gate switch is correspondingly connected to the input end of an NMOS tail current source, the output ends of the plurality of NMOS tail current sources are respectively connected to the input end of the PMOS current mirror, the output end of the PMOS current mirror is connected to the input end of the first NMOS field effect transistor, and the output end of the first NMOS field effect transistor is connected to the second input end of the decision feedback equalizer circuit; The signal control end of the transmission gate switch receives the control code word and controls the on / off state of the transmission gate switch based on the control code word; When the transmission gate switch is in the on state, the NMOS tail current source is in the on state, the output current of the reference current source passes through at least one NMOS tail current source in the on state, flows through the PMOS current mirror, and outputs a control voltage through the output end of the first NMOS field-effect transistor.

8. The adaptive equalization circuit of the decision feedback equalizer according to claim 1, wherein: The NMOS tail current source includes a second NMOS field effect transistor and a third NMOS field effect transistor, and the transmission gate switch includes a first signal control terminal and a second signal control terminal; The second signal control terminal of the transmission gate switch is connected to the gate of the second NMOS field effect transistor, the source of the second NMOS field effect transistor is connected to the ground terminal, and the drain of the second NMOS field effect transistor is connected to the output terminal of the transmission gate switch; The output end of the transmission gate switch is also connected to the gate of the third NMOS field effect transistor, the source of the third NMOS field effect transistor is connected to the ground end, and the drain of the third NMOS field effect transistor is connected to the input end of the PMOS current mirror; The first signal control terminal and the second signal control terminal of the transmission gate switch are respectively connected to the output terminal of the adaptive algorithm circuit, the first signal control terminal of the transmission gate switch receives a first control signal based on the control codeword, and the second signal control terminal of the transmission gate switch receives a second control signal based on the control codeword; When the first control signal is a high level signal and the second control signal is a low level signal, the transmission gate switch is in an on state; When the first control signal is a low level signal and the second control signal is a high level signal, the transmission gate switch is in an off state.

9. An adaptive equalization method for a decision feedback equalizer, characterized in that: The method is applied to an adaptive equalization circuit of a decision feedback equalizer according to any one of claims 1 to 8, and the method comprises: The decision feedback equalizer circuit receives an original data signal, makes a decision on the original data signal to obtain a decision result, and outputs sampled data and error data based on the decision result; The adaptive algorithm circuit receives the sampled data and the error data, processes the sampled data and the error data using a least mean square algorithm, and outputs a control codeword; The digital-to-analog converter circuit receives the control code word, converts the control code word into a control voltage and outputs the control voltage; The decision feedback equalizer circuit receives the control voltage and adjusts a feedback coefficient based on the control voltage.

10. The adaptive equalization method of decision feedback equalizer according to claim 9, characterized in that: The adaptive algorithm circuit includes a minimum mean square root logic circuit, a voting circuit, and an accumulation circuit; the adaptive algorithm circuit receives the sampled data and the error data, processes the sampled data and the error data using a minimum mean square root algorithm, and outputs a control codeword, including: The least mean square logic circuit performs adaptive logic processing on the sampled data and the error data to obtain a tap coefficient increase signal and a tap coefficient decrease signal and outputs them; The voting circuit calculates the tap coefficient increase signal and the tap coefficient decrease signal to obtain a tap coefficient output result step length and outputs the result; The accumulation circuit accumulates the tap coefficient output result step size to obtain an accumulation result, and performs a right shift operation on the accumulation result to obtain a control codeword and output it.

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