Imaging element and imaging device

Abstract

An imaging element includes: a first substrate provided with a photoelectric conversion unit that generates electric charges by photoelectric conversion, a signal line to which a signal based on the electric charges generated by the photoelectric conversion unit is output, and a supply unit that supplies a voltage to the signal line so that the voltage of the signal line does not become equal to or less than a predetermined voltage; and a second substrate laminated on the first substrate and provided with a processing unit for processing a signal output to the signal line.

Description

[0001] This invention is a divisional application of the invention application with an international application date of September 30, 2020, international application number PCT / JP2020 / 037288, national application number 202080067636.1 entering the Chinese national phase, and invention name “Image capture element and image capture device”. Technical Field

[0002] The present invention relates to an imaging element and an imaging device. Background Art

[0003] An imaging element is known in which a transistor for clamping a signal output from a pixel to a predetermined voltage level is provided for each column (Patent Document 1).

[0004] Prior art literature

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent Application Laid-Open No. 2004-222273 Summary of the Invention

[0007] According to the first aspect, the imaging element comprises: a first substrate, which is provided with a photoelectric conversion portion that generates charges through photoelectric conversion, a signal line to which a signal based on the charges generated by the photoelectric conversion portion is output, and a supply portion that supplies a voltage to the signal line in a manner that does not cause the voltage of the signal line to become lower than a specified voltage; and a second substrate stacked on the first substrate, which is provided with a processing portion that processes the signal output to the signal line.

[0008] According to a second aspect, an imaging device includes: the imaging element according to the first aspect; and a generating unit that generates image data based on the signal processed by the processing unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 This is a diagram showing a configuration example of an imaging device according to the first embodiment.

[0010] Figure 2 This is a block diagram showing a configuration example of an image pickup element according to the first embodiment.

[0011] Figure 3 This is a diagram showing an example of a cross-sectional structure of a portion of the imaging element according to the first embodiment.

[0012] Figure 4 This is a diagram showing a configuration example of a portion of the image sensor according to the first embodiment.

[0013] Figure 5 This is a timing chart showing an example of the operation of the imaging element according to the first embodiment.

[0014] Figure 6 This is a timing chart showing an example of the operation of the imaging element according to the first embodiment.

[0015] Figure 7 This is a diagram showing an example of a layout of a portion of the imaging element according to the first embodiment.

[0016] Figure 8 This is a diagram showing an example of a layout of a portion of an imaging element according to a modified example.

[0017] Figure 9 This is a diagram showing another example of the layout of a portion of an imaging element according to a modified example. DETAILED DESCRIPTION

[0018] (First embodiment)

[0019] Figure 1 This figure shows an example configuration of a camera 1, which is an example of an imaging device according to the first embodiment. The camera 1 includes a photographing optical system (imaging optical system) 2, an imaging element 3, a control unit 4, a memory 5, a display unit 6, and an operating unit 7. The photographing optical system 2 includes multiple lenses, including a focus adjustment lens (focusing lens), and an aperture stop, and forms a subject image on the imaging element 3. The photographing optical system 2 may also be detachable from the camera 1.

[0020] The imaging element 3 is an imaging element such as a CMOS image sensor or a CCD image sensor. The imaging element 3 receives the light beam passing through the imaging optical system 2 and captures the subject image formed by the imaging optical system 2. The imaging element 3 has a plurality of pixels having a photoelectric conversion unit arranged two-dimensionally (in the row and column directions). The photoelectric conversion unit is composed of a photodiode (PD). The imaging element 3 performs photoelectric conversion on the received light to generate a signal, which is then output to the control unit 4.

[0021] The memory 5 is a recording medium such as a memory card. Image data, control programs, and the like are recorded in the memory 5. Writing data to and reading data from the memory 5 are controlled by the control unit 4. The display unit 6 displays images based on the image data, shooting-related information such as shutter speed and aperture value, and menu screens. The operating unit 7 includes various setting switches, such as a release button, a power switch, and switches for switching between various modes, and outputs signals based on their respective operations to the control unit 4.

[0022] The control unit 4 is composed of a processor such as a CPU, FPGA, or ASIC, and memory such as ROM and RAM, and controls various components of the camera 1 based on a control program. The control unit 4 supplies control signals to the imaging element 3, thereby controlling the operation of the imaging element 3. The control unit 4 causes the imaging element 3 to capture an image of the subject and output a signal, such as when capturing still images, capturing moving images, or displaying a live view image of the subject on the display unit 6.

[0023] The control unit 4 performs various image processing on the signal output from the imaging element 3 to generate image data. The control unit 4 is also the image data generation unit 4, and generates still image data and moving image data based on the signal output from the imaging element 3. Image processing includes grayscale conversion processing, color interpolation processing, and other image processing.

[0024] Figure 2 This is a block diagram illustrating an example configuration of an imaging element according to the first embodiment. The imaging element 3 is constructed by laminating a first substrate 111 on which a plurality of pixels 10 are provided and a second substrate 112 on which a readout unit 60 is provided. The first substrate 111 and the second substrate 112 are each formed using a semiconductor substrate. The circuits provided on the first substrate 111 and the circuits provided on the second substrate 112 are electrically connected using connectors such as electrodes and bumps.

[0025] The first substrate 111 includes a plurality of regions 20 in which a plurality of pixels 10 are arranged. Figure 2 In the example shown, four regions 20 are illustrated. These four regions 20 each represent a region where the area where the pixels 10 of the first substrate 111 are arranged is divided into regions containing a predetermined number of pixels. Furthermore, the regions 20 may or may not partially overlap. The number of pixels in each region 20 can be 4 pixels (2 pixels x 2 pixels), or 16 pixels (4 pixels x 4 pixels), or any other number. Hereinafter, the regions 20 are referred to as pixel blocks 20.

[0026] For each pixel block 20, a signal line 22 and a supply unit 30 (described later) are provided on the first substrate 111. Furthermore, for each pixel block 20, a pixel control unit and a supply control unit are provided on the first substrate 111, which will be described in detail later. The signal line 22 connects the pixel block 20 to the readout unit 60 and outputs a signal from the pixel 10. The signal line 22 uses a connecting portion such as an electrode or bump.

[0027] The readout section 60 includes a processing section 50 including an analog / digital converter (AD converter) 40. The processing section 50 is provided for each pixel block 20. In the imaging element 3 of this embodiment, the signals from the pixels of the plurality of pixel blocks 20 are read in parallel using the signal lines 22 provided for each pixel block 20. The readout section 60 can simultaneously (in parallel) output the signals of the pixels of each pixel block 20 to the processing section 50 provided for each pixel block 20, and simultaneously perform signal processing on the pixel signals in each processing section 50. Since each processing section 50 simultaneously processes the signals output from each pixel block 20, the readout section 60 can perform high-speed signal processing.

[0028] The AD converter 40 of the processing unit 50 converts the pixel signal, which is an analog signal input from each pixel 10 of the pixel block 20 via the signal line 22, into a digital signal. Furthermore, the processing unit 50 may include an amplifier that amplifies the pixel signal input via the signal line 22 at a predetermined gain (amplification rate). In this case, the AD converter 40 converts the pixel signal amplified by the amplifier into a digital signal.

[0029] The pixel signals converted into digital signals undergo signal processing such as correlated double sampling (CDS) or signal quantity correction in the processing unit 50 before being output to the control unit 4 of the camera 1. Alternatively, signal processing such as correlated double sampling may be performed on the pixel signals in a signal processing unit (not shown). In this case, the processing unit 50 outputs the pixel signals converted into digital signals by the A / D conversion unit 40 to the signal processing unit. The signal processing unit performs signal processing such as correlated double sampling on the input pixel signals and then outputs the processed pixel signals to the control unit 4.

[0030] A plurality of electrodes (pads) 200 for supplying (applying) the power supply voltage VDD are provided around the area where each pixel 10 is arranged on the first substrate 111. The electrodes 200 are connected to the plurality of pixels 10 and the supply unit 30 arranged on the first substrate 111 via wiring (power supply line) 121. The power supply voltage VDD is supplied to the pixels 10 and the supply unit 30 via the power supply line 121. The electrode 200 is a common electrode for the plurality of pixels 10 and the supply unit 30. Figure 2 As shown, it is arranged on one surface of the first substrate 111.

[0031] Hereinafter, the configuration of the image pickup element 3 according to the present embodiment will be further described with reference to the drawings.

[0032] Figure 3 This is a diagram showing an example of a cross-sectional structure of a portion of the imaging element according to the first embodiment. Figure 4This is a diagram showing a configuration example of a portion of the image sensor according to the first embodiment. Figure 3 The image sensor 3 shown is a back-illuminated image sensor. It includes a first substrate 111, a wiring layer 101 stacked on the first substrate 111, a second substrate 112, and a wiring layer 102 stacked on the second substrate 112. Wiring layers 101 and 102 are each composed of a conductor film (metal film) and an insulating film, and are provided with a plurality of wirings, connecting portions, interlayer insulating films, and the like.

[0033] Direction of light from the subject Figure 3 The Z axis is incident. In addition, if Figure 3 As shown in the coordinate axis, the right direction of the paper perpendicular to the Z axis is set as the positive direction of the X axis, and the front direction of the paper perpendicular to the Z axis and the X axis is set as the positive direction of the Y axis. Figure 3 The coordinate axes are displayed using the coordinate axes of FIG. 1 as a reference to understand the orientation of each figure. On the first substrate 111 and wiring layer 101, a plurality of pixel blocks 20, each including a plurality of pixels 10 and a supply unit 30, are arranged in the X-axis and Y-axis directions. On the second substrate 112 and wiring layer 102, a plurality of processing units 50 are arranged in the X-axis and Y-axis directions.

[0034] exist Figure 4 , a portion of the pixels 10, a portion of the current source 25 and the supply unit 30, a portion of the pixel control unit 35 and the supply control unit 36, and a readout control unit 70 are shown among the plurality of pixels 10 provided in the image sensor 3. The current source 25 and the supply unit 30 are provided with respect to the signal line 22. The pixel control unit 35 and the supply control unit 36 are provided for each pixel block 20. Figure 4 In order to simplify the drawing, only one pixel 10 is shown for one pixel block 20.

[0035] The pixel 10 includes a photoelectric converter 11, a transfer unit 12, a floating diffusion (FD) 13, a reset unit 14, an amplifier 15, and a selection unit 16. The photoelectric converter 11 is a photodiode PD that converts incident light into charges and accumulates the photoelectrically converted charges.

[0036] The transfer unit 12, comprised of a transistor M1 controlled by a signal TX, transfers the charge photoelectrically converted by the photoelectric converter 11 to the FD 13. Transistor M1 is a transfer transistor. The FD 13 accumulates (holds) the charge transferred to it and converts the resulting voltage into a voltage divided by its capacitance. The FD 13 is the storage unit 13, storing the charge generated by the photoelectric converter 11.

[0037] The amplifier 15 is composed of a transistor M3 whose gate (terminal) is connected to the FD13, and amplifies and outputs a signal based on the charge accumulated in the FD13. The drain (terminal) of the transistor M3 is connected to the electrode 200 (see Figure 2 ), and is supplied with power supply voltage VDD. The source (terminal) of transistor M3 is connected to signal line 22 via selector 16. Amplifier 15 uses current source 25 as a load current source, functioning as part of a source-follower circuit. Transistor M3 is an amplifier transistor. Amplifier 15 and selector 16 constitute an output unit that generates and outputs a signal based on the charge generated by photoelectric converter 11.

[0038] The reset unit 14, comprised of a transistor M2 controlled by a signal RST, electrically connects or disconnects the FD 13 and the power supply line 121. The reset unit 14 resets the charge accumulated in the FD 13. The reset unit 14 discharges the charge accumulated in the FD 13, resetting the voltage of the FD 13. Transistor M2 is a reset transistor. The selector 16, comprised of a transistor M4 controlled by a signal SEL, electrically connects or disconnects the amplifier 15 and the signal line 22. When transistor M4 of the selector 16 is on, it outputs the signal from the amplifier 15 to the signal line 22. Transistor M4 is a selector transistor.

[0039] The current source 25 is composed of a transistor M5 that inputs a signal VB to the gate. The current source 25 is connected to each pixel 10 of the pixel block 20 and the supply unit 30 via the signal line 22. The current source 25 generates a current based on the signal level of the signal VB and supplies the generated current to the signal line 22, the pixel 10, and the supply unit 30. In addition, the current source 25 can also be composed of two transistors connected in cascade. The signal VB is generated by a signal generating unit (not shown). The signal generating unit is commonly connected to the current source 25 provided for each signal line 22, and supplies the signal VB to each current source 25. The gates of the transistors M5 of each current source 25 are electrically connected to each other, and the signal VB is input from the signal generating unit.

[0040] The signal (dark signal) when the voltage of FD13 is reset, and the signal (photoelectric conversion signal) based on the charge transferred from the photoelectric conversion unit 11 to FD13 by the transfer unit 12 are sequentially output to the signal line 22. The dark signal is used to remove the noise contained in the photoelectric conversion signal. The dark signal is also called an analog signal representing a reference level relative to the photoelectric conversion signal, and is used to correct the photoelectric conversion signal. The photoelectric conversion signal is an analog signal generated based on the charge photoelectrically converted by the photoelectric conversion unit 11. The dark signal and the photoelectric conversion signal are input to the processing unit 50 of the readout unit 60 via the signal line 22 (refer to Figure 2In this embodiment, the processing unit 50 includes a calculation unit that performs subtraction between the photoelectric conversion signal and the dark signal, performs CDS based on the subtraction between the photoelectric conversion signal and the dark signal, and removes noise components from the photoelectric conversion signal.

[0041] The supply unit 30 is as follows Figure 4 The circuit 200 is provided with a signal output section 31 and a switch section 32, which has the function of supplying voltage to the signal line 22. The signal output section 31 is composed of a transistor M11 to which a signal CLIP is input to the gate, and generates and outputs a signal based on the voltage level of the signal CLIP. The drain of the transistor M11 is connected to the electrode 200 (see FIG. 1 ) via the power supply line 121. Figure 2 ), and is supplied with the power supply voltage VDD. The source of the transistor M11 is connected to the signal line 22 via the switch unit 32.

[0042] The switch section 32 is composed of a transistor M12 controlled by the signal CLIP_SW, and electrically connects and disconnects the signal output section 31 and the signal line 22. When the transistor M12 of the switch section 32 is in the on state, it can output the signal from the signal output section 31 to the signal line 22. In this embodiment, when the switch section 32 is in the on state, the voltage (potential) of the signal line 22 is limited by the signal output section 31 to a value within a range where the voltage based on the signal CLIP is set as the lower limit value. The supply section 30 supplies voltage to the signal line 22 so that the voltage of the signal line 22 does not fall below a predetermined voltage. The supply section 30 can also be a limiting section 30 that limits the voltage of the signal line 22. In other words, the supply section 30 supplies voltage to the signal line 22 so that the voltage of the signal line 22 reaches a value ranging from the power supply voltage VDD to the voltage based on the signal CLIP, thereby controlling (adjusting) the voltage of the signal line 22.

[0043] The pixel control unit 35 includes switches and buffers and is controlled by the readout control unit 70. The pixel control unit 35 supplies signals such as the aforementioned signal TX, signal RST, and signal SEL to the pixels 10 of the pixel block 20 to control the operation of each pixel 10. The pixel control unit 35 supplies signals to the gates of the transistors in the pixels 10 to set the transistors to an on state (connected state, conductive state, short-circuited state) or an off state (disconnected state, non-conductive state, open state, cutoff state).

[0044] The readout control unit 70 and the pixel control unit 35 control the period of charge accumulation in the pixel block 20 and the timing of reading pixel signals by controlling signals such as the TX and SEL signals input to the pixels 10. The pixel control unit 35 provided for each pixel block 20 can control the pixels 10 so that the charge accumulation time varies for each pixel block 20, or so that the charge accumulation time is the same for all pixel blocks 20. Furthermore, each pixel control unit 35 can control the pixels 10 so that the timing of reading pixel signals varies for each pixel block 20, or so that the timing of reading pixel signals is the same for all pixel blocks 20. By controlling the pixels 10 so that the charge accumulation time varies for each pixel block 20, the pixel control unit 35 can capture images that match the brightness of each subject, even when multiple subjects are present. Furthermore, by controlling the pixels 10 so that the timing of reading pixel signals varies for each pixel block 20, the pixel control unit 35 can capture images that match the speed of movement of each subject, even when multiple subjects are present.

[0045] The supply control unit 36 is composed of switches and buffers and is controlled by the readout control unit 70. As described above, the pixel control unit 35 can control the pixels 10 so that the charge accumulation time varies for each pixel block 20, and so that the timing of reading the pixel signal varies for each pixel block 20. In this case, the timing of outputting signals to the signal line 22 varies for each pixel block 20, so the supply control unit 36 must control the operation of each switch unit 32 for each pixel block 20. The supply control unit 36 supplies the aforementioned signal CLIP_SW to the switch unit 32 in each pixel block 20 to control the operation of each switch unit 32. The supply control unit 36 turns the switch unit 32 on and off, and starts and stops the supply of voltage from the signal output unit 31 to the signal line 22. In this embodiment, the supply control unit 36, provided for each pixel block 20, adjusts the timing of supplying voltage from the signal output unit 31 to the signal line 22 in the pixel block 20 based on the timing of reading the dark signal and the photoelectric conversion signal in the pixel block 20. For example, the supply control section 36 of each pixel block 20 controls the switch section 32 so that voltage can be supplied at different timings to the signal line 22 provided for a certain pixel block 20 and the signal line 22 provided for another pixel block 20. Alternatively, each supply control section 36 may control each switch section 32 so that voltage can be supplied at the same timing in all pixel blocks 20.

[0046] The readout control unit 70 is commonly provided for multiple pixel blocks 20. The readout control unit 70 is composed of multiple circuits, including a timing generator, and is disposed on the second substrate 112. The readout control unit 70 is controlled by the control unit 4 of the camera 1. The readout control unit 70 controls signals such as the TX signal, the RST signal, and the SEL signal input to the pixels 10 via the pixel control unit 35, thereby controlling the operation of the pixels 10. Furthermore, the readout control unit 70 controls the CLIP_SW signal input to the supply unit 30 via the supply control unit 36, thereby controlling the operation of the supply unit 30.

[0047] Furthermore, the pixel control unit 35 and the supply control unit 36 may be disposed on either the first substrate 111 or the second substrate 112, or may be disposed separately on the first substrate 111 and the second substrate 112. Alternatively, the pixel control unit 35 and the supply control unit 36 may be disposed on a substrate separate from the first substrate 111 and the second substrate 112. The readout control unit 70 may be disposed separately on the first substrate 111 and the second substrate 112, or may be disposed on the first substrate 111. Alternatively, the readout control unit 70 may be disposed on a substrate separate from the first substrate 111 and the second substrate 112.

[0048] The selection unit 16 of the pixel 10 and the switch unit 32 of the supply unit 30 are each turned on, thereby electrically connecting the source of the amplifier unit 15 and the source of the signal output unit 31 to the signal line 22. In this case, the path of the current flowing from the current source 25 connected to the signal line 22 changes based on the magnitude relationship between the voltage at the gate of the amplifier unit 15 (i.e., the voltage of the FD 13) and the voltage at the gate of the supply unit 30 (i.e., the voltage of the signal CLIP).

[0049] When the voltage of FD13 is higher than the voltage of signal CLIP, the current of current source 25 flows primarily to amplifier section 15 via signal line 22 and selector section 16. Amplifier section 15 outputs a signal based on the voltage of FD13 to signal line 22. As a result, the voltage of signal line 22 becomes a voltage corresponding to the voltage of FD13. When the voltage of FD13 is lower than the voltage of signal CLIP, the current of current source 25 flows primarily to signal output section 31 via signal line 22 and switch section 32. In this case, signal output section 31 outputs a signal based on the voltage of signal CLIP to signal line 22, thereby limiting the voltage of signal line 22 to a voltage based on the voltage of signal CLIP. The voltage of signal line 22 becomes a voltage corresponding to the voltage of signal CLIP.

[0050] In this manner, when the switch section 32 is in the on state, the supply section (limiting section) 30 limits the voltage of the signal line 22 based on the voltage of the FD13 and the voltage of the signal CLIP. The transistor M11 of the supply section 30 is a transistor that limits (clips) the voltage of the signal line 22 and is also referred to as a limiting transistor or a clamping transistor. When the voltage of the FD13 is relatively low, the voltage of the signal line 22 is limited to the voltage based on the signal CLIP. This prevents the current source 25 from malfunctioning due to a drop in the voltage of the signal line 22. As a result, the current source 25 can be prevented from being unable to supply current. Furthermore, the voltage of the signal line 22 can be prevented from becoming a voltage outside the intended range and being input to the readout section 60.

[0051] Furthermore, in the imaging element 3 of this embodiment, when reading a dark signal and when reading a photoelectric conversion signal, a signal CLIP having different signal levels is input to the supply unit 30. Thus, the supply unit 30 can supply different voltages to the signal line 22 when reading a dark signal and when reading a photoelectric conversion signal.

[0052] When reading a dark signal, a first voltage V1 is supplied to the gate of transistor M11 of signal output unit 31. In this case, the voltage of signal line 22 is limited so that a voltage based on first voltage V1 reaches a lower limit. Consequently, the voltage of the signal output to readout unit 60 as a dark signal is limited. When reading a photoelectric conversion signal, a second voltage V2, which is lower than first voltage V1, is supplied to the gate of transistor M11. In this case, the voltage of signal line 22 is limited so that a voltage based on second voltage V2 reaches a lower limit. Consequently, the voltage of the signal output to readout unit 60 as a photoelectric conversion signal is limited.

[0053] Due to a lack of pixels, charge accumulates in FD 13, sometimes causing a drop in the dark signal voltage. This can also occur when capturing a brightly lit subject. In this case, the difference between the dark signal and the photoelectric conversion signal decreases, reducing the quality of images generated using the CDS-processed signal. In this embodiment, as described above, the dark signal voltage is limited, ensuring the difference between the dark signal level and the photoelectric conversion signal level. This prevents image quality degradation caused by a decrease in the difference between the dark signal and the photoelectric conversion signal.

[0054] The second voltage V2 is set so that the voltage of the signal line 22 does not drop below the voltage required for the operation of the transistor M5 of the current source 25, and is kept as low as possible. This suppresses voltage variations on the signal line 22 that would otherwise interfere with the transfer of charge generated by the photoelectric converter 11 to the FD 13. Furthermore, fluctuations in the current of the current source 25 can be suppressed, and the incorporation of noise into the photoelectric conversion signal output to the signal line 22 can be suppressed.

[0055] Figure 5 as well as Figure 6 Each of them is a timing chart showing an example of the operation of the image pickup element 3 according to the first embodiment. Figure 5 as well as Figure 6 In the timing chart shown, the vertical axis represents the voltage level of the signal, and the horizontal axis represents the time. FD represents the signal (voltage signal) of FD13, and VOUT represents the signal output to the signal line 22. Figure 5 as well as Figure 6 In the example shown, the signal CLIP_SW is set to a high level, and the switch section 32 of the supply section 30 is turned on. Figure 5 as well as Figure 6 In the embodiment, a transistor to which a high-level (eg, power supply voltage VDD) control signal (signal SEL, signal RST, signal TX) is input is turned on, and a transistor to which a low-level (eg, ground voltage) control signal is input is turned off.

[0056] exist Figure 5 At time t1 shown, signal RST goes high, turning on transistor M2 of reset unit 14 of pixel 10 and electrically connecting FD13 to power line 121. This resets the charge of FD13, and the voltage of FD13 reaches the reset voltage. Also, at time t1, signal SEL goes high, turning on transistor M4 of selector 16. This allows amplifier 15 and selector 16 to output a signal based on the reset voltage of pixel 10, i.e., a signal resulting from resetting the charge of FD13 in pixel 10, to signal line 22. At time t2, signal RST goes low, turning off transistor M2 of reset unit 14.

[0057] The signal output unit 31 of the supply unit 30 is input with the signal CLIP of the first voltage V1, which is a signal that can convert a voltage based on the first voltage V1 (in Figure 5 The state where the limit voltage Vc1 shown by the dotted line is supplied to the signal line 22. Figure 5 In the example shown, during the period from time t2 to time t3, the voltage of FD13 ( Figure 5The voltage of the FD shown in FIG1 is higher than the first voltage V1 of the signal CLIP. Therefore, the voltage of the signal VOUT output to the signal line 22 is based on the voltage of the FD 13, that is, based on the reset voltage after the charge accumulated in the FD 13 is reset.

[0058] At time t3, the processing unit 50 of the readout unit 60 samples the signal VOUT which is a voltage based on the reset voltage as a dark signal. In other words, the voltage of the dark signal is determined at time t3. The AD conversion unit 40 of the processing unit 50 converts the dark signal into a digital signal. At time t4, the signal CLIP of the second voltage V2 which is lower than the first voltage V1 is input to the signal output unit 31. The voltage of the signal CLIP changes from the first voltage V1 to the second voltage V2, and the signal output unit 31 becomes a voltage based on the second voltage V2 (at Figure 5 The state in which the limiter voltage Vc2 (shown by the dotted line in FIG) is supplied to the signal line 22.

[0059] At time t5, signal TX goes high, turning on transistor M1 of transfer section 12 and transferring the charge photoelectrically converted by photoelectric conversion section 11 to FD 13. Consequently, the voltage of FD 13 becomes a voltage based on the charge transferred from photoelectric conversion section 11. Furthermore, signal SEL goes high, enabling amplifier section 15 and selector section 16 to output a signal based on the charge generated by photoelectric conversion section 11 to signal line 22. At time t6, signal TX goes low, turning off transistor M1 of transfer section 12.

[0060] exist Figure 5 In the example shown, the voltage of FD 13 is higher than second voltage V2, which is the voltage of signal CLIP, during the period from time t6 to time t7. Therefore, the voltage of signal VOUT output to signal line 22 is based on the voltage of FD 13, that is, the voltage based on the charge photoelectrically converted by photoelectric conversion section 11.

[0061] At time t7, the processing unit 50 samples signal VOUT, which is a voltage based on the charge photoelectrically converted by the photoelectric conversion unit 11, as a photoelectric conversion signal. Alternatively, the voltage of the photoelectric conversion signal is determined at time t7. The AD converter 40 of the processing unit 50 converts the photoelectric conversion signal into a digital signal. The processing unit 50 performs CDS on the digitally converted dark signal and the photoelectric conversion signal. CDS performs differential processing on the dark signal and the photoelectric conversion signal. After performing signal processing such as CDS, the processing unit 50 outputs the processed signal to the control unit 4.

[0062] Next, refer to Figure 6 Another example of the operation of the imaging element 3 will be described. Figure 6 At time t11 shown, signal RST goes high, turning on transistor M2 of reset unit 14 of pixel 10. This resets the charge of FD 13, and the voltage of FD 13 reaches the reset voltage. Also, at time t11, signal SEL goes high, turning on transistor M4 of selector 16. This enables amplifier 15 and selector 16 to output a signal based on the reset voltage of pixel 10 to signal line 22. At time t12, signal RST goes low, turning off transistor M2 of reset unit 14.

[0063] The signal output unit 31 of the supply unit 30 is in a state where the signal CLIP of the first voltage V1 is input and a voltage (clipping voltage Vc1) based on the first voltage V1 can be supplied to the signal line 22. Figure 6 In the example shown, the voltage of FD13 is higher than the first voltage V1 of signal CLIP during the period from time t12 to time t13. Therefore, the voltage of signal VOUT output to signal line 22 is based on the reset voltage of FD13.

[0064] At time t13, the processing unit 50 of the readout unit 60 samples the signal VOUT, which is a voltage based on the reset voltage, as a dark signal. The processing unit 50 converts the dark signal into a digital signal. At time t14, the signal output unit 31 receives the signal CLIP, which is a second voltage V2 lower than the first voltage V1, and is in a state where it can supply a voltage based on the second voltage V2 (clip voltage Vc2) to the signal line 22.

[0065] At time t15, signal TX goes high, turning on transistor M1 of transfer section 12 and transferring the charge photoelectrically converted by photoelectric converter 11 to FD 13. Consequently, the voltage of FD 13 becomes a voltage based on the charge transferred from photoelectric converter 11. Furthermore, signal SEL goes high, enabling amplifier 15 and selector 16 to output a signal based on the charge generated by photoelectric converter 11 to signal line 22. At time t16, signal TX goes low, turning off transistor M1 of transfer section 12.

[0066] exist Figure 6 In the example shown, the voltage of FD 13 is lower than second voltage V2, which is the voltage of signal CLIP, during the period from time t16 to time t17. Therefore, the voltage of signal VOUT output to signal line 22 is limited to a voltage based on second voltage V2, i.e., clip voltage Vc2.

[0067] At time t17, the processing unit 50 samples the signal VOUT, which has become the clipping voltage Vc2, as a photoelectric conversion signal. The processing unit 50 converts the photoelectric conversion signal into a digital signal. After performing signal processing such as CDS using the dark signal and the photoelectric conversion signal converted into digital signals, the processing unit 50 outputs the processed signal to the control unit 4. Thus, in this embodiment, the supply unit 30 receives the signal CLIP at different signal levels when reading the dark signal and when reading the photoelectric conversion signal. The supply unit 30 supplies a voltage to the signal line 22 based on the voltage of the signal CLIP and the voltage of the FD 13, thereby limiting the voltage of the signal line 22.

[0068] like Figure 4 As shown, the gates of the transistors M5 of the current sources 25 provided for each signal line 22 are commonly connected to the signal line to which the signal VB is input. In addition, a parasitic capacitance (load capacitance) may be added between the signal line 22 from which the pixel signal is output and the gate of the transistor M5 connected to the signal line 22. Due to the influence of this parasitic capacitance, the voltage of the signal VB fluctuates according to the fluctuation of the voltage of the signal line 22, and the magnitude of the current flowing through each current source 25 fluctuates. Assuming that the imaging element 3 does not have a supply unit 30, the voltage of the signal line 22 drops significantly, and the voltage of the signal VB also drops significantly. Considering that the current supplied from the current source 25 decreases, or no current is supplied from the current source 25. In the case where the voltage of the signal line 22 provided for a certain pixel block 20 fluctuates, the voltage of the signal VB commonly supplied to each current source 25 fluctuates, causing the voltage of the signal lines 22 provided for other pixel blocks 20 to also fluctuate.

[0069] On the other hand, the imaging element 3 of this embodiment is provided with a supply unit 30 for each pixel block 20. When the switch unit 32 is in the on state, the supply unit 30 can supply a voltage based on the signal CLIP to the signal line 22, thereby limiting the voltage of the signal line 22. Therefore, the imaging element 3 can suppress fluctuations in the voltage of the signal VB by limiting the voltage of the signal line 22. This can prevent noise caused by fluctuations in the voltage of the signal VB from being mixed into the signal (photoelectric conversion signal, dark signal) output to the signal line 22.

[0070] In this embodiment, when the voltage of FD13 is relatively low, the voltage of the signal line 22 is limited (limiting operation), and when the voltage of FD13 is relatively high, the limiting operation is not performed. When the limiting operation is performed and when the limiting operation is not performed, the flow path of the current of the current source 25 changes as described above. When the limiting operation is performed, the current of the current source 25 flows between the power supply line 121 and the power supply line 122. Figure 4The current of the current source 25 flows between the power supply line 121 and the ground line (ground wiring) 131 via the signal output unit 31 of the supply unit 30. When the limiting operation is not performed, the current of the current source 25 flows between the power supply line 121 and the ground line (ground wiring) 131 via the amplifier unit 15 of the pixel 10. Figure 4 As schematically shown, wiring resistance is added to the power supply line 121 and the ground line 131 , and therefore a voltage drop (IR drop) due to the wiring resistance occurs.

[0071] Due to the influence of the aforementioned changes in the current path, the voltage drop in power supply line 121 and ground line 131 varies between when a clipping operation is in effect and when a clipping operation is not in effect, resulting in differences in the value of power supply voltage VDD supplied to each pixel 10 via power supply line 121. When signals are read simultaneously from multiple pixel blocks 20, pixel signals in pixel blocks 20 where a clipping operation is performed in other pixel blocks 20 during signal readout differ from those in pixel blocks 20 where a clipping operation is not performed during signal readout due to fluctuations in power supply voltage VDD. Furthermore, if power supply voltage VDD fluctuates during photoelectric conversion signal readout, the reset voltage level of FD 13, i.e., the signal level that serves as a reference for voltage fluctuations caused by charge transferred from photoelectric converter 11, also fluctuates. If there is a difference in the reset voltage signal level between the dark signal readout period and the photoelectric conversion signal readout period, CDS processing may be performed using a dark signal at a different signal level than the reference signal level for the photoelectric conversion signal. This may result in, for example, blackening or streaking in the image generated using the CDS-processed signal. In particular, when the power supply voltage is supplied to the pixel 10 and the supply unit 30 from different electrodes via different power supply lines, the difference in the power supply voltage supplied to the pixel 10 between when the clipping operation is performed and when the clipping operation is not performed may be greater.

[0072] In this embodiment, the pixels 10 and the supply unit 30 are arranged on the same first substrate 111. Furthermore, the power supply voltage VDD is supplied to the pixels 10 and the supply unit 30 from a common electrode 200 via a common power line 121. This reduces the difference in power supply voltage VDD applied to the pixels 10 when the clipping operation is in progress and when it is not. Consequently, variations in the signal generation between the pixels due to fluctuations in the power supply voltage can be suppressed. Consequently, the generation of blackouts or streaks in images generated using the pixel signals can be prevented.

[0073] Figure 7This is a diagram showing an example of a layout of a portion of the imaging element of the first embodiment. In each of the plurality of pixel blocks 20 of the imaging element 3, a plurality of pixels 10 including a photoelectric conversion unit 11 are arranged along a row direction (X direction) which is a first direction and a column direction (Y direction) which is a second direction intersecting the first direction. Figure 7 In the example shown, the pixel block 20 is provided with four pixels 10, four switch sections 32, and one signal output section 31. In the first substrate 111 of the imaging element 3, a plurality of pixel blocks 20 including four pixels 10 are arranged in the row direction (horizontal direction) and the column direction (vertical direction). The four switch sections 32 and one signal output section 31 constitute the supply section 30. In addition, Figure 7 , a portion of wiring provided in the pixel block 20 is schematically shown.

[0074] exist Figure 7 In the example shown, the signal output unit 31 is connected to each of the four switch units 32, supplying a voltage to each of the four switch units 32. A single signal output unit 31, provided for each pixel block 20, performs the limiting operation. Therefore, compared to a case where multiple signal output units 31 are provided within a pixel block 20, the light-receiving area of the photoelectric converter 11 can be increased. This prevents a decrease in the pixel aperture ratio. Furthermore, the limiting operation can be performed without increasing the chip area, suppressing degradation in the image quality of images generated using pixel signals.

[0075] According to the above-described embodiment, the following effects can be obtained.

[0076] (1) The imaging element 3 includes: a first substrate 111 having a photoelectric converter 11 that generates charge through photoelectric conversion; a signal line 22 to which a signal based on the charge generated by the photoelectric converter 11 is output; and a supply unit 30 that supplies a voltage to the signal line 22; and a second substrate 112 stacked on the first substrate 111 and having a processing unit 50 that processes the signal output to the signal line 22. In this embodiment, the pixel 10 having the photoelectric converter 11 and the supply unit 30 are arranged on the same first substrate 111. Therefore, fluctuations in the power supply voltage associated with the operation of the supply unit 30 can be reduced, preventing degradation in the quality of the pixel signal. Consequently, degradation in the quality of an image generated using the pixel signal can be suppressed.

[0077] (2) In this embodiment, the readout unit 60 including the plurality of processing units 50 is disposed on the second substrate 112. This allows for the arrangement of a plurality of circuits for processing pixel signals without increasing the chip area. Furthermore, a decrease in the pixel aperture ratio can be suppressed.

[0078] The following modifications also fall within the scope of the present invention, and one or more modifications may be combined with the above-described embodiment.

[0079] (Variation 1)

[0080] Figure 8 FIG. 1 is a diagram showing an example of a layout of a portion of an imaging element according to Modification 1. Figure 8 As shown, the pixel block 20 can also be configured without the switch unit 32. The signal output unit 31 is electrically connected to the signal line 22 without the switch unit 32, allowing a voltage to be supplied to the signal line 22 both when reading a dark signal and when reading a photoelectric conversion signal. In this variation, the switch unit 32 can be reduced, reducing the chip area. Furthermore, the light-receiving area of the photoelectric conversion unit 11 can be increased.

[0081] (Variation 2)

[0082] Figure 9 1 is a diagram showing an example of a layout of a portion of an imaging element according to Modification 2. Figure 9 As shown, a signal output unit 31 may be provided for each pixel 10. Figure 9 In the illustrated example, four signal output sections 31 and four switch sections 32 are provided for each pixel block 20 .

[0083] Alternatively, a different wiring may be used to supply the signal CLIP to each signal output section 31 or to each of a plurality of signal output sections 31. In this case, the number of signal output sections 31 connected to one wiring can be reduced, and the signal level of the signal CLIP can be switched at high speed.

[0084] (Variation 3)

[0085] In the above embodiment, an example in which a signal line 22 and a supply unit 30 are provided for each pixel block 20 has been described. However, a signal line 22 may be provided for each pixel 10, and a supply unit 30 may be provided for each signal line 22. In this case, a pixel control unit 35 may be provided for each pixel 10, and a supply control unit 36 may be provided for each supply unit 30. Each supply control unit 36 may control the supply unit 30 provided for each signal line 22 so that a voltage can be supplied at a different timing for each signal line 22.

[0086] (Variation 4)

[0087] The pixel 10 and the supply unit 30 are composed of analog circuits using MOS transistors. The analog circuit is provided on the first substrate 111, and the digital circuit such as the AD conversion unit 40 is provided on the second substrate 112. The process most suitable for the analog circuit can be applied to the first substrate 111, and the process most suitable for the digital circuit can be applied to the second substrate 112. Moreover, if NMOS transistors (or PMOS transistors) are used to form the pixel 10 and the supply unit 30, well isolation is no longer required. In addition, by using the same NMOS transistors to form the pixel 10 and the supply unit 30, the manufacturing process of the imaging element can be shortened.

[0088] The pixel 10 and the supply unit 30 can be configured using either NMOS or PMOS transistors. Alternatively, both NMOS and PMOS transistors can be used to configure the pixel 10 and the supply unit 30. When the amplifier unit 15 and the signal output unit 31 are configured using NMOS transistors, as described above, when reading the photoelectric conversion signal, a signal CLIP having a lower voltage than when reading the dark signal can be supplied to the signal output unit 31. When the amplifier unit 15 and the signal output unit 31 are configured using PMOS transistors, when reading the photoelectric conversion signal, a signal CLIP having a higher voltage than when reading the dark signal can be supplied to the signal output unit 31. The supply unit 30 supplies voltage to the signal line 22 so that the voltage of the signal line 22 ranges from the power supply voltage (or ground voltage) to the voltage based on the signal CLIP. The voltage of the signal line 22 is limited by the supply unit 30 to a value within a range where the voltage based on the signal CLIP serves as the upper or lower limit.

[0089] (Variant 5)

[0090] In the above embodiment, an example has been described in which the image sensor 3 is configured by laminating the first substrate 111 and the second substrate 112. However, the first substrate 111 and the second substrate 112 do not need to be laminated.

[0091] (Variant 6)

[0092] In the above embodiment, an example in which the imaging element 3 is a back-illuminated type has been described. However, the imaging element 3 may be a front-illuminated type in which the wiring layer 101 is provided on the incident surface side where light enters.

[0093] (Variant 7)

[0094] In the above-described embodiment and modified examples, examples using photodiodes as photoelectric conversion units have been described. However, a photoelectric conversion film (organic photoelectric film) may also be used as the photoelectric conversion unit.

[0095] (Variation 8)

[0096] The imaging elements and imaging devices described in the above embodiments and variations can be applied to cameras built into cameras, smartphones, tablet computers, PCs, vehicle-mounted cameras, cameras mounted on unmanned aerial vehicles (drones, radio-controlled machines, etc.), etc.

[0097] Although various embodiments and modifications have been described above, the present invention is not limited to these contents, and other aspects that can be considered within the scope of the technical concept of the present invention are also included in the scope of the present invention.

[0098] The disclosures of the following priority basic applications are incorporated herein by reference.

[0099] Japanese Special Application No. 2019-180780 (filed on September 30, 2019)

[0100] Description of Reference Numerals

[0101] 1…imaging device, 3…imaging element, 4…control unit, 10…pixel, 11…photoelectric conversion unit, 20…pixel block, 30…supply unit, 35…pixel control unit, 36…supply control unit, 40…AD conversion unit, 50…processing unit, 60…readout unit, 70…readout control unit, 111…first substrate, 112…second substrate.

Claims

1. An imaging element, characterized in that: comprising a first substrate and a second substrate, The first substrate has: a first pixel including a first photoelectric conversion portion that converts light into electric charges, and outputting a first signal based on the electric charges converted by the first photoelectric conversion portion; The second pixel includes a second photoelectric conversion portion that converts light into electric charges, and outputs a second signal based on the electric charges converted by the second photoelectric conversion portion. a first supply unit that controls a voltage of a first signal line to which the first signal read out from the first pixel is output; and a second supply unit configured to control a voltage of a second signal line to which the second signal read from the second pixel is output; The second substrate is a substrate stacked together with the first substrate. The second substrate has: a first processing unit that performs signal processing on the first signal output to the first signal line; and A second processing unit performs signal processing on the second signal output to the second signal line.

2. The imaging element according to claim 1, wherein comprising a wiring layer having the first signal line and the second signal line, The wiring layer is arranged between the first substrate and the second substrate in a stacking direction of the first substrate and the second substrate.

3. The imaging element according to claim 2, wherein The first supply unit is controlled so that the voltage of the first signal line does not fall below a predetermined voltage. The second supply unit is controlled so that the voltage of the second signal line does not fall below a predetermined voltage.

4. The imaging element according to claim 1, wherein The first pixel outputs the first signal and a first dark signal used for correction of the first signal to the first signal line. The second pixel outputs the second signal and a second dark signal used for correction of the second signal to the second signal line. The first supply unit supplies a different voltage when the first signal is output from the first pixel to the first signal line and when the first dark signal is output from the first pixel to the first signal line. The second supply section supplies a different voltage when the second pixel outputs the second signal to the second signal line and when the second pixel outputs the second dark signal to the second signal line.

5. The imaging element according to claim 4, wherein The first supply unit supplies a first voltage when the first dark signal is output from the first pixel to the first signal line, and supplies a second voltage lower than the first voltage when the first signal is output from the first pixel to the first signal line. The second supply unit supplies a third voltage when the second dark signal is output from the second pixel to the second signal line, and supplies a fourth voltage lower than the third voltage when the second signal is output from the second pixel to the second signal line.

6. The imaging element according to claim 5, wherein The first dark signal is used to correct the noise contained in the first signal. The second dark signal is used for correction to remove noise included in the second signal.

7. The imaging element according to claim 4, wherein The first processing unit corrects the first signal using the first dark signal. The second processing unit corrects the second signal using the second dark signal.

8. The imaging element according to claim 4, wherein The first processing unit converts the first signal and the first dark signal into digital signals. The second processing unit converts the second signal and the second dark signal into digital signals.

9. The imaging element according to claim 8, wherein The first processing unit corrects the first signal converted into a digital signal using the first dark signal converted into a digital signal. The second processing unit corrects the second signal converted into a digital signal using the second dark signal converted into a digital signal.

10. The imaging element according to any one of claims 1 to 9, wherein have: a first pixel control unit that controls an accumulation time of the charge converted by the first photoelectric conversion unit; and The second pixel control unit controls the accumulation time of the charge converted by the second photoelectric conversion unit.

11. The imaging element according to claim 10, wherein The second pixel control section performs control so that an accumulation time of the charge converted by the second photoelectric conversion section becomes an accumulation time different from an accumulation time of the charge converted by the first photoelectric conversion section.

12. The imaging element according to claim 10, wherein The first pixel control section and the second pixel control section are arranged on the second substrate.

13. A camera device, characterized in that: A device comprising the imaging element according to claim 12.

14. The imaging element according to any one of claims 1 to 9, wherein have: a first supply control section that controls a timing of supplying a voltage from the first supply section to the first signal line; and A second supply control section controls a timing of supplying a voltage from the second supply section to the second signal line.

15. The imaging element according to claim 14, wherein The first supply control section supplies a voltage from the first supply section to the first signal line when the first signal is output from the first pixel to the first signal line. The second supply control section supplies a voltage from the second supply section to the second signal line when the second pixel outputs the second signal to the second signal line.

16. The imaging element according to claim 14, wherein The second supply control section performs control so that a timing at which the second supply section supplies a voltage to the second signal line is different from a timing at which the first supply section supplies a voltage to the first signal line.

17. The imaging element according to claim 16, wherein The first supply control unit and the second supply control unit are arranged on the second substrate.

18. A camera device, characterized in that: A device comprising the imaging element according to claim 17.

19. The imaging element according to any one of claims 1 to 9, wherein The second photoelectric conversion section is arranged in parallel with the first photoelectric conversion section in a column direction.

20. A camera device, characterized in that: A device comprising the imaging element according to claim 19.

21. The imaging element according to any one of claims 1 to 9, wherein comprising an electrode provided on the first substrate and supplied with a power supply voltage, The first supply unit and the second supply unit are electrically connected to the electrode.

22. A camera device, characterized in that: A device comprising the imaging element according to claim 21.

23. A camera device, characterized in that: An imaging device according to any one of claims 1 to 9 is provided.

24. The imaging device according to claim 23, wherein: A generating unit is provided, the generating unit being electrically connected to the imaging element and generating image data.

25. The imaging device according to claim 23, wherein An optical system is provided for emitting light toward the imaging element.

Images