Semiconductor device

Abstract

A semiconductor device includes a peripheral circuit structure including a circuit substrate and a circuit on the circuit substrate, and a through electrode region overlapping the peripheral circuit structure in a vertical direction, wherein the through electrode region includes an insulating structure, an interlayer dielectric covering an upper surface of the insulating structure, and a through electrode, the insulating structure including first insulating films and second insulating films, the first insulating films and the second insulating films including materials different from each other and alternately stacked one after the other in a vertical direction, and an insulating structure having an upper surface having a height that varies in a vertical direction along each of a first horizontal direction and a second horizontal direction perpendicular to the first horizontal direction, and a plurality of through electrodes passing through the insulating structure and the interlayer dielectric in the vertical direction in a partial region of the through electrode region, and each through electrode is configured to be connected to one circuit selected from the circuits of the peripheral circuit structure.

Description

Technical Field

[0001] The inventive concept relates to a semiconductor device and an electronic system including the same, and more particularly, to a semiconductor device including a nonvolatile vertical memory device and an electronic system including the same. Background Art

[0002] Semiconductor devices capable of storing large amounts of data are required in electronic systems requiring data storage. Therefore, in order to increase the data storage capacity of semiconductor devices, semiconductor devices including vertical memory devices including memory cells arranged three-dimensionally have been proposed. Summary of the Invention

[0003] Some example embodiments of the inventive concept provide a semiconductor device having a structure capable of ensuring reliability and improving electrical characteristics of the semiconductor device by omitting structures that may generate structural defects (such as cracks) during a process of manufacturing the integrated circuit device, even when the integration density of the semiconductor device including three-dimensionally arranged memory cells increases.

[0004] Some example embodiments of the inventive concept provide an electronic system including a semiconductor device having a structure capable of ensuring reliability and improving electrical characteristics of the semiconductor device by omitting structures that may generate structural defects (such as cracks) during a process of manufacturing the integrated circuit device, even when the integration density of the semiconductor device including three-dimensionally arranged memory cells increases.

[0005] According to an example embodiment of the inventive concept, a semiconductor device includes a peripheral circuit structure and a through-electrode region, the peripheral circuit structure including a circuit substrate and a plurality of circuits on the circuit substrate, the through-electrode region overlapping with the peripheral circuit structure in a vertical direction, wherein the through-electrode region includes an insulating structure, an interlayer dielectric and a plurality of through-electrodes, the insulating structure including a plurality of first insulating films and a plurality of second insulating films and having an upper surface with a height varying in the vertical direction along each of a first horizontal direction and a second horizontal direction perpendicular to the first horizontal direction, the plurality of first insulating films and the plurality of second insulating films including materials different from each other and alternately stacked one after another in the vertical direction, the interlayer dielectric covering the upper surface of the insulating structure, the plurality of through-electrodes penetrating the insulating structure and the interlayer dielectric in the vertical direction in a local region of the through-electrode region, each of the plurality of through-electrodes being configured to be connected to one circuit selected from the plurality of circuits of the peripheral circuit structure.

[0006] According to an example embodiment of the inventive concept, a semiconductor device includes a peripheral circuit structure, a plurality of memory cell blocks, and a through-electrode region vertically overlapping the peripheral circuit structure, the peripheral circuit structure including a circuit substrate and a plurality of circuits on the circuit substrate, each of the plurality of memory cell blocks vertically overlapping the peripheral circuit structure, each of the plurality of memory cell blocks longitudinally extending in a first horizontal direction, the through-electrode region being located between two adjacent memory cell blocks selected from the plurality of memory cell blocks, wherein the through-electrode region includes an insulating structure, an interlayer dielectric covering an upper surface of the insulating structure, and a plurality of through-electrodes, the insulating structure including a plurality of first insulating films and a plurality of second insulating films and having an upper surface having a varying height in the vertical direction along each of a first horizontal direction and a second horizontal direction perpendicular to the first horizontal direction, the plurality of first insulating films and the plurality of second insulating films including materials different from each other and alternately stacked one after another in the vertical direction, the plurality of through-electrodes vertically penetrating the insulating structure and the interlayer dielectric in a local region of the through-electrode region, and each of the plurality of through-electrodes being configured to be connected to one circuit selected from the plurality of circuits of the peripheral circuit structure.

[0007] According to an example embodiment of the inventive concept, a semiconductor device includes: a peripheral circuit structure including a circuit substrate and a plurality of circuits on the circuit substrate; a plurality of pads overlapping the peripheral circuit structure in a vertical direction, each of the plurality of pads including a plurality of memory cell blocks extending longitudinally in a first horizontal direction; and at least one through-electrode region overlapping the peripheral circuit structure in the vertical direction, the at least one through-electrode region being located at at least one of a first position and a second position, the first position being between two adjacent memory cell blocks selected from the plurality of memory cell blocks, and the second position being between two adjacent pads in a second horizontal direction perpendicular to the first horizontal direction among the plurality of pads, wherein the at least one through-electrode region includes an insulating structure, an interlayer dielectric covering an upper surface of the insulating structure, and a plurality of through-electrodes, the insulating structure including a plurality of first insulating films, a plurality of second insulating films, and a plurality of through-electrodes. A film and a plurality of third insulating films, the plurality of first insulating films and the plurality of second insulating films include materials different from each other, the plurality of first insulating films and the plurality of second insulating films are alternately stacked one after another in a vertical direction, the plurality of third insulating films are in contact with the second insulating film at the upper portion of the plurality of second insulating films, the insulating structure has an upper surface, the upper surface has a height varying in the vertical direction along each of a first horizontal direction and a second horizontal direction, the plurality of through-electrodes penetrate the insulating structure and the interlayer dielectric in the vertical direction in a local region of the at least one through-electrode region, each of the plurality of through-electrodes is configured to be connected to one circuit selected from the plurality of circuits of the peripheral circuit structure, wherein each of the plurality of first insulating films includes a silicon oxide film, and each of the plurality of second insulating films and the plurality of third insulating films includes a silicon nitride film or a hydrogenated silicon nitride film.

[0008] According to an example embodiment of the inventive concept, an electronic system includes a main substrate, a semiconductor device on the main substrate, and a controller on the main substrate and electrically connected to the semiconductor device, wherein the semiconductor device includes a peripheral circuit structure and a through-electrode region, the peripheral circuit structure includes a circuit substrate and a plurality of circuits on the circuit substrate, the through-electrode region overlaps with the peripheral circuit structure in a vertical direction, wherein the through-electrode region includes an insulating structure, an interlayer dielectric covering an upper surface of the insulating structure, and a plurality of through-electrodes, the insulating structure includes a plurality of first insulating films and a plurality of second insulating films and has an upper surface with a varying height in the vertical direction along each of a first horizontal direction and a second horizontal direction perpendicular to the first horizontal direction, the plurality of first insulating films and the plurality of second insulating films contain materials different from each other and are alternately stacked one after another in the vertical direction, the plurality of through-electrodes penetrate the insulating structure and the interlayer dielectric in the vertical direction in a local region of the through-electrode region, and each of the plurality of through-electrodes is configured to be connected to one circuit selected from the plurality of circuits of the peripheral circuit structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a block diagram of a semiconductor device according to an example embodiment;

[0011] Figure 2A and Figure 2B are plan views each illustrating a schematic plan structure of a memory cell array that may be used for a semiconductor device according to some example embodiments;

[0012] Figure 3 is included Figure 2A A schematic perspective view of a semiconductor device in a region EX1;

[0013] Figure 4 is a schematic plan view of a portion of a cell array structure of a semiconductor device according to example embodiments;

[0014] Figure 5 is an equivalent circuit diagram of a memory cell array of a semiconductor device according to example embodiments;

[0015] Figure 6A It shows Figure 4 A plan view of an example of the configuration of the area NB, Figure 6B is a plan view illustrating some components of a through-electrode region of a semiconductor device according to example embodiments, Figure 6C It is shown in detail Figure 4 A plan view of an example of the configuration of the area EX2;

[0016] Figures 7 to 11 is a cross-sectional view illustrating in detail a semiconductor device according to an example embodiment, particularly, Figure 7 It is along Figure 6A A cross-sectional view taken along line X1-X1', Figure 8 It is along Figure 6A A cross-sectional view taken along line Y1-Y1', Figure 9 It is along Figure 6B A cross-sectional view taken along line Y2-Y2', Figure 10 It is along Figure 6B A cross-sectional view taken along line Y3-Y3', Figure 11 It is along Figure 6B A cross-sectional view taken along line Y4-Y4';

[0017] Figure 12A 、 Figure 12B and Figure 12C is a cross-sectional view illustrating a semiconductor device according to example embodiments;

[0018] Figure 13A and Figure 13B is a cross-sectional view illustrating a semiconductor device according to example embodiments;

[0019] Figure 14A and Figure 14B is a cross-sectional view illustrating a semiconductor device according to example embodiments;

[0020] Figure 15A and Figure 15B is a cross-sectional view illustrating a semiconductor device according to example embodiments;

[0021] Figure 16 is a cross-sectional view illustrating a semiconductor device according to example embodiments;

[0022] Figure 17 is a plan view illustrating a semiconductor device according to example embodiments;

[0023] Figure 18 is a diagram schematically illustrating an electronic system including a semiconductor device according to example embodiments;

[0024] Figure 19A is a perspective view schematically illustrating an electronic system including a semiconductor device according to an example embodiment;

[0025] Figure 19B It is along Figure 19A The cross-sectional view taken along line II' conceptually shows Figure 19A The semiconductor package shown; and

[0026] 20A to 32D is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to an example embodiment. Specifically, Figure 20A 、 Figure 21A 、 Figure 22A 、 Figure 23 、 Figure 24A 、 Figure 25A 、 Figure 26 、 Figure 27A 、 Figure 28A 、 Figure 29 、 Figure 31A and Figure 32A It shows the process sequence and the Figure 6A A cross-sectional view of some components of the region corresponding to the cross section taken along the line X1-X1', Figure 20B 、 Figure 21B 、 Figure 22B 、 Figure 25B and Figure 28B It shows the process sequence and the Figure 6A A cross-sectional view of some components of the region corresponding to the cross-section taken along the line Y1-Y1', Figure 24B、 Figure 27B 、 Figure 28C 、 Figure 30A 、 Figure 31B and Figure 32B It shows the process sequence and the Figure 6B A cross-sectional view of some components of the region corresponding to the cross section taken along the line Y2-Y2', Figure 24C 、 Figure 27C 、 Figure 28D 、 Figure 30B 、 Figure 31C and Figure 32C It shows the process sequence and the Figure 6B A cross-sectional view of some components of the region corresponding to the cross section taken along the line Y3-Y3', Figure 24D 、 Figure 27D 、 Figure 28E 、 Figure 30C 、 Figure 31D and Figure 32D It shows the process sequence and the Figure 6B A cross-sectional view of some components of an area corresponding to a cross section taken along line Y4 - Y4 ′. DETAILED DESCRIPTION

[0027] Hereinafter, some exemplary embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. Throughout the specification, the same components are denoted by the same reference numerals, and repeated descriptions thereof are omitted.

[0028] Although the terms "same," "equal," or "equivalent" are used in the description of example embodiments, it should be understood that some imprecision may exist. Thus, when one element is referred to as being the same as another element, it should be understood that the element or value is the same as that of the other element within an expected manufacturing or operating tolerance range (e.g., ±10%).

[0029] When the terms "about," "substantially," or "approximately" are used in conjunction with a numerical value in this specification, it is intended that the associated numerical value include a manufacturing or operating tolerance (e.g., ±10%) around the numerical value. Furthermore, when the terms "about," "substantially," or "approximately" are used in conjunction with a geometric shape, it is intended that the precision of the geometric shape is not required, but rather that the latitude of the shape is within the scope of the present disclosure. Furthermore, regardless of whether a numerical value or shape is modified as "about" or "substantially," it will be understood that these values and shapes should be interpreted as including a manufacturing or operating tolerance (e.g., ±10%) around the numerical value or shape.

[0030] As used herein, expressions such as "at least one of," when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list. Thus, for example, "at least one of A, B, or C" and "at least one of A, B, and C" both mean A, B, C, or any combination thereof. Similarly, A and / or B means A, B, or A and B.

[0031] Figure 1 is a block diagram of a semiconductor device 100 according to an example embodiment.

[0032] Reference Figure 1 , the semiconductor device 100 may include a memory cell array 20 and a peripheral circuit 30. The memory cell array 20 may include a plurality of pads MT. Each of the plurality of pads MT may include a plurality of memory cell blocks BLK1, BLK2, ..., and BLKp. Each of the plurality of memory cell blocks BLK1, BLK2, ..., and BLKp may include a plurality of memory cells. The memory cell blocks BLK1, BLK2, ..., or BLKp may be connected to the peripheral circuit 30 via bit lines BL, word lines WL, string selection lines SSL, and ground selection lines GSL. Here, the memory cell array 20 may be referred to as a memory cell array MCA.

[0033] The peripheral circuit 30 may include a row decoder 32, a page buffer 34, a data input / output (I / O) circuit 36, a control logic 38, and a common source line (CSL) driver 39. The peripheral circuit 30 may further include various circuits such as a voltage generation circuit for generating various voltages required for the operation of the semiconductor device 100, an error correction circuit for correcting errors in data read from the memory cell array 20, an input / output interface, and the like.

[0034] The memory cell array 20 may be connected to a row decoder 32 via word lines WL, string select lines SSL, and ground select lines GSL, and may be connected to a page buffer 34 via bit lines BL. In the memory cell array 20, each of the plurality of memory cells included in the plurality of memory cell blocks BLK1, BLK2, ..., and BLKp may include a flash memory cell. The memory cell array 20 may include a three-dimensional memory cell array. The three-dimensional memory cell array may include a plurality of NAND strings, and each of the plurality of NAND strings may include a plurality of memory cells respectively connected to a plurality of word lines WL stacked vertically.

[0035] The peripheral circuit 30 may receive an address ADDR, a command CMD, and a control signal CTRL from outside the semiconductor device 100 , and may transmit and receive data DATA to and from a device outside the semiconductor device 100 .

[0036] The row decoder 32 may select at least one of the plurality of memory cell blocks BLK1, BLK2, . . . , and BLKp in response to an address ADDR from outside the semiconductor device 100, and may select a word line WL, a string selection line SSL, and a ground selection line GSL of the selected memory cell block. The row decoder 32 may transmit a voltage for performing a memory operation to the word line WL of the selected memory cell block.

[0037] The page buffer 34 may be connected to the memory cell array 20 via the bit lines BL. The page buffer 34 may apply a voltage according to the data DATA intended to be stored in the memory cell array 20 to the bit lines BL by operating as a write driver during a program operation, and may sense the data DATA stored in the memory cell array 20 by operating as a sense amplifier during a read operation. The page buffer 34 may operate according to a control signal PCTL provided by the control logic 38.

[0038] The data input / output circuit 36 may be connected to the page buffer 34 via a plurality of data lines DL. During a program operation, the data input / output circuit 36 may receive data DATA from a memory controller (not shown) and may provide the program data DATA to the page buffer 34 based on a column address C_ADDR provided by the control logic 38. During a read operation, the data input / output circuit 36 may provide read data DATA stored in the page buffer 34 to the memory controller based on the column address C_ADDR provided by the control logic 38.

[0039] The data input / output circuit 36 may transfer an address or a command input thereto to the control logic 38 or the row decoder 32. The peripheral circuit 30 may further include an electrostatic discharge (ESD) circuit and a pull-up / pull-down driver.

[0040] The control logic 38 may receive a command CMD and a control signal CTRL from the memory controller. The control logic 38 may provide a row address R_ADDR to the row decoder 32 and a column address C_ADDR to the data input / output circuit 36. The control logic 38 may generate various internal control signals used in the semiconductor device 100 in response to the control signal CTRL. For example, when performing a memory operation such as a program operation or an erase operation, the control logic 38 may adjust the levels of the voltages provided to the word lines WL and the bit lines BL, respectively.

[0041] The common source line driver 39 may be connected to the memory cell array 20 via the common source line CSL. The common source line driver 39 may apply a common source voltage (eg, power supply voltage) or a ground voltage to the common source line CSL based on a control signal CTRL_BIAS of the control logic 38.

[0042] Figure 2A and Figure 2B are plan views each illustrating a schematic plan structure of a memory cell array MCA that may be used in the semiconductor device 100 according to some example embodiments. Figure 2A and Figure 2B Each of the memory cell arrays MCA shown in FIG can be constructed Figure 1 A portion of memory cell array 20 is shown.

[0043] Reference Figure 2A , the memory cell array MCA may include four pads MT arranged one after another in four quadrants dividing a rectangular area, respectively. Each of the four pads MT may include a memory cell region MEC and connection regions CON respectively arranged on both sides of the memory cell region MEC with respect to the first horizontal direction (X direction). In each of the four pads MT, one of the two connection regions CON respectively arranged on both sides of the memory cell region MEC with respect to the first horizontal direction (X direction) may be omitted. For example, the connection region CON adjacent to the center portion of the rectangular area including the four pads MT with respect to the first horizontal direction (X direction) may be omitted. In this case, in each of the four pads MT, the memory cell region MEC may be closer to the center portion of the rectangular area with respect to the first horizontal direction (X direction). Figure 2A Further extension shown.

[0044] Reference Figure 2B , the memory cell array MCA may include four pads MT arranged one after another in four quadrants dividing a rectangular area, respectively, similar to the reference Figure 2A However, in Figure 2B In the illustrated memory cell array MCA, a connection region CON may be disposed in a central portion of each of four pads MT. Each of the four pads MT may have a structure divided into a first pad MTA and a second pad MTB by the connection region CON.

[0045] Figure 3 is included Figure 2A A schematic perspective view of the semiconductor device 100 in the region EX1 is shown below. Figure 2A area EX1, but refer to the following Figure 3 The configuration described can also be applied to Figure 2B area EX1B.

[0046] Reference Figure 2A and Figure 3 , the semiconductor device 100 may include a cell array structure CAS and a peripheral circuit structure PCS that overlap each other in a vertical direction (Z direction). The cell array structure CAS may include a reference Figure 1 The memory cell array 20 is described. The peripheral circuit structure PCS may include reference Figure 1 The peripheral circuit 30 is described.

[0047] The cell array structure CAS may include a plurality of mats MT, and each of the plurality of mats MT may include a plurality of memory cell blocks BLK1, BLK2, . . . and BLKp (see Figure 1 ) and a plurality of through-electrode regions TA1. Each of the plurality of through-electrode regions TA1 included in one pad MT may correspond to a dummy memory cell block that does not include actually operating memory cells.

[0048] In one pad MT, each of the plurality of through-electrode regions TA1 may longitudinally extend through the memory cell region MEC and the connection region CON in a first horizontal direction (X direction). In one pad, the plurality of through-electrode regions TA1 are separated from each other in a second horizontal direction (Y direction) and are selected from a plurality of memory cell blocks BLK1, BLK2, . . . and BLKp (see Figure 1 ) may be arranged between adjacent through-electrode regions among the plurality of through-electrode regions TA1.

[0049] The through-electrode region TAX may be arranged in a tile cut area TCA between two pads MT adjacent to each other in the second horizontal direction (Y direction) among the plurality of pads MT. Each of the plurality of through-electrode regions TA1 arranged in the pad MT and the through-electrode region TAX arranged in the tile cut area TCA may have substantially the same configuration. In some example embodiments, the through-electrode region TAX arranged in the tile cut area TCA may be omitted, in which case the through-electrode region TAX may be replaced by an insulating structure.

[0050] Figure 4 is a schematic plan view of a portion of a cell array structure CAS of a semiconductor device 100 according to example embodiments.

[0051] Reference Figure 4 , the cell array structure CAS of the semiconductor device 100 may include a plate common source line 110 and a plurality of memory cell blocks arranged on the plate common source line 110. The plurality of memory cell blocks may correspond to the reference Figure 1The plurality of memory cell blocks BLK1, BLK2, ... and BLKp are described. The peripheral circuit structure PCS (see Figure 3 ) can be arranged below the plate common source line 110. A plurality of memory cell blocks can be arranged to overlap with the peripheral circuit structure PCS in the vertical direction (Z direction) with the plate common source line 110 located therebetween. Figure 4 When viewed in an XY plane in the image display, each of the plurality of memory cell blocks may have a shape extending longitudinally in a first horizontal direction (X direction).

[0052] The cell array structure CAS may include a memory cell area MEC and connection areas CON arranged on both sides of the memory cell area MEC with respect to a first horizontal direction (X direction). Each of the plurality of memory cell blocks may include a memory stacking structure MST extending throughout the memory cell area MEC and the connection area CON in the first horizontal direction (X direction). The memory stacking structure MST may include a plurality of gate lines 130 stacked in the memory cell area MEC and the connection area CON on a plate common source line 110 so as to overlap with each other in a vertical direction (Z direction). In each of the plurality of memory stacking structures MST, the plurality of gate lines 130 may constitute a gate stack GS. In each of the plurality of memory stacking structures MST, the plurality of gate lines 130 may respectively constitute as follows Figure 1 The ground selection line GSL, the plurality of word lines WL, and the string selection line SSL are shown. The plurality of gate lines 130 may each have an area that decreases in the XY plane as the distance from the plate common source line 110 increases. The center portions of the plurality of gate lines 130 that overlap each other in the vertical direction (Z direction) may constitute the memory cell region MEC, and the edge portions of the plurality of gate lines 130 may constitute the connection region CON. Although Figure 4 The edge portion of each of the plurality of gate lines 130 in the connection region CON is shown to extend in a straight line shape in the second horizontal direction (Y direction), but this is for simplification of the illustration. Figure 4 When viewed in the XY plane in FIG, an edge portion of each of the plurality of gate lines 130 in the connection region CON of each of the plurality of memory cell blocks may extend in an uneven shape in the second horizontal direction (Y direction).

[0053] A plurality of word line cutting structures WLC may be arranged on the plate common source line 110 in the memory cell region MEC and the connection region CON to extend longitudinally in the first horizontal direction (X direction). The plurality of word line cutting structures WLC may be separated from each other in the second horizontal direction (Y direction). Each of the plurality of memory cell blocks may be arranged between a pair of word line cutting structures WLC adjacent to each other among the plurality of word line cutting structures WLC. The plurality of word line cutting structures WLC may be arranged one after another on both sides of each of the plurality of memory cell blocks with respect to the second horizontal direction (Y direction) to define the width of each of the plurality of memory cell blocks in the second horizontal direction (Y direction). In at least some of the plurality of memory cell blocks, the plurality of separation cutting structures HLC may be arranged to extend longitudinally in the first horizontal direction (X direction). A certain area of each of the at least some of the memory cell blocks may be separated in the second horizontal direction (Y direction) by the separation cutting structure HLC. In some example embodiments, as Figure 4 As shown in the region N1 of FIG. 1 , the separation cut structure HLC in the memory cell block may include a portion extending discontinuously in the first horizontal direction (X direction). In some example embodiments, as shown in FIG. Figure 4 As shown in the region N2 of the memory cell block, the separation cut structure HLC may include a portion extending continuously in the first horizontal direction (X direction). In some example embodiments, the plurality of word line cut structures WLC and the plurality of separation cut structures HLC may each include, but are not limited to, a silicon oxide film.

[0054] A width WT of the through-electrode region TA1 in the second horizontal direction (Y direction) may be defined by a pair of word line cutting structures WLC respectively arranged on both sides of the through-electrode region TA1 , wherein the through-electrode region TA1 is located between the pair of word line cutting structures WLC.

[0055] In some example embodiments, in the second horizontal direction (Y direction), the width WT of the through-electrode region TA1 may be greater than the width of each of the plurality of memory cell blocks included in the cell array structure CAS. In some example embodiments, in the second horizontal direction (Y direction), the width WT of the through-electrode region TA1 may be at least twice the width of each of the plurality of memory cell blocks. In some example embodiments, different from Figure 4 In the illustrated example, in the second horizontal direction (Y direction), the width WT of the through-electrode area TA1 may be equal to or similar to the width of each of the plurality of memory cell blocks.

[0056] In some example embodiments, the semiconductor device 100 may further include a plurality of through-electrode regions TAY1 and TAY2 that penetrate the memory cell block of the cell array structure CAS in the vertical direction (Z direction). The plurality of through-electrode regions TAY1 may be arranged in the memory cell region MEC of the cell array structure CAS, and the plurality of through-electrode regions TAY2 may be arranged in the connection region CON of the cell array structure CAS. Figure 2A 、 Figure 2B and Figure 3 The through-electrode region TAX and Figure 4 The illustrated plurality of through-electrode regions TAY1 and TAY2 may each include at least some of the characteristic components of the plurality of through-electrode regions TA1 , which are described below.

[0057] The semiconductor device 100 may not include a separate dam structure that defines the width of each of the plurality of through-electrode regions (ie, TA1 , TAX , TAY1 , and TAY2 ).

[0058] Figure 5 is an equivalent circuit diagram of a memory cell array MCA of the semiconductor device 100 according to example embodiments. Figure 5 An equivalent circuit diagram of a vertical NAND flash memory device having a vertical channel structure is shown.

[0059] Reference Figure 5 , the memory cell array MCA may include a plurality of memory cell strings MS. The memory cell array MCA may include a plurality of bit lines BL (i.e., BL1, BL2, ..., and BLm), a plurality of word lines WL (i.e., WL1, WL2, ..., WLn-1, and WLn), at least one string selection line SSL, at least one ground selection line GSL, and a common source line CSL. The plurality of memory cell strings MS may be formed between the plurality of bit lines BL and the common source line CSL. Although Figure 5 An example is shown in which each of the plurality of memory cell strings MS includes one ground selection line GSL and two string selection lines SSL, but the inventive concept is not limited thereto. For example, each of the plurality of memory cell strings MS may include one string selection line SSL.

[0060] Each of the plurality of memory cell strings MS may include a string selection transistor SST, a ground selection transistor GST, and a plurality of memory cell transistors MC1, MC2, ..., MCn-1, and MCn. The drain region of the string selection transistor SST may be connected to a bit line BL, and the source region of the ground selection transistor GST may be connected to a common source line CSL. The common source line CSL may be a region to which the source regions of the plurality of ground selection transistors GST are commonly connected.

[0061] The string selection transistor SST may be connected to a string selection line SSL, and the ground selection transistor GST may be connected to a ground selection line GSL. Each of the plurality of memory cell transistors MC1, MC2, . . . , MCn-1, and MCn may be connected to a word line WL.

[0062] Figure 6A It is shown in detail Figure 4 A plan view of an example of the configuration of the area NB, Figure 6B is a plan view illustrating some components of a through-electrode region TA1 of a semiconductor device according to example embodiments, Figure 6C It is shown in detail Figure 4 FIG. 1 is a plan view of an example of a configuration of the through-electrode region EX2 of the memory cell block BLK, and shows an example of a configuration of the through-electrode region TAY2 of the memory cell block BLK. Figure 6C The memory cell block BLK in the Figure 1 One of the memory cell blocks BLK1, BLK2, . . . and BLKp. Figures 7 to 11 is a cross-sectional view showing in detail a semiconductor device according to an example embodiment. More specifically, Figure 7 It is along Figure 6A 1 is a cross-sectional view of the semiconductor device taken along line X1 - X1 ′. Figure 8 It is along Figure 6A 1 is a cross-sectional view of the semiconductor device taken along line Y1 - Y1 ′. Figure 9 It is along Figure 6B 1 is a cross-sectional view of the semiconductor device taken along line Y2 - Y2 ′. Figure 10 It is along Figure 6B 1 is a cross-sectional view of the semiconductor device taken along line Y3 - Y3 ′. Figure 11 It is along Figure 6B A cross-sectional view of the semiconductor device taken along line Y4-Y4'. Figures 6A to 11 In, with Figures 1 to 5 The same reference numerals in the drawings represent the same components, and repeated descriptions thereof are omitted here.

[0063] Reference Figures 6A to 11 , the semiconductor device 100 may include a peripheral circuit structure PCS and a cell array structure CAS arranged on the peripheral circuit structure PCS and overlapping the peripheral circuit structure PCS in a vertical direction (Z direction).

[0064] The cell array structure CAS may include a plate common source line 110, a first conductive plate 114, a second conductive plate 118, a memory stack structure MST arranged in a memory cell area MEC, and an insulating plate 112, a second conductive plate 118 and a memory stack structure MST (for example, edge portions of multiple gate lines 130) arranged in a connection area CON.

[0065] like Figure 7 As shown, in the connection region CON of the cell array structure CAS, the insulating plate 112, the second conductive plate 118, and the edge portions of the plurality of gate lines 130 may be sequentially stacked on the plate common source line 110 in the stated order. Figure 8 As shown, in the memory cell region MEC of the cell array structure CAS, the first conductive plate 114 , the second conductive plate 118 , and the memory stack structure MST may be sequentially stacked on the plate common source line 110 in the stated order.

[0066] The plate common source line 110 , the first conductive plate 114 , and the second conductive plate 118 may serve as a common source line CSL for supplying current to vertical memory cells of the cell array structure CAS.

[0067] In some example embodiments, the plate common source line 110 may include a semiconductor material such as polysilicon. Each of the first conductive plate 114 and the second conductive plate 118 may include a doped polysilicon film, a metal film, or a combination thereof. The metal film may include, but is not limited to, tungsten (W). The memory stack structure MST may include a gate stack GS. The gate stack GS may include a plurality of gate lines 130 extending parallel to each other in the horizontal direction and overlapping each other in the vertical direction (Z direction). Each of the plurality of gate lines 130 may include a metal, a metal silicide, an impurity-doped semiconductor, or a combination thereof. For example, each of the plurality of gate lines 130 may include a metal (such as tungsten, nickel, cobalt, or tantalum), a metal silicide (such as tungsten silicide, nickel silicide, cobalt silicide, or tantalum silicide), doped polysilicon, or a combination thereof.

[0068] The first insulating film 132 may be disposed between the second conductive plate 118 and the plurality of gate lines 130 and between adjacent gate lines among the plurality of gate lines 130. The uppermost gate line 130 among the plurality of gate lines 130 may be covered by the first insulating film 132. The first insulating film 132 may include silicon oxide.

[0069] like Figure 6A and Figure 8 As shown, in the memory cell region MEC (and in the connection region CON), a plurality of word line cutting structures WLC may extend longitudinally in a first horizontal direction (X direction) on the plate common source line 110. The width of each of the plurality of gate lines 130 in a second horizontal direction (Y direction) may be defined by the plurality of word line cutting structures WLC.

[0070] Each of the plurality of word line cut structures WLC may include an insulating structure. In some example embodiments, the insulating structure may include silicon oxide, silicon nitride, silicon oxynitride, or a low-k material. For example, the insulating structure may include a silicon oxide film, a silicon nitride film, a SiON film, a SiOCN film, a SiCN film, or a combination thereof. In some example embodiments, at least a portion of the insulating structure may include an air gap. As used herein, the term "air" may refer to atmospheric air or other gases that may be present during the manufacturing process.

[0071] The plurality of gate lines 130 constituting one gate stack GS may be stacked on the second conductive plate 118 between two adjacent word line cutting structures WLC to overlap each other in the vertical direction (Z direction). The plurality of gate lines 130 constituting one gate stack GS may include reference Figure 1 A ground selection line GSL, a plurality of word lines WL, and a string selection line SSL are described.

[0072] like Figure 8 As shown, among the plurality of gate lines 130, each of the two upper gate lines 130 may be separated (e.g., separated) in the second horizontal direction (Y direction) with a string selection line cutting structure SSLC therebetween. The two gate lines 130 separated from each other with the string selection line cutting structure SSLC therebetween may both constitute a reference Figure 1 The string selection line SSL is described. Figure 8 An example is shown in which one string selection line cutting structure SSLC is formed in one gate stack GS, but the inventive concept is not limited to Figure 8 For example, at least two string selection line cut structures SSLC may be formed in one gate stack GS. The string selection line cut structure SSLC may include an insulating film. In some example embodiments, the string selection line cut structure SSLC may include an insulating film including an oxide film, a nitride film, or a combination thereof. In some example embodiments, at least a portion of the string selection line cut structure SSLC may include an air gap.

[0073] like Figures 7 to 11 As shown, the peripheral circuit structure PCS may include a substrate 52 , a plurality of peripheral circuits on the substrate 52 , and a multilayer wiring structure MWS for connecting the plurality of peripheral circuits to each other or to components in the memory cell region MEC.

[0074] The substrate 52 may include a semiconductor substrate. For example, the substrate 52 may include Si, Ge, or SiGe. An active region AC may be defined in the substrate 52 by a device isolation film 54. Multiple transistors TR constituting multiple peripheral circuits may be formed on the active region AC. Each of the multiple transistors TR may include a gate PG and multiple ion implantation regions PSD formed in the active region AC on both sides of the gate PG. Each of the multiple ion implantation regions PSD may constitute a source region or a drain region of the transistor TR.

[0075] The peripheral circuit structure PCS may include multiple circuits with reference to Figure 1 The various circuits included in the peripheral circuit 30 are described. In some example embodiments, the plurality of circuits of the peripheral circuit structure PCS may include Figure 1 Shown are a row decoder 32 , a page buffer 34 , a data input / output circuit 36 , control logic 38 , and a common source line driver 39 .

[0076] The multilayer wiring structure MWS of the peripheral circuit structure PCS may include multiple wiring layers ML60, ML61, and ML62 and multiple contacts MC60, MC61, and MC62. At least some of the multiple wiring layers ML60, ML61, and ML62 may be configured to be electrically connected to transistors TR. The multiple contacts MC60, MC61, and MC62 may be configured to respectively connect the multiple transistors TR to some wiring layers selected from the multiple wiring layers ML60, ML61, and ML62. A conductive landing pad LP may be arranged on a portion of the uppermost wiring layer ML62 among the multiple wiring layers ML60, ML61, and ML62. The conductive landing pad LP may include polysilicon. The multiple transistors TR, the multilayer wiring structure MWS, and the conductive landing pad LP included in the peripheral circuit structure PCS may be covered by an interlayer dielectric 70. The interlayer dielectric 70 may include a silicon oxide film, a silicon nitride film, a SiON film, a SiOCN film, or a combination thereof. The board common source line 110 may be arranged on the interlayer dielectric 70.

[0077] The plate common source line 110 , the insulating plate 112 , the first conductive plate 114 , and the second conductive plate 118 may each extend in a horizontal direction to cover the peripheral circuit structure PCS.

[0078] like Figures 7 to 11 As shown, in some areas of each of the memory cell region MEC and the connection region CON, a plurality of through openings 120H may be formed to pass through the plate common source line 110, the insulating plate 112, the first conductive plate 114, and the second conductive plate 118. Each of the plurality of through openings 120H may be filled with an insulating plug 120. The insulating plug 120 may include a silicon oxide film, a silicon nitride film, or a combination thereof.

[0079] like Figure 8 As shown, in the memory cell region MEC, a plurality of channel structures 140 may pass through a plurality of gate lines 130, a plurality of first insulating films 132, a second conductive plate 118, a first conductive plate 114, and a plate common source line 110 in a vertical direction (Z direction). The plurality of channel structures 140 may be arranged to be separated from each other at a certain pitch in a first horizontal direction (X direction) and a second horizontal direction (Y direction). Each of the plurality of channel structures 140 may include a gate dielectric film 142, a channel region 144, a buried insulating film 146, and a drain region 148.

[0080] The gate dielectric film 142 may include a tunneling dielectric film, a charge storage film, and a blocking dielectric film formed in the order described above on the channel region 144. The tunneling dielectric film may include silicon oxide, hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide, or the like. The charge storage film is a region in which electrons that have passed through the tunneling dielectric film from the channel region 144 can be stored, and may include silicon nitride, boron nitride, silicon boron nitride, or impurity-doped polysilicon. The blocking dielectric film may include silicon oxide, silicon nitride, or a metal oxide having a dielectric constant greater than that of silicon oxide. The metal oxide may include hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide, or a combination thereof.

[0081] like Figure 8 As shown, the first conductive plate 114 may pass through a portion of the gate dielectric film 142 in a horizontal direction (X direction and / or Y direction) to contact the channel region 144. The gate dielectric film 142 may include a portion arranged at a higher level than the first conductive plate 114 and covering the sidewalls of the channel region 144, and a portion arranged at a lower level than the first conductive plate 114 and covering the lower surface of the channel region 144. The channel region 144 may be separated from the plate common source line 110, with the gate dielectric film 142 located therebetween. The sidewalls of the channel region 144 may be in contact with the first conductive plate 114 and may be configured to be electrically connected to the first conductive plate 114.

[0082] like Figure 8 As shown, the channel region 144 may have a cylindrical shape. The channel region 144 may include doped polysilicon or undoped polysilicon. A buried insulating film 146 may fill the interior space of the channel region 144. The buried insulating film 146 may include an insulating material. For example, the buried insulating film 146 may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In some example embodiments, the buried insulating film 146 may be omitted. In this case, the channel region 144 may have a pillar structure without an interior space.

[0083] The drain region 148 may include doped polysilicon. The plurality of drain regions 148 may be insulated from one another by the first upper insulating film UL1. In the memory cell region MEC, the plurality of channel structures 140 and the first upper insulating film UL1 may be covered by the second upper insulating film UL2.

[0084] The string selection line cut structure SSLC may pass through the first upper insulating film UL1, the second upper insulating film UL2, and the third upper insulating film UL3 in the vertical direction (Z direction). The upper surface of the string selection line cut structure SSLC, the upper surface of the word line cut structure WLC, and the upper surface of the third upper insulating film UL3 may extend at substantially the same vertical level. The fourth upper insulating film UL4 and the fifth upper insulating film UL5 may be sequentially formed on the string selection line cut structure SSLC, the word line cut structure WLC, and the third upper insulating film UL3 in the order described. Each of the first upper insulating film UL1, the second upper insulating film UL2, the third upper insulating film UL3, the fourth upper insulating film UL4, and the fifth upper insulating film UL5 may include an oxide film, a nitride film, or a combination thereof.

[0085] like Figure 6A and Figure 8 As shown, a plurality of bit lines BL may be arranged on the fifth upper insulating film UL5 in the memory cell region MEC of the memory stack structure MST. The plurality of bit lines BL may extend in the second horizontal direction (Y direction) and be separated from each other in the first horizontal direction (X direction). The plurality of channel structures 140 may be connected to the plurality of bit lines BL via a plurality of contact plugs 176 passing through the second upper insulating film UL2, the third upper insulating film UL3, the fourth upper insulating film UL4, and the fifth upper insulating film UL5.

[0086] like Figure 7 As shown, in the connection region CON of the memory stack structure MST, the insulating plate 112 and the second conductive plate 118 may be sequentially stacked in the stated order on the plate common source line 110. The insulating plate 112 may include a multi-layered insulating film including a first insulating film 112A, a second insulating film 112B, and a third insulating film 112C sequentially stacked in the stated order on the plate common source line 110. In some example embodiments, the first insulating film 112A and the third insulating film 112C may each include a silicon oxide film, and the second insulating film 112B may include a silicon nitride film.

[0087] In the connection region CON, each of the plurality of gate lines 130 may include a gate pad portion 130A having a greater thickness in the vertical direction (Z direction) than other portions of the gate line 130. The gate pad portion 130A of the gate line 130 may be arranged in an edge portion of the gate line 130 farthest from the memory cell region MEC. Figure 7It is shown that the gate pad portion 130A is arranged only in one side end portion of some gate lines 130 among the plurality of gate lines 130, but some gate lines 130 that do not have the gate pad portion 130A in the one side end portion thereof may include the gate pad portion 130A in the other side end portion thereof.

[0088] In the connection region CON, an edge portion of each of the plurality of gate lines 130 and the plurality of first insulating films 132 may be covered by an interlayer dielectric 138. The interlayer dielectric 138 may include, but is not limited to, a silicon oxide film.

[0089] like Figure 7 As shown, a plurality of memory cell contacts MCC may be arranged in the connection region CON. Each of the plurality of memory cell contacts MCC may be arranged in a vertical hole H1 that passes through at least some of the interlayer dielectric 138, the plurality of gate lines 130, and the plurality of first insulating films 132. Each of the plurality of memory cell contacts MCC may pass through at least one gate line 130, at least one first insulating film 132, the insulating plug 120, and the conductive landing pad LP in the vertical direction (Z direction) and may be connected to one wiring layer ML62 selected from the plurality of wiring layers ML60, ML61, and ML62 of the multilayer wiring structure MWS of the peripheral circuit structure PCS.

[0090] Each of the plurality of memory cell contacts MCC may be connected to one gate line 130 selected from the plurality of gate lines 130 and may not be connected to other gate lines 130 other than the selected one gate line 130. Each of the plurality of memory cell contacts MCC may be in contact with the gate pad portion 130A of one gate line 130 selected from the plurality of gate lines 130 and may be connected to the selected one gate line 130 via the gate pad portion 130A. The memory cell contact MCC in the vertical hole H1 may be separated from the other gate lines 130 other than the selected one gate line 130 in the horizontal direction. An insulating ring 152 may be arranged between the memory cell contact MCC and the gate lines 130 not connected to the memory cell contact MCC. In some example embodiments, the insulating ring 152 may include, but is not limited to, a silicon oxide film.

[0091] like Figure 6A and Figure 7As shown, a plurality of dummy channel structures D140 may be arranged in the connection region CON. Each of the plurality of dummy channel structures D140 may pass through at least some of the interlayer dielectric 138, the plurality of gate lines 130, and the plurality of first insulating films 132. Each of the plurality of dummy channel structures D140 may pass through at least one of the plurality of gate lines 130. Each of the plurality of dummy channel structures D140 may pass through at least one gate line 130, at least one first insulating film 132, the second conductive plate 118, and the insulating plate 112 in the vertical direction (Z direction), and may pass through a portion of the plate common source line 110 in the vertical direction (Z direction).

[0092] Similar to the channel structure 140, each of the plurality of dummy channel structures D140 may include a gate dielectric film 142, a channel region 144, a buried insulating film 146, and a drain region 148. However, a planar size of each of the plurality of dummy channel structures D140 may be larger than a planar size of the channel structure 140. In some example embodiments, Figure 7 Unlike the illustrated example, the plurality of dummy channel structures D140 may each include a silicon oxide plug. Figure 6A and Figure 6C The number and arrangement shape of the dummy channel structures D140 shown in FIG are merely examples, and the inventive concept is not limited thereto. In the connection region CON, a plurality of dummy channel structures D140 may be variously arranged at various positions selected in the memory stack structure MST.

[0093] like Figure 7 As shown, in the connection region CON, the interlayer dielectric 138 may be covered by the first upper insulating film UL1. The drain regions 148 of the plurality of dummy channel structures D140 may be insulated from each other by the first upper insulating film UL1. In the connection region CON, the plurality of dummy channel structures D140 and the first upper insulating film UL1 may be covered by the second upper insulating film UL2.

[0094] like Figure 6A and Figure 7 As shown, a conductive plate contact 164 may be arranged in the connection region CON. The conductive plate contact 164 may extend in the vertical direction (Z direction) through the third upper insulating film UL3, the second upper insulating film UL2, the first upper insulating film UL1, the interlayer dielectric 138, the second conductive plate 118, and the insulating plate 112 to the plate common source line 110. The sidewalls of the conductive plate contact 164 may be covered by the insulating spacer 162. The fourth upper insulating film UL4 may cover the upper surface of each of the conductive plate contact 164 and the insulating spacer 162.

[0095] The plurality of memory cell contacts MCC may pass through the first, second, third, and fourth upper insulating films UL1, UL2, UL3, and UL4, and the upper surface of each of the plurality of memory cell contacts MCC may be covered by the fifth and sixth upper insulating films UL5 and UL6.

[0096] The conductive plate contact 164 can be connected to one of the plurality of upper wiring layers UML via a contact plug 172 passing through the fourth upper insulating film UL4 and the fifth upper insulating film UL5. The plurality of upper wiring layers UML can be arranged at the same level as the plurality of bit lines BL arranged in the memory cell region MEC. The spaces between adjacent upper wiring layers in the plurality of upper wiring layers UML and the spaces between adjacent bit lines in the plurality of bit lines BL can be filled with a sixth upper insulating film UL6. The sixth upper insulating film UL6 may include an oxide film, a nitride film, or a combination thereof.

[0097] The plurality of memory cell contacts MCC, the conductive plate contacts 164 , the plurality of contact plugs 172 , and the plurality of upper wiring layers UML may each include tungsten, titanium, tantalum, copper, aluminum, titanium nitride, tantalum nitride, tungsten nitride, or a combination thereof.

[0098] In the connection region CON, the plate common source line 110 , the insulating plate 112 , and the second conductive plate 118 may extend in a horizontal direction to cover the peripheral circuit structure PCS.

[0099] Each of the plurality of memory cell contacts MCC may be configured to be connected to at least one peripheral circuit selected from the plurality of peripheral circuits via the multi-layer wiring structure MWS of the peripheral circuit structure PCS. Figures 7 to 11 An example is shown in which the multilayer wiring structure MWS includes three wiring layers in the vertical direction (Z direction), but the inventive concept is not limited to Figures 7 to 11 For example, the multilayer wiring structure MWS may include two wiring layers or four or more wiring layers.

[0100] Each of the plurality of wiring layers ML60, ML61, and ML62 and the plurality of contacts MC60, MC61, and MC62 may include a metal, a conductive metal nitride, a metal silicide, or a combination thereof. For example, each of the plurality of wiring layers ML60, ML61, and ML62 and the plurality of contacts MC60, MC61, and MC62 may include a conductive material such as tungsten, molybdenum, titanium, cobalt, tantalum, nickel, tungsten silicide, titanium silicide, cobalt silicide, tantalum silicide, or nickel silicide.

[0101] although Figure 6AA configuration is shown in which a plurality of memory cell contacts MCC are arranged in a row along a straight line in the first horizontal direction (X direction), but the inventive concept is not limited thereto. Without departing from the scope of the inventive concept, the planar placement structure of each of the plurality of memory cell contacts MCC can be variously selected.

[0102] like Figure 6B 、 Figure 9 、 Figure 10 and Figure 11 As shown, the through-electrode region TA1 may include a first through-electrode portion TA11, a second through-electrode portion TA12, and a third through-electrode portion TA13 arranged at different positions in the first horizontal direction (X direction) and having different configurations. The first through-electrode portion TA11 may be arranged at a position facing the memory cell region MEC adjacent thereto in the second horizontal direction (Y direction) (hereinafter referred to as the memory cell region MEC). Each of the second through-electrode portion TA12 and the third through-electrode portion TA13 may be arranged at a position facing the connection region CON adjacent thereto in the second horizontal direction (Y direction) (hereinafter referred to as the connection region CON).

[0103] According to some example embodiments, the through-electrode area TA1 may be omitted. Figure 9 The first through-electrode portion TA11 is shown arranged in the memory cell region MEC. According to some example embodiments, the through-electrode region TA1 may be omitted as shown. Figure 10 The second through-electrode portion TA12 arranged at the first position in the connection region CON as shown and Figure 11 According to some example embodiments, the semiconductor device 100 includes only the second through-electrode portion TA12 (e.g., the second through-electrode portion TA13) arranged at the first position in the connection region CON among the components of the through-electrode region TA1. Figure 10 ) or the third through-electrode portion TA13 arranged at the second position in the connection region CON (as shown Figure 11 As used herein, the terms "first position" and "second position" may refer to Figure 6B The different regions shown are separated from each other in the first horizontal direction (X direction), or the different regions are separated from each other in the second horizontal direction (Y direction).

[0104] The through-electrode region TA1 may include an insulating structure INS arranged in the memory cell region MEC and the connection region CON on the insulating plug 120 and a plurality of through-electrodes THV passing through the insulating structure INS in a vertical direction (Z direction).

[0105] Each of the plurality of through electrodes THV may be configured to pass through the insulating structure INS, the insulating plug 120, and the conductive landing pad LP in the vertical direction (Z direction), and configured to be connected to one circuit selected from a plurality of circuits in the multilayer wiring structure MWS of the peripheral circuit structure PCS. For example, some of the plurality of through electrodes THV may be configured to be connected to the page buffer 34 (see FIG. 1 ) of the peripheral circuit structure PCS. Figure 1 Some other through-electrodes THV among the plurality of through-electrodes THV may be configured to be connected to the row decoder 32 of the peripheral circuit structure PCS (see Figure 1 ). In addition, still other through electrodes THV among the plurality of through electrodes THV may be configured to be connected to a common source driver 39 of the peripheral circuit structure PCS (see Figure 1 ). Still other through-electrodes THV among the plurality of through-electrodes THV may be configured to be connected to a transmission circuit included in the peripheral circuit structure PCS and including a plurality of transmission transistors. However, the inventive concept is not limited to the examples set forth above, and various modifications and changes may be made thereto without departing from the scope of the inventive concept.

[0106] In the memory cell region MEC, an upper surface of the insulating structure INS penetrating the electrode region TA1 may be in contact with the first upper insulating film UL1 . Figure 9 As shown, in the connection region CON, the upper surface of the insulating structure INS penetrating the electrode region TA1 may be covered by the interlayer dielectric 138, as shown in FIG. Figure 10 and Figure 11 In the connection region CON, an upper surface of the insulating structure INS penetrating the electrode region TA1 may be in contact with the interlayer dielectric 138 .

[0107] The insulating structure INS may include a plurality of first insulating films 132 and a plurality of second insulating films 134 alternately stacked one after another in the vertical direction (Z direction) in each of the memory cell region MEC and the connection region CON, and a plurality of third insulating films 134R in contact with the upper second insulating films 134 adjacent to the interlayer dielectric 138 among the plurality of second insulating films 134 in the connection region CON. Figure 10 and Figure 11As shown, in the second through-electrode portion TA12 and the third through-electrode portion TA13 of the through-electrode region TA1 in the connection region CON, the third insulating film 134R may be disposed between the upper second insulating film 134 adjacent to the interlayer dielectric 138 among the plurality of second insulating films 134 and the interlayer dielectric 138, and may be in contact with each of the upper second insulating film 134 and the interlayer dielectric 138. In the second through-electrode portion TA12 and the third through-electrode portion TA13, at least one through-electrode THV selected from the plurality of through-electrodes THV may pass through the third insulating film 134R in the vertical direction (Z direction).

[0108] like Figure 9 As shown, in the memory cell region MEC, the upper surface US1 of the insulating structure INS penetrating the electrode region TA1 may be horizontally ( Figure 9 As used herein, the term "vertical level" refers to the distance in the vertical direction (Z direction) from the upper surface of the insulating plug 120 facing the insulating structure INS.

[0109] like Figure 10 and Figure 11 As shown, in the connection region CON, the upper surface of the insulating structure INS penetrating the electrode region TA1 may have a varying height in the vertical direction (Z direction) along each of the first horizontal direction (X direction) and the second horizontal direction (Y direction). Figure 10 As shown, in the second through-electrode portion TA12 of the through-electrode area TA1, the upper surface US2 of the second insulating film 134 forming the upper surface of the insulating structure INS may be closer to the substrate 52 of the peripheral circuit structure PCS in the vertical direction (Z direction) than the upper surface US3 of the third insulating film 134R forming the upper surface of the insulating structure INS. Figure 11 As shown, in the third through-electrode portion TA13 of the through-electrode area TA1, the upper surface US4 of the second insulating film 134 forming the upper surface of the insulating structure INS may be closer to the substrate 52 of the peripheral circuit structure PCS in the vertical direction (Z direction) than the upper surface US5 of the third insulating film 134R forming the upper surface of the insulating structure INS. Figure 10 The upper surface of the insulating structure INS in the second through-electrode portion TA12 shown in FIG. 1 may be higher in the vertical direction (Z direction) than the upper surface US4 of the second insulating film 134 and the upper surface US5 of the third insulating film 134R (both of which form Figure 11Each of the upper surfaces of the insulating structures INS in the third through-electrode portion TA13 is shown farther away from the substrate 52 of the peripheral circuit structure PCS.

[0110] The vertical levels of the plurality of third insulating films 134R arranged in the through-electrode region TA1 may differ depending on their positions in the first horizontal direction (X direction). As the distance from the memory cell region MEC in the first horizontal direction (X direction) increases, the plurality of third insulating films 134R in the through-electrode region TA1 may be arranged at vertical levels closer to the substrate 52 of the peripheral circuit structure PCS. For example, the vertical level of the third insulating film 134R of the second through-electrode portion TA12 may be higher in the vertical direction (Z direction) from the substrate 52 of the peripheral circuit structure PCS than the vertical level of the third insulating film 134R of the third through-electrode portion TA13.

[0111] like Figure 10 and Figure 11 As shown, because the upper surface of the insulating structure INS that penetrates the electrode area TA1 in the connection area CON has a varying height in the vertical direction (Z direction) along each of the first horizontal direction (X direction) and the second horizontal direction (Y direction), the lower surface of the interlayer dielectric 138 (which contacts the upper surface of the insulating structure INS that penetrates the electrode area TA1 in the connection area CON) can have a plurality of step portions with varying heights corresponding to the upper surface of the insulating structure INS.

[0112] In some example embodiments, the first insulating film 132, the second insulating film 134, and the third insulating film 134R may each include different materials. For example, the first insulating film 132 may include a silicon oxide film, and each of the second insulating film 134 and the third insulating film 134R may include a silicon nitride film or a hydrogenated silicon nitride film, and may satisfy at least one of a first condition (a silicon atom (Si) content ratio in the third insulating film 134R is less than a silicon atom (Si) content ratio in the second insulating film 134), a second condition (a nitrogen atom (N) content ratio in the third insulating film 134R is greater than a nitrogen atom (N) content ratio in the second insulating film 134), or a third condition (a hydrogen atom (H) content ratio in the third insulating film 134R is greater than a hydrogen atom (H) content ratio in the second insulating film 134).

[0113] When the first condition is satisfied, the content ratio of nitrogen atoms (N) in the third insulating film 134R may be equal to or greater than the content ratio of nitrogen atoms (N) in the second insulating film 134, and the content ratio of hydrogen atoms (H) in the third insulating film 134R may be equal to or greater than the content ratio of hydrogen atoms (H) in the second insulating film 134. When the second condition is satisfied, the content ratio of silicon atoms (Si) in the third insulating film 134R may be equal to or less than the content ratio of silicon atoms (Si) in the second insulating film 134, and the content ratio of hydrogen atoms (H) in the third insulating film 134R may be equal to or greater than the content ratio of hydrogen atoms (H) in the second insulating film 134. When the third condition is satisfied, the content ratio of silicon atoms (Si) in the third insulating film 134R may be equal to or less than the content ratio of silicon atoms (Si) in the second insulating film 134, and the content ratio of nitrogen atoms (N) in the third insulating film 134R may be equal to or greater than the content ratio of nitrogen atoms (N) in the second insulating film 134.

[0114] In some example embodiments, the first insulating film 132 may include a material different from the constituent material of each of the second insulating film 134 and the third insulating film 134R, and the second insulating film 134 and the third insulating film 134R may include the same material. For example, the first insulating film 132 may include a silicon oxide film, and the second insulating film 134 and the third insulating film 134R may each include the same material selected from a silicon nitride film and a hydrogenated silicon nitride film. Here, the content ratio of silicon atoms (Si) and the content ratio of nitrogen atoms (N) may be equal between the second insulating film 134 and the third insulating film 134R.

[0115] like Figures 9 to 11 As shown, the word line cut structure WLC may be arranged on both sides of the through-electrode region TA1 with respect to the second horizontal direction (Y direction). The through-electrode region TA1 may include a plurality of dummy conductive layers 130D between the word line cut structure WLC and the insulation structure INS. Each of the plurality of dummy conductive layers 130D may be in contact with the adjacent word line cut structure WLC. Each of the plurality of dummy conductive layers 130D may be arranged between the word line cut structure WLC and the insulation structure INS. Each of the plurality of dummy conductive layers 130D may be arranged at the same vertical level as a corresponding one of the plurality of gate lines 130 selected from the plurality of gate lines 130 arranged in the memory cell region MEC. Each of the plurality of dummy conductive layers 130D may include the same material as that constituting each of the plurality of gate lines 130.

[0116] The plurality of dummy conductive layers 130D may include a group of dummy conductive layers 130D that contact one word line cut structure WLC and are arranged in a row in the vertical direction (Z direction). The plurality of dummy conductive layers 130D included in the group of dummy conductive layers 130D may be separated from each other in the vertical direction (Z direction). In the group of dummy conductive layers 130D, each of the plurality of dummy conductive layers 130D may be arranged at the same vertical level as a corresponding one of the plurality of gate lines 130 selected from the plurality of gate lines 130 arranged in the memory cell region MEC.

[0117] like Figure 9 As shown, in the first through-electrode portion TA11 arranged in the memory cell region MEC, the thicknesses of the group of dummy conductive layers 130D in the vertical direction (Z direction) may be equal to or similar to each other. One of the two sidewalls of each of the multiple dummy conductive layers 130D in the group of dummy conductive layers 130D in terms of the second horizontal direction (Y direction) may be in contact with the word line cutting structure WLC, and the other sidewall may be in contact with the second insulating film 134. In some example embodiments, the widths of the multiple dummy conductive layers 130D included in the group of dummy conductive layers 130D in the second horizontal direction (Y direction) may be equal to or similar to each other. In some example embodiments, the widths of at least some of the multiple dummy conductive layers 130D included in the group of dummy conductive layers 130D in the second horizontal direction (Y direction) may be different. In some example embodiments, the width of each of the multiple dummy conductive layers 130D included in the group of dummy conductive layers 130D in the second horizontal direction (Y direction) may be greater than Figure 9 In this case, the separation distance between each of the plurality of dummy conductive layers 130D and the through electrode THV may be less than Figure 9 Separation distance shown.

[0118] like Figure 10 and Figure 11 As shown, in the second through-electrode portion TA12 and the third through-electrode portion TA13 arranged in the connection region CON, the upper dummy conductive layer 130D farthest from the peripheral circuit structure PCS among the plurality of dummy conductive layers 130D in the group of dummy conductive layers 130D may have a thickness greater than that of the other dummy conductive layers 130D in the vertical direction (Z direction). In the second through-electrode portion TA12 and the third through-electrode portion TA13, the upper dummy conductive layer 130D farthest from the peripheral circuit structure PCS among the group of dummy conductive layers 130D may both be arranged at the same vertical level as that of one gate pad portion 130A selected from the plurality of gate pad portions 130A arranged in the memory cell region MEC.

[0119] exist Figure 10 In the second through-electrode portion TA12 shown, one sidewall of the two sidewalls of the upper dummy conductive layer 130D among the plurality of dummy conductive layers 130D in the set of dummy conductive layers 130D in the second horizontal direction (Y direction) may be in contact with the word line cut structure WLC, and the other sidewall may be in contact with the interlayer dielectric 138. In the second through-electrode portion TA12, one sidewall of the two sidewalls of each of the remaining dummy conductive layers 130D in the set of dummy conductive layers 130D except the upper dummy conductive layer 130D in the second horizontal direction (Y direction) may be in contact with the word line cut structure WLC, and the other sidewall may be in contact with the second insulating film 134. In the second through-electrode portion TA12, the widths of the plurality of dummy conductive layers 130D in the set of dummy conductive layers 130D in the second horizontal direction (Y direction) may be equal to or similar to each other.

[0120] exist Figure 11 In the third through-electrode portion TA13 shown, one of the two sidewalls of an upper dummy conductive layer 130D among the plurality of dummy conductive layers 130D in the set of dummy conductive layers 130D, with respect to the second horizontal direction (Y direction), may be in contact with the word line cut structure WLC, and the other sidewall may be in contact with the interlayer dielectric 138 and the second insulating film 134. In the third through-electrode portion TA13, one of the two sidewalls of each of the remaining dummy conductive layers 130D among the plurality of dummy conductive layers 130D in the set of dummy conductive layers 130D, excluding the upper dummy conductive layer 130D, with respect to the second horizontal direction (Y direction), may be in contact with the word line cut structure WLC, and the other sidewall may be in contact with the second insulating film 134. In the third through-electrode portion TA13, the widths of the plurality of dummy conductive layers 130D in the set of dummy conductive layers 130D in the second horizontal direction (Y direction) may vary depending on the position of the plurality of dummy conductive layers 130D. For example, Figure 11 As shown, a portion of the upper dummy conductive layer 130D farthest from the peripheral circuit structure PCS in the vertical direction (Z direction) among the plurality of dummy conductive layers 130D in the group of dummy conductive layers 130D may extend longer than the other dummy conductive layers 130D in the second horizontal direction (Y direction) toward the through electrode THV. Figure 11 As shown, the end portion E1 of the upper dummy conductive layer U1 may overlap the third insulating film 134R of the insulating structure INS in the vertical direction (Z direction), but the inventive concept is not limited thereto.

[0121] like Figure 10As shown, in the second through-electrode portion TA12 of the through-electrode area TA1, among the first group of dummy conductive layers 130D arranged in a row along the vertical direction (Z direction), each remaining dummy conductive layer 130D except the upper dummy conductive layer 130D farthest from the peripheral circuit structure PCS may be arranged at the same vertical level as the vertical level of one second insulating film 134 selected from the plurality of second insulating films 134 of the insulation structure INS. In the second through-electrode portion TA12 of the through-electrode area TA1, a vertical level LV1A of an upper surface US3 of the third insulating film 134R corresponding to a local area of the insulation structure INS pierced by the through-electrode THV in the vertical direction (Z direction) may be closer to the peripheral circuit structure PCS than a vertical level LV1B of an upper surface 130DT of the upper dummy conductive layer 130D farthest from the peripheral circuit structure PCS among the plurality of dummy conductive layers 130D in the second through-electrode portion TA12.

[0122] like Figure 11 As shown, in the third through-electrode portion TA13 of the through-electrode area TA1, the second group of dummy conductive layers 130D arranged in a row in the vertical direction (Z direction) may all be arranged at the same vertical level as the vertical level of a corresponding one of the second insulating films 134 selected from the plurality of second insulating films 134 of the insulating structure INS. In the third through-electrode portion TA13 of the through-electrode area TA1, a vertical level LV1C of an upper surface US5 of the third insulating film 134R corresponding to a local area of the insulating structure INS pierced by the through-electrode THV in the vertical direction (Z direction) may be farther from the peripheral circuit structure PCS than a vertical level LV1D of an upper surface 130DT of an upper dummy conductive layer 130D farthest from the peripheral circuit structure PCS among the second group of dummy conductive layers 130D.

[0123] like Figure 9 As shown, in the first through-electrode portion TA11 of the through-electrode area TA1, the upper surface US1 of the insulating structure INS may be covered by the first upper insulating film UL1, the second upper insulating film UL2, the third upper insulating film UL3, the fourth upper insulating film UL4, the fifth upper insulating film UL5, and the sixth upper insulating film UL6. The second upper insulating film UL2, the third upper insulating film UL3, the fourth upper insulating film UL4, the fifth upper insulating film UL5, and the sixth upper insulating film UL6 may be stacked on the first upper insulating film UL1 in the stated order.

[0124] like Figure 10 and Figure 11As shown, in each of the second through-electrode portion TA12 and the third through-electrode portion TA13 of the through-electrode area TA1, the upper surfaces US2 and US3 of the insulating structure INS may be covered by the interlayer dielectric 138, and the first upper insulating film UL1, the second upper insulating film UL2, the third upper insulating film UL3, the fourth upper insulating film UL4, the fifth upper insulating film UL5 and the sixth upper insulating film UL6 may be stacked on the interlayer dielectric 138 in the order stated.

[0125] like Figures 9 to 11 As shown, in each of the first through-electrode portion TA11, the second through-electrode portion TA12, and the third through-electrode portion TA13 of the through-electrode area TA1, each of the plurality of through-electrodes THV may pass through the first upper insulating film UL1, the second upper insulating film UL2, the third upper insulating film UL3, and the fourth upper insulating film UL4. Each of the plurality of through-electrodes THV may be connected to one upper wiring layer UML among the plurality of upper wiring layers UML via a contact plug 172 passing through the fifth upper insulating film UL5.

[0126] Even if a separate dam structure is not arranged around the through-electrode region TA1 in which the plurality of through-electrodes THV are arranged in order to ensure the insulation distance of the insulation structure, referring to Figures 1 to 11 The described semiconductor device 100 also has a structure that can ensure the structural stability of the insulating structure INS surrounding the multiple through-electrodes THV and ensure a stable insulation distance between the multiple through-electrodes THV and other conductive regions around the multiple through-electrodes THV. Therefore, in the process of manufacturing the semiconductor device 100 according to the above example embodiment, by omitting structures such as dam structures that may produce structural defects such as cracks, the area of the through-electrode area TA1 in which the multiple through-electrodes THV are arranged can be fully ensured, and a structure with improved integration can be provided. In addition, in the semiconductor device 100 including a plurality of memory cells arranged in three dimensions, even when the height of the cell array structure CAS in the vertical direction (Z direction) is increased due to an increase in the number of stacked gate lines 130 to improve integration, the cell array structure CAS can be alleviated or prevented from being tilted or collapsed, thereby suppressing process defects and improving reliability in the manufacturing process of the semiconductor device 100.

[0127] Figure 12A 、 Figure 12B and Figure 12C is a cross-sectional view illustrating a semiconductor device 200 according to an example embodiment. Figure 12A 、 Figure 12B and Figure 12C In, with Figures 1 to 11 The same reference numerals in the drawings respectively denote the same components, and here, repeated descriptions thereof are omitted.

[0128] Reference Figure 12A 、 Figure 12B and Figure 12C , the semiconductor device 200 has the same Figures 1 to 11 The semiconductor device 200 has substantially the same configuration as the semiconductor device 100 described above. However, the semiconductor device 200 may include a through-electrode region TA2. The through-electrode region TA2 may have the same configuration as the reference Figure 6B and Figures 9 to 11 The through-electrode region TA1 described above has substantially the same configuration. However, the through-electrode region TA2 may include a plurality of dummy conductive layers 130D2 between the word line cutting structure WLC and the insulating structure INS. Each of the plurality of dummy conductive layers 130D2 may be in contact with the word line cutting structure WLC adjacent thereto. The plurality of dummy conductive layers 130D2 may have the same configuration as that of the reference numerals. Figures 9 to 11 The plurality of dummy conductive layers 130D2 described above may have substantially the same configuration. The plurality of dummy conductive layers 130D2 may include a group of dummy conductive layers 130D2 that contact one word line cut structure WLC and are arranged in a row in the vertical direction (Z direction). The plurality of dummy conductive layers 130D2 included in the group of dummy conductive layers 130D2 may be separated from each other in the vertical direction (Z direction). In the group of dummy conductive layers 130D2, each of the plurality of dummy conductive layers 130D2 may be arranged at the same vertical level as the vertical level of a corresponding gate line 130 selected from the plurality of gate lines 130 arranged in the memory cell region MEC. The respective widths of the plurality of dummy conductive layers 130D2 included in the group of dummy conductive layers 130D2 in the second horizontal direction (Y direction) may vary depending on the respective positions of the plurality of dummy conductive layers 130D2 in the vertical direction (Z direction).

[0129] like Figure 12A As shown, in the first through-electrode portion TA21 of the through-electrode area TA2 arranged in the memory cell area MEC, the respective thicknesses of the group of dummy conductive layers 130D2 in the vertical direction (Z direction) may be equal to or similar to each other. In addition, in the first through-electrode portion TA21, the respective widths W21 of the group of dummy conductive layers 130D2 in the second horizontal direction (Y direction) may be equal to or similar to each other. In some example embodiments, the width W21 of each of the group of dummy conductive layers 130D2 in the second horizontal direction (Y direction) may be equal to or greater than approximately 1 / 2 of the pitch of the plurality of word line cutting structures WLC in the second horizontal direction (Y direction). In some example embodiments, when the plurality of separation cutting structures HLC are arranged in the memory cell block BLK, as Figure 4 and Figure 6CAs shown, the width W21 of each of the dummy conductive layers 130D2 in the second horizontal direction (Y direction) may be equal to or greater than about ½ of the pitch of the cutting structures in the second horizontal direction (Y direction), the cutting structures including the word line cutting structure WLC and the separation cutting structure HLC adjacent thereto. In the first through-electrode portion TA21, one of the two sidewalls of each of the plurality of dummy conductive layers 130D2 in the set of dummy conductive layers 130D2 in the second horizontal direction (Y direction) may be in contact with the word line cutting structure WLC, and the other sidewall may be in contact with the second insulating film 134.

[0130] like Figure 12B and Figure 12C As shown, in the second through-electrode portion TA22 and the third through-electrode portion TA23 arranged in the connection region CON, the upper dummy conductive layer 130D2 farthest from the peripheral circuit structure PCS in the vertical direction (Z direction) among the plurality of dummy conductive layers 130D2 in the group of dummy conductive layers 130D2 may have a greater thickness in the vertical direction (Z direction) than the other dummy conductive layers 130D2. Figure 12B In the second through-electrode portion TA22 shown, the first dummy conductive layer U21 arranged on the same vertical level as the second insulating film 134 contacting the lower surface of the third insulating film 134R among the multiple dummy conductive layers 130D2 in the group of dummy conductive layers 130D2 can extend longer than the other dummy conductive layers 130D2 in the second horizontal direction (Y direction) toward the through-electrode THV. The first dummy conductive layer U21 may include an end portion E21 in contact with the third insulating film 134R. The end portion E21 of the first dummy conductive layer U21 in contact with the third insulating film 134R may have a thickness greater than that of other portions of the first dummy conductive layer U21 in the vertical direction (Z direction). The width W22 of the dummy conductive layer 130D2 in the second horizontal direction (Y direction) that is closer to the peripheral circuit structure PCS than the first dummy conductive layer U21 among the multiple dummy conductive layers 130D2 may be equal to or similar to that arranged in the Figure 12A The dummy conductive layer 130D2 in the first through-electrode portion TA21 is shown to have a width W21 in the second horizontal direction (Y direction).

[0131] exist Figure 12CIn the third through-electrode portion TA23 shown, the upper dummy conductive layer U22, which is the farthest from the peripheral circuit structure PCS in the vertical direction (Z direction) among the plurality of dummy conductive layers 130D2 in the group of dummy conductive layers 130D2, may have a greater thickness in the vertical direction (Z direction) than the other dummy conductive layers 130D2. A portion of the upper dummy conductive layer U22 may extend toward the through-electrode THV in the second horizontal direction (Y direction) longer than the other dummy conductive layers 130D2. Figure 12C As shown, the end portion E22 of the upper dummy conductive layer U22 may overlap with the third insulating film 134R of the insulating structure INS in the vertical direction (Z direction), but the inventive concept is not limited thereto. The widths of the other dummy conductive layers 130D2 in the second horizontal direction (Y direction) other than the upper dummy conductive layer U22 may be equal to or similar to each other. The width W23 of the dummy conductive layer 130D2 in the second horizontal direction (Y direction) that is closer to the peripheral circuit structure PCS than the upper dummy conductive layer U22 among the plurality of dummy conductive layers 130D2 may be equal to or similar to the width W23 of the dummy conductive layer 130D2 arranged in the second horizontal direction (Y direction) Figure 12A The dummy conductive layer 130D2 in the first through-electrode portion TA21 shown has a width W21 in the second horizontal direction (Y direction). Among the plurality of dummy conductive layers 130D2, the dummy conductive layer 130D2 that is closer to the peripheral circuit structure PCS than the upper dummy conductive layer U22 may include a portion overlapping with the third insulating film 134R of the insulating structure INS in the vertical direction (Z direction), but the inventive concept is not limited thereto. A more detailed configuration of the group of dummy conductive layers 130D2 may be similar to that of FIG. Figures 9 to 11 The configurations of the described set of dummy conductive layers 130D are substantially the same.

[0132] Figure 13A and Figure 13B is a cross-sectional view illustrating a semiconductor device 300 according to an example embodiment. Figure 13A and Figure 13B In, with Figures 1 to 11 The same reference numerals in the drawings respectively denote the same components, and repeated descriptions thereof are omitted here.

[0133] Reference Figure 13A and Figure 13B , the semiconductor device 300 has the same Figures 1 to 11 The semiconductor device 300 has substantially the same configuration as the semiconductor device 100 described above. However, the semiconductor device 300 may include a through-electrode region TA3. The through-electrode region TA3 may have the same configuration as that of the reference numeral 100. Figure 6B and Figures 9 to 11The through-electrode region TA1 described above has substantially the same configuration. However, the through-electrode region TA3 may include a plurality of dummy conductive layers 130D3 between the word line cutting structure WLC and the insulating structure INS. Each of the plurality of dummy conductive layers 130D3 may be in contact with the word line cutting structure WLC adjacent thereto. The plurality of dummy conductive layers 130D3 may have the same configuration as that of the reference numerals. Figures 9 to 11 The plurality of dummy conductive layers 130D3 described above may have substantially the same configuration. The plurality of dummy conductive layers 130D3 may include a group of dummy conductive layers 130D3 that contact one word line cut structure WLC and are arranged in a row in the vertical direction (Z direction). The plurality of dummy conductive layers 130D3 included in the group of dummy conductive layers 130D3 may be separated from each other in the vertical direction (Z direction). In the group of dummy conductive layers 130D3, each of the plurality of dummy conductive layers 130D3 may be arranged at the same vertical level as a corresponding one of the plurality of gate lines 130 selected from the plurality of gate lines 130 arranged in the memory cell region MEC. The widths of the plurality of dummy conductive layers 130D3 included in the group of dummy conductive layers 130D3 in the second horizontal direction (Y direction) may vary with the thicknesses of the plurality of dummy conductive layers 130D3 in the vertical direction (Z direction).

[0134] like Figure 13A and Figure 13B As shown, in the second through-electrode portion TA32 and the third through-electrode portion TA33 arranged in the connection region CON, the upper dummy conductive layer U31 or U32, which is farthest from the peripheral circuit structure PCS among the plurality of dummy conductive layers 130D3 included in the group of dummy conductive layers 130D3 contacting one word line cutting structure WLC and arranged in a row in the vertical direction (Z direction), may have a thickness greater than that of the other dummy conductive layers 130D3 in the vertical direction (Z direction). In the second through-electrode portion TA32 and the third through-electrode portion TA33, the widths of the other dummy conductive layers 130D3, except for the upper dummy conductive layer U31 or U32, in the second horizontal direction (Y direction) may be equal to or similar to each other and may be smaller than the width of the upper dummy conductive layer U31 or U32 in the second horizontal direction (Y direction).

[0135] like Figure 13AAs shown, the separation distance G31 between the third insulating film 134R in the second through-electrode portion TA32 and the upper dummy conductive layer U31 in the group of dummy conductive layers 130D3 in the second horizontal direction (Y direction) may be smaller than the separation distance G32 between the third insulating film 134R and each of the other dummy conductive layers 130D3 in the group of dummy conductive layers 130D3 except the upper dummy conductive layer U31 in the second horizontal direction (Y direction).

[0136] like Figure 13B As shown, in the third through-electrode portion TA33, the widths of the plurality of dummy conductive layers 130D3 included in the set of dummy conductive layers 130D3 in the second horizontal direction (Y direction) may vary depending on the positions of the plurality of dummy conductive layers 130D3. For example, a portion of the upper dummy conductive layer U32, which is farthest from the peripheral circuit structure PCS in the vertical direction (Z direction) among the plurality of dummy conductive layers 130D3 in the set of dummy conductive layers 130D3, may extend longer than the other dummy conductive layers 130D3 in the second horizontal direction (Y direction) toward the through-electrode THV. An end portion E32 of the upper dummy conductive layer U32 may overlap with the third insulating film 134R of the insulating structure INS in the vertical direction (Z direction), but the inventive concept is not limited thereto.

[0137] like Figure 13B As shown, the separation distance G33 between the third insulating film 134R and a portion of the upper dummy conductive layer U32 in the group of dummy conductive layers 130D3 in the third through-electrode portion TA33 in the second horizontal direction (Y direction) may be smaller than the separation distance G34 between the third insulating film 134R and each of the other dummy conductive layers 130D3 in the group of dummy conductive layers 130D3 except the upper dummy conductive layer U32 in the second horizontal direction (Y direction).

[0138] The more detailed configuration of the dummy conductive layer 130D3 is shown in FIG. Figures 9 to 11 The configurations of the described set of dummy conductive layers 130D are substantially the same.

[0139] Figure 14A and Figure 14B is a cross-sectional view illustrating a semiconductor device 400 according to an example embodiment. Figure 14A and Figure 14B In, with Figures 1 to 13B The same reference numerals in the drawings denote the same components, respectively, and repeated descriptions thereof are omitted here.

[0140] Reference Figure 14A and Figure 14B , the semiconductor device 400 has the same Figure 13A and Figure 13BThe semiconductor device 300 has substantially the same configuration as described above. However, the semiconductor device 400 may include a through-electrode region TA4. The through-electrode region TA4 may have the same configuration as described above. Figure 6B and Figures 9 to 11 The through-electrode region TA1 described above has substantially the same configuration. However, the through-electrode region TA4 may include a plurality of dummy conductive layers 130D4 between the word line cutting structure WLC and the insulating structure INS. Each of the plurality of dummy conductive layers 130D4 may be in contact with the word line cutting structure WLC adjacent thereto. The plurality of dummy conductive layers 130D4 may have the same configuration as that of the reference numerals. Figures 9 to 11 The plurality of dummy conductive layers 130D4 described above may have substantially the same configuration. The plurality of dummy conductive layers 130D4 may include a group of dummy conductive layers 130D4 that contact one word line cut structure WLC and are arranged in a row in the vertical direction (Z direction). The plurality of dummy conductive layers 130D4 included in the group of dummy conductive layers 130D4 may be separated from each other in the vertical direction (Z direction). In the group of dummy conductive layers 130D4, each of the plurality of dummy conductive layers 130D4 may be arranged at the same vertical level as the vertical level of a corresponding gate line 130 selected from the plurality of gate lines 130 arranged in the memory cell region MEC. The widths of the plurality of dummy conductive layers 130D4 included in the group of dummy conductive layers 130D4 in the second horizontal direction (Y direction) may be substantially equal to or similar to each other.

[0141] like Figure 14A and Figure 14B As shown, in the second through-electrode portion TA42 and the third through-electrode portion TA43 of the through-electrode area TA4 arranged in the connection area CON, the upper dummy conductive layer 130D4 farthest from the peripheral circuit structure PCS among the multiple dummy conductive layers 130D4 in the group of dummy conductive layers 130D4 can have a greater thickness in the vertical direction (Z direction) than the other dummy conductive layers 130D4.

[0142] The semiconductor device 400 may further include an additional third insulating film 434R in the second through-electrode portion TA42 and the third through-electrode portion TA43 of the through-electrode region TA4 arranged in the connection region CON, the additional third insulating film 434R being in contact with the upper dummy conductive layer 130D4 in the group of dummy conductive layers 130D4. The additional third insulating film 434R may be arranged outside the local region where the third insulating film 134R pierced by the through-electrode THV in the vertical direction (Z direction) is arranged. The additional third insulating film 434R may be separated from the third insulating film 134R with an interlayer dielectric 138 therebetween. The additional third insulating film 434R may be separated from the plurality of through-electrodes THV in the second horizontal direction (Y direction). In the second horizontal direction (Y direction), the separation distance between the additional third insulating film 434R and the plurality of through-electrodes THV may be greater than the separation distance between the additional third insulating film 434R and the third insulating film 134R arranged in the local region. In the second horizontal direction (Y direction), the width of the additional third insulating film 434R can be smaller than the width of the third insulating film 134R arranged in the local area. The constituent material of the additional third insulating film 434R can be substantially the same as the constituent material of the third insulating film 134R arranged in the local area and described above. For example, the additional third insulating film 434R and the third insulating film 134R arranged in the local area can include the same material selected from a silicon nitride film and a hydrogenated silicon nitride film, and the silicon atom (Si) content ratio and the nitrogen atom (N) content ratio between the additional third insulating film 434R and the third insulating film 134R arranged in the local area can be equal. Here, the additional third insulating film 434R can be simply referred to as the third insulating film 434R.

[0143] The more detailed configurations of the set of dummy conductive layers 130D4 and the additional third insulating film 434R are respectively similar to those in FIG. Figures 9 to 11 The configurations of the described set of the dummy conductive layer 130D and the third insulating film 134R are substantially the same.

[0144] Figure 15A and Figure 15B is a cross-sectional view illustrating a semiconductor device 500 according to an example embodiment. Figure 15A and Figure 15B In, with Figures 1 to 11 The same reference numerals in the drawings respectively denote the same components, and repeated descriptions thereof are omitted here.

[0145] Reference Figure 15A and Figure 15B , the semiconductor device 500 has the same Figures 1 to 11The semiconductor device 100 has substantially the same configuration as described above. However, the second through-electrode portion TA52 and the third through-electrode portion TA53 of the through-electrode region TA5 arranged in the connection region CON in the semiconductor device 500 may include an insulating structure INS5. The upper surface of the insulating structure INS5 may have a varying height in the vertical direction (Z direction) along each of the first horizontal direction (X direction) and the second horizontal direction (Y direction).

[0146] In the through-electrode region TA5 of the semiconductor device 500, the third insulating film 134R may be separated from the through-electrode THV in the second horizontal direction (Y direction). The third insulating film 134R may be arranged in a region between the through-electrode THV and the word line cutting structure WLC. Figure 15A As shown, in the second through-electrode portion TA52 of the through-electrode area TA5, a local region of the insulating structure INS5 pierced by the plurality of through-electrodes THV in the vertical direction (Z direction) may have an upper surface corresponding to the upper surface US52 of the first insulating film 132, and the upper surface US52 of the first insulating film 132 may be in contact with the interlayer dielectric 138. In the second through-electrode portion TA52 of the through-electrode area TA5, a vertical level LV5A of the upper surface US52 of the first insulating film 132 corresponding to the local region of the insulating structure INS5 pierced by the through-electrode THV in the vertical direction (Z direction) may be closer to the peripheral circuit structure PCS than a vertical level LV5B of an upper surface 130DT of an upper portion of the plurality of dummy conductive layers 130D in the second through-electrode portion TA52 that is farthest from the peripheral circuit structure PCS.

[0147] like Figure 15B As shown, in the third through-electrode portion TA53 of the through-electrode area TA5, a local region of the insulating structure INS5 pierced by the plurality of through-electrodes THV in the vertical direction (Z direction) may have an upper surface corresponding to the upper surface US53 of the first insulating film 132, and the upper surface US53 of the first insulating film 132 may be in contact with the interlayer dielectric 138. In the third through-electrode portion TA53 of the through-electrode area TA5, a vertical level of the upper surface US53 of the first insulating film 132 corresponding to the local region of the insulating structure INS5 pierced by the through-electrode THV in the vertical direction (Z direction) may be equal to or similar to a vertical level LV5D of an upper surface 130DT of an upper portion of the plurality of dummy conductive layers 130D in the third through-electrode portion TA53, which is farthest from the peripheral circuit structure PCS.

[0148] The more detailed configurations of the second through-electrode portion TA52 and the third through-electrode portion TA53 are respectively referred to Figure 10 and Figure 11 Configurations of the second through-electrode portion TA12 and the third through-electrode portion TA13 of the described through-electrode area TA1 are substantially the same.

[0149] Figure 16 is a cross-sectional view illustrating a semiconductor device 500A according to an example embodiment. Figure 16 In, with Figures 1 to 15B The same reference numerals in the drawings respectively denote the same components, and repeated descriptions thereof are omitted here.

[0150] Reference Figure 16 , the semiconductor device 500A has the same Figures 1 to 11 The semiconductor device 100 has substantially the same configuration as described above. However, in the semiconductor device 500A, the second through-electrode portion TA52 of the through-electrode region TA5 arranged in the connection region CON may include an insulating structure INS5A. The insulating structure INS5A does not include the third insulating film 134R. The upper surface of the insulating structure INS5A may have a varying height in the vertical direction (Z direction) along each of the first horizontal direction (X direction) and the second horizontal direction (Y direction).

[0151] Local regions of the insulating structure INS5A pierced by the plurality of through electrodes THV in the vertical direction (Z direction) may have upper surfaces corresponding to the upper surface US52 of the first insulating film 132 , and the upper surface US52 of the first insulating film 132 may be in contact with the interlayer dielectric 138 .

[0152] Figure 17 is a plan view illustrating a semiconductor device 600 according to an example embodiment. Figure 17 In, with Figure 4 The same reference numerals in the drawings respectively denote the same components, and repeated descriptions thereof are omitted here.

[0153] Reference Figure 17 , the semiconductor device 600 has the same Figures 1 to 11 The semiconductor device 100 has substantially the same configuration as described above. However, the cell array structure CAS6 of the semiconductor device 600 may include a through electrode region TA6.

[0154] The through-electrode region TA6 may have a Figure 6B and Figures 9 to 11 The through-electrode region TA1 is described as having substantially the same configuration. However, in the second horizontal direction (Y direction), the width WT6 of the through-electrode region TA6 may be equal to or similar to the width of each of the plurality of memory cell blocks.

[0155] With reference Figures 1 to 11 The semiconductor device 100 is similar to that described in Figures 12A to 17 Each of the semiconductor devices 200, 300, 400, 500, 500A, and 600 described above has a structure that ensures the structural stability of the insulating structure INS, INS5, or INS5A surrounding the plurality of through-electrodes THVs, and ensures a stable insulation distance between the plurality of through-electrodes THVs and other conductive regions surrounding the plurality of through-electrodes THVs, even without a separate dam structure being arranged around the through-electrode region TA2, TA3, TA4, TA5, or TA6 in which the plurality of through-electrodes THVs are arranged. Therefore, in the process of manufacturing each of the semiconductor devices 200, 300, 400, 500, 500A, and 600 according to the above-described example embodiments, by omitting a structure such as a dam structure that may generate structural defects such as cracks, the area of the through-electrode region TA2, TA3, TA4, TA5, or TA6 in which the plurality of through-electrodes THVs are arranged can be sufficiently ensured, and a structure having the advantage of improved integration can be provided. In addition, in the semiconductor devices 200, 300, 400, 500, 500A and 600 each including a plurality of memory cells arranged in three dimensions, even when the height of the cell array structure CAS or CAS6 in the vertical direction (Z direction) is increased due to an increase in the number of stacked gate lines 130 to improve the integration, the cell array structure CAS or CAS6 can be prevented from tilting or collapsing, thereby suppressing process defects and improving the reliability of the manufacturing process of each of the semiconductor devices 200, 300, 400, 500, 500A and 600.

[0156] Figure 18 is a diagram schematically illustrating an electronic system including a semiconductor device according to example embodiments.

[0157] Reference Figure 18 An electronic system 1000B according to an embodiment may include a semiconductor device 1100 and a controller 1200 electrically connected to the semiconductor device 1100. The electronic system 1000B may include a storage device including one or more semiconductor devices 1100 or an electronic device including a storage device. For example, the electronic system 1000B may include a solid-state drive (SSD) device including at least one semiconductor device 1100, a universal serial bus (USB), a computing system, a medical device, or a communication device.

[0158] The semiconductor device 1100 may also include a non-volatile memory device. For example, the semiconductor device 1100 may include a NAND flash memory device including a reference Figures 1 to 17At least one of the characteristic structures of the semiconductor devices 100, 200, 300, 400, 500, 500A, and 600 described above. The semiconductor device 1100 may include a first structure 1100F and a second structure 1100S on the first structure 1100F. In some example embodiments, the first structure 1100F may be arranged next to the second structure 1100S. The first structure 1100F may include a peripheral circuit structure including a decoder circuit 1110, a page buffer 1120, and a logic circuit 1130. The second structure 1100S may include a memory cell structure including a bit line BL, a common source line CSL, a plurality of word lines WL, a first upper gate line UL1 and a second upper gate line UL2, a first lower gate line LL1 and a second lower gate line LL2, and a plurality of memory cell strings CSTR located between the bit line BL and the common source line CSL.

[0159] In the second structure 1100S, each of the plurality of memory cell strings CSTR may include lower transistors LT1 and LT2 adjacent to a common source line CSL, upper transistors UT1 and UT2 adjacent to a bit line BL, and a plurality of memory cell transistors MCT between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. The number of the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2 may be variously modified according to the embodiment.

[0160] In some example embodiments, the upper transistors UT1 and UT2 may include string selection transistors, and the lower transistors LT1 and LT2 may include ground selection transistors. A plurality of lower gate lines (i.e., LL1 and LL2) may be gate electrodes of the lower transistors LT1 and LT2, respectively. The word line WL may be a gate electrode of the memory cell transistor MCT, and a plurality of upper gate lines (i.e., UL1 and UL2) may be gate electrodes of the upper transistors UT1 and UT2, respectively.

[0161] The common source line CSL, the plurality of lower gate lines (i.e., LL1 and LL2), the plurality of word lines WL, and the plurality of upper gate lines (i.e., UL1 and UL2) may be electrically connected to the decoder circuit 1110 via the plurality of first connection wirings 1115 extending from the interior of the first structure 1100F to the second structure 1100S. The plurality of bit lines BL may be electrically connected to the page buffer 1120 via the plurality of second connection wirings 1125 extending from the interior of the first structure 1100F to the second structure 1100S.

[0162] In the first structure 1100F, the decoder circuit 1110 and the page buffer 1120 may perform a control operation on at least one of the plurality of memory cell transistors MCT. The decoder circuit 1110 and the page buffer 1120 may be controlled by a logic circuit 1130.

[0163] The semiconductor device 1100 may communicate with the controller 1200 via input / output pads 1101 electrically connected to the logic circuit 1130. The input / output pads 1101 may be electrically connected to the logic circuit 1130 via input / output connection wirings 1135 extending from the inside of the first structure 1100F to the second structure 1100S.

[0164] The controller 1200 may include a processor 1210 , a NAND controller 1220 , and a host interface 1230 . According to some example embodiments, the electronic system 1000B may include a plurality of semiconductor devices 1100 , in which case the controller 1200 may control the plurality of semiconductor devices 1100 .

[0165] Processor 1210 can control all operations of electronic system 1000B, including controller 1200. Processor 1210 can be operated by certain firmware and can access semiconductor device 1100 by controlling NAND controller 1220. NAND controller 1220 may include a NAND interface 1221 for handling communication with semiconductor device 1100. Control commands for controlling semiconductor device 1100, data intended to be written to the plurality of memory cell transistors MCT of semiconductor device 1100, data intended to be read from the plurality of memory cell transistors MCT, etc. can be transmitted via NAND interface 1221. Host interface 1230 can provide communication functionality between electronic system 1000B and an external host. When a control command is received from an external host via host interface 1230, processor 1210 can control semiconductor device 1100 in response to the control command.

[0166] Figure 19A is a perspective view schematically illustrating an electronic system including a semiconductor device according to example embodiments.

[0167] Reference Figure 19A , an electronic system 2000 according to an example embodiment may include a main substrate 2001, and a controller 2002, one or more semiconductor packages 2003, and a DRAM 2004 mounted on the main substrate 2001. The semiconductor package 2003 and the DRAM 2004 may be connected to the controller 2002 through a plurality of wiring patterns 2005 formed on the main substrate 2001.

[0168] The main substrate 2001 may include a connector 2006, which includes a plurality of pins to be connected to an external host. The number of pins in the connector 2006 and the arrangement of the plurality of pins may vary according to the communication interface between the electronic system 2000 and the external host. In some example embodiments, the electronic system 2000 may communicate with the external host according to one of the interfaces such as a universal serial bus (USB), a peripheral component interconnect high speed (PCI-Express), a serial advanced technology attachment (SATA), and M-Phy for universal flash storage (UFS). In some example embodiments, the electronic system 2000 may operate by power supplied from the external host via the connector 2006. The electronic system 2000 may further include a power management integrated circuit (PMIC) that can distribute the power supplied from the external host to the controller 2002 and the semiconductor package 2003.

[0169] The controller 2002 may write data to or read data from the semiconductor package 2003 and may increase the operating speed of the electronic system 2000 .

[0170] DRAM 2004 may be a buffer memory for alleviating the speed difference between an external host and semiconductor package 2003, which serves as a data storage space. DRAM 2004 in electronic system 2000 may operate as a cache memory and may provide a space for temporarily storing data during control operations of semiconductor package 2003. When DRAM 2004 is included in electronic system 2000, controller 2002 may further include a DRAM controller for controlling DRAM 2004 in addition to a NAND controller for controlling semiconductor package 2003.

[0171] The semiconductor package 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b that are separated from each other. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may be a semiconductor package including a plurality of semiconductor chips 2200. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may include a package substrate 2100, a plurality of semiconductor chips 2200 on the package substrate 2100, an adhesive layer 2300 on the lower surface of each of the plurality of semiconductor chips 2200, a connection structure 2400 that electrically connects the plurality of semiconductor chips 2200 to the package substrate 2100, and a mold layer 2500 disposed on the package substrate 2100 to cover the plurality of semiconductor chips 2200 and the connection structure 2400.

[0172] The package substrate 2100 may include a printed circuit board including a plurality of package pads 2130. Each of the plurality of semiconductor chips 2200 may include an input / output pad 2210. The input / output pad 2210 may correspond to Figure 18 Each of the plurality of semiconductor chips 2200 may include a plurality of gate stacks 3210 and a plurality of channel structures 3220. Each of the plurality of semiconductor chips 2200 may include a reference Figures 1 to 17 At least one of the features of the described semiconductor devices 100 , 200 , 300 , 400 , 500 , 500A, and 600 .

[0173] In some example embodiments, the connection structure 2400 may include bonding wires electrically connecting the input / output pads 2210 with the package on-pads 2130. Therefore, in the first semiconductor package 2003a and the second semiconductor package 2003b, the plurality of semiconductor chips 2200 may be electrically connected to each other in a bonding wire manner and may be electrically connected to the package on-pads 2130 of the package substrate 2100. In some example embodiments, in the first semiconductor package 2003a and the second semiconductor package 2003b, the plurality of semiconductor chips 2200 may be electrically connected to each other by a connection structure including through-silicon vias (TSVs) rather than by a bonding wire-type connection structure 2400.

[0174] In some example embodiments, the controller 2002 and the plurality of semiconductor chips 2200 may be included in one package. In some example embodiments, the controller 2002 and the plurality of semiconductor chips 2200 may be mounted on a separate interposer substrate different from the main substrate 2001 and may be connected to each other via wiring formed on the interposer substrate.

[0175] Figure 19B It is along Figure 19A The cross-sectional view taken along line II' is conceptually shown. Figure 19A The semiconductor package 2003 is shown in FIG.

[0176] Reference Figure 19B In the semiconductor package 2003 , the plurality of semiconductor chips 2200 a may each include a semiconductor substrate 4010 , a first structure 4100 on the semiconductor substrate 4010 , and a second structure 4200 arranged on the first structure 4100 and bonded to the first structure 4100 in a wafer bonding manner.

[0177] The first structure 4100 may include a peripheral circuit region including a peripheral wiring 4110 and a first bonding structure 4150. The second structure 4200 may include a common source line 4205, a gate stack structure 4210 between the common source line 4205 and the first structure 4100, a memory channel structure 4220 and a separation structure 4230 each passing through the gate stack structure 4210, and word lines (i.e., word lines) electrically connected to the memory channel structure 4220 and the gate stack structure 4210, respectively. Figure 1 For example, the second bonding structure 4250 may be electrically connected to the bit line 4240 of the memory channel structure 4220 and electrically connected to the word line (ie, Figure 1 The gate connection wiring of WL) is electrically connected to the memory channel structure 4220 and the word line (that is, Figure 1 The first bonding structures 4150 of the first structure 4100 may be in contact with and bonded to the second bonding structures 4250 of the second structure 4200, respectively. Bonding portions of the first bonding structures 4150 and the second bonding structures 4250 may include, for example, copper (Cu).

[0178] The second structure 4200 may include reference Figures 1 to 17 At least one of the features of the semiconductor devices 100, 200, 300, 400, 500, 500A, and 600 described above. Each semiconductor chip 2200a may further include an input / output pad 2210 and an input / output connection wiring 4265 below the input / output pad 2210. The input / output connection wiring 4265 may be electrically connected to some of the second bonding structures 4250.

[0179] The semiconductor chips 2200a may be electrically connected to each other through a bonding wire type connection structure 2400. In some example embodiments, semiconductor chips in the same semiconductor package, such as the semiconductor chip 2200a, may be electrically connected to each other through a connection structure including TSVs.

[0180] Next, a method of manufacturing a semiconductor device according to example embodiments is described in detail.

[0181] 20A to 32D is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to an example embodiment. More specifically, Figure 20A 、 Figure 21A 、 Figure 22A 、 Figure 23 、 Figure 24A 、 Figure 25A 、 Figure 26 、 Figure 27A 、 Figure 28A 、 Figure 29 、 Figure 31A and Figure 32A It shows the process sequence and the Figure 6A A cross-sectional view of some components of the region corresponding to the cross section taken along the line X1-X1', Figure 20B 、 Figure 21B 、 Figure 22B 、 Figure 25B and Figure 28B It shows the process sequence and the Figure 6A A cross-sectional view of some components of the region corresponding to the cross-section taken along the line Y1-Y1', Figure 24B 、 Figure 27B 、 Figure 28C 、 Figure 30A 、 Figure 31B and Figure 32B It shows the process sequence and the Figure 6B A cross-sectional view of some components of the region corresponding to the cross section taken along the line Y2-Y2', Figure 24C 、 Figure 27C 、 Figure 28D 、 Figure 30B 、 Figure 31C and Figure 32C It shows the process sequence and the Figure 6B A cross-sectional view of some components of the region corresponding to the cross section taken along the line Y3-Y3', Figure 24D 、 Figure 27D 、 Figure 28E 、 Figure 30C 、 Figure 31D and Figure 32D It shows the process sequence and the Figure 6B The cross-sectional view of some components of the region corresponding to the cross-sectional view taken along the line Y4-Y4' is shown. 20A to 32D Describes the reference Figures 1 to 11 An example of a method of manufacturing the semiconductor device 100 is described.

[0182] Reference Figure 20A and Figure 20B , a peripheral circuit structure PCS including a substrate 52, a plurality of transistors TR, a multilayer wiring structure MWS, a plurality of conductive landing pads LP, and an interlayer dielectric 70 may be formed. Each of the plurality of conductive landing pads LP may be arranged with a memory cell contact MCC or a through electrode THV (see Figure 7 、 Figure 9 、 Figure 10 and Figure 11 The interlayer dielectric 70 may be formed to cover the plurality of wiring layers ML62 at the uppermost position among the plurality of wiring layers ML60, ML61, and ML62.

[0183] Reference Figure 21A and Figure 21B, you can Figure 20A and Figure 20B A plate common source line 110 is formed on the resultant product, and an insulating plate 112 and a second conductive plate 118 may be formed in the stated order to cover the plate common source line 110. The insulating plate 112 may include an insulating film of a multi-layer structure including a first insulating film 112A, a second insulating film 112B, and a third insulating film 112C.

[0184] Next, if Figure 21A As shown, a plurality of third through openings 120H may be formed in a portion of the connection region CON to pass through the plate common source line 110, the insulating plate 112, and the second conductive plate 118, and a plurality of insulating plugs 120 may be formed to fill the plurality of third through openings 120H, respectively. Here, Figures 9 to 11 The plurality of insulating plugs 120 shown may also be used with Figure 21A The formation of the plurality of insulating plugs 120 shown is performed simultaneously.

[0185] Reference Figure 22A and Figure 22B In the memory cell region MEC and the connection region CON, a plurality of first insulating films 132 and a plurality of second insulating films 134 may be alternately stacked one after another on the second conductive plate 118 and the insulating plug 120. The plurality of first insulating films 132 may each include a silicon oxide film, and the plurality of second insulating films 134 may each include a silicon nitride film or a hydrogenated silicon nitride film. Some of the plurality of second insulating films 134 may be used to ensure that the film is used to form a silicon nitride film in a subsequent process. Figure 7 and Figure 8 In the subsequent process, some other insulating films in the plurality of second insulating films 134 may be used to form Figures 9 to 11 A portion of the insulating structure INS is shown extending through the electrode area TA1 .

[0186] Reference Figure 23 , having experienced the reference Figure 22A and Figure 22B In the resulting product of the described process, an etching stop film 136 may be formed to cover the uppermost first insulating film 132 among the plurality of first insulating films 132, and then a portion of each of the plurality of first insulating films 132 and the plurality of second insulating films 134 in the connection region CON may be removed by a photolithography process, thereby forming a stepped structure ST in which an end portion of each of the plurality of first insulating films 132 and the plurality of second insulating films 134 has a gradually decreasing width in the horizontal direction as it moves away from the plate common source line 110.

[0187] Reference Figure 24A 、 Figure 24B 、 Figure 24C and Figure 24D , having experienced the use Figure 23 In a resultant product of the described process, the third insulating film 134R may be formed on the end portion of each of the plurality of second insulating films 134 constituting the stepped structure ST.

[0188] Although Figure 24A The third insulating films 134R are shown as being respectively formed on the end portions of some of the second insulating films 134 among the plurality of second insulating films 134, but Figure 24A The second insulating film 134 not covered by the third insulating film 134R among the plurality of second insulating films 134 shown may have Figure 24A Another portion not shown in the figure but covered by the third insulating film 134R.

[0189] In some example embodiments, in order to form the third insulating film 134R on the end portion of each of the plurality of second insulating films 134, a preliminary third insulating film may be formed to cover the end portion of the second insulating film 134R. Figure 23 The entire surface of the resulting product of the described process can then be freed from unnecessary portions of the preliminary third insulating film.

[0190] In some example embodiments, reference Figure 22A and Figure 22B The process of forming the second insulating film 134 described and referring to Figure 24A 、 Figure 24B 、 Figure 24C and Figure 24D The described process of forming the preliminary third insulating film (the preliminary third insulating film is required to form the third insulating film 134R) may be performed through an atomic layer deposition (ALD) process or a plasma enhanced chemical vapor deposition (PECVD) process.

[0191] For example, to form the second insulating film 134 and the preliminary third insulating film, a silicon nitride film or a hydrogenated silicon nitride film may be formed in a plasma atmosphere using SiH4 or Si2H6 as a silicon atom (Si) source gas and using NH3 or N2 as a nitrogen atom (N) source gas. In some example embodiments, while performing the process of forming each of the second insulating film 134 and the preliminary third insulating film, when the flow rate of the silicon atom (Si) source gas is relatively increased, the silicon atom (Si) content ratio in the resulting second insulating film 134 or the preliminary third insulating film may be relatively increased, and when the flow rate of the nitrogen atom (N) source gas is relatively increased, the nitrogen atom (N) content ratio and / or the hydrogen atom (H) content ratio in the resulting second insulating film 134 or the preliminary third insulating film may be relatively increased depending on the type of the nitrogen atom (N) source gas. For each of the second insulating film 134 and the third insulating film 134R obtained from the preliminary third insulating film, the etching rate in a wet etching solution (e.g., a phosphoric acid solution) may decrease as the content ratio of silicon atoms (Si) increases, and the etching rate in the wet etching solution (e.g., a phosphoric acid solution) may increase as the content ratio of nitrogen atoms (N) and the content ratio of hydrogen atoms (H) increase. In some example embodiments, when power having a relatively low frequency (e.g., approximately 380 kHz) is applied to the inside of a reaction chamber for performing a process for forming each of the second insulating film 134 and the preliminary third insulating film, the etching rate of the second insulating film 134 or the third insulating film 134R corresponding to the resulting product in a wet etching solution (e.g., a phosphoric acid solution) may decrease compared to a case where power having a relatively high frequency (e.g., approximately 13.56 MHz) is applied. As described above, by controlling the flow rate of silicon atom (Si) source gas and / or nitrogen atom (N) source gas, or by controlling the frequency of power applied during the deposition process, each of the second insulating film 134 and the third insulating film 134R can be formed so that each of the second insulating film 134 and the third insulating film 134R has an expected etching rate in a wet etching solution (e.g., a phosphoric acid solution).

[0192] In this way, by controlling the amount of each of the second insulating film 134 and the third insulating film 134R to be removed in the subsequent process as much as the expected amount when each of the second insulating film 134 and the third insulating film 134R is removed, the amount remaining can be determined. Figures 9 to 11 The respective amounts of the second insulating film 134 and the third insulating film 134R in the insulating structure INS through the electrode area TA1 are shown.

[0193] As described above, the interlayer dielectric 138 may be formed to cover the resultant product in which the third insulating film 134R is formed on the end portion of each of the plurality of second insulating films 134. During the formation of the interlayer dielectric 138, the etch stopper film 136 may be removed by performing a chemical mechanical polishing (CMP) process for planarizing the upper surface of the interlayer dielectric 138. As a result, the uppermost first insulating film 132 among the plurality of first insulating films 132 may be exposed around the interlayer dielectric 138. Next, the first upper insulating film UL1 may be formed to cover the upper surfaces of the uppermost first insulating film 132 and each of the interlayer dielectrics 138.

[0194] Reference Figure 25A and Figure 25B , a plurality of channel structures 140 and a plurality of dummy channel structures D140 can be formed, the plurality of channel structures 140 longitudinally extending in the vertical direction (Z direction) through the first upper insulating film UL1, the plurality of first insulating films 132 and the plurality of second insulating films 134 in the memory cell region MEC, and the plurality of dummy channel structures D140 longitudinally extending in the vertical direction (Z direction) through the first upper insulating film UL1, the plurality of first insulating films 132, the plurality of second insulating films 134 and the interlayer dielectric 138 in the connection region CON.

[0195] Reference Figure 26 , you can refer to Figure 25A and Figure 25B A second upper insulating film UL2 is formed on the resultant product of the described process, and then a plurality of vertical holes H1 may be formed in the connection region CON of the memory cell block. A conductive landing pad LP of the peripheral circuit structure PCS may be exposed at a lower surface of each of the plurality of vertical holes H1.

[0196] Each of the plurality of vertical holes H1 may pass through the second upper insulating film UL2, the first upper insulating film UL1, the interlayer dielectric 138, one third insulating film 134R, the plurality of second insulating films 134, the plurality of first insulating films 132, the insulating plug 120, and a portion of the interlayer dielectric 70 of the peripheral circuit structure PCS in the vertical direction (Z direction).

[0197] Next, the horizontal width of each of the plurality of vertical holes H1 can be expanded by etching portions of the second insulating film 134 and the third insulating film 134R exposed in each of the plurality of vertical holes H1, thereby forming a plurality of indented spaces ID. In some of the plurality of indented spaces ID, only the third insulating film 134R and the second insulating film 134 can be exposed, and in some other of the plurality of indented spaces ID, both the second insulating film 134 and the third insulating film 134R can be exposed.

[0198] Reference Figure 27A 、 Figure 27B 、 Figure 27C and Figure 27D , after performing the process described with reference to FIG. 6 , as Figure 27A As shown, among the plurality of indented spaces ID of each of the plurality of vertical holes H1 in the connection region CON connected to the memory cell block, the indented space ID exposing the second insulating film 134 may be filled with an insulating ring 152, and the indented space ID exposing both the second insulating film 134 and the third insulating film 134R may be filled with a sacrificial insulating ring 154. The insulating ring 152 may include a silicon oxide film. The sacrificial insulating ring 154 may include the same material as the second insulating film 134.

[0199] In some example embodiments, a process may be performed such that an insulating ring 152 is first formed in the indentation ID of the second insulating film 134 in each of the plurality of vertical holes H1, and then a sacrificial insulating ring 154 is formed in the indentation ID that exposes both the second insulating film 134 and the third insulating film 134R in each of the plurality of vertical holes H1. In some example embodiments, an etch-stop insulating liner (not shown) may be disposed between the second insulating film 134 and the insulating ring 152. The etch-stop insulating liner may include a silicon nitride film.

[0200] Next, the inside of each of the plurality of vertical holes H1 may be filled with insulating spacers 156 and sacrificial plugs 158. In some example embodiments, the insulating spacers 156 may include silicon oxide, and the sacrificial plugs 158 may include polysilicon, but the inventive concept is not limited thereto.

[0201] like Figure 27B 、 Figure 27C and Figure 27D As shown, in the area where the through-electrode area TA1 is to be formed, according to the position of the area, a plurality of vertical holes H2 can be formed to selectively pass through the second upper insulating film UL2, the first upper insulating film UL1, the interlayer dielectric 138, the third insulating film 134R, the plurality of second insulating films 134, the plurality of first insulating films 132, the insulating plug 120, and a portion of the interlayer dielectric 70 of the peripheral circuit structure PCS in the vertical direction (Z direction), and then, the interior of each of the plurality of vertical holes H2 can be filled with an insulating spacer 156 and a sacrificial plug 158.

[0202] In some example embodiments, as shown in FIG. Figure 26 and Figure 27AThe process of forming a plurality of vertical holes H1 in the connection area CON of the memory cell block and forming insulating spacers 156 and sacrificial plugs 158 to fill the interiors of the plurality of vertical holes H1, the process of forming a plurality of vertical holes H2 in the area where the through-electrode area TA1 is to be formed and forming insulating spacers 156 and sacrificial plugs 158 to fill the interiors of the plurality of vertical holes H2 can be performed simultaneously, or can be performed separately from each other and sequentially.

[0203] Reference Figure 28A 、 Figure 28B 、 Figure 28C 、 Figure 28D and Figure 28E , a third upper insulating film UL3 may be formed to cover upper surfaces of the plurality of insulating spacers 156 , the plurality of sacrificial plugs 158 , and the second upper insulating film UL2 in the memory cell region MEC and the connection region CON.

[0204] In the resulting product in which the third upper insulating film UL3 is formed, a hole SH can be formed by etching the third upper insulating film UL3, the second upper insulating film UL2, the first upper insulating film UL1, some of the multiple first insulating films 132 and some of the multiple second insulating films 134 in the memory cell area MEC, and a string selection line cutting structure SSLC can be formed to fill the hole SH.

[0205] A plurality of word line cutting holes WCH may be formed through the third upper insulating film UL3, the second upper insulating film UL2, the first upper insulating film UL1, the interlayer dielectric 138, the plurality of first insulating films 132, the plurality of second insulating films 134, the second conductive plate 118, and the insulating plate 112 in the memory cell region MEC and the connection region CON to expose the plate common source line 110.

[0206] Only in the memory cell region MEC and the connection region CON, the insulating plate 112 may be selectively removed through the inner space of each of the plurality of word line cut holes WCH, and the resulting empty space may be filled with the first conductive plate 114. When the insulating plate 112 in the memory cell region MEC is removed, a portion of the gate dielectric film 142 of the channel structure 140 in the memory cell region MEC, which is adjacent to the insulating plate 112, may be removed together with the insulating plate 112. As a result, the first conductive plate 114 may pass through a portion of the gate dielectric film 142 in the horizontal direction and contact the channel region 144.

[0207] In the memory cell region MEC and the connection region CON, the plurality of second insulating films 134, the third insulating films 134R, and the sacrificial insulating rings 154 may be replaced with the plurality of gate lines 130 through the inner space of each of the plurality of word line cutting holes WCH. In each of the plurality of gate lines 130, a relatively thick end portion obtained by replacing the sacrificial insulating ring 154 and both the second insulating film 134 and the third insulating film 134R in contact with the sacrificial insulating ring 154 may constitute the gate pad portion 130A.

[0208] After forming the first conductive plate 114 and the plurality of gate lines 130, the plurality of word line cutting holes WCH may be filled with the plurality of word line cutting structures WLC. The width of each of the memory cell block and the through electrode region TA1 in the second horizontal direction (Y direction) may be determined by the plurality of word line cutting structures WLC.

[0209] In the memory cell region MEC and the connection region CON, the plurality of second insulating films 134 and the third insulating films 134R are replaced by the plurality of gate lines 130 through the inner space of each of the plurality of word line cutting holes WCH, and at the same time, a portion of each of the plurality of second insulating films 134 and the third insulating films 134R in the through-electrode region TA1 may be replaced by a conductive layer, thereby forming a plurality of dummy conductive layers 130D in the through-electrode region TA1. Figure 24A 、 Figure 24B 、 Figure 24C and Figure 24D As described above, while forming each of the second insulating film 134 and the preliminary third insulating film for forming the third insulating film 134R, the etching rate of each of the second insulating film 134 and the third insulating film 134R in the wet etching solution (e.g., phosphoric acid solution) can be controlled by controlling various process conditions. Thus, the widths of the plurality of dummy conductive layers 130D in the second horizontal direction (Y direction) are determined, as shown in FIG. Figure 28C 、 Figure 28D and Figure 28E Each of the shown.

[0210] Reference Figure 29 In the connection region CON of the memory cell block, a hole PH may be formed through the third upper insulating film UL3, the second upper insulating film UL2, the first upper insulating film UL1, the interlayer dielectric 138, the second conductive plate 118, and the insulating plate 112 to expose the plate common source line 110, and then, an insulating spacer 162 and a conductive plate contact 164 may be sequentially formed in the hole PH in the stated order.

[0211] Reference Figure 30A 、 Figure 30B and Figure 30C , you can refer to Figure 29A fourth upper insulating film UL4 is formed on the resultant product of the described process, and then a portion of each of the fourth upper insulating film UL4 and the third upper insulating film UL3 is removed, thereby exposing the insulating spacers 156 and the sacrificial plugs 158. Next, the plurality of vertical holes H1 can be emptied by removing the exposed insulating spacers 156 and the sacrificial plugs 158 (see FIG. Figure 29 ) and the inside of each of the multiple vertical holes H2.

[0212] Reference Figure 31A 、 Figure 31B 、 Figure 31C and Figure 31D ,exist Figure 30A 、 Figure 30B and Figure 30C In the resulting product, the length of each of the multiple vertical holes H1 and H2 in the vertical direction (Z direction) can be increased by etching the conductive landing pad LP exposed at the lower surface of each of the multiple vertical holes H1 and H2, and the wiring layer ML62 of the multi-layer wiring structure MWS of the peripheral circuit structure PCS can be exposed at the lower surface of each of the multiple vertical holes H1 and H2.

[0213] Reference Figure 32A 、 Figure 32B 、 Figure 32C and Figure 32D , a plurality of memory cell contacts MCC respectively filling the plurality of vertical holes H1 in the connection region CON of the memory cell block and a plurality of through electrodes THV respectively filling the plurality of vertical holes H2 in the through electrode region TA1 may be formed.

[0214] In reference Figures 30A to 32D In the described process, in the through-electrode area TA1, the process of removing the insulating spacer 156 and the sacrificial plug 158 in each of the plurality of vertical holes H1 and forming a plurality of memory cell contacts MCC respectively in the plurality of vertical holes H1 in the connection area CON of the memory cell block, and the process of removing the insulating spacer 156 and the sacrificial plug 158 in each of the plurality of vertical holes H2 and forming a plurality of through-electrodes THV respectively filling the plurality of vertical holes H2 can be performed simultaneously or can be performed sequentially.

[0215] Next, if Figures 7 to 11 As shown, it can be Figure 32A 、 Figure 32B 、 Figure 32C and Figure 32DA fifth upper insulating film UL5 is formed on the resulting product, and contact plugs 172 can be formed that pass through the fifth upper insulating film UL5 and the fourth upper insulating film UL4 in the connection area CON of the memory cell block and are connected to the conductive plate contact 164, a plurality of contact plugs 176 that pass through the fifth upper insulating film UL5, the fourth upper insulating film UL4 and the third upper insulating film UL3 in the memory cell area MEC and are respectively connected to the drain regions 148 of the plurality of channel structures 140, and a plurality of contact plugs 172 that pass through the fifth upper insulating film UL5 in the through-electrode area TA1 and are respectively connected to the through-electrodes THV.

[0216] Next, a plurality of upper wiring layers UML may be formed on the fifth upper insulating film UL5 in the connection region CON of the memory cell block, and a plurality of bit lines BL may be formed on the fifth upper insulating film UL5 in the memory cell region MEC. In addition, a sixth upper insulating film UL6 may be formed to fill spaces between adjacent upper wiring layers in the plurality of upper wiring layers UML and spaces between adjacent bit lines in the plurality of bit lines BL.

[0217] Although reference has been 20A to 32D Describes the reference Figures 1 to 11 The method for manufacturing the semiconductor device 100 is described, but those skilled in the art will understand that by making reference to the present invention without departing from the spirit and scope of the inventive concept, 20A to 32D Various modifications and variations of the described methods may be made with reference to Figures 12A to 17 The described integrated circuit devices 200 , 300 , 400 , 500 , 500A, and 600 and semiconductor devices having various structures modified and changed therefrom.

[0218] For example, to create a reference Figures 12A to 14B The semiconductor devices 200, 300 and 400 described above can be manufactured by referring to Figure 24A 、 Figure 24B 、 Figure 24C and Figure 24D When the process of forming each of the second insulating film 134 and the preliminary third insulating film for forming the third insulating film 134R is performed as described, various process conditions are controlled to control the etching rate of each of the second insulating film 134 and the third insulating film 134R in the wet etching solution, thereby forming Figures 12A to 14B A plurality of dummy conductive layers 130D2 , 130D3 , and 130D4 are shown having various widths in the second horizontal direction (Y direction).

[0219] To create a reference Figure 15A and Figure 15B The semiconductor device 500 described in reference Figure 24A 、 Figure 24B 、 Figure 24Cand Figure 24D In the process described above, the third insulating film 134R may be formed in a local area of the through-electrode region TA1 where a plurality of through-electrodes THV are arranged, and then a portion of the third insulating film 134R may be removed from the local area. Here, a portion of the second insulating film 134 exposed by removing the third insulating film 134R may also be removed. Next, the process may be performed with reference to 25A to 32D The process described thereby makes reference Figure 15A and Figure 15B A semiconductor device 500 is described.

[0220] To create a reference Figure 16 The semiconductor device 500A described above can be used with reference to Figure 15A and Figure 15B The method described is similar to the process of manufacturing the semiconductor device 500. However, in order to manufacture the semiconductor device 500A, in reference to Figure 24A 、 Figure 24B 、 Figure 24C and Figure 24D In the process described above, the third insulating film 134R in the local area of the through-electrode region TA1 where the plurality of through-electrodes THV are arranged can be completely removed. Here, a portion of the second insulating film 134 exposed by removing the third insulating film 134R can also be removed together. 25A to 32D The process described thereby makes reference Figure 16 A semiconductor device 500A is described.

[0221] According to the reference 20A to 32D According to some example embodiments, even if a separate dam structure is not arranged around the through-electrode region TA1 in which the plurality of through-electrodes THV are arranged to ensure the insulation distance of the insulation structure, in the method of manufacturing a semiconductor device as described with reference to FIG. Figure 24A 、 Figure 24B 、 Figure 24C and Figure 24DWhen performing the process of forming each of the second insulating film 134 and the preliminary third insulating film for forming the third insulating film 134R as described above, the etching rate of each of the second insulating film 134 and the third insulating film 134R in the wet etching solution can be controlled by controlling various process conditions, thereby ensuring the structural stability of the insulating structure INS surrounding the plurality of through-hole electrodes THV in the through-electrode area TA1. Therefore, according to the method of manufacturing a semiconductor device, according to some example embodiments, the manufacturing process of the semiconductor device can be simplified, and the area of the through-electrode area TA1 in which the plurality of through-electrodes THV are arranged can be sufficiently ensured, thereby providing a structure with the advantage of increased integration. In addition, in a semiconductor device including a plurality of memory cells arranged in a three-dimensional manner, even when the height of the cell array structure CAS in the vertical direction (Z direction) is increased due to an increase in the number of stacked gate lines 130 to improve integration, the cell array structure CAS can be reduced or prevented from being tilted or collapsed, thereby suppressing process defects and improving reliability in the manufacturing process of the semiconductor device.

[0222] Any functional blocks shown in the figures and described above may be implemented in a processing circuit (such as hardware including logic circuits, a hardware / software combination such as a processor executing software, or a combination thereof). For example, the processing circuit may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc.

[0223] While the inventive concept has been particularly shown and described with reference to certain example embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims.

[0224] CROSS-REFERENCE TO RELATED APPLICATIONS

[0225] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2024-0018416 filed in the Korean Intellectual Property Office on February 6, 2024, the disclosure of which is incorporated herein in its entirety by reference.

Claims

1. A semiconductor device comprising: a peripheral circuit structure comprising a circuit substrate and a plurality of circuits on the circuit substrate; as well as penetrating the electrode region and overlapping with the peripheral circuit structure in the vertical direction, Wherein, the through-electrode region includes: an insulating structure including a plurality of first insulating films and a plurality of second insulating films, the insulating structure having an upper surface having a height varying in each of a first horizontal direction and a second horizontal direction perpendicular to the first horizontal direction, the plurality of first insulating films and the plurality of second insulating films including materials different from each other and being alternately stacked one after another in the vertical direction, an interlayer dielectric covering the upper surface of the insulating structure, and A plurality of through electrodes penetrate the insulating structure and the interlayer dielectric in the vertical direction in a local region of the through electrode region, each of the plurality of through electrodes being configured to be connected to one circuit selected from the plurality of circuits of the peripheral circuit structure.

2. The semiconductor device according to claim 1, further comprising: a word line cutting structure, located on one side of the through-electrode region in the second horizontal direction; as well as a plurality of dummy conductive layers, in the through-electrode region between the word line cutting structure and the insulating structure, the plurality of dummy conductive layers being separated from each other in the vertical direction; The vertical level of the upper surface of the insulating structure in the local area of the through-electrode area is closer to the peripheral circuit structure than the vertical level of the upper surface of the dummy conductive layer farthest from the peripheral circuit structure among the multiple dummy conductive layers.

3. The semiconductor device according to claim 1 , further comprising: a word line cutting structure, located on one side of the through-electrode region in the second horizontal direction; as well as a plurality of dummy conductive layers, in the through-electrode region between the word line cutting structure and the insulating structure, the plurality of dummy conductive layers being separated from each other in the vertical direction; The vertical level of the upper surface of the insulating structure in the local area of the through-electrode area is farther away from the peripheral circuit structure than the vertical level of the upper surface of the dummy conductive layer farthest from the peripheral circuit structure among the multiple dummy conductive layers. The semiconductor device according to claim 1 , wherein The insulating structure further includes a plurality of third insulating films, the plurality of third insulating films contacting an upper second insulating film adjacent to the interlayer dielectric among the plurality of second insulating films in a portion of the through-electrode region, each of the plurality of first insulating films includes a silicon oxide film, each of the plurality of second insulating films and the plurality of third insulating films includes a silicon nitride film or a hydrogenated silicon nitride film, At least one of the first condition that the content ratio of silicon atoms (Si) in each of the multiple third insulating films is less than the content ratio of silicon atoms (Si) in each of the multiple second insulating films, the second condition that the content ratio of nitrogen atoms (N) in each of the multiple third insulating films is greater than the content ratio of nitrogen atoms (N) in each of the multiple second insulating films, or the third condition that the content ratio of hydrogen atoms (H) in each of the multiple third insulating films is greater than the content ratio of hydrogen atoms (H) in each of the multiple second insulating films is satisfied. The semiconductor device according to claim 1 , wherein The insulating structure further includes a third insulating film arranged in the local area of the through-electrode region, the third insulating film includes a constituent material different from a constituent material of each of the plurality of first insulating films and a constituent material of each of the plurality of second insulating films, At least one through-electrode selected from the plurality of through-electrodes passes through the third insulating film in the vertical direction.

6. The semiconductor device according to claim 1, further comprising: a plurality of memory cell blocks overlapping the peripheral circuit structure in the vertical direction, the plurality of memory cell blocks extending longitudinally in the first horizontal direction, Each of the plurality of memory cell blocks includes a memory cell region and a connection region, the memory cell region including a plurality of gate lines and a plurality of vertical channel structures passing through the plurality of gate lines in the vertical direction, the connection region being arranged on one side of the memory cell region and including an edge portion of each of the plurality of gate lines, the through-electrode region includes a first through-electrode portion facing the memory cell region in the second horizontal direction, a second through-electrode portion facing the connection region in the second horizontal direction and arranged at a first position in the through-electrode region, and a third through-electrode portion facing the connection region in the second horizontal direction and arranged at a second position in the through-electrode region, In each of the second through-electrode portion and the third through-electrode portion, the insulating structure further includes a third insulating film contacting an upper second insulating film adjacent to the interlayer dielectric among the plurality of second insulating films, and The third insulating film of the second through-electrode portion and the third insulating film of the third through-electrode portion are respectively at different vertical levels.

7. A semiconductor device comprising: a peripheral circuit structure comprising a circuit substrate and a plurality of circuits on the circuit substrate; a plurality of memory cell blocks, each of the plurality of memory cell blocks overlapping the peripheral circuit structure in a vertical direction, each of the plurality of memory cell blocks extending longitudinally in a first horizontal direction; as well as a through-electrode region overlapping with the peripheral circuit structure in the vertical direction, the through-electrode region being located between two adjacent memory cell blocks selected from the plurality of memory cell blocks, Wherein, the through-electrode region includes: an insulating structure including a plurality of first insulating films and a plurality of second insulating films, the insulating structure having an upper surface having a height varying in the vertical direction along each of the first horizontal direction and a second horizontal direction perpendicular to the first horizontal direction, the plurality of first insulating films and the plurality of second insulating films including materials different from each other and being alternately stacked one after another in the vertical direction; an interlayer dielectric covering the upper surface of the insulating structure; and A plurality of through electrodes penetrate the insulating structure and the interlayer dielectric in the vertical direction in a local region of the through electrode region, each of the plurality of through electrodes being configured to be connected to one circuit selected from the plurality of circuits of the peripheral circuit structure.

8. The semiconductor device according to claim 7, further comprising: a plurality of word line cutting structures arranged one by one on both sides of each of the plurality of memory cell blocks in the second horizontal direction to define a width of each of the plurality of memory cell blocks in the second horizontal direction, The width of the through-electrode region in the second horizontal direction is defined by a pair of word line cutting structures, the pair of word line cutting structures being adjacent to each other and selected from the plurality of word line cutting structures, and The through-electrode region further includes a plurality of dummy conductive layers located between the insulating structure and at least one of the pair of word line cutting structures, and the plurality of dummy conductive layers are separated from each other in the vertical direction.

9. The semiconductor device according to claim 7, wherein The insulating structure further includes a plurality of third insulating films contacting an upper second insulating film adjacent to the interlayer dielectric among the plurality of second insulating films in a portion of the through-electrode region, and Each of the plurality of third insulating films includes a constituent material different from a constituent material of each of the plurality of first insulating films and a constituent material of each of the plurality of second insulating films.

10. The semiconductor device according to claim 9, wherein The plurality of third insulating films include at least one third insulating film arranged in the local region of the through-electrode region, and At least one through-electrode selected from the plurality of through-electrodes passes through the at least one third insulating film in the vertical direction.

11. The semiconductor device according to claim 9, wherein The plurality of third insulating films include at least one third insulating film arranged outside the local region of the through-electrode region, and The at least one third insulating film is separated from the plurality of through electrodes.

12. The semiconductor device according to claim 9, wherein Each of the plurality of first insulating films includes a silicon oxide film. Each of the plurality of second insulating films and the plurality of third insulating films includes a silicon nitride film or a hydrogenated silicon nitride film, and A content ratio of silicon atoms (Si) in a constituent material of each of the plurality of second insulating films is different from a content ratio of silicon atoms (Si) in a constituent material of each of the plurality of third insulating films.

13. The semiconductor device according to claim 7, further comprising: a pair of word line cutting structures, defining a width of the through-electrode region in the second horizontal direction; as well as a plurality of dummy conductive layers arranged in the through-electrode region and contacting the pair of word line cutting structures; The vertical level of the upper surface of the insulating structure in the local area of the through-electrode area is closer to the peripheral circuit structure than the vertical level of the upper surface of the dummy conductive layer farthest from the peripheral circuit structure among the multiple dummy conductive layers.

14. The semiconductor device according to claim 7, further comprising: a pair of word line cutting structures, defining a width of the through-electrode region in the second horizontal direction; as well as a plurality of dummy conductive layers arranged in the through-electrode region and contacting the pair of word line cutting structures; The vertical level of the upper surface of the insulating structure in the local area of the through-electrode area is farther away from the peripheral circuit structure than the vertical level of the upper surface of the dummy conductive layer farthest from the peripheral circuit structure among the multiple dummy conductive layers.

15. The semiconductor device according to claim 7, further comprising: a pair of word line cutting structures, defining a width of the through-electrode region in the second horizontal direction; as well as a plurality of dummy conductive layers arranged in the through-electrode region and contacting the pair of word line cutting structures; wherein the local area of the electrode region includes a first local area and a second local area, A vertical level of the upper surface of the insulating structure in the first partial region is closer to the peripheral circuit structure than a vertical level of an upper surface of a dummy conductive layer farthest from the peripheral circuit structure among the plurality of dummy conductive layers, and A vertical level of the upper surface of the insulating structure in the second partial region is farther away from the peripheral circuit structure than a vertical level of the upper surface of the dummy conductive layer farthest from the peripheral circuit structure among the plurality of dummy conductive layers.

16. The semiconductor device according to claim 7, wherein The insulating structure further includes at least one third insulating film, the at least one third insulating film being located between an upper second insulating film adjacent to the interlayer dielectric among the plurality of second insulating films in the local region of the through-electrode region and the interlayer dielectric, the at least one third insulating film being in contact with the upper second insulating film. each of the plurality of first insulating films includes a silicon oxide film, the at least one third insulating film and each of the plurality of second insulating films include a silicon nitride film or a hydrogenated silicon nitride film, a content ratio of silicon atoms (Si) in the at least one third insulating film is greater than a content ratio of silicon atoms (Si) in each of the plurality of second insulating films, At least one through-electrode selected from the plurality of through-electrodes passes through the at least one third insulating film in the vertical direction.

17. The semiconductor device according to claim 7 , wherein each of the plurality of memory cell blocks includes a memory cell region and a connection region, the memory cell region including a plurality of gate lines and a plurality of vertical channel structures passing through the plurality of gate lines in the vertical direction, the connection region being arranged on one side of the memory cell region and including an edge portion of each of the plurality of gate lines, the through-electrode region includes a first through-electrode portion facing the memory cell region in the second horizontal direction, a second through-electrode portion facing the connection region in the second horizontal direction and arranged at a first position in the through-electrode region, and a third through-electrode portion facing the connection region in the second horizontal direction and arranged at a second position in the through-electrode region, In each of the second through-electrode portion and the third through-electrode portion, the insulating structure further includes a third insulating film contacting an upper second insulating film adjacent to the interlayer dielectric among the plurality of second insulating films, and The third insulating film of the second through-electrode portion and the third insulating film of the third through-electrode portion are respectively at different vertical levels. 18 . The semiconductor device according to claim 7 , wherein in the second horizontal direction, a width of the through-electrode region is greater than a width of each of the plurality of memory cell blocks. 19 . The semiconductor device according to claim 7 , wherein in the second horizontal direction, a width of the through-electrode region is equal to a width of each of the plurality of memory cell blocks.

20. A semiconductor device comprising: a peripheral circuit structure comprising a circuit substrate and a plurality of circuits on the circuit substrate; a plurality of pads overlapping the peripheral circuit structure in a vertical direction, each of the plurality of pads including a plurality of memory cell blocks extending longitudinally in a first horizontal direction; as well as at least one through-electrode region overlapping with the peripheral circuit structure in the vertical direction, the at least one through-electrode region being at least one of a first position between two adjacent memory cell blocks selected from the plurality of memory cell blocks, and a second position between two adjacent pads in a second horizontal direction perpendicular to the first horizontal direction among the plurality of pads, Wherein, the at least one through-electrode region comprises: an insulating structure comprising a plurality of first insulating films, a plurality of second insulating films, and a plurality of third insulating films, the plurality of first insulating films and the plurality of second insulating films comprising materials different from each other, the plurality of first insulating films and the plurality of second insulating films being alternately stacked one after another in the vertical direction, the plurality of third insulating films being in contact with upper second insulating films among the plurality of second insulating films, the insulating structure having an upper surface having a varying height in the vertical direction along each of the first horizontal direction and the second horizontal direction; an interlayer dielectric covering the upper surface of the insulating structure; and a plurality of through-electrodes penetrating the insulating structure and the interlayer dielectric in the vertical direction in a local region of the at least one through-electrode region, each of the plurality of through-electrodes being configured to be connected to one circuit selected from the plurality of circuits of the peripheral circuit structure; and wherein each of the plurality of first insulating films includes a silicon oxide film, and Each of the plurality of second insulating films and the plurality of third insulating films includes a silicon nitride film or a hydrogenated silicon nitride film.

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