Memory device

Abstract

A memory device includes a plurality of memory cells. Each memory cell includes a bottom electrode disposed on the substrate, a ferroelectric layer disposed on the bottom electrode, a barrier layer disposed on the ferroelectric layer, and a top electrode disposed on the barrier layer. The barrier layer is sandwiched between the top electrode and the ferroelectric layer, and the thickness of the barrier layer is smaller than that of the ferroelectric layer.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, and more particularly to a memory device. Background Art

[0002] The ferroelectric tunnel junction (FTJ), first proposed in 1996, has been studied for applications in high-density data storage, non-volatile memory, and neural-like computing. The basic FTJ structure consists of a thin layer of ferroelectric material sandwiched between two metal electrodes. When a voltage is applied between the electrodes, the polarization energy of the ferroelectric material is transformed, causing a change in the tunneling current between the electrodes. This change in current can be used to store and retrieve information.

[0003] In memory devices using FTJs, such as ferroelectric random-access memory (FRAM), a larger on / off ratio allows for the display of more multilevel states by applying more pulse voltages of varying amplitudes. In other words, a larger on / off ratio allows for higher storage density. However, as electronic devices continue to evolve toward smaller sizes and higher performance, existing FTJ memory devices may not be able to meet the demands of current or future electronic devices. Summary of the Invention

[0004] The present invention provides a memory device, wherein the FTJ structure included in the memory cell is designed to include a barrier layer sandwiched between a top electrode and a ferroelectric layer, and the barrier layer can serve as a tunneling barrier to effectively reduce the leakage current of the tunneling current through the insulating layer, thereby improving the on / off ratio of the FTJ structure by reducing the off current of the memory device.

[0005] One embodiment of the present invention provides a memory device comprising a plurality of memory cells, each of which includes a bottom electrode disposed on a substrate, a ferroelectric layer disposed on the bottom electrode, a barrier layer disposed on the ferroelectric layer, and a top electrode disposed on the barrier layer. The barrier layer is sandwiched between the top electrode and the ferroelectric layer, and the thickness of the barrier layer is less than the thickness of the ferroelectric layer.

[0006] In some embodiments, the barrier layer includes magnesium oxide (MgO).

[0007] In some embodiments, the ferroelectric layer includes hafnium zirconium oxide (HfZrO 2 , HZO).

[0008] In some embodiments, the material of the bottom electrode is different from the material of the top electrode.

[0009] In some embodiments, the bottom electrode includes titanium nitride (TiN) and the top electrode includes tungsten (W).

[0010] In some embodiments, the ferroelectric layer has a thickness of about 6 nm.

[0011] In some embodiments, the barrier layer has a thickness of less than or equal to about 1 nm.

[0012] In some embodiments, the barrier layer has a thickness of less than or equal to about 0.5 nm.

[0013] In some embodiments, the memory device further includes a gate structure and a source and a drain. The gate structure is disposed on a substrate. The source and the drain are disposed in the substrate on opposite sides of the gate structure, wherein the drain is electrically connected to the bottom electrode, and the source is electrically connected to the bit line.

[0014] In some embodiments, the bottom electrode is in direct contact with the ferroelectric layer, and the barrier layer is in direct contact with the top electrode and the ferroelectric layer.

[0015] Based on the above, in the memory device of the above embodiment, the FTJ structure included in the memory cell is designed to include a barrier layer sandwiched between the top electrode and the ferroelectric layer, and the barrier layer can serve as a tunneling barrier to effectively reduce the leakage current of the tunneling current through the insulating layer, thereby improving the on / off ratio of the FTJ structure by reducing the off current of the memory device. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 FIG. 1 is a cross-sectional diagram of a memory device according to an embodiment of the present invention.

[0017] Explanation of symbols

[0018] 10: Semiconductor devices

[0019] 100: Base

[0020] 102: semiconductor layer

[0021] 104: Drain

[0022] 106: Source

[0023] 110: memory unit

[0024] 112: bottom electrode

[0025] 114: Ferroelectric layer

[0026] 116: Barrier layer

[0027] 118: Top electrode

[0028] 120: dielectric layer

[0029] 130: conductive contact

[0030] 132: Wiring

[0031] BL: bit line

[0032] CH: Channel

[0033] GS: Gate structure

[0034] t1, t2: thickness

[0035] WL: Word Line DETAILED DESCRIPTION

[0036] The present invention will be more fully described with reference to the accompanying drawings illustrating the present embodiment. However, the present invention may be embodied in various forms and should not be limited to the embodiments described herein. The thicknesses of layers and regions in the accompanying drawings may be exaggerated for clarity. Identical or similar reference numbers denote identical or similar elements, and detailed descriptions will not be repeated in the following paragraphs.

[0037] It should be understood that when an element is referred to as being "on" or "connected to" another element, it may be directly on or connected to another element, or there may be an intermediate element. If an element is referred to as being "directly on" or "directly connected to" another element, there are no intermediate elements. As used herein, "connection" may refer to physical and / or electrical connection, while "electrical connection" or "coupling" may refer to the presence of other elements between two elements. As used herein, "electrical connection" may include physical connection (e.g., wired connection) and physical disconnection (e.g., wireless connection).

[0038] As used herein, "about," "approximately," or "substantially" includes the stated value and the average within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, taking into account the measurement in question and the particular amount of error associated with the measurement (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, or ±5%. Furthermore, as used herein, "about," "approximately," or "substantially" may be selected based on the optical property, etching property, or other property, and may not apply to all properties with a single standard deviation.

[0039] The terms used herein are intended to illustrate exemplary embodiments only and are not intended to limit the present invention. In this case, unless the context otherwise indicates, the singular includes the plural.

[0040] Figure 1 FIG. 1 is a cross-sectional diagram of a memory device according to an embodiment of the present invention.

[0041] In some embodiments, the semiconductor device 10 may include a plurality of memory cells 110, each of which may include a bottom electrode 112 disposed on the substrate 100, a ferroelectric layer 114 disposed on the bottom electrode 112, a barrier layer 116 disposed on the ferroelectric layer 114, and a top electrode 118 disposed on the barrier layer 116. The barrier layer 116 is sandwiched between the top electrode 118 and the ferroelectric layer 114, thereby effectively reducing leakage current caused by tunneling current through the insulating layer, thereby improving the on / off ratio of the FTJ structure. Furthermore, the barrier layer 116 sandwiched between the top electrode 118 and the ferroelectric layer 114 improves the interface quality between the top electrode 118 and the ferroelectric layer 114, thereby reducing leakage current caused by charge scattering and interface defects, thereby improving the on / off ratio of the FTJ.

[0042] The substrate 100 may include a semiconductor substrate or a semiconductor-on-insulator (SOI) substrate. The semiconductor material in the semiconductor substrate or SOI substrate may include an elemental semiconductor, an alloy semiconductor, or a compound semiconductor. For example, the elemental semiconductor may include Si or Ge. The alloy semiconductor may include SiGe, SiGeC, or the like. The compound semiconductor may include SiC, a III-V semiconductor material, or a II-VI semiconductor material. The III-V semiconductor material may include GaN, GaP, GaAs, AlN, AlP, AlAs, InN, InP, InAs, GaNPs, GaNAs, GaPAs, AlNPs, AlNAs, AlPAs, InNPs, InNAs, InPAs, GaAlNPs, GaAlNAs, GaAlPAs, GaInNPs, GaInNAs, GaInPAs, InAlNPs, InAlNAs, or InAlPAs. The II-VI semiconductor material may include CdS, CdSe, CdTe, ZnS, ZnSe, ZnTe, HgS, HgSe, HgTe, CdSeS, CdSeTe, CdSTe, ZnSeS, ZnSeTe, ZnSTe, HgSeS, HgSeTe, HgSTe, CdZnS, CdZnSe, CdZnTe, CdHgS, CdHgSe, CdHgTe, HgZnS, HgZnSe, HgZnTe, CdZnSeS, CdZnSeTe, CdZnSTe, CdHgSeS, CdHgSeTe, CdHgSTe, HgZnSeS, HgZnSeTe, or HgZnSTe. The semiconductor material may be doped with a dopant of a first conductivity type or a dopant of a second conductivity type complementary to the first conductivity type. For example, the first conductivity type may be P-type, and the second conductivity type may be N-type.

[0043] The bottom electrode 112 may include a conductive material. For example, the bottom electrode 112 may include a conductive material such as copper (Cu), aluminum (Al), zirconium (Zr), titanium (Ti), titanium nitride (TiN), tungsten (W), tantalum (Ta), tantalum nitride (TaN), molybdenum (Mo), ruthenium (Ru), palladium (Pd), platinum (Pt), cobalt (Co), nickel (Ni), or iridium (Ir).

[0044] The ferroelectric layer 114 may include a ferroelectric material. For example, the ferroelectric layer 114 may include a ferroelectric material such as Hf x Zr 1-x A ferroelectric material such as O2 (HZO), where x is between 0 and 1, is used for the ferroelectric layer 114. When the ferroelectric layer 114 is HZO, the thickness t1 of the ferroelectric layer 114 is approximately 6 nm. In this case, if the thickness of the ferroelectric layer 114 is less than 6 nm (e.g., 3 nm), the memory cell 110 may not exhibit ferroelectric properties. If the thickness of the ferroelectric layer 114 is greater than 6 nm (e.g., 8.5 nm), the on-state current of the memory cell 110 may be reduced, thereby lowering the on / off ratio of the FTJ structure.

[0045] The barrier layer 116 may comprise a wide-bandgap material, such as magnesium oxide (MgO). This can adjust the energy band of the FTJ structure, resulting in a significant difference in its band structure when voltages of opposite polarity are applied, further improving the on / off ratio of the FTJ structure. The thickness t2 of the barrier layer 116 is less than the thickness t1 of the ferroelectric layer 114. This allows the barrier layer 116 to not only function as a tunneling barrier (reducing the off-current of the memory device), but also improve the on-current of the memory device due to the thinner tunneling barrier, resulting in a good on / off ratio for the FTJ structure. In some embodiments, the thickness t2 of the barrier layer 116 is less than or equal to approximately 1 nm. In alternative embodiments, the thickness t2 of the barrier layer 116 is less than or equal to approximately 0.5 nm.

[0046] When the ferroelectric layer 114 is a HZO layer having a thickness t1 of 6 nm and the barrier layer 116 is a MgO layer having a thickness t2 of 0.5 nm, the on / off ratio of the memory cell 110 is approximately 32.

[0047] The top electrode 118 may include a conductive material. For example, the top electrode 118 may include a conductive material such as copper (Cu), aluminum (Al), zirconium (Zr), titanium (Ti), titanium nitride (TiN), tungsten (W), tantalum (Ta), tantalum nitride (TaN), molybdenum (Mo), ruthenium (Ru), palladium (Pd), platinum (Pt), cobalt (Co), nickel (Ni), or iridium (Ir).

[0048] In some embodiments, the material of the bottom electrode 112 can be different from the material of the top electrode 118. This allows for the asymmetric electrode configuration to counteract the internal bias generated by the barrier layer 116 and achieve desired device performance. For example, the bottom electrode 112 can include titanium nitride (TiN), while the top electrode 118 can include tungsten (W).

[0049] In some embodiments, the bottom electrode 112 is in direct contact with the ferroelectric layer 114 , and the barrier layer 116 is in direct contact with the top electrode 118 and the ferroelectric layer 114 .

[0050] In some embodiments, the semiconductor device 10 may further include a gate structure GS disposed on the substrate 100, and a drain 104 and a source 106 disposed in the substrate 100 on opposite sides of the gate structure GS. The gate structure GS is electrically connected to a word line WL. In some embodiments, the word line WL may be disposed on the gate structure GS. The drain 104 is electrically connected to a bottom electrode 112. In some embodiments, the drain 104 may be electrically connected to the bottom electrode 112 via a conductive contact 130. The source 106 is electrically connected to a bit line BL. In some embodiments, the bit line BL is disposed on the source 106. The word line WL, the bit line BL, and the conductive contact 130 may each include a conductive material such as a metal or a metal alloy. The metal or metal alloy may be, for example, Cu, Al, Ti, Ta, W, Pt, Cr, Mo, or alloys thereof.

[0051] In some embodiments, a channel CH of a transistor including a gate structure GS and a drain 104 and a source 106 may be formed in the substrate 100 below the gate structure GS and between the drain 104 and the source 106. In some embodiments, the drain 104, the source 106, and the channel CH may be formed by the following steps. First, a semiconductor layer 102 may be formed on the substrate 100 (e.g., an amorphous silicon substrate or a polycrystalline silicon substrate). The semiconductor layer 102 may include a drain 104 and a source 106, wherein the drain 104 and the source 106 may be formed by doping portions of the substrate 100 with a first conductivity type dopant or a second conductivity type dopant. For example, the drain 104 and the source 106 may be formed by an ion implantation process or a similar process. The channel CH of the transistor may be formed between the drain 104 and the source 106. The channel CH may include dopants having a different conductivity type from dopants doped into the drain 104 and the source 106, such that the channel CH has a different conductivity type from the drain 104 and the source 106. In alternative embodiments, the semiconductor layer 102 may utilize other suitable semiconductor materials (e.g., polysilicon, amorphous silicon, or semiconductive oxides (e.g., InGaZnO (IGZO), indium tin oxide (ITO), InWO, InZnO, InSnO, GaOx, InOx, or the like) to form the channel CH, and utilize other non-silicon materials to form the drain 104 and the source 106.

[0052] In some embodiments, the semiconductor device 10 may further include a dielectric layer 120 disposed on the substrate 100, wherein the gate structure GS, the bit line BL, the word line WL, the memory cell 110, and the conductive contact 130 may be embedded in the dielectric layer 120. The dielectric layer 120 may include a dielectric material such as an oxide (e.g., silicon oxide). In some embodiments, the top electrode 118 of the memory cell 110 may be electrically connected to a wiring 132 formed thereon. The wiring 132 may be embedded in the dielectric layer 120 and may include a conductive material such as a metal or a metal alloy. The metal or metal alloy may be, for example, Cu, Al, Ti, Ta, W, Pt, Cr, Mo, or alloys thereof.

[0053] In some embodiments, the FTJ structure included in the memory cell 110 can be applied to neural-like computing. For example, in biology, chemical synapses are often found in the human brain. After neurotransmitters are transmitted to the synapses through exocytosis and diffusion, the change in synaptic weight is synaptic plasticity. When the FTJ structure of the above-mentioned memory device has a larger on / off ratio, more multilevel states can be displayed by applying more pulse voltages of different amplitudes, so that the memory device can achieve changes corresponding to synaptic weights through good multilevel state characteristics. In other words, the FTJ structure included in the memory cell 110 can effectively mimic synaptic behavior and is suitable for application in neural-like computing.

[0054] In summary, in the above-mentioned memory device, the FTJ structure included in the memory cell is designed to include a barrier layer sandwiched between the top electrode and the ferroelectric layer, and the barrier layer can serve as a tunneling barrier to effectively reduce the leakage current of the tunneling current through the insulating layer. In this way, the on / off ratio of the FTJ structure can be improved by reducing the off current of the memory device.

Claims

1. A memory device comprising a plurality of memory cells, each of the memory cells comprising: a bottom electrode disposed on the substrate; a ferroelectric layer, disposed on the bottom electrode; a barrier layer disposed on the ferroelectric layer; as well as a top electrode disposed on the barrier layer, The barrier layer is sandwiched between the top electrode and the ferroelectric layer, and the thickness of the barrier layer is smaller than the thickness of the ferroelectric layer.

2. The memory device of claim 1, wherein the barrier layer comprises magnesium oxide (MgO).

3. The memory device of claim 2, wherein the ferroelectric layer comprises hafnium zirconium oxide (HfZrO, HZO).

4. The memory device of claim 1, wherein a material of the bottom electrode is different from a material of the top electrode.

5. The memory device of claim 4, wherein the bottom electrode comprises titanium nitride (TiN) and the top electrode comprises tungsten (W).

6. The memory device of claim 1, wherein the ferroelectric layer has a thickness of approximately 6 nm.

7. The memory device of claim 6, wherein the barrier layer has a thickness of less than or equal to about 1 nm.

8. The memory device of claim 6, wherein the barrier layer has a thickness of less than or equal to about 0.5 nm.

9. The memory device of claim 1 , further comprising: a gate structure, disposed on the substrate; as well as A drain and a source are respectively disposed in the substrate at opposite sides of the gate structure, wherein the drain is electrically connected to the bottom electrode, and the source is electrically connected to a bit line.

10. The memory device of claim 1, wherein the bottom electrode is in direct contact with the ferroelectric layer, and the barrier layer is in direct contact with the top electrode and the ferroelectric layer.

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