Phase change memory and preparation method thereof, micro-control unit, controller and vehicle

Abstract

The invention discloses a phase change memory and a preparation method thereof, a micro-control unit, a controller and a vehicle, relates to the technical field of semiconductors, and aims to solve the problem that the yield of the phase change memory is low due to high manufacturing difficulty caused by more thin film layers of the phase change memory. The phase change memory comprises at least one phase change memory unit; the phase change storage unit comprises a first electrode, a second electrode and a gating storage layer, the gate storage layer is arranged between the first electrode and the second electrode; the materials of the gate storage layer comprise a chalcogenide phase change material and a doping element doped in the chalcogenide phase change material; the doping element is at least configured to enable the crystallization temperature of the material of the gate storage layer to be higher than the crystallization temperature of the chalcogenide phase change material; wherein the mass ratio range of the doped element in the material of the gate storage layer is 30%-48%.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a phase change memory and a preparation method thereof, a microcontroller unit, a controller, and a vehicle. Background Art

[0002] Traditional phase-change memory cells consist of a storage cell and a gate cell. For example, the 1S1R structure consists of a threshold bidirectional switch gate transistor and a phase-change cell. To construct the storage cell and gate cell structure, multiple thin film layers must be stacked vertically, resulting in a complex process and increased manufacturing difficulty, which reduces the yield of phase-change memory. Summary of the Invention

[0003] The purpose of this application is to provide a phase change memory and its preparation method, micro control unit, controller, and vehicle, aiming to solve the problem that the phase change memory has more thin film layers, which makes manufacturing more difficult and leads to lower yield of the phase change memory.

[0004] To achieve the above objectives, this application adopts the following technical solutions:

[0005] In a first aspect, the present application provides a phase change memory comprising: at least one phase change memory unit.

[0006] The phase-change memory cell includes a first electrode, a second electrode and a gate memory layer.

[0007] The gate storage layer is arranged between the first electrode and the second electrode.

[0008] The material of the gate memory layer includes a chalcogenide phase change material and a doping element doped in the chalcogenide phase change material. The doping element is configured to at least make the crystallization temperature of the material of the gate memory layer higher than the crystallization temperature of the chalcogenide phase change material.

[0009] The mass proportion of the doping element in the material of the gate storage layer is in the range of 30% to 48%.

[0010] In the phase change memory provided in the embodiment of the present application, the material of the selection storage layer is a sulfur-based phase change material, and the switch of the selection storage layer can be controlled by an electrical signal. When the voltage applied to the selection storage layer is higher than its threshold voltage, the sulfur-based phase change material will change from a high-resistance state to a low-resistance state, and the device is in the on state; when the electrical signal is removed, the sulfur-based phase change material will return to the high-resistance state, and the selection storage layer will be in the off state, thereby realizing the selection function.

[0011] Sulfur-based phase change materials can undergo a reversible phase change process under specific conditions and can quickly switch between amorphous and crystalline states. At the same time, the doping elements make the crystallization temperature of the material of the strobing storage layer higher than the crystallization temperature of the sulfide phase change material, which can reduce the possibility of crystallization of the material of the strobing storage layer in a low-temperature environment, avoid the material of the strobing storage layer from being unable to change back to the amorphous state due to low-temperature crystallization, enhance the thermal stability of the strobing storage layer material, thereby ensuring the stability of data storage, and thus realizing the reliable storage function of the strobing storage layer.

[0012] Among them, the mass proportion of the doping elements in the material of the gate storage layer is in the range of 30% to 48%, which helps to fine-tune the crystallization temperature of the gate storage layer material to a reasonable range, and can optimize the phase change behavior of the gate storage layer material, so that the gate storage layer material can maintain its thermal stability and improve the reliability of data storage.

[0013] Therefore, the phase change memory is provided with a phase change memory unit, and the phase change memory unit includes a first electrode, a second electrode and a selection storage layer, so that the phase change storage and the selection are combined into a layer of material, which reduces the number of thin film layers of the phase change memory and greatly reduces the etching aspect ratio in the preparation process. At the same time, the types of materials of the thin films used in the phase change memory are reduced, and the switching of gases in the etching process and the accumulation of by-products are reduced, thereby reducing the complexity of the process, simplifying the difficulty of manufacturing, and improving the manufacturing yield of the phase change memory.

[0014] In some embodiments, the doping element includes at least one of a Group III non-metal element, a Group IV non-metal element, a Group V non-metal element, and a metal element.

[0015] In some embodiments, the doping element includes at least one of carbon, nitrogen, silicon, arsenic, silver, boron, manganese, magnesium, and aluminum.

[0016] In some embodiments, the doping element includes arsenic.

[0017] In some embodiments, the doping element further includes silicon.

[0018] In some embodiments, in the material of the gate memory layer, the mass ratio of silicon to arsenic is in a range of 0.1 to 0.5.

[0019] In some embodiments, the chalcogenide phase change material includes germanium and selenium.

[0020] In some embodiments, the mass ratio of selenium to germanium in the material of the gate memory layer is in a range of 2-3.

[0021] In some embodiments, a size of the gate memory layer in a first direction ranges from 20 nm to 40 nm, and the first direction is a thickness direction of the phase change memory.

[0022] In some embodiments, the phase change memory further includes: a substrate.

[0023] At least one phase change memory unit is disposed on a substrate, and the first electrode is closer to the substrate than the second electrode.

[0024] The first electrode and the second electrode are sheet-shaped electrodes perpendicular to the substrate; the first electrode and the second electrode are arranged in a cross-like manner.

[0025] In some embodiments, the thickness of the first electrode is in a range of 6 nm to 10 nm.

[0026] In some embodiments, the second electrode has a thickness ranging from 10 nm to 30 nm.

[0027] In some embodiments, the phase-change memory cell further includes a dielectric layer.

[0028] The dielectric layer is disposed between the second electrode and the gate storage layer.

[0029] In some embodiments, the phase-change memory unit further includes a barrier layer.

[0030] The portion of the barrier layer close to the substrate is arranged around the side of the gate storage layer, and the portion of the barrier layer away from the substrate is arranged around the side of the dielectric layer.

[0031] In some embodiments, the phase change memory includes: a plurality of phase change memory cells arranged in a second direction, where the second direction intersects with a thickness direction of the phase change memory.

[0032] The barrier layers of any two adjacent phase-change memory units are connected to each other.

[0033] In some embodiments, a phase change memory includes: a plurality of phase change memory layers stacked in a first direction, wherein the first direction is a thickness direction of the phase change memory.

[0034] The phase-change memory layer includes a plurality of phase-change memory units arranged in a second direction, where the second direction intersects the first direction.

[0035] In some embodiments, in any two adjacent phase change memory cells overlapping in the first direction in the multi-layer phase change memory layer, the second electrode of the phase change memory cell relatively close to the substrate is reused as the first electrode of the phase change memory cell relatively far from the substrate.

[0036] In a second aspect, the present application provides a method for preparing a phase change memory. The method for preparing the phase change memory comprises:

[0037] At least one phase-change memory cell is formed. The phase-change memory cell includes a first electrode, a second electrode, and a gate memory layer. The gate memory layer is disposed between the first electrode and the second electrode. The gate memory layer comprises a chalcogenide phase-change material and a doping element doped in the chalcogenide phase-change material. The doping element is configured to at least: cause the crystallization temperature of the gate memory layer material to be greater than the crystallization temperature of the chalcogenide phase-change material. The doping element accounts for 30% to 48% by weight of the gate memory layer material.

[0038] It can be understood that the beneficial effects achieved by the method for preparing the phase change memory provided in the above embodiments of the present application can be referred to the beneficial effects of the phase change memory described above, and will not be repeated here.

[0039] In some embodiments, forming a phase change memory cell includes:

[0040] A substrate is provided.

[0041] A first electrode is formed on a substrate.

[0042] An initial gate storage layer is formed on a side of the first electrode away from the substrate.

[0043] An initial dielectric layer is formed on a side of the initial selection memory layer away from the first electrode.

[0044] The initial gating memory layer and the initial dielectric layer are etched, and the initial gating memory layer and the initial dielectric layer located on a side of the first electrode away from the substrate are retained to form a gating memory layer and a dielectric layer respectively.

[0045] A second electrode is formed on a side of the dielectric layer away from the gate memory layer.

[0046] In some embodiments, during the etching of the initial gate memory layer and the initial dielectric layer, a plurality of gate memory layers are formed, arranged and spaced apart in a second direction, and a plurality of dielectric layers are also formed, arranged and spaced apart in the second direction, where the second direction intersects the thickness direction of the phase change memory. After etching the initial gate memory layer and the initial dielectric layer, the method further includes:

[0047] A high aspect ratio process or an ethyl silicate process is used to deposit materials in the gaps between adjacent gate storage layers, in the gaps between adjacent dielectric layers, and on the side of multiple dielectric layers away from the substrate to form a first interlayer dielectric layer.

[0048] In some embodiments, after etching the initial gate memory layer and the initial dielectric layer and before forming the first interlayer dielectric layer, the preparation method further includes:

[0049] A material is deposited on a side surface of the gate memory layer, a side surface of the dielectric layer, and a surface of the dielectric layer away from the gate memory layer to form an initial blocking layer.

[0050] In the process of forming the first interlayer dielectric layer, the first interlayer dielectric layer covers the initial barrier layer.

[0051] In some embodiments, forming a second electrode on a side of the dielectric layer away from the gate storage layer includes:

[0052] The first interlayer dielectric layer and the initial barrier layer are etched to expose at least a portion of the dielectric layer.

[0053] A second electrode is formed on the dielectric layer.

[0054] In some embodiments, a phase change memory includes: a plurality of phase change memory cells arranged in a second direction, the second direction intersecting with a thickness direction of the phase change memory. A first electrode is formed on a substrate, including:

[0055] A second interlayer dielectric layer is formed on the substrate.

[0056] The second interlayer dielectric layer is etched to form a trench.

[0057] A conductive material is deposited on the surface of the second interlayer dielectric layer away from the substrate, and on the bottom surface and sidewall of the trench to form a first electrode layer.

[0058] The first electrode layer is etched to remove the portion of the first electrode layer located at the bottom of the trench and the portion of the second interlayer dielectric layer located on the surface away from the substrate. The portion of the first electrode layer located on the sidewall of the trench is retained to form the first electrodes of multiple phase change memory cells.

[0059] In a third aspect, the present application provides a microcontroller unit comprising: a control circuit and a phase change memory as described in any of the above embodiments. The control circuit is coupled to the phase change memory.

[0060] It can be understood that the beneficial effects achieved by the micro control unit provided in the above embodiments of the present application can be referred to the beneficial effects of the phase change memory mentioned above, and will not be repeated here.

[0061] In a fourth aspect, the present application provides a controller comprising: a circuit board and a microcontroller unit as described in the above embodiment. The microcontroller unit is coupled to the circuit board.

[0062] It can be understood that the beneficial effects that can be achieved by the controller provided in the above embodiments of the present application can be referred to the beneficial effects of the phase change memory mentioned above, and will not be repeated here.

[0063] In a fifth aspect, the present application provides a vehicle. The vehicle includes: an execution unit and a controller as described in the above embodiment. The controller is used to control the execution unit.

[0064] It can be understood that the beneficial effects that can be achieved by the vehicle provided by the above-mentioned embodiments of the present application can be referred to the beneficial effects of the phase change memory mentioned above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0065] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0066] Figure 1 Schematic diagram of the structure of an existing phase change memory;

[0067] Figure 2 A schematic diagram of a phase change memory is provided for an embodiment of the present application;

[0068] Figure 3 A schematic diagram of another phase change memory is provided for an embodiment of the present application;

[0069] Figure 4 A flow chart of a method for preparing a phase change memory is provided for an embodiment of the present application;

[0070] Figure 5 A schematic diagram of a method for preparing a phase change memory is provided for an embodiment of the present application.

[0071] Reference numerals:

[0072] 100-phase change memory, 10-first electrode, 20-second electrode, 30-substrate, 40-selection storage layer, 50-dielectric layer, 60-barrier layer, P-phase change memory cell, PM-phase change memory layer, 11-phase change memory layer, 12-first dielectric layer, 13-selection layer, 14-second dielectric layer, 70-first interlayer dielectric layer, 80-second interlayer dielectric layer, G-groove, 40A-initial selection storage layer, 50A-initial dielectric layer, 60A-initial barrier layer. DETAILED DESCRIPTION

[0073] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0074] In the description of this application, it should be understood that the terms "upper," "lower," "left," "right," "front," "back," "inner," "outer," and the like, indicating directions or positional relationships, are based on the directions or relative positional relationships shown in the accompanying drawings and are intended solely to facilitate the description of this application and simplify the description. They do not indicate or imply that the devices or components referred to must have a specific direction, be constructed, or operate in a specific direction. Therefore, they should not be construed as limitations on this application. Unless otherwise specified, the above-mentioned directionality descriptions may be flexibly set in actual application, provided that the relative positional relationships shown in the accompanying drawings are met.

[0075] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature specified as "first" or "second" may explicitly or implicitly include one or more of such features. Throughout this application, unless otherwise specified, "plurality" means two or more.

[0076] In the embodiments of the present application, the terms "comprises," "comprising," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, article, or device comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not preclude the presence of other identical elements in the process, article, or device comprising the element.

[0077] In the embodiments of this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of this application should not be interpreted as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0078] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0079] The present application provides a vehicle. The vehicle includes an execution unit and a controller. The controller is used to control the execution unit.

[0080] The actuator is the component in a vehicle that actually performs an operation or task. Depending on the vehicle, these components may include the engine, motor, braking system, steering mechanism, suspension system, and more. These actuators execute actions such as acceleration, deceleration, and steering based on received commands or signals.

[0081] The controller is the intelligent part of the vehicle, responsible for receiving input signals, processing data, and issuing control instructions to the actuators. The controller interprets the control instructions and sends them to the corresponding actuators. Communication between the controller and actuators occurs via an electrical connection, either a direct wire connection or a more complex network such as the CAN bus.

[0082] The present application provides a controller. The controller includes a circuit board and a microcontroller unit. The microcontroller unit is coupled to the circuit board.

[0083] Circuit boards are the basic components of electronic devices, used to support and connect electronic components.

[0084] A microcontroller unit (MCU) is an integrated circuit chip that integrates multiple functions such as a processor core, memory, and input / output ports.

[0085] The microcontroller unit is mounted on a circuit board and connected to other electronic components via conductive traces on the circuit board. This coupling between the microcontroller unit and the circuit board enables the microcontroller unit to receive signals from other components, execute the corresponding program logic, and control the operating status of other components.

[0086] The present application provides a microcontroller unit. The microcontroller unit includes a control circuit and a phase change memory. The control circuit is coupled to the phase change memory.

[0087] The control circuit is the core part of the microcontroller, which can execute instructions, process data, and control external devices. The control circuit performs various operations by reading instructions and data stored in the memory.

[0088] With the rapid development of artificial intelligence technology, the requirements for memory capacity, speed, and energy consumption are also increasing. For example, the training and reasoning of AI models have put forward higher requirements on the performance and capacity of memory.

[0089] Phase Change Memory (PCM) can reversibly switch between high and low resistance states based on its inherent material properties. PCM utilizes the reversible transformation of phase change materials for binary data storage, with the high resistance state (amorphous) representing 0 and the low resistance state (crystalline) representing 1. PCM stores data based on the intrinsic properties of the material, exploiting the difference in conductivity exhibited by special materials (such as chalcogenides or oxides) when transitioning between crystalline and amorphous states.

[0090] Moreover, each unit of the phase change memory can be programmed individually, so each phase change unit needs to be equipped with a gating device for individual operation. Commonly used gating devices include MOS tubes (metal oxide semiconductor field effect transistors, abbreviated as MOSFET), bipolar junction transistors (BJTs), diodes, and threshold bidirectional switches (OTS).

[0091] As a new type of non-volatile memory, three-dimensional phase change memory has the advantages of high density, high speed, low power consumption and long life. It adopts a 1S1R structure that combines OTS and phase change memory cells, that is, a threshold bidirectional switch gate tube and a phase change cell. OTS materials and phase change memory materials are both chalcogenides, so they can be stacked in a vertical direction in terms of process. In order to construct the 1S1R structure, multiple thin film layers need to be stacked in the vertical direction, which causes process complexity, increases the difficulty of manufacturing, and leads to a reduction in the yield of phase change memory.

[0092] In some examples, such as Figure 1 As shown, an existing phase change memory adopts a 1S1R structure, including a substrate 30 layers, a first electrode 10 layers, a phase change storage layer 11, a first dielectric layer 12, a selection layer 13, a second dielectric layer 14, and a second electrode 20 layers, a total of six layers. During the etching process, the high aspect ratio formed by the multi-layer thin film increases the process difficulty and reduces the yield.

[0093] Based on this, the embodiment of the present application provides a phase change memory 100. Figure 2 As shown, the phase change memory 100 includes: at least one phase change memory unit P.

[0094] The phase change memory cell P includes a first electrode 10 , a second electrode 20 and a gate memory layer 40 . The gate memory layer 40 is disposed between the first electrode 10 and the second electrode 20 .

[0095] The first electrode 10 is an electrical contact point of the phase change memory unit P. In the phase change memory 100 , the first electrode 10 is used to apply a current or a voltage to the gate memory layer 40 , thereby inducing a phase transition of the phase change material.

[0096] For example, the material of the first electrode 10 may be tungsten (W), titanium nitride (TiN), etc., which is not limited here.

[0097] The second electrode 20 is another electrical contact point of the phase change memory unit P, opposite to the first electrode 10 , and its main function is to provide a current path to ensure that current can flow evenly through the selection memory layer 40 , thereby effectively inducing phase change.

[0098] For example, the material and structure of the second electrode 20 may be similar to or the same as those of the first electrode 10 , which is not limited here.

[0099] The material of the gate memory layer 40 includes a chalcogenide phase change material and a doping element doped in the chalcogenide phase change material. The doping element is configured to at least make the crystallization temperature of the gate memory layer 40 higher than the crystallization temperature of the chalcogenide phase change material.

[0100] It can be understood that the sulfur-based phase change material uses an electrical signal to control the switch of the selection storage layer 40. When the voltage applied to the selection storage layer 40 is higher than its threshold voltage, the sulfur-based phase change material will change from a high-resistance state to a low-resistance state, and the device is in the on state; when the electrical signal is removed, the sulfur-based phase change material will maintain a low-resistance state. When a high and short pulse electrical signal is applied, the sulfur-based phase change material will return to a high-resistance state, and the selection storage layer 40 will be in the off state, thereby realizing the selection function.

[0101] Sulfur-based phase change materials can undergo a reversible phase change process under specific conditions and can quickly convert between amorphous and crystalline states. At the same time, the doping elements make the crystallization temperature of the material of the selection storage layer 40 higher than the crystallization temperature of the sulfur-based phase change material, which can reduce the possibility of crystallization of the material of the selection storage layer 40 in a low-temperature environment, avoid the material of the selection storage layer 40 from being unable to change back to the amorphous state due to low-temperature crystallization, enhance the thermal stability of the material of the selection storage layer 40, thereby ensuring the stability of data storage, and thus realizing the reliable storage function of the selection storage layer 40.

[0102] The mass proportion of the doping element in the material of the gate storage layer 40 is in the range of 30% to 48%.

[0103] For example, the mass proportion of the doping element in the material of the gate storage layer 40 may be 30%, 35%, 38%, 40%, 45% or 48%, etc., which is not limited here.

[0104] The above-mentioned setting helps to finely adjust the crystallization temperature of the material of the selection storage layer 40 to a reasonable range, and can optimize the phase change behavior of the material of the selection storage layer 40, so as to avoid excessive increase in phase change temperature caused by excessive doping (the mass proportion of the doping element in the material of the selection storage layer 40 is greater than 7%), thereby affecting the operability of the material; or the situation where less doping (the mass proportion of the doping element in the material of the selection storage layer 40 is less than 3%) does not change the crystallization temperature of the sulfur-based phase change material, thereby enabling the material of the selection storage layer 40 to maintain its thermal stability and improve the reliability of data storage.

[0105] Therefore, the above-mentioned phase change memory unit P includes the configuration of the first electrode 10, the second electrode 20 and the selection storage layer 40, which merges the phase change storage and selection into a layer of material, reduces the number of film layers of the phase change memory 100, greatly reduces the etching aspect ratio during the preparation process, and at the same time reduces the types of materials of the thin film used in the phase change memory 100, reduces the switching of gases in the etching process, and the accumulation of by-products, thereby reducing the complexity of the process, simplifying the difficulty of manufacturing, and improving the manufacturing yield of the phase change memory 100.

[0106] In some embodiments, the doping element includes at least one of a Group III non-metal element, a Group IV non-metal element, a Group V non-metal element, and a metal element.

[0107] It can be understood that the Group III non-metallic elements can enhance the thermal stability of the material of the gate storage layer 40 and enhance the crystal structure stability of the material of the gate storage layer 40, so that the material of the gate storage layer 40 can maintain excellent phase change performance under high and low temperature conditions.

[0108] The Group IV non-metallic elements can enhance the strength, toughness or electrical conductivity of the material of the gate storage layer 40 , while improving its thermal conductivity, thereby facilitating rapid thermal regulation and enhancing the stability of the material of the gate storage layer 40 .

[0109] The Group V non-metallic elements can improve the thermal stability of the material of the gate memory layer 40 , and can also improve the phase change performance of the material of the gate memory layer 40 under high and low temperature conditions.

[0110] The metal element can improve the conductivity of the material of the gate storage layer 40 , so that the material of the gate storage layer 40 has a faster switching speed and improves the data reading and writing efficiency.

[0111] By selecting the doping elements in the material of the gate memory layer 40 , the thermal stability, electrical conductivity and phase change characteristics of the material of the gate memory layer 40 can be improved, thereby improving the reliability and efficiency of the phase change memory 100 .

[0112] In some embodiments, the doping element includes at least one of carbon, nitrogen, silicon, arsenic, silver, boron, manganese, magnesium, and aluminum.

[0113] Carbon (C) improves the mechanical properties and thermal conductivity of the gate storage layer 40 material by forming different compounds and structures, promotes the stability and flexibility of the gate storage layer 40 material, helps to improve phase change efficiency, and enhances adaptability to environmental changes.

[0114] Nitrogen (N) can change the electronic and crystal structures of the gate storage layer 40 material, improve the electrical properties, increase the range of resistivity, and enhance the thermal stability of the gate storage layer 40 material, thereby enabling the gate storage layer 40 material to maintain a good phase state under both high and low temperature conditions.

[0115] Silicon (Si) increases the strength of the material of the gate storage layer 40 and its responsiveness to heat and current, thereby improving conductivity and optimizing the performance of the material of the gate storage layer 40 during phase change, thereby enhancing the reliability of data storage.

[0116] Arsenic (As) can increase the carrier concentration of the gate memory layer 40 material, thereby enhancing conductivity; and improve the phase change performance of the gate memory layer 40 material at high temperatures, so that the phase change memory 100 has good reactivity and operational flexibility.

[0117] Silver (Ag) can improve the electrical conductivity and thermal conductivity of the material of the gate memory layer 40 , promote fast switching capability, shorten data writing and reading time, and improve the overall performance of the phase change memory 100 .

[0118] Boron (B) can increase the charge carrier density of the gate memory layer 40 material by providing additional electrons, thereby improving the conductivity and phase change efficiency, and at the same time enhancing the crystal structure stability of the gate memory layer 40 material.

[0119] Manganese (Mn) can adjust the conductivity and carrier density of the gate storage layer 40 material, improve the current conduction performance and maintain good phase change capability, thereby increasing the service life and efficiency of the gate storage layer 40 material.

[0120] The magnesium element (Mg) can affect the crystal structure of the material of the gate memory layer 40 , improve the thermal stability of the material of the gate memory layer 40 , optimize the performance of the material of the gate memory layer 40 at high temperatures, and ensure its reliability.

[0121] Aluminum (Al) can enhance the corrosion resistance and electrical properties of the material of the gate storage layer 40 , improve the stability and phase change capability of the material of the gate storage layer 40 , and adapt to more application environments.

[0122] By selecting doping elements such as carbon, nitrogen, silicon, arsenic, silver, boron, manganese, magnesium and aluminum, the thermal stability, electrical performance and mechanical properties of the gate storage layer 40 material can be further optimized according to their different characteristics and functions.

[0123] In some embodiments, the doping element includes arsenic.

[0124] It can be understood that the incorporation of arsenic elements can not only adjust the phase change temperature of the gate storage layer 40 material, but also increase the carrier concentration in the gate storage layer 40 material, thereby improving the conductivity of the gate storage layer 40 material. The enhanced conductivity properties contribute to the rapid electron transfer during the phase change process, which can accelerate the conversion of the gate storage layer 40 material from a high resistance state to a low resistance state, and can also quickly recover to a high resistance state, thereby achieving excellent switching behavior; and arsenic can improve the phase change speed and efficiency, that is, the arsenic-doped gate storage layer 40 material can provide better retention ability during data storage, thereby ensuring the stability of data storage.

[0125] In addition, arsenic doping can extend the service life of the phase change memory 100 by improving the fatigue resistance of the phase change material, so that the performance of the phase change memory 100 can be kept stable during repeated read and write cycles.

[0126] In some embodiments, the doping element further includes silicon.

[0127] It can be understood that in addition to the above-mentioned arsenic and silicon elements being able to improve the stability, conductivity and phase change characteristics of the material of the selection storage layer 40; arsenic is compatible with silicon and forms a stable compound during the synthesis process. This compound can maintain good compatibility in structure and can form a uniform doping system; that is, arsenic and silicon elements can form a composite material of the selection storage layer 40, thereby further improving the integration of the phase change memory 100, so that the phase change memory 100 can achieve higher storage capacity in a smaller space.

[0128] In some embodiments, the mass ratio of silicon to arsenic in the material of the gate memory layer 40 is in a range of 0.1 to 0.5.

[0129] For example, in the material of the gate storage layer 40 , the mass ratio of silicon to arsenic can be 0.1, 0.2, 0.3, 0.4, or 0.5, etc., which is not limited here.

[0130] Through the above configuration, the performance of the material of the gate memory layer 40 can be effectively optimized, and the phase change characteristics can be improved while ensuring the stability and conductivity of the gate memory layer 40; the storage capacity of the phase change memory 100 can also be further improved.

[0131] In some embodiments, the chalcogenide phase change material includes germanium and selenium.

[0132] It can be understood that germanium (Ge) can effectively regulate the carrier concentration in the material, thereby improving the current response during the phase change process. The germanium material exhibits rapid phase change behavior under thermal stimulation and can complete data writing and reading within nanoseconds; and germanium can enhance the thermal stability of the selection storage layer 40 material, which helps to maintain superior performance over a wider temperature range.

[0133] Selenium (Se) is a non-metallic element that can combine with germanium to form a chalcogenide compound, which can interact positively, affect the structure and electronic properties of the gate storage layer 40 material, and optimize the phase change characteristics of the gate storage layer 40 .

[0134] In some embodiments, the mass ratio of selenium to germanium in the material of the gate memory layer 40 is in the range of 2-3.

[0135] For example, the mass ratio of selenium to germanium can be 2, 2.25, 2.5, 2.8 or 3, etc., which is not limited here.

[0136] The above arrangement can not only maintain the excellent electrical properties of germanium, but also utilize the chemical properties of selenium to improve the overall performance; and achieve a good balance between the germanium and selenium elements, thereby optimizing the electrical conductivity, thermal stability and phase change speed of the phase change material.

[0137] In some embodiments, as Figure 2 As shown, a dimension D of the gate memory layer 40 in a first direction Y ranges from 20 nm to 40 nm, and the first direction Y is a thickness direction of the phase change memory 100 .

[0138] For example, the dimension D of the gate memory layer 40 in the first direction Y may be 20 nm, 25 nm, 30 nm, 35 nm or 40 nm, etc., which is not limited here.

[0139] The above configuration can integrate more phase change memory cells P, thereby increasing the density of the phase change memory 100 and significantly improving the storage capacity; and helps to reduce the thermal diffusion distance of the material of the gate storage layer 40, thereby accelerating the response time of the phase change process and achieving faster writing and reading speeds.

[0140] In some embodiments, as Figure 2 As shown, the phase change memory 100 further includes a substrate 30 .

[0141] At least one phase change memory unit P is provided on a substrate 30, and the first electrode 10 is closer to the substrate 30 than the second electrode 20. The first electrode 10 and the second electrode 20 are sheet-shaped electrodes perpendicular to the substrate 30. The first electrode 10 and the second electrode 20 are arranged in a cross pattern.

[0142] The substrate 30 is the foundation of the entire phase change memory 100 and provides a foundation for mechanical support and electrical connection.

[0143] Exemplarily, the material of the substrate 30 may be silicon, germanium, silicon-germanium alloy or other semiconductor materials, or silicon on insulator (SOI), etc., which is not limited here.

[0144] The first electrode 10 is closer to the substrate 30 than the second electrode 20, indicating that the first electrode 10 is in direct contact with the substrate 30, while the second electrode 20 is located on the other side of the gate memory layer 40. Furthermore, the first electrode 10 and the second electrode 20 are both sheet-shaped electrodes perpendicular to the substrate 30 and arranged in a staggered manner, which helps reduce the interaction between the first electrode 10, the second electrode 20, and the gate memory layer 40 during the fabrication of the phase change memory 100, thereby simplifying the fabrication process.

[0145] In some embodiments, the thickness of the first electrode 10 is in the range of 6 nm to 10 nm.

[0146] For example, the thickness of the first electrode 10 may be 6 nm, 7 nm, 8 nm, 9 nm, or 10 nm, etc., which is not limited here.

[0147] In some embodiments, the thickness of the second electrode 20 ranges from 10 nm to 30 nm.

[0148] Illustratively, the thickness of the second electrode 20 may be 10 nm, 15 nm, 20 nm, 25 nm, or 30 nm, etc., which is not limited here.

[0149] The above-mentioned arrangement can reduce the contact area between the first electrode 10 and the second electrode 20 and the selection storage layer 40, concentrate heat, thereby reducing heat power consumption and increasing the heating speed of the selection storage layer 40; and based on the above-mentioned phase change memory unit P, it can be stacked in the vertical direction (the thickness direction of the phase change memory 100) to achieve three-dimensional integration.

[0150] In some implementations, such as Figure 1 As shown, it includes two dielectric layers (12 / 14), and the dielectric layer includes an etch stop layer 122 and an adhesion layer 121. The etch stop layer 122 is mainly for the switching point of the etching process. The adhesion layer 121 ensures the connection strength between the materials to prevent peeling during use, and also plays a certain etching selectivity.

[0151] In some embodiments, as Figure 2 As shown, the phase change memory cell P further includes a dielectric layer 50 . The dielectric layer 50 is disposed between the second electrode 20 and the gate memory layer 40 .

[0152] For example, the material of the dielectric layer 50 may be titanium nitride, etc., which is not limited here.

[0153] It can be understood that the dielectric layer 50 can form good adhesion between the second electrode 20 and the selection storage layer 40, which helps to ensure the overall structural stability and long-term reliability of the device; and the dielectric layer 50 can provide a conductive channel between the selection storage layer 40 and the second electrode 20, which helps to quickly conduct current during the phase change process and improve the performance of the phase change memory 100; in addition, the dielectric layer 50 can protect the underlying structure (the selection storage layer 40 and the second electrode 20) during the manufacturing process, preventing excessive removal of material during etching, thereby ensuring the accuracy and consistency of the characteristic size of the phase change memory 100.

[0154] In some embodiments, as Figure 2 As shown, the phase-change memory cell P further includes a barrier layer 60 .

[0155] For example, the material of the barrier layer 60 may be aluminum oxide, silicon nitride, etc., which is not limited here.

[0156] The portion of the barrier layer 60 close to the substrate is disposed around the side of the gate memory layer 40. The portion of the barrier layer 60 away from the substrate 30 is disposed around the side of the dielectric layer 50.

[0157] It can be understood that the barrier layer 60 plays a key role in protection, thermal isolation and electrical isolation in the phase change memory unit P, and can isolate oxygen and prevent oxidation of the material of the selection memory layer 40. By arranging the barrier layer 60 on the side of the selection memory layer 40 and around the dielectric layer 50, the structural stability of the phase change memory 100 can be improved.

[0158] In some embodiments, as Figure 2 As shown, the phase change memory 100 includes: a plurality of phase change memory cells P arranged in a second direction X, and the second direction X intersects with the thickness direction of the phase change memory 100 .

[0159] The barrier layers 60 of any two adjacent phase-change memory cells P are connected to each other.

[0160] It can be understood that by connecting the barrier layer 60, heat can be transferred more effectively between adjacent cells P; and making the barrier layer 60 continuous can be more easily achieved, simplifying the manufacturing process; in addition, the connected barrier layer 60 may provide additional structural support, increasing the mechanical stability of the entire phase change memory 100.

[0161] In some embodiments, as Figure 3 As shown, the phase change memory 100 includes: a plurality of phase change memory layers PM stacked in a first direction Y. The first direction Y is a thickness direction of the phase change memory 100 .

[0162] The phase-change memory layer PM includes a plurality of phase-change memory cells P arranged in a second direction X intersecting the first direction Y.

[0163] It can be understood that the phase-change memory cells P are arranged in the second direction X (e.g., horizontally), while the phase-change memory layers PM are stacked in the first direction Y (e.g., vertically). This arrangement increases the number of phase-change memory cells P, thereby increasing the density of the phase-change memory cells P, significantly improving the storage density and thus the storage capacity of the phase-change memory 100. Furthermore, the phase-change memory 100 of the present application avoids the high-temperature process required of conventional silicon-based gate devices, thereby increasing the stability of the phase-change memory cells P during the process.

[0164] For a multi-layer phase change memory layer PM structure, such as Figure 3 The upper second electrode 20 can be a columnar electrode, and the lower first electrode 10 and the first electrode 10 or the second electrode 20 of the middle layer can be sheet electrodes, that is, as described in the above embodiments, the thickness range of the first electrode 10 is 6nm to 10nm, or the thickness range of the second electrode 20 is 10nm to 30nm.

[0165] In some embodiments, as Figure 3 As shown, in any two adjacent phase change memory cells P overlapping in the first direction Y in the multi-layer phase change memory layer PM, the second electrode 20 of the phase change memory cell P relatively close to the substrate 30 is reused as the first electrode 10 of the phase change memory cell P relatively far away from the substrate 30.

[0166] The above-mentioned arrangement can reduce the total number of electrodes by reusing the second electrode 20 of the phase change memory unit P relatively close to the substrate 30 and the first electrode 10 of the phase change memory unit P relatively far away from the substrate 30, so that the reused electrodes can serve two adjacent phase change memory units P at the same time, and more phase change memory units P can be integrated within a limited area, which can reduce material costs and manufacturing complexity, and simplify the overall structure of the multi-layer phase change memory layer PM.

[0167] The embodiment of the present application provides a method for preparing a phase change memory. Figure 4 As shown, the preparation method of the phase change memory includes: S1.

[0168] S1: Form at least one phase-change memory cell P. The phase-change memory cell P includes a first electrode 10, a second electrode 20, and a gate memory layer 40. The gate memory layer 40 is disposed between the first electrode 10 and the second electrode 20. The material of the gate memory layer 40 includes a chalcogenide phase-change material and a doping element doped in the chalcogenide phase-change material. The doping element is configured to at least: cause the crystallization temperature of the material of the gate memory layer 40 to be greater than the crystallization temperature of the chalcogenide phase-change material. The mass percentage of the doping element in the material of the gate memory layer 40 ranges from 30% to 48%.

[0169] In some embodiments, combined Figure 2 , refer to Figure 5 , S1 forms a phase change memory unit including: S1.1~S1.6.

[0170] S1.1: Provide a substrate 30.

[0171] S1.2: Forming a first electrode 10 on the substrate 30 .

[0172] S1.3: forming an initial gate memory layer 40A on a side of the first electrode 10 away from the substrate 30 .

[0173] S1.4: forming an initial dielectric layer 50A on a side of the initial selection memory layer 40A away from the first electrode 10 .

[0174] S1.5: Etching the initial selection memory layer 40A and the initial dielectric layer 50A. The initial selection memory layer 40A and the initial dielectric layer 50A located on the side of the first electrode 10 away from the substrate 30 are retained to form the selection memory layer 40 and the dielectric layer 50 respectively.

[0175] S1.6: forming a second electrode 20 on a side of the dielectric layer 50 away from the gate memory layer 40 .

[0176] In some embodiments, reference Figure 5 During the etching process of the initial gate memory layer and the initial dielectric layer (S1.5), a plurality of gate memory layers 40 are formed, arranged and spaced apart in a second direction X. Furthermore, a plurality of dielectric layers 50 are formed, arranged and spaced apart in the second direction X. The second direction X intersects the thickness direction of the phase change memory 100. After etching the initial gate memory layer and the initial dielectric layer, S1.5 further includes: S1.5.2.

[0177] S1.5.2: Using a high aspect ratio process or an ethyl silicate process, material is deposited in the gaps between adjacent selection storage layers 40, in the gaps between adjacent dielectric layers 50, and on the side of multiple dielectric layers 50 away from the substrate 30 to form a first interlayer dielectric layer 70.

[0178] In some embodiments, reference Figure 5 , S1.5 After etching the initial selection memory layer 40A and the initial dielectric layer 50A and before forming the first interlayer dielectric layer 70, the preparation method further includes: S1.5.1.

[0179] S1.5.1: Deposit material on the side surfaces of the gate storage layer 40 , the side surfaces of the dielectric layer 50 , and the surface of the dielectric layer 50 away from the gate storage layer 40 to form an initial blocking layer 60A.

[0180] In the process of forming the first interlayer dielectric layer 70 , the first interlayer dielectric layer 70 covers the initial barrier layer 60A.

[0181] In some embodiments, reference Figure 5 , S1.6 forms a second electrode 20 on a side of the dielectric layer 50 away from the gate storage layer 40, including: S1.6.1 ~ S1.6.2.

[0182] S1.6.1: Etch the first interlayer dielectric layer 70 and the initial barrier layer 60A to expose at least a portion of the dielectric layer 50 .

[0183] S1.6.2: Form a second electrode 20 on the dielectric layer 50 .

[0184] In some embodiments, see Figure 5 The phase change memory 100 includes: a plurality of phase change memory cells P arranged in a second direction X, and the second direction X intersects with the thickness direction of the phase change memory 100. Figure 5 , S1.2 forms a first electrode 10 on the substrate 30, including: S1.2.1 to S1.2.4.

[0185] S1.2.1: Form a second interlayer dielectric layer 80 on the substrate 30 .

[0186] S1.2.2: Etch the second interlayer dielectric layer 80 to form a trench G.

[0187] S1.2.3: Deposit a conductive material on the surface of the second interlayer dielectric layer 80 away from the substrate 30 and the bottom surface and sidewalls of the trench G to form a first electrode 10 layer.

[0188] S1.2.4: Etch the first electrode 10 layer to remove the portion of the first electrode 10 layer located at the bottom of the trench G and the portion located on the surface of the second interlayer dielectric layer 80 away from the substrate 30. The portion of the first electrode 10 layer located on the side wall of the trench G is retained to form the first electrodes 10 of multiple phase change memory units P.

[0189] The above are only specific embodiments of the present application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A phase change memory, characterized in that: include: At least one phase-change memory unit, the phase-change memory unit comprising: a first electrode and a second electrode; A gate storage layer is provided between the first electrode and the second electrode; the material of the gate storage layer includes: a chalcogenide phase change material and a doping element doped in the chalcogenide phase change material; the doping element is configured to at least: make the crystallization temperature of the material of the gate storage layer higher than the crystallization temperature of the chalcogenide phase change material; The doping element accounts for 30% to 48% by mass of the material of the gate storage layer.

2. The phase change memory according to claim 1, wherein: The doping element includes at least one of group III non-metallic elements, group IV non-metallic elements, group V non-metallic elements and metal elements.

3. The phase change memory according to claim 2, wherein: The doping element includes at least one of carbon, nitrogen, silicon, arsenic, silver, boron, manganese, magnesium and aluminum.

4. The phase change memory according to claim 2, wherein: The doping element includes arsenic.

5. The phase change memory according to claim 4, wherein: The doping element further includes silicon.

6. The phase change memory according to claim 5, characterized in that In the material of the gate storage layer, the mass ratio of silicon to arsenic is in the range of 0.1 to 0.

5.

7. The phase change memory according to claim 1, wherein: The chalcogenide phase change material includes germanium and selenium.

8. The phase change memory according to claim 7, wherein: In the material of the gate storage layer, the mass ratio of the selenium element to the germanium element is in a range of 2 to 3.

9. The phase change memory according to any one of claims 1 to 8, wherein: The size of the selection memory layer in the first direction is in the range of 20 nm to 40 nm, and the first direction is the thickness direction of the phase change memory.

10. The phase change memory according to any one of claims 1 to 8, wherein: The phase change memory further includes: substrate; the at least one phase change memory unit is provided on the substrate, and the first electrode is closer to the substrate than the second electrode; The first electrode and the second electrode are sheet-shaped electrodes perpendicular to the substrate; the first electrode and the second electrode are arranged in a cross-arrangement.

11. The phase change memory according to claim 10, wherein: The thickness of the first electrode is in the range of 6 nm to 10 nm; and / or, The thickness of the second electrode ranges from 10 nm to 30 nm.

12. The phase change memory according to claim 10, wherein: The phase change memory unit further includes: A dielectric layer is provided between the second electrode and the selection storage layer.

13. The phase change memory according to claim 12, wherein: The phase change memory unit further includes: a portion of the barrier layer close to the substrate, arranged around the side of the strobe storage layer; a portion of the barrier layer away from the substrate, arranged around the side of the dielectric layer.

14. The phase change memory according to claim 13, wherein: The phase change memory comprises: a plurality of phase change memory cells arranged in a second direction, wherein the second direction intersects with a thickness direction of the phase change memory; Wherein, the barrier layers of any two adjacent phase-change memory units are connected to each other.

15. The phase change memory according to claim 10, wherein: The phase change memory comprises: a plurality of phase change memory layers stacked in a first direction, wherein the first direction is a thickness direction of the phase change memory; The phase-change memory layer includes: a plurality of the phase-change memory units arranged in a second direction, where the second direction intersects the first direction.

16. The phase change memory according to claim 15, wherein: In any two adjacent phase change memory units overlapped in the first direction in the multiple phase change memory layers, the second electrode of the phase change memory unit relatively close to the substrate is reused as the first electrode of the phase change memory unit relatively far from the substrate.

17. A method for preparing a phase change memory, characterized in that: include: forming at least one phase change memory cell; The phase change memory cell includes a first electrode, a second electrode and a gate storage layer; The selection storage layer is arranged between the first electrode and the second electrode; the material of the selection storage layer includes: a sulfur-based phase change material and an impurity element doped in the sulfur-based phase change material; the impurity element is at least configured to: make the crystallization temperature of the material of the selection storage layer greater than the crystallization temperature of the sulfur-based phase change material; wherein the mass proportion of the impurity element in the material of the selection storage layer is in the range of 30% to 48%.

18. The method for preparing a phase change memory according to claim 17, wherein: Forming the phase change memory unit includes: providing a substrate; forming a first electrode on the substrate; forming an initial gate storage layer on a side of the first electrode away from the substrate; forming an initial dielectric layer on a side of the initial selection memory layer away from the first electrode; Etching the initial gating memory layer and the initial dielectric layer, wherein the initial gating memory layer and the initial dielectric layer located on a side of the first electrode away from the substrate are retained to form a gating memory layer and a dielectric layer respectively; A second electrode is formed on a side of the dielectric layer away from the gate memory layer.

19. The method for preparing a phase change memory according to claim 18, wherein: During the etching of the initial gate memory layer and the initial dielectric layer, a plurality of gate memory layers arranged and spaced apart in a second direction are formed, and a plurality of dielectric layers arranged and spaced apart in the second direction are also formed, wherein the second direction intersects with a thickness direction of the phase change memory; After etching the initial selection memory layer and the initial dielectric layer, the method further includes: A high aspect ratio process or an ethyl silicate process is used to deposit materials in the gaps between adjacent gate storage layers, in the gaps between adjacent dielectric layers, and on the side of multiple dielectric layers away from the substrate to form a first interlayer dielectric layer.

20. The method for preparing a phase change memory according to claim 19, wherein: After etching the initial selection memory layer and the initial dielectric layer and before forming the first interlayer dielectric layer, the preparation method further includes: Depositing material on the side of the gate storage layer, the side of the dielectric layer, and the surface of the dielectric layer away from the gate storage layer to form an initial blocking layer; Wherein, during the process of forming the first interlayer dielectric layer, the first interlayer dielectric layer covers the initial barrier layer.

21. The method for preparing a phase change memory according to claim 20, wherein: The forming of the second electrode on a side of the dielectric layer away from the gate storage layer comprises: Etching the first interlayer dielectric layer and the initial barrier layer to expose at least a portion of the dielectric layer; The second electrode is formed on the dielectric layer.

22. The method for preparing a phase change memory according to claim 18, wherein: The phase change memory comprises: a plurality of phase change memory cells arranged in a second direction, wherein the second direction intersects with a thickness direction of the phase change memory; The step of forming a first electrode on the substrate comprises: forming a second interlayer dielectric layer on the substrate; etching the second interlayer dielectric layer to form a trench; Depositing a conductive material on a surface of the second interlayer dielectric layer away from the substrate, and on a bottom surface and sidewalls of the trench to form a first electrode layer; The first electrode layer is etched to remove a portion of the first electrode layer located at the bottom of the trench and a portion of the second interlayer dielectric layer located on the surface away from the substrate. A portion of the first electrode layer located on the sidewall of the trench is retained to form a plurality of first electrodes of the phase change memory cells.

23. A micro control unit, characterized in that: include: A control circuit and a phase change memory according to any one of claims 1 to 16; The control circuit is coupled to the phase change memory.

24. A controller, characterized in that: include: A circuit board and a micro control unit as claimed in claim 23; the micro control unit is coupled to the circuit board.

25. A vehicle, characterized in that: include: An execution unit and a controller as claimed in claim 24; The controller is used for the control execution unit.

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