Memory and memory system

Abstract

The invention provides a memory and a memory system. The memory comprises a substrate, memory cells and a first blocking structure, wherein the memory cells and the first blocking structure are separated from each other. The storage unit is located on the substrate, and the first blocking structure is located on the side wall of the storage unit. The first barrier structure comprises a first nitride layer, a first three-dimensional gallium nitride layer and a first oxide layer, the first nitride layer is located between the storage unit and the first three-dimensional gallium nitride layer, and the first three-dimensional gallium nitride layer is located between the first nitride layer and the first oxide layer. The first three-dimensional gallium nitride layer can protect the first nitride layer from being passivated by oxygen atoms, so that lattice distortion and generation of defects in the first nitride layer are reduced, the stability of the microstructure of the first nitride layer is maintained, stable distribution of atoms in a storage unit material is indirectly protected, and the electrical performance of the storage unit material is maintained. Moreover, the first three-dimensional gallium nitride layer can release the interface stress in the first nitride layer, thereby optimizing the microstructure of the storage unit material.

Description

Technical Field

[0001] The present application relates generally to the field of semiconductors, and more particularly to a memory and a storage system. Background Art

[0002] The development of artificial intelligence and integrated storage and computing technologies has placed higher demands on data storage and computing capabilities. In current von Neumann computing architectures, large amounts of data must be read and stored between dynamic random access memory (DRAM) and solid-state drives (SSDs). This significant performance gap between the two has led to a performance bottleneck in current von Neumann computing systems. Currently, the use of storage-class memory (SCM) to bridge DRAM and SSDs is being proposed to improve the current storage architecture. SCM must achieve speeds significantly faster than NAND and exhibit excellent non-volatility. Among several emerging SCM storage technologies, 3D crosspoint (3D Xpoint) memory is the most promising, offering advantages such as large capacity, high speed, non-volatility, and excellent cycle performance. Recently, research has become active on high-capacity non-volatile memory technologies, such as phase change memory (PCM) and selector-only memory (SOM), to mitigate the weaknesses of 3D Xpoint memory.

[0003] For phase-change memory and select-only memory, a linear barrier layer is typically formed on the sidewalls of the memory cell to protect the cell material from process influences. However, the linear barrier layer currently used can easily cause element segregation in the memory cell material, thereby affecting the electrical properties of the memory cell. Summary of the Invention

[0004] The purpose of the present application is to provide a memory and a storage system, aiming to reduce the segregation of elements in the storage unit material.

[0005] An embodiment of the present application provides a memory, comprising: a substrate; discrete memory cells located on the substrate; and a first barrier structure located on sidewalls of the memory cells, the first barrier structure comprising a first nitride layer, a first three-dimensional gallium nitride layer, and a first oxide layer, the first nitride layer being located between the memory cells and the first three-dimensional gallium nitride layer, and the first three-dimensional gallium nitride layer being located between the first nitride layer and the first oxide layer.

[0006] In some embodiments, the memory cell includes a stacked selection element and a memory element, the selection element is located between the memory element and the substrate; and the first blocking structure is located on a sidewall of the selection element or a sidewall of the memory element.

[0007] In some embodiments, the first blocking structure is located on a sidewall of the storage element, and the memory further includes: a second blocking structure located on a sidewall of the first blocking structure facing away from the storage element and on a sidewall of the selection element; wherein the second blocking structure includes a second nitride layer, a second three-dimensional gallium nitride layer, and a second oxide layer, the second nitride layer is located between the storage unit and the second three-dimensional gallium nitride layer, and the second three-dimensional gallium nitride layer is located between the second nitride layer and the second oxide layer.

[0008] In some embodiments, the second nitride layer is made of the same material as the first nitride layer, and the second oxide layer is made of the same material as the first oxide layer; the first nitride layer and the second nitride layer are made of silicon nitride, and the first oxide layer and the second oxide layer are made of silicon oxide.

[0009] In some embodiments, the memory cell includes a stacked first electrode, a gating layer, and a second electrode, the gating layer being located between the first electrode and the second electrode; the first blocking structure is located on the sidewalls of the first electrode, the sidewalls of the gating layer, and the sidewalls of the second electrode.

[0010] In some embodiments, the thickness of the first nitride layer is smaller than the thickness of the first oxide layer, and the thickness of the first three-dimensional gallium nitride layer is smaller than the thickness of the first oxide layer.

[0011] In some embodiments, the thickness of the first nitride layer is 0.5 to 1.5 nm, the thickness of the first three-dimensional gallium nitride layer is 0.5 to 1.5 nm, and the thickness of the first oxide layer is 1 to 1.5 nm.

[0012] In some embodiments, the dielectric constant of the first three-dimensional gallium nitride layer is within 20% of the dielectric constant of the first nitride layer.

[0013] In some embodiments, the density of the first three-dimensional gallium nitride layer is greater than the density of the first nitride layer.

[0014] An embodiment of the present application further provides a storage system, comprising: a memory as in any of the above embodiments; and a controller coupled to the memory and configured to control the memory.

[0015] In the memory device provided by the embodiments of the present application, the first three-dimensional gallium nitride layer protects the first nitride layer from passivation by oxygen atoms, thereby reducing lattice distortion and defect formation in the first nitride layer and maintaining the stability of the first nitride layer's microstructure. This indirectly protects the stable distribution of atoms in the memory cell material, thereby maintaining its electrical performance. Furthermore, the first three-dimensional gallium nitride layer relieves interfacial stress in the first nitride layer, thereby optimizing the microstructure of the memory cell material. The denser atomic arrangement limits the atomic diffusion rate, resulting in more optimized atomic mobility, thereby maintaining its electrical performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The following detailed description of the specific embodiments of the present application in conjunction with the accompanying drawings will make the technical solutions and other beneficial effects of the present application apparent.

[0017] Figure 1 1 is a schematic diagram of the three-dimensional structure of a memory provided by an embodiment of the present application;

[0018] Figure 2 yes Figure 1 Schematic diagram of the microstructure of the storage element and linear barrier layer under oxygen passivation;

[0019] Figure 3 yes Figure 2 A graph showing the mean square displacement of atoms in a storage element;

[0020] Figure 4 is a schematic diagram of the three-dimensional structure of a memory provided in some embodiments of the present application;

[0021] Figure 5 yes Figure 4 A schematic diagram of the cross-sectional structure of the memory;

[0022] Figure 6 yes Figure 5 Molecular structure diagram of the first three-dimensional gallium nitride layer;

[0023] Figure 7 is a schematic diagram of the microstructure of the phase change layer and the silicon nitride layer;

[0024] Figure 8 yes Figure 7 MSD curve of atoms in the phase change layer material;

[0025] Figure 9 yes Figure 7 Average void diameter distribution of atoms in the phase change layer material;

[0026] Figure 10 Schematic diagram of the microstructure of the phase change layer, silicon nitride layer and the first three-dimensional gallium nitride layer;

[0027] Figure 11yes Figure 10 MSD curve of atoms in the phase change layer material;

[0028] Figure 12 yes Figure 10 Average void diameter distribution of atoms in the phase change layer material;

[0029] Figure 13 This is a schematic diagram of the microstructure of the phase change layer and silicon nitride layer under oxygen passivation;

[0030] Figure 14 yes Figure 13 MSD curve of atoms in the phase change layer material;

[0031] Figure 15 This is a schematic diagram of the microstructure of the phase change layer and silicon nitride layer under oxygen passivation;

[0032] Figure 16 yes Figure 15 MSD curve of atoms in the phase change layer material;

[0033] Figure 17 is a schematic cross-sectional structural diagram of a memory provided in some embodiments of the present application;

[0034] Figure 18 This is a block diagram of a storage system provided in some embodiments of the present application. DETAILED DESCRIPTION

[0035] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of this application.

[0036] It should be understood that although the terms first, second, etc. may be used herein to describe various components, these components should not be limited by these terms. These terms are used to distinguish one component from another. For example, a first component can be referred to as a second component, and similarly, a second component can be referred to as a first component without departing from the scope of this application.

[0037] It should be understood that when a component is said to be "on" or "connected" to another component, it can be directly on or connected to the other component, or there may be intervening components. Other words used to describe the relationship between components should be interpreted in a similar manner.

[0038] As used herein, the term "layer" refers to a portion of a material that includes an area having a thickness. A layer may extend over the entire underlying or superstructure, or may have an extent that is less than the extent of the underlying or superstructure. In addition, a layer may be an area of a uniform or non-uniform continuous structure having a thickness that is less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any set of horizontal planes at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer that may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more second conductive layers and a contact layer and one or more dielectric layers.

[0039] It should be noted that the illustrations provided in the embodiments of the present application are only schematic illustrations of the basic concept of the present application. Although the illustrations only show components related to the present application and are not drawn according to the number, shape and size of components in actual implementation, the type, quantity and proportion of each component in actual implementation may be changed at will, and the component layout may also be more complicated.

[0040] See also Figures 1 to 3 , Figure 1 is a schematic diagram of the three-dimensional structure of a memory provided by an embodiment of the present application, Figure 2 yes Figure 1 Schematic diagram of the microstructure of the storage element and linear barrier layer under oxygen passivation. Figure 3 yes Figure 2 A graph showing the mean square displacement of atoms in a storage element.

[0041] The memory includes a first conductive line 10, a second conductive line 20, and a discrete memory cell 30 located between the first conductive line 10 and the second conductive line 20. The memory cell 30 includes a stacked selection element 31 and a storage element 32. The selection element 31 includes a bidirectional threshold switching material, and the storage element 32 includes a phase change material.

[0042] like Figure 1 As shown, a linear barrier layer 40 is formed on the sidewall of the memory element 32. The linear barrier layer 40 includes a silicon nitride layer 41 in contact with the memory element 32 and a silicon oxide layer 42 in contact with the silicon nitride layer 41. Since oxygen exists in the chamber during the etching process of the memory cell 30 and also exists in the chamber in subsequent processes, Figure 3 The silicon nitride layer 41 and the storage element 32 were tested under the passivation effect of oxygen, and a mean squared displacement (MSD) curve of each atom in the storage element 32 was obtained.

[0043] like Figure 3As shown, under the passivation effect of oxygen on silicon nitride layer 41, the mobility of atoms (e.g., In, Ge, Sb, Te) in storage element 32 increases dramatically, resulting in the storage element 32 being easily migrated under the action of an electric field, thus causing electrical failure. Where tot represents the average mobility of each atom.

[0044] In addition, the silicon nitride layer 41 (Si 3 N 4 ) itself has a large interface stress, which, as a sidewall structure, will cause obvious element segregation in the phase change material of the storage element 32 , thereby causing obvious stratification of elements.

[0045] Similarly, the silicon nitride layer 41 located on the sidewalls of the bidirectional threshold switch material of the select element 31 can easily cause element segregation in the bidirectional threshold switch material, thereby affecting the electrical properties of the device. Therefore, the linear barrier layer 40 composed of the silicon nitride layer 41 and the silicon oxide layer 42 can easily cause element segregation in the material of the memory cell 30, thereby affecting the electrical properties of the memory cell 30.

[0046] Based on this, an embodiment of the present application provides a memory, comprising: a substrate; mutually discrete memory cells located on the substrate; a first barrier structure located on the sidewalls of the memory cells, the first barrier structure comprising a first nitride layer, a first three-dimensional gallium nitride layer, and a first oxide layer, the first nitride layer being located between the memory cells and the first three-dimensional gallium nitride layer, and the first three-dimensional gallium nitride layer being located between the first nitride layer and the first oxide layer.

[0047] In the memory device provided by the embodiments of the present application, the first three-dimensional gallium nitride layer protects the first nitride layer from passivation by oxygen atoms, thereby reducing lattice distortion and defect formation in the first nitride layer and maintaining the stability of the first nitride layer's microstructure. This indirectly protects the stable distribution of atoms in the memory cell material, thereby maintaining its electrical performance. Furthermore, the first three-dimensional gallium nitride layer relieves interfacial stress in the first nitride layer, thereby optimizing the microstructure of the memory cell material. The denser atomic arrangement limits the atomic diffusion rate, resulting in more optimized atomic mobility, thereby maintaining its electrical performance.

[0048] The structure of the memory provided in the embodiments of the present application is described below with reference to the accompanying drawings.

[0049] See also Figures 4 to 6 , Figure 4 is a schematic diagram of the three-dimensional structure of a memory provided in some embodiments of the present application, Figure 5 yes Figure 4 Schematic diagram of the cross-sectional structure of the memory, Figure 6 yes Figure 5 Molecular structure diagram of the first three-dimensional gallium nitride layer.

[0050] The memory device 100 includes a substrate 1, discrete memory cells 30, and a first barrier structure 50. The memory cells 30 are located on the substrate 1, and the first barrier structure 50 is located on the sidewalls of the memory cells 30. The first barrier structure 50 includes a first nitride layer 51, a first three-dimensional gallium nitride layer 52, and a first oxide layer 53. The first nitride layer 51 is located between the memory cells 30 and the first three-dimensional gallium nitride layer 52, and the first three-dimensional gallium nitride layer 52 is located between the first nitride layer 51 and the first oxide layer 53.

[0051] The memory 100 may further include a first conductive line 10 and a second conductive line 20 , and each memory cell 30 is located between the first conductive line 10 and the second conductive line 20 and at a crossing point between the first conductive line 10 and the second conductive line 20 .

[0052] The first barrier structure 50 may be located on the entire sidewall of the memory cell 30 or on a portion of the sidewall of the memory cell 30. The first barrier structure 50 may be disposed around the four sidewalls of the memory cell 30 to protect the memory cell 30 from the effects of the manufacturing process.

[0053] like Figure 5 As shown, this embodiment takes a phase change memory as an example, and the memory unit 30 includes a selection element 31 and a memory element 32 that are stacked. The selection element 31 is located between the memory element 32 and the substrate 1 .

[0054] The selection element 31 may include a first electrode 311, a bidirectional threshold switching layer 312, and a second electrode 313. The bidirectional threshold switching layer 312 is located between the first electrode 311 and the second electrode 313. The storage element 32 may include a phase change layer 321 and a third electrode 322. The phase change layer 321 is located between the second electrode 313 and the third electrode 322.

[0055] The material of the phase change layer 321 may include a first chalcogenide compound, and the first chalcogenide compound includes at least one of a germanium telluride (Ge-Te) compound, an antimony telluride (Sb-Te) compound, a germanium antimony telluride (Ge-Sb-Te) compound, a silicon antimony telluride (Si-Sb-Te) compound, a titanium antimony telluride (Ti-Sb-Te) compound, an aluminum antimony telluride (Al-Sb-Te) compound, a germanium antimony selenide (Ge-Sb-Se); a germanium selenide gallium (Ge-Sb-Ga); and a germanium selenium bismuth (Ge-Sb-Bi).

[0056] The material of the bidirectional threshold switch layer 312 may include a second chalcogenide, and the first chalcogenide and the second chalcogenide may be made of different materials. For example, the second chalcogenide includes at least one of AsSeGe, SeGe, AsSe, InAsSeGe, SiAsSeGe, InSiAsSeGe, Ge-Te, B-Te, Ge-Te-As, Ge-S, Ga-S, and Ge-As-S.

[0057] It should be noted that the first barrier structure 50 can be regarded as a whole, that is, the first nitride layer 51, the first three-dimensional gallium nitride layer 52 and the first oxide layer 53 in the first barrier structure 50 can extend to the sidewall of the memory cell 30 to the same length.

[0058] The first barrier structure 50 can be located on the sidewalls of the selection element 31 to protect the selection element 31 and improve the element segregation phenomenon in the material of the bidirectional threshold switch layer 312. Alternatively, the first barrier structure 50 can be located on the sidewalls of the storage element 32 to protect the storage element 32 and improve the element segregation phenomenon in the material of the bidirectional phase change layer 321. Alternatively, the first barrier structure 50 can be located on the sidewalls of the selection element 31 and the sidewalls of the storage element 32 to improve the element segregation phenomenon in the material of the bidirectional threshold switch layer 312 and the material of the phase change layer 321.

[0059] Figure 5 The first barrier structure 50 is shown as being located on the sidewall of the memory element 32, that is, directly contacting the sidewall of the memory element 32. The memory 100 may further include a second barrier structure 50a, located on the sidewall of the first barrier structure 50 facing away from the memory element 32, and on the sidewall of the selection element 31. The second barrier structure 50a includes a second nitride layer 51a, a second three-dimensional gallium nitride layer 52a, and a second oxide layer 53a. The second nitride layer 51a is located between the memory cell 30 and the second three-dimensional gallium nitride layer 52a, and the second three-dimensional gallium nitride layer 52a is located between the second nitride layer 51a and the second oxide layer 53a.

[0060] The primary function of the second three-dimensional gallium nitride layer 52a is to protect the second nitride layer 51a from passivation by oxygen atoms, thereby maintaining the stability of the microstructure of the second nitride layer 51a and indirectly protecting the stable distribution of atoms in the material of the selection element 31. The second barrier structure 50a is also located on the outer sidewall of the first barrier structure 50, which simplifies the process and improves the protection of the storage element 32.

[0061] It should be noted that the second barrier structure 50a can be regarded as a whole, that is, the second nitride layer 51a, the second three-dimensional gallium nitride layer 52a and the second oxide layer 53a in the second barrier structure 50a can extend to the same length on the sidewall of the memory cell 30.

[0062] In some embodiments, the second nitride layer 51a is made of the same material as the first nitride layer 51, and the second oxide layer 53a is made of the same material as the first oxide layer 53. The first nitride layer 51 and the second nitride layer 51a are made of silicon nitride, and the first oxide layer 53 and the second oxide layer 53a are made of silicon oxide. In this way, the first barrier structure 50 and the second barrier structure 50a are formed using the same process, but at different locations, which can simplify the process.

[0063] In the above Figure 1 In the embodiment, the thickness of the silicon oxide layer 42 can be comparable to the thickness of the silicon nitride layer 41, and the thickness of the first oxide layer 53 can be comparable to the thickness of the silicon nitride layer 41. Figure 1 The thickness of the silicon oxide layer 42 is the same, and the sum of the thickness of the first nitride layer 51 and the first three-dimensional gallium nitride layer 52 can be equal to Figure 1 The thickness of the silicon nitride layer 41 is the same. Thus, the thickness of the first nitride layer 51 is less than the thickness of the first oxide layer 53, and the thickness of the first three-dimensional gallium nitride layer 52 is less than the thickness of the first oxide layer 53. In this way, the thickness of the barrier structure on the sidewall of the memory cell 30 can be kept substantially unchanged, wherein the first nitride layer 51 and the first three-dimensional gallium nitride layer 52 are used instead of Figure 1 The silicon nitride layer 41 in the embodiment has a substantially constant thickness, which can enhance protection of the memory cell 30 while reducing the impact on the electrical properties of the memory cell 30 .

[0064] For example, the thickness of the first nitride layer 51 is 0.5-1.5 nm, the thickness of the first three-dimensional gallium nitride layer 52 is 0.5-1.5 nm, and the thickness of the first oxide layer 53 is 1-1.5 nm. Thus, the provision of the first three-dimensional gallium nitride layer 52 does not increase the size of the memory cell 30.

[0065] In some embodiments, the dielectric constant of the first 3D GaN layer 52 is within 20% of the dielectric constant of the first nitride layer 51. This ensures that the first 3D GaN layer 52 can meet various performance requirements (such as leakage) of the memory cell 30.

[0066] In some embodiments, the density of the first three-dimensional gallium nitride layer 52 is greater than the density of the first nitride layer 51. By creating an interface density difference, the system's antioxidant capacity is enhanced, thereby improving the stability of the material in the memory cell 30.

[0067] The following combination Figures 7 to 12 The simulation test is used to illustrate the influence of the first three-dimensional gallium nitride layer 52 on the atomic mobility and atomic void diameter in the phase change layer 321 material.

[0068] Figures 7 to 9 The interaction between the phase change layer 321 and the silicon nitride layer 41 (Si3N4) is shown. Figure 7 is a schematic diagram of the microstructure of the phase change layer 321 and the silicon nitride layer 41. Figure 8 yes Figure 7 MSD curve of atoms in the phase change layer 321 material, Figure 9 yes Figure 7 The average void diameter distribution of atoms in the phase change layer 321 material.

[0069] Microstructural analysis shows that due to the large interface stress at the Si3N4 interface, the phase change layer 321 material will be induced to undergo obvious phase segregation. Figure 7 The dashed line in the figure indicates significant delamination. Phase segregation creates larger atomic gaps (2.415 Å), which promotes atomic diffusion. This is particularly evident for Ge and Te atoms, as evidenced by a significant increase in their mobility distribution (MSD).

[0070] Figures 10 to 12 The interaction between the phase change layer 321, the silicon nitride layer (Si3N4) 41 and the first three-dimensional gallium nitride layer (three-dimensional GaN) 52 is shown. Figure 10 is a schematic diagram of the microstructure of the phase change layer 321, the silicon nitride layer 41 and the first three-dimensional gallium nitride layer 52, Figure 11 yes Figure 10 MSD curve of atoms in the phase change layer 321 material, Figure 12 yes Figure 10 The average void diameter distribution of atoms in the phase change layer 321 material, wherein the void diameter corresponding to the peak value of the distribution is the average void diameter.

[0071] The presence of three-dimensional GaN releases part of the interface stress in Si3N4, thereby optimizing the microstructure of the phase change material. The tighter atomic arrangement limits the diffusion rate of atoms, resulting in a more optimized atomic mobility. It can be seen that the migration of Ge and Te atoms is significantly optimized.

[0072] The following combination Figures 13 to 16 The influence of the first three-dimensional gallium nitride layer 52 on the atomic mobility in the phase change layer 321 material under the passivation effect of oxygen is illustrated through simulation tests.

[0073] Figure 13 and Figure 14 The phase change layer 321 and the silicon nitride layer 41 (Si3N4) are shown under the passivation effect of oxygen, wherein Figure 13 is a schematic diagram of the microstructure of the phase change layer 321 and the silicon nitride layer 41 under the effect of oxygen passivation. Figure 14 yes Figure 13 MSD curve of atoms in the phase change layer 321 material.

[0074] Since the passivation of oxygen atoms destroys the structure of Si3N4, the microstructure of the phase change layer 321 material in contact with Si3N4 undergoes a huge change, and the atomic gaps are further increased, resulting in a dramatic atomic diffusion rate.

[0075] Figures 15 and 16 The phase change layer 321, the silicon nitride layer 41 (Si3N4) and the first three-dimensional gallium nitride layer (three-dimensional GaN) 52 are shown under the passivation effect of oxygen, wherein Figure 15 is a schematic diagram of the microstructure of the phase change layer 321 and the silicon nitride layer 41 under the effect of oxygen passivation. Figure 16 yes Figure 15 MSD curve of atoms in the phase change layer 321 material.

[0076] The presence of 3D GaN protects Si3N4 from oxygen passivation, maintaining the stability of the Si3N4 microstructure and indirectly protecting the stable distribution of atoms in the phase-change layer 321. Furthermore, it can be seen that the 3D GaN microstructure does not significantly change after being passivated by oxygen atoms, indicating that its stable structure helps protect the phase-change material.

[0077] See also Figure 17 , Figure 17 is a schematic diagram of the cross-sectional structure of the memory provided by some embodiments of the present application. Figure 5 The embodiments differ in the type of memory.

[0078] This embodiment takes a select-only memory as an example. The memory cell 30 includes a stacked first electrode 301, a gating layer 302, and a second electrode 303. The gating layer 302 is located between the first electrode 301 and the second electrode 303. The first blocking structure 50 is located on the sidewalls of the first electrode 301, the sidewalls of the gating layer 302, and the sidewalls of the second electrode 303.

[0079] The gating layer 302 material may include an ovonic threshold switch (OTS) material, such as a chalcogenide, wherein the chalcogenide includes at least one of AsSeGe, SeGe, AsSe, InAsSeGe, SiAsSeGe, InSiAsSeGe, Ge-Te, B-Te, Ge-Te-As, Ge-S, Ga-S, and Ge-As-S.

[0080] The first three-dimensional gallium nitride layer 52 in the first barrier structure 50 can protect the first nitride layer 51 from passivation by oxygen atoms and release the interface stress of the first nitride layer 51 , thereby maintaining the stability of the material of the gate layer 302 .

[0081] The present application also provides a storage system. Figure 18 , Figure 18 This is a block diagram of a storage system provided in some embodiments of the present application.

[0082] The storage system 200 includes: a memory 201 , which is the memory in any of the above embodiments; and a controller 202 coupled to the memory 201 and configured to control the memory 201 .

[0083] The description of the above embodiments is only used to help understand the technical solutions and core ideas of this application; ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A memory, characterized in that: include: substrate; Separate memory cells are located on the substrate; A first blocking structure is located on a sidewall of the memory cell, the first blocking structure comprising a first nitride layer, a first three-dimensional gallium nitride layer, and a first oxide layer, the first nitride layer being located between the memory cell and the first three-dimensional gallium nitride layer, and the first three-dimensional gallium nitride layer being located between the first nitride layer and the first oxide layer.

2. The memory according to claim 1, wherein The memory cell includes a selection element and a memory element that are stacked, wherein the selection element is located between the memory element and the substrate; The first blocking structure is located on a sidewall of the selection element or a sidewall of the storage element.

3. The memory according to claim 2, wherein: The first blocking structure is located on a sidewall of the storage element, and the memory further comprises: a second blocking structure located on a sidewall of the first blocking structure facing away from the storage element and a sidewall of the selection element; The second blocking structure includes a second nitride layer, a second three-dimensional gallium nitride layer, and a second oxide layer. The second nitride layer is located between the storage unit and the second three-dimensional gallium nitride layer. The second three-dimensional gallium nitride layer is located between the second nitride layer and the second oxide layer.

4. The memory according to claim 3, wherein: The second nitride layer is made of the same material as the first nitride layer, and the second oxide layer is made of the same material as the first oxide layer; The materials of the first nitride layer and the second nitride layer are silicon nitride, and the materials of the first oxide layer and the second oxide layer are silicon oxide.

5. The memory according to claim 1, wherein: The memory cell comprises a first electrode, a gating layer, and a second electrode that are stacked, wherein the gating layer is located between the first electrode and the second electrode; The first blocking structure is located on a sidewall of the first electrode, a sidewall of the gating layer, and a sidewall of the second electrode. The memory according to claim 1 , wherein: The thickness of the first nitride layer is smaller than the thickness of the first oxide layer, and the thickness of the first three-dimensional gallium nitride layer is smaller than the thickness of the first oxide layer.

7. The memory according to claim 6, wherein: The thickness of the first nitride layer is 0.5 to 1.5 nm, the thickness of the first three-dimensional gallium nitride layer is 0.5 to 1.5 nm, and the thickness of the first oxide layer is 1 to 1.5 nm.

8. The memory according to claim 1, wherein: The dielectric constant of the first three-dimensional gallium nitride layer is within 20% of the dielectric constant of the first nitride layer.

9. The memory according to claim 1, wherein: The density of the first three-dimensional gallium nitride layer is greater than the density of the first nitride layer.

10. A storage system, characterized in that: include: The memory according to any one of claims 1 to 9; as well as A controller is coupled to the memory and configured to control the memory.

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