Shield gate MOSFET structure and process method

Abstract

The invention discloses a shield gate MOSFET structure and a process method, a shield gate dielectric layer at the lower part has a thickness change with a thick lower part and a thin upper part, the shield gate dielectric layer is matched with a shield gate with a wider section to form a field plate structure, and the upper top surface of the shield gate forms an arc protruding upwards; meanwhile, an arc-shaped concave surface is formed at the bottom of the upper grid to half wrap the upper part of the shield grid, the thicker shield grid in the middle section serves as an internal field plate, and the electric field distribution of a drift region is optimized; and the thinner gate oxide layer at the middle section of the shielding gate is enhanced and assisted to deplete, so that a new electric field peak value is formed, the withstand voltage of the device is improved, and meanwhile, higher doping concentration of a drift region is allowed, so that lower on-resistance is obtained. After the bottom of the complete gate polycrystalline silicon is removed, a certain hollow structure is formed, and the parasitic capacitance of the gate is reduced, so that the withstand voltage BVDS of the device is higher, the on resistance Rdson is lower, the RSP is smaller, and the dynamic characteristic is better.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor devices and process manufacturing, and in particular to a process method for shielded gate MOSFET. Background Art

[0002] The shielded-gate MOSFET (SGT MOSFET) is a semiconductor device widely used in medium- and low-voltage power devices. Compared to traditional MOSFETs, SGT MOSFETs not only increase switching speed but also reduce switching losses, making them highly competitive in a variety of applications, including power management, motor drives, current switching in DC / DC and AC / DC subsystems, load switching, and fast / wireless charging. The gate structure of an SGT device consists of shielding polysilicon and a polysilicon gate. The shielding polysilicon, also known as the source polysilicon, is formed in a trench. Depending on the placement of the shielding polysilicon and polysilicon gate in the trench, SGT devices are typically categorized as either a top-and-bottom structure or a left-and-right structure. In the top-and-bottom structure, the shielding gate polysilicon is located in the lower portion of the trench, while the polysilicon gate is located in the upper portion. An insulating dielectric layer separates the polysilicon gate and shielding polysilicon.

[0003] The source-drain on-resistance (RDSon) of a power MOSFET is a key parameter. RDSon is the resistance between the drain (D) and source (S) when the MOSFET is operating, measured in ohms. For similar MOSFET devices, the smaller the RDSon value, the lower the losses (power loss) during operation. For MOSFETs, RDSon is used to calculate power consumption. The power consumed by a MOSFET, PD, is expressed as the MOSFET's own RDSon multiplied by the square of the drain current (ID): PD = on-resistance RDSon * drain current ID 2 .

[0004] Since the consumed power will be dissipated as heat, which will have a negative impact on the equipment, certain countermeasures are taken during circuit design to reduce heat generation, that is, reduce power consumption.

[0005] Since the main cause of MOSFET heat generation is the on-resistance RDSon, RDSon is generally required to be below the Ω level in general applications.

[0006] like Figure 1Figure 2 shows a cross-sectional view of a shielded-gate trench MOSFET with a top-bottom structure. The on-resistance, Rdson, is primarily composed of RCH + REPI + RSUB. The device's breakdown voltage (BVDSS) requirements are increasing, which in turn requires an epitaxial layer with a lower doping concentration. Breakdown voltage and low on-resistance are contradictory. As the breakdown voltage increases, REPI significantly increases. Summary of the Invention

[0007] The technical problem to be solved by the present invention is to provide a shielded gate trench MOSFET structure. Another technical problem to be solved by the present invention is to provide a process method for the shielded gate trench MOSFET.

[0008] To solve the above problems, the present invention provides a method for preparing a shielded gate MOSFET, comprising: Step 1: providing a semiconductor substrate of the first conductivity type, forming an epitaxial layer of the first conductivity type on the semiconductor substrate; depositing a hard mask layer, defining a trench etching area on the hard mask layer by photolithography and etching, and performing trench etching to form a plurality of trenches; Step 2: growing a liner layer to cover the inside of the trench and the surface of the epitaxial layer; Step 3: Filling the dielectric layer with a high selectivity ratio to fill most of the trenches completely; Step 4: removing a portion of the high selectivity filling dielectric layer to define the height of the gate dielectric layer in the trench; and removing the sidewall liner layer in the exposed area of the trench; Step 5: etching again to completely remove all remaining high selectivity dielectric layers inside the trench; depositing a gate dielectric layer on the inner wall of the trench and performing an annealing process; Step 6: performing a first polysilicon deposition to fill the trench; Step seven, grinding and etching back the polysilicon to form a shield gate in the trench; removing the hard mask layer on the surface of the epitaxial layer; Step eight, forming a sacrificial oxide layer and etching back; forming a gate dielectric layer; fusing the gate dielectric layer with the original liner layer inside the trench to wrap and isolate the shielding gate; Step nine, performing a second polysilicon deposition to fill the remaining trenches; Step 10, etching back the second deposited polysilicon to form the gate of the shielded gate MOSFET; implanting the second conductivity type well region and the first conductivity type heavily doped region; Step 11: depositing an interlayer dielectric layer, performing contact hole etching in the interlayer dielectric layer to form a contact hole; the bottom of the contact hole is located in the well region; performing ion implantation at the bottom of the contact hole to form a contact lead region; Step 12: depositing a work function layer on the entire wafer surface, the work function layer covering the inner wall of the contact hole, and then depositing the contact hole filling metal and etching back to form a contact hole structure; Step 13: deposit a top metal layer on the entire wafer surface, and etch back to form a top metal interconnect; deposit a pad oxide layer and etch back.

[0009] Furthermore, in step 1, the semiconductor substrate is a silicon substrate, a silicon germanium substrate, a gallium arsenide substrate, a silicon carbide substrate, or a gallium nitride substrate; and the hard mask layer is a silicon oxide layer.

[0010] Furthermore, in the step 2, the liner layer is a silicon oxide layer, formed by a furnace tube process; the liner layer formed by oxidation is connected to the hard mask layer on the epitaxial surface as a whole.

[0011] Furthermore, in the step three, the filled dielectric layer is a dielectric layer with a high selectivity ratio.

[0012] Furthermore, in step 4, the high selectivity dielectric layer is a photoresist; and the residual amount of the photoresist in the groove is achieved by controlling different photolithography exposure doses.

[0013] Furthermore, in step five, the gate dielectric layer is a silicon oxide layer, which is deposited using a CVD process; after the silicon oxide layer is deposited, thermal annealing is performed to ensure the quality of the pad oxide layer.

[0014] Furthermore, in the step seven, the grinding process adopts a CMP process to grind to the surface of the epitaxial layer and remove all the polysilicon on the surface of the epitaxial layer; and the polysilicon in the trench is removed by a dry etching process.

[0015] Furthermore, in the step eight, a sacrificial oxide layer is formed and removed by back etching to repair the damage to the polysilicon caused by the previous dry etching process and form an arc-shaped morphology on the top of the polysilicon.

[0016] Furthermore, in the step eleven, the interlayer dielectric layer is a stack of a silicon oxide layer and borophosphosilicate glass.

[0017] Furthermore, in the step 12, the work function layer is a Ti / TiN layer to increase adhesion with the substrate material; tungsten metal is deposited inside the contact hole and wet-etched back to form a contact hole structure.

[0018] Furthermore, in step thirteen, the top metal is an aluminum-copper alloy.

[0019] The first conductivity type is N-type, and the second conductivity type is P-type.

[0020] The present invention provides a shielded gate MOSFET, comprising: An epitaxial layer of the first conductivity type is provided on a semiconductor substrate of the first conductivity type, and an interlayer dielectric layer is provided on a surface of the epitaxial layer; The epitaxial layer has a plurality of parallel trenches, and the trenches have a shielding grid located in the lower part of the trenches and a gate located in the upper part of the trenches; a gate dielectric layer is provided between the shielding grid and the gate and the epitaxial layer material of the trenches; The gate dielectric layers on both sides of the shielding grid are thin in the middle and thick at the upper and lower ends, so that the cross-sectional morphology of the isolated shielding grid is a spindle shape with opposite shapes, thick in the middle and thin at the two ends, and the top of the shielding grid has an upwardly convex arc surface; The gate is located above the shielding grid, with its upper top surface being a horizontal plane and its lower bottom surface being an inwardly concave arc surface that matches the upper top surface of the shielding grid, so that the upper gate half-wraps the upper top surface of the lower shielding grid, and a portion of the grounded shielding grid is widened to serve as an internal field plate to optimize the electric field distribution in the drift region.

[0021] The epitaxial layer between the trenches has a well region of the second conductivity type and a heavily doped region of the first conductivity type, and the depth of the well region exceeds that of the heavily doped region.

[0022] The interlayer dielectric layer is a stacked layer, comprising a lower silicon oxide layer and an upper BPSG layer; the interlayer dielectric layer is covered with a top metal layer and connected to the well region via a contact hole penetrating the interlayer dielectric layer.

[0023] The first conductivity type is N-type, and the second conductivity type is P-type.

[0024] The shielded gate MOSFET described in the present invention is a trench-type shielded gate MOSFET with an upper and lower structure. The lower shielding gate is formed into a spindle shape with a thick middle and thin ends. At the same time, the bottom of the upper gate forms an arc-shaped concave surface to form a semi-wrapped shape on the upper part of the shielding gate. The thicker shielding gate in the middle section serves as an internal field plate to optimize the electric field distribution in the drift region. The thinner gate oxide layer in the middle section of the shielding gate enhances auxiliary depletion, forming a new electric field peak, improving the device's withstand voltage, while allowing a higher drift region doping concentration and thus lowering the on-resistance. The bottom of the complete gate polysilicon is removed to form a certain hollow structure, reducing the parasitic capacitance of the gate, resulting in a higher withstand voltage (BVDS) of the device, a lower on-resistance (Rdson), a smaller RSP, and better dynamic characteristics. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is a schematic diagram of the cross-sectional structure of an existing shielded gate MOSFET.

[0026] Figure 2 yes Figure 1 Schematic diagram of the on-resistance composition of the cross-sectional structure of the shielded gate MOSFET shown.

[0027] Figure 3 It is a schematic diagram of the cross-sectional structure of the shielded gate MOSFET disclosed in the present invention.

[0028] Figure 4 This is a schematic diagram of process step 1 of the present invention, which completes hard mask deposition and trench etching.

[0029] Figure 5 It is a schematic diagram of the second process step of the present invention, growing a liner oxide layer.

[0030] Figure 6 It is a schematic diagram of the third process step of the present invention, which is depositing a high selectivity dielectric layer.

[0031] Figure 7 This is a schematic diagram of process step four of the present invention, which is etching back of the high selectivity dielectric layer.

[0032] Figure 8 It is a schematic diagram of the fifth process step of the present invention, depositing a gate dielectric layer.

[0033] Figure 9 This is a schematic diagram of process step six of the present invention, the first polysilicon deposition.

[0034] Figure 10 This is a schematic diagram of process step seven of the present invention, in which the polysilicon deposited for the first time is etched back to form a shielding grid.

[0035] Figure 11 It is a schematic diagram of process step eight of the present invention, depositing a gate dielectric layer.

[0036] Figure 12 It is a schematic diagram of the ninth step of the process of the present invention, in which a second polysilicon deposition is performed.

[0037] Figure 13 This is a schematic diagram of step ten of the process of the present invention, which is the second polysilicon etching back and well region implantation.

[0038] Figure 14 This is a schematic diagram of process step eleven of the present invention, which includes depositing interlayer dielectric and etching contact holes.

[0039] Figure 15 Schematic diagram of step twelve of the process of the present invention, forming a contact hole structure.

[0040] Figure 16 It is a schematic diagram of process step thirteen of the present invention, forming a top metal interconnection.

[0041] Description of Reference Numerals 1 is the substrate, 2 is the epitaxial layer, 3 is the oxide layer, 4 is the shield gate (polysilicon), 5 is the gate (polysilicon), 6 is the N+ injection region, 7 is the P well, 8 is the metal in the contact hole (tungsten), 9 is Ti / TiN, 10 is the top metal layer (AiCu), 11 is the injection region at the bottom of the contact hole, 12 is the interlayer dielectric layer (BPSG), 13 is the hard mask, and 14 is the high selectivity filling dielectric layer (photoresist). DETAILED DESCRIPTION

[0042] The following is a specific embodiment of the present invention in conjunction with the accompanying drawings, which clearly and completely describes the technical solutions in the present invention, but the present invention is not limited to the following embodiments. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. According to the following description and claims, the advantages and features of the present invention will be clearer. It should be noted that the drawings are all in a very simplified form and use non-precise ratios, which are only used to conveniently and clearly assist in explaining the embodiments of the present invention. All other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0043] The present invention can be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, providing these embodiments will make the disclosure thorough and complete and fully convey the scope of the present invention to those skilled in the art. In the accompanying drawings, for clarity, the sizes and relative sizes of layers and regions may be exaggerated, and the same reference numerals represent the same elements throughout. In the description of this application, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inside", "outside", etc. is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing this application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the application. In addition, the terms "first", "second", and "third" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.

[0044] To further reduce the on-resistance (Rdson) of shielded-gate trench SGT MOSFET devices, this invention modifies the morphology of the grounded shield gate, widening a portion to serve as an internal field plate and optimizing the electric field distribution in the drift region. Furthermore, a thin oxide layer in the middle of the shield gate enhances auxiliary depletion, forming a new electric field peak, increasing the device's withstand voltage while allowing for higher drift region doping concentrations, resulting in lower on-resistance. The bottom of the entire gate polysilicon is removed to create a hollow structure, reducing gate parasitic capacitance and thereby improving the device's gate charge and switching characteristics.

[0045] The structure of the device of the present invention is as follows Figure 3 As shown, an N-type epitaxial layer is provided on an N-type silicon substrate 1, and an interlayer dielectric layer is covered on the surface of the epitaxial layer; the interlayer dielectric layer 12 is a composite laminate, including a silicon oxide layer at the bottom and borophosphosilicate glass BPSG at the top.

[0046] The epitaxial layer 2 has multiple parallel trenches, as shown in the figure. It should be noted that the present invention primarily addresses the trenches in the active area. The structure and process of the trenches in the non-active area (as shown on the right side of the figure) are beyond the scope of this invention and are provided for illustrative purposes only.

[0047] The trench has a shield gate 4 located in the lower part of the trench and a gate 5 in the upper part of the trench; a gate dielectric layer (silicon oxide layer) 3 is provided between the shield gate and the gate and the epitaxial layer material of the trench, which is generally an insulating material with a high dielectric constant and stable performance. In this embodiment, it is made of silicon oxide; the shield gate and the gate are made of polysilicon, the gate is the gate of the control channel of the MOSFET device, and the shield gate is connected to the ground potential.

[0048] The gate dielectric layers on both sides of the shielding grid located at the bottom of the trench are thin in the middle and thick at the top and bottom ends, giving the isolated shielding grid a spindle-shaped cross-section, with a thick center and thin ends. The top of the shielding grid has an upwardly convex curved surface. The thicker center portion of the shielding grid acts as an internal field plate, optimizing the electric field distribution in the drift region.

[0049] The gate is located above the shielding gate, its upper top surface is a horizontal plane, and its lower bottom surface is an inwardly concave arc surface that matches the upper top surface of the shielding gate, that is, the upper gate forms a cover that matches the morphology of the lower shielding gate, so that the upper gate half-wraps the upper top surface of the lower shielding gate, and a part of the grounded shielding gate is widened as an internal field plate to optimize the electric field distribution in the drift region; and a thin oxide layer in the middle section of the shielding gate enhances auxiliary depletion to form a new electric field peak, thereby improving the device's withstand voltage and allowing a higher drift region doping concentration to obtain a lower on-resistance. After the bottom of the complete gate polysilicon is removed, a certain hollow structure is formed to reduce the parasitic capacitance of the gate, thereby improving the gate charge and switching characteristics of the device.

[0050] The epitaxial layer between the trenches has a P-type well region 7 and an N-type heavily doped region 6 , and the depth of the well region exceeds that of the heavily doped region.

[0051] The interlayer dielectric layer is covered with a top metal layer 10 and connected to the well region 7 via a contact hole that penetrates the interlayer dielectric layer. A contact hole injection region is provided at the bottom of the contact hole to reduce the contact resistance of the contact region. A work function layer 9 is first attached to the inner wall of the contact hole. The work function layer acts as an intermediate transition layer to increase the adhesion between the metal material and the silicon epitaxial layer and the interlayer dielectric layer, thereby improving the stability of the contact hole. The contact hole is filled with metal tungsten, and metal aluminum and copper are deposited on the surface of the interlayer dielectric layer. The metal aluminum and copper are in contact with the metal tungsten in the contact hole, and the metal tungsten in the contact hole is in contact with the contact hole injection region, forming an electrical lead.

[0052] The process method of shielded gate MOSFET of the present invention comprises: Step 1: Provide an N-type semiconductor substrate 1, such as a conventional silicon substrate. Other common semiconductor substrate materials in the industry, such as gallium nitride, silicon carbide, etc., also conform to the process ideas and principles of the present invention. Form an N-type epitaxial layer 2 on the silicon substrate. Deposit a hard mask layer 13, such as a silicon oxide layer, on the surface of the epitaxial layer. The hard mask layer in the present invention is a composite layer of silicon oxide-silicon nitride-silicon oxide; photolithography and etching define a groove etching area on the hard mask layer, and perform groove etching to form multiple parallel grooves, such as Figure 4 shown.

[0053] Step 2: Use furnace tube process to grow the liner layer, and cover the inside of the trench and the surface of the epitaxial layer with a liner layer, refer to Figure 5 The liner layer is a silicon oxide layer, which is integrated with the top oxide layer of the previous hard mask layer.

[0054] Step 3: Fill the dielectric layer with a high selectivity ratio to fill most of the trenches. Figure 6 The high selectivity filling dielectric layer in this embodiment uses a photoresist 14, and the effect on other film properties when etching the photoresist is minimized.

[0055] Step 4: remove part of the high selectivity filling dielectric layer to define the height of the gate dielectric layer in the trench, such as Figure 7 As shown in FIG. 1 , the sidewall liner layer in the exposed area of the trench is removed; the trench sidewall above the remaining photoresist is exposed again. The amount of photoresist remaining in the trench can be adjusted by controlling different photolithography exposure doses.

[0056] Step 5: Etching is performed again to completely remove all the remaining high selectivity dielectric layers in the trench; a gate dielectric layer, such as a silicon oxide layer, is deposited on the inner wall of the trench using a CVD process. Figure 8 After the silicon oxide layer is deposited, a thermal anneal is performed to ensure the quality of the liner oxide layer. The thickness of the newly deposited oxide layer at the bottom of the trench overlaps with the thickness of the original liner oxide layer, making the silicon oxide layer at the bottom of the trench thicker than the oxide layer at the top of the trench.

[0057] Step 6: Deposit polysilicon for the first time to fill the trench. During the deposition process, a polysilicon layer is also covered on the surface of the epitaxial layer. Figure 9 shown.

[0058] Step seven, the polysilicon is subjected to CMP grinding and back etching, CMP grinding to the surface of the epitaxial layer, and all the polysilicon on the surface of the epitaxial layer is removed; the polysilicon in the trench is removed by dry etching back etching to remove a certain amount of polysilicon, and the remaining polysilicon forms a shield gate in the trench. The height of the remaining polysilicon after back etching must at least fill the height of the trench space defined by the thicker oxide layer at the bottom of the trench and fill it up to a certain height, so that the morphology of the formed shield gate is thick at the top and slightly thin at the bottom. Figure 10 shown.

[0059] The hard mask layer on the surface of the epitaxial layer is removed.

[0060] Step 8: Form a sacrificial oxide layer and etch it back. The sacrificial oxide layer is formed by thermal oxidation and then etched back to remove it, repairing the polysilicon damage caused by the previous dry etching process and forming the arc-shaped morphology of the top of the shield gate polysilicon. Utilizing the thermal oxidation process and the different oxidation rates of polysilicon and single crystal silicon, the oxidation rates of the shield gate polysilicon and Mesa single crystal silicon are different. Due to the presence of grain boundary defects in polysilicon, the grain boundaries provide a rapid diffusion channel for oxidized oxygen atoms, resulting in an oxidation rate that is generally faster than that of single crystal. Under the same oxidation environment, the shield gate polysilicon in the trench will grow a thicker oxide layer than the epitaxial Mesa single crystal silicon. After wet etching back, a portion of the oxide film formed by the oxidation of the thicker shield gate polysilicon will remain, forming a shield gate wrapping isolation. After the gate dielectric layer is subsequently oxidized again, the polysilicon on the top of the shield gate becomes narrower and the top becomes rounded and protruding upward in an arc-shaped morphology.

[0061] Then a gate dielectric layer is formed; the gate dielectric layer is integrated with the original liner layer inside the trench to wrap and isolate the shielding grid, forming an arc-shaped convex morphology, such as Figure 11 shown.

[0062] Step nine: perform a second polysilicon deposition to fill the remaining trenches. Figure 12 As shown in the figure, the filled polysilicon fills the remaining space in the trench and covers the surface of the epitaxial layer with a layer of polysilicon.

[0063] Step 10: Etch back the polysilicon deposited for the second time until it is flush with the surface of the epitaxial layer, and form the gate of the shielded gate MOSFET in the upper part of the trench. Implant the P-type well region to form a P-well in the epitaxial layer between the trenches and implant the N-type heavily doped region to form an N-type heavily doped region. Figure 13 shown.

[0064] Step 11: deposit an interlayer dielectric layer. The interlayer dielectric layer is a composite layer comprising a lower silicon oxide layer and an upper borophosphosilicate glass (BPSG). Contact holes are formed by etching the interlayer dielectric layer. Figure 14 As shown; the contact hole passes through the N-type heavily doped region, and its bottom is located in the P well.

[0065] Ion implantation is performed at the bottom of the contact hole at the bottom of the touch panel to form a contact lead-out region.

[0066] Step 12: deposit a work function layer on the entire wafer surface, such as a Ti / TiN layer, to enhance the adhesion stability between the contact hole metal and the epitaxial layer. The work function layer covers the inner wall of the contact hole, and then deposits the contact hole filling metal tungsten and performs wet etching back to form a contact hole structure, such as Figure 15 shown.

[0067] Step 13: deposit a top metal layer, such as AlCu, on the entire wafer surface, and etch back to form the top metal interconnect; deposit a pad oxide layer and etch back. The deposited pad oxide layer can isolate external humidity, pollutants and chemical corrosion, preventing damage to the internal structure of the device; secondly, it can reduce surface leakage current, inhibit charge accumulation, resist mechanical stress (such as packaging stress), and enhance the stability of the device structure. The final structure is as shown in the figure. Figure 16 shown.

[0068] The shielded gate MOSFET prepared by the above process has a higher withstand voltage BVDS, a lower on-resistance Rdson, a smaller RSP, better dynamic characteristics, and stronger product competitiveness. Figure 2 As shown in the electric field distribution simulation on the middle right, the breakdown voltage of the device with the traditional structure is 109V, while the breakdown voltage of the structure of the present invention can reach 114V under the same conditions.

[0069] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Those skilled in the art will appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention are intended to be within the scope of protection of the present invention.

Claims

1. A method for preparing a shielded gate MOSFET, characterized in that: Include: Step 1: providing a semiconductor substrate of the first conductivity type, forming an epitaxial layer of the first conductivity type on the semiconductor substrate; depositing a hard mask layer, defining a trench etching area on the hard mask layer by photolithography and etching, and performing trench etching to form a plurality of trenches; Step 2: growing a liner layer to cover the inside of the trench and the surface of the epitaxial layer; Step 3: Filling the dielectric layer with a high selectivity ratio to fully fill most of the trenches; Step 4: removing a portion of the high selectivity filling dielectric layer to define the height of the gate dielectric layer in the trench; removing the sidewall liner layer from the exposed area in the trench; Step 5: etching again to completely remove all remaining high selectivity dielectric layers inside the trench; depositing a gate dielectric layer on the inner wall of the trench and performing an annealing process; Step 6: performing a first polysilicon deposition to fill the trench; Step seven, grinding and etching back the polysilicon to form a shield grid in the trench; removing the hard mask layer on the surface of the epitaxial layer; Step eight, forming a sacrificial oxide layer and etching back; forming a gate dielectric layer; The gate dielectric layer is fused with the original liner layer inside the trench to wrap and isolate the shielding grid; Step nine, performing a second polysilicon deposition to fill the remaining trenches; Step ten, etching back the polysilicon deposited for the second time to form the gate of the shielded gate MOSFET; Performing implantation of the second conductivity type well region and the first conductivity type heavily doped region; Step 11, depositing an interlayer dielectric layer, and performing contact hole etching in the interlayer dielectric layer to form contact holes; The bottom of the contact hole is located in the well region; Performing ion implantation at the bottom of the contact hole to form a contact lead-out region; Step 12: depositing a work function layer on the entire wafer surface, the work function layer covering the inner wall of the contact hole, and then depositing the contact hole filling metal and etching back to form a contact hole structure; Step 13: depositing a top metal layer on the entire wafer surface, etching back the top metal layer to form a top metal interconnect; depositing a pad oxide layer and etching back.

2. The method for preparing a shielded gate MOSFET according to claim 1, wherein: In the step 1, the semiconductor substrate is a silicon substrate, a silicon germanium substrate, a gallium arsenide substrate, a silicon carbide substrate or a gallium nitride substrate; and the hard mask layer is a silicon oxide layer.

3. The method for preparing a shielded gate MOSFET according to claim 1, wherein: In the second step, the liner layer is a silicon oxide layer formed by a furnace tube process; the liner layer formed by oxidation is connected to the hard mask layer on the epitaxial surface.

4. The method for preparing a shielded gate MOSFET according to claim 1, wherein: In the step three, the filled dielectric layer is a dielectric layer with a high selectivity ratio.

5. The method for preparing a shielded gate MOSFET according to claim 4, wherein: In the step 4, the high selectivity dielectric layer is a photoresist; and the residual amount of the photoresist in the groove is achieved by controlling different photolithography exposure doses.

6. The method for preparing a shielded gate MOSFET according to claim 1, wherein: In the step 5, the gate dielectric layer is a silicon oxide layer, which is deposited by a CVD process; after the silicon oxide layer is deposited, thermal annealing is performed to ensure the quality of the pad oxide layer.

7. The method for preparing a shielded gate MOSFET according to claim 1, wherein: In the step 7, the CMP process is used to grind the surface of the epitaxial layer to remove all the polysilicon on the surface of the epitaxial layer; The polysilicon in the trench is removed by dry etching process.

8. The method for preparing a shielded gate MOSFET according to claim 1, wherein: In the step eight, a sacrificial oxide layer is formed and removed by back etching to repair the polysilicon damage caused by the previous dry etching process and form an arc-shaped morphology on the top of the polysilicon.

9. The method for preparing a shielded gate MOSFET according to claim 1, wherein: In the step eleven, the interlayer dielectric layer is a stack of a silicon oxide layer and borophosphosilicate glass.

10. The method for preparing a shielded gate MOSFET according to claim 1, wherein: In the step 12, the work function layer is a Ti / TiN layer to increase the adhesion with the substrate material; tungsten metal is deposited inside the contact hole and wet-etched back to form a contact hole structure.

11. The method for preparing a shielded gate MOSFET according to claim 1, wherein: In the step thirteen, the top metal is an aluminum-copper alloy.

12. The method for preparing a shielded gate MOSFET according to any one of claims 1 to 11, wherein: The first conductivity type is N-type, and the second conductivity type is P-type.

13. A shielded gate MOSFET structure, characterized in that: An epitaxial layer of the first conductivity type is provided on a semiconductor substrate of the first conductivity type, and an interlayer dielectric layer is provided on a surface of the epitaxial layer; The epitaxial layer has a plurality of parallel trenches, and the trenches have a shielding grid located in the lower part of the trenches and a gate located in the upper part of the trenches; a gate dielectric layer is provided between the shielding grid and the gate and the epitaxial layer material of the trenches; The gate dielectric layers on both sides of the shielding grid are thin in the middle and thick at the upper and lower ends, so that the cross-sectional morphology of the isolated shielding grid is a spindle shape with opposite shapes, thick in the middle and thin at the two ends, and the top of the shielding grid has an upwardly convex arc surface; The gate is located above the shielding grid, with its upper top surface being a horizontal plane and its lower bottom surface being an inwardly concave arc surface that matches the upper top surface of the shielding grid, so that the upper gate half-wraps the upper top surface of the lower shielding grid, and a portion of the grounded shielding grid is widened to serve as an internal field plate to optimize the electric field distribution in the drift region.

14. The shielded gate MOSFET structure of claim 13, wherein: The epitaxial layer between the trenches has a well region of the second conductivity type and a heavily doped region of the first conductivity type, and the depth of the well region exceeds that of the heavily doped region.

15. The shielded gate MOSFET structure of claim 13, wherein: The interlayer dielectric layer is a stacked layer, comprising a lower silicon oxide layer and an upper BPSG layer; the interlayer dielectric layer is covered with a top metal layer and connected to the well region via a contact hole penetrating the interlayer dielectric layer.

16. The shielded gate MOSFET structure according to any one of claims 13 to 15, wherein: The first conductivity type is N-type, and the second conductivity type is P-type.

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