Semiconductor structure and method of forming the same

Abstract

The present disclosure provides a semiconductor structure and a forming method thereof, wherein the forming method of the semiconductor structure comprises: providing a substrate, the substrate having a drift region therein, the drift region being different from the doping type of the substrate; forming a dielectric layer, the dielectric layer covering part of the drift region and part of the substrate adjacent to the part of the drift region; forming a body region in the substrate exposed by one side of the dielectric layer, the body region being adjacent to the drift region, the body region being different from the doping type of the drift region; forming a source region in the body region, the source region being different from the doping type of the substrate; forming a drain region in the drift region exposed by the other side of the dielectric layer, the doping type of the drain region being consistent with the doping type of the drift region; and forming a field plate on the dielectric layer, the field plate being a multi-stage ladder structure with a top surface height gradually decreasing along a first direction, wherein the first direction is parallel to the surface of the drift region and points from the drain region to the source region. By using the above technical solution, the breakdown voltage of the semiconductor structure can be improved, and the electrical performance of the semiconductor structure can be improved.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] Voltage-controlled power devices are electronic devices that control power by controlling voltage. They are commonly used in AC / DC (Alternating Current / Direct Current) conversion, DC / DC (Direct Current / Direct Current) conversion, and voltage regulation in power supplies.

[0003] However, the electrical performance of existing voltage-controlled power devices is poor.

[0004] Therefore, how to provide technical solutions to improve the electrical performance of voltage-controlled power devices has become an urgent technical problem to be solved. Summary of the Invention

[0005] In view of this, the present disclosure provides a semiconductor structure and a method for forming the same, which can improve the electrical performance of the semiconductor structure.

[0006] To address the aforementioned technical problems, this disclosure provides a method for forming a semiconductor structure, the method comprising:

[0007] A substrate is provided, wherein the substrate has a drift region, and the doping type of the drift region is different from the doping type of the substrate;

[0008] A dielectric layer is formed, the dielectric layer covering a portion of the drift region and a portion of the substrate adjacent to the drift region;

[0009] A body region is formed within the substrate exposed on one side of the dielectric layer. The body region is adjacent to the drift region, and the doping type of the body region is different from that of the drift region.

[0010] A source region is formed in the body region, and the doping type of the source region is different from the doping type of the substrate;

[0011] A drain region is formed in the drift region exposed on the other side of the dielectric layer, and the doping type of the drain region is the same as that of the drift region;

[0012] A field plate is formed on the dielectric layer. The field plate is a multi-level stepped structure with a top surface height that gradually decreases along a first direction, wherein the first direction is parallel to the surface of the drift region and points from the drain region to the source region.

[0013] Optionally, the dielectric layer is a multi-level stepped structure in which the height of the top surface gradually decreases along the first direction, wherein the number of steps in the dielectric layer is greater than or equal to three.

[0014] Optionally, the dielectric layer includes a first dielectric layer and a second dielectric layer, and the step of forming the dielectric layer includes:

[0015] A first dielectric material layer and a second dielectric material layer are formed on the substrate, wherein the second dielectric material layer covers the first dielectric material layer;

[0016] A portion of the first dielectric material layer and a portion of the second dielectric material layer are removed to obtain a first dielectric layer and an initial second dielectric layer, wherein the first dielectric layer covers a portion of the drift region and a portion of the substrate adjacent to the portion of the drift region along a first direction, and the initial second dielectric layer covers the first dielectric layer;

[0017] A portion of the initial second dielectric layer is removed to obtain a second dielectric layer, wherein the second dielectric layer covers a portion of the drift region and exposes a first dielectric layer located above the region adjacent to the substrate, and the top surface height of the multi-level stepped structure formed by the second dielectric layer and the first dielectric layer gradually decreases along the first direction.

[0018] Optionally, the second dielectric layer is a multi-level stepped structure in which the height of the top surface gradually decreases along the first direction.

[0019] Optionally, the projection position of the corner position of the top surface of the field plate onto the surface of the drift region does not overlap with the projection position of the corner position of the top surface of the dielectric layer onto the surface of the drift region.

[0020] Optionally, there are multiple second dielectric layers, and each second dielectric layer is distributed at intervals along a second direction, wherein the second direction is parallel to the surface of the drift region and perpendicular to the first direction.

[0021] Optionally, before forming the field plate, the following steps are also included:

[0022] A gate body is formed on the first dielectric layer exposed by the second dielectric layer, the gate body being located above a portion of the drift region and a portion of the substrate adjacent to the portion of the drift region;

[0023] A gate sidewall is formed on the sidewall of the gate body;

[0024] The first dielectric layer covered by the gate body is used as the gate dielectric layer, and the remaining first dielectric layer and the second dielectric layer, excluding the gate dielectric layer, are used as field dielectric layers.

[0025] Optionally, the order of each second dielectric layer is consistent, and at least one of the spacings between the steps of the same order in each second dielectric layer and the gate body is different from the other spacings.

[0026] Optionally, there are multiple field plates, which are spaced apart along the second direction, with one field plate corresponding to one second dielectric layer.

[0027] Optionally, the order of each field plate is the same, and among the corresponding spacings between the steps of the same order in each field plate and the gate body, at least one spacing is different in size from the other spacings.

[0028] This disclosure also provides a semiconductor structure, the semiconductor structure comprising:

[0029] A substrate having a drift region, wherein the doping type of the drift region is different from the doping type of the substrate;

[0030] A dielectric layer that covers a portion of the drift region and the portion of the substrate adjacent to that drift region;

[0031] The body region is located on one side of the dielectric layer and adjacent to the drift region. The doping type of the body region is different from that of the drift region.

[0032] The source region is located within the body region, and the doping type of the source region is different from the doping type of the substrate;

[0033] The drain region is located in the drift region exposed on the other side of the dielectric layer, and the doping type of the drain region is the same as that of the drift region.

[0034] A field plate covers the dielectric layer, and the field plate has a multi-level stepped structure with the top surface height gradually decreasing along a first direction, wherein the first direction is parallel to the surface of the drift region and points from the drain region to the source region.

[0035] Optionally, the dielectric layer is a multi-level stepped structure in which the height of the top surface gradually decreases along the first direction, wherein the number of steps in the dielectric layer is greater than or equal to three.

[0036] Optionally, the dielectric layer includes:

[0037] A first dielectric layer covers a portion of the drift region and a portion of the substrate adjacent to the drift region along a first direction;

[0038] The second dielectric layer covers part of the drift region and exposes the first dielectric layer located above the region adjacent to the substrate. The top surface height of the multi-level stepped structure formed by the second dielectric layer and the first dielectric layer gradually decreases along the first direction.

[0039] Optionally, the second dielectric layer is a multi-level stepped structure that gradually decreases in size along the first direction.

[0040] Optionally, the projection position of the corner position of the top surface of the field plate onto the surface of the drift region does not overlap with the projection position of the corner position of the top surface of the dielectric layer onto the surface of the drift region.

[0041] Optionally, there are multiple second dielectric layers, and each second dielectric layer is distributed at intervals along a second direction, wherein the second direction is parallel to the surface of the drift region and perpendicular to the first direction.

[0042] Optionally, the semiconductor structure further includes:

[0043] The gate body is located on the first dielectric layer exposed by the second dielectric layer, and is located above a portion of the drift region and a portion of the substrate adjacent to the portion of the drift region;

[0044] Gate sidewall, located on the sidewall of the gate body;

[0045] The first dielectric layer covered by the gate body is used as the gate dielectric layer, and the remaining first dielectric layer and the second dielectric layer, excluding the gate dielectric layer, are used as field dielectric layers.

[0046] Optionally, the order of each second dielectric layer is consistent, and at least one of the spacings between the steps of the same order in each second dielectric layer and the gate body is different from the other spacings.

[0047] Optionally, there are multiple field plates, which are spaced apart along the second direction, with one field plate corresponding to one second dielectric layer.

[0048] Optionally, the order of each field plate is the same, and at least one of the spacings between the same order step in each field plate and the gate body is different from the other spacings.

[0049] Compared with the prior art, the technical solution of the present disclosure has the following advantages:

[0050] In this embodiment, a dielectric layer is formed on a substrate, covering a portion of the drift region within the substrate and a portion of the substrate adjacent to the drift region. A body region is formed within the substrate exposed on one side of the dielectric layer, adjacent to the drift region, and the doping types of the body region and the drift region are different. A source region is formed within the body region, and the doping type of the source region is different from the doping type of the substrate. A drain region is formed within the drift region exposed on the other side of the dielectric layer, and the doping type of the drain region is the same as that of the drift region. A field plate is formed on the dielectric layer, and the field plate is a multi-level stepped structure with a top surface height gradually decreasing along a first direction, wherein the first direction is parallel to the surface of the drift region and points from the drain region to the source region. Using the above scheme, the field plate is a multi-level stepped structure with a top surface height gradually decreasing along the first direction. The corner positions on the top surface of the field plate can introduce multiple electric field peaks distributed along the first direction on the substrate surface, thereby optimizing the electric field distribution along the first direction on the substrate surface, improving the breakdown voltage of the semiconductor structure, and thus improving the electrical performance of the semiconductor structure. Attached Figure Description

[0051] To more clearly illustrate the technical solutions of the embodiments of this specification, the drawings used in the description of the embodiments of this specification or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this specification. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0052] Figure 1 This is a flowchart of a method for forming a semiconductor structure according to an embodiment of this disclosure;

[0053] Figures 2 to 5 This is a schematic cross-sectional view of each step in a method for forming a semiconductor structure according to an embodiment of the present disclosure.

[0054] Figure 6 This is a top view schematic diagram of a semiconductor structure according to an embodiment of the present disclosure;

[0055] Figure 7 This is a top view schematic diagram of a semiconductor structure according to an embodiment of the present disclosure.

[0056] Explanation of reference numerals in the attached figures:

[0057] 100 for the substrate, 110 for the drift region, 120 for the volume region, 130 for the source region, 140 for the drain region, and 150 for the extraction region.

[0058] Dielectric layer 200, first dielectric material layer 210, first dielectric layer 211, second dielectric material layer 220, initial second dielectric layer 221, second dielectric layer 222.

[0059] Gate body 310, gate sidewall 320;

[0060] Field plate 400, bottom field plate unit 410, middle field plate unit 420, top field plate unit 430;

[0061] First direction F1, second direction F2. Detailed Implementation

[0062] As described in the background section, existing voltage-controlled power devices have poor performance.

[0063] Taking the lateral double diffused metal-oxide-semiconductor field-effect transistor (LDMOS) device as an example, if the peak electric field in the LDMOS device exceeds the critical electric field, the device will break down. The voltage at this time is called the breakdown voltage of the LDMOS device.

[0064] Existing LDMOS devices have low breakdown voltages.

[0065] To address the aforementioned technical problems, in this embodiment, a dielectric layer is formed on a substrate, covering a portion of the drift region within the substrate and a portion of the substrate adjacent to the drift region; a body region is formed within the substrate exposed on one side of the dielectric layer, adjacent to the drift region, and the doping types of the body region and the drift region are different; a source region is formed within the body region, and the doping type of the source region is different from the doping type of the substrate; a drain region is formed within the drift region exposed on the other side of the dielectric layer, and the doping type of the drain region is consistent with the doping type of the drift region; a field plate is formed on the dielectric layer, the field plate being a multi-level stepped structure with a top surface height gradually decreasing along a first direction, wherein the first direction is parallel to the surface of the drift region and points from the drain region to the source region.

[0066] Using the above scheme, the field plate is a multi-level stepped structure with the top surface height gradually decreasing along the first direction. The corner position on the top surface of the field plate can introduce multiple electric field peaks distributed along the first direction on the substrate surface, thereby optimizing the electric field distribution on the substrate surface along the first direction, improving the breakdown voltage of the semiconductor structure, and thus improving the electrical performance of the semiconductor structure.

[0067] To make the above-mentioned objectives, features and beneficial effects of this disclosure more apparent and understandable, specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings.

[0068] Reference Figure 1 , Figure 1 A flowchart illustrating a method for forming a semiconductor structure according to an embodiment of this disclosure is shown. The method for forming a semiconductor device may include steps S11 to S16:

[0069] Step S11: Provide a substrate with a drift region, the doping type of the drift region being different from the doping type of the substrate;

[0070] Step S12: Form a dielectric layer that covers a portion of the drift region and a portion of the substrate adjacent to the drift region;

[0071] Step S13: A bulk region is formed in the substrate exposed on one side of the dielectric layer. The bulk region is adjacent to the drift region, and the doping type of the bulk region is different from that of the drift region.

[0072] Step S14: Form a source region in the bulk region. The doping type of the source region is different from that of the substrate.

[0073] Step S15: A drain region is formed in the drift region exposed on the other side of the dielectric layer. The doping type of the drain region is the same as that of the drift region.

[0074] Step S16: Form a field plate on the dielectric layer. The field plate is a multi-level stepped structure with the top surface height gradually decreasing along the first direction, wherein the first direction is parallel to the surface of the drift region and points from the drain region to the source region.

[0075] The following combination Figures 2 to 7 The above formation method will be explained.

[0076] Figures 2 to 5 This is a schematic cross-sectional view of each step in a method for forming a semiconductor structure according to an embodiment of this disclosure.

[0077] Reference Figure 2 Provides a base of 100.

[0078] Substrate 100 is used to provide a process platform for the formation of subsequent semiconductor structures.

[0079] The substrate 100 may be a silicon substrate, or the material of the substrate 100 may include germanium, silicon germanide, silicon carbide, gallium arsenide or indium gallium. The substrate 100 may also be a silicon substrate on an insulator or a germanium substrate on an insulator, or a substrate on which an epitaxy layer (Epi layer) has been grown.

[0080] The substrate 100 can be doped with either P-type or N-type doping.

[0081] A drift region 110 is formed within the substrate 100.

[0082] The doping type of drift region 110 can be either N-type doping or P-type doping.

[0083] The doping type of substrate 100 is different from that of drift region 110.

[0084] It should be noted that N-type doping may be used as an example in the following description, but this does not constitute a limitation on the specific doping type used in drift region 110.

[0085] Continue to refer to Figure 2 A first dielectric material layer 210 is formed on the substrate 100.

[0086] Specifically, the first dielectric material layer 210 covers the drift region 110 and the substrate 100 adjacent to the drift region 110 along the first direction F1, wherein the first direction F1 is parallel to the top surface of the drift region 110.

[0087] In some embodiments, the first dielectric material layer 210 is formed using a thermal oxidation process.

[0088] Compared to low-temperature deposition processes, the interface state between the first dielectric material layer 210 formed on the substrate 100 using thermal oxidation processes is lower, the interface defect density is smaller, and the interface quality is higher.

[0089] In some embodiments, the first dielectric material layer 210 may be a silicon dioxide layer.

[0090] In some embodiments, the thickness of the first dielectric material layer 210 can be between 100 angstroms and 300 angstroms, for example, the thickness of the first dielectric material layer 210 can be 120 angstroms.

[0091] It should be noted that the thickness referred to in this article refers to the dimension along the direction perpendicular to the top surface of the substrate 100.

[0092] Continue to refer to Figure 2 A second dielectric material layer 220 is formed on the first dielectric material layer 210.

[0093] Specifically, the second dielectric material layer 220 covers the drift region 110.

[0094] In some embodiments, the second dielectric material layer 220 is formed using a low-temperature deposition process. For example, the second dielectric material layer 220 can be formed using a low-temperature deposition process such as plasma-enhanced chemical vapor deposition (PECVD) or atomic layer deposition (ALD).

[0095] The process temperature of thermal oxidation is usually above 800 degrees Celsius, while the process temperature of low-temperature deposition is usually below 300 degrees Celsius. Compared with the degree of redistribution of doping concentration in each doped region of the substrate 100 caused by thermal oxidation in forming the second dielectric material layer 220, the degree of redistribution of doping concentration in each doped region of the substrate 100 caused by low-temperature deposition in forming the second dielectric material layer 220 is negligible.

[0096] It should be noted that both the first dielectric material layer 210 and the second dielectric material layer 220 are used to form the final dielectric layer 200. Compared with forming the final dielectric layer 200 directly through a thermal oxidation process or a low-temperature deposition process, in this embodiment, the first dielectric material layer 210 is first formed by thermal oxidation, and then the second dielectric material layer 220 is formed by low-temperature deposition. This can achieve a balance between reducing the "interface defect density between the field dielectric layer 200 and the drift region 110" and reducing the "redistribution of doping concentration in each doped region within the substrate 100 during the formation of the field dielectric layer 200".

[0097] In some embodiments, the thickness of the second dielectric material layer 220 is greater than the thickness of the first dielectric material layer 210. The thickness of the second dielectric material layer 220 can be from 100 nanometers to 300 nanometers. For example, the thickness of the second dielectric material layer 220 can be 200 nanometers.

[0098] In some embodiments, the second dielectric material layer 220 may be a silicon dioxide layer.

[0099] Combined with reference Figure 2 and Figure 3 Part of the first dielectric material layer 210 and the second dielectric material layer 220 are removed to obtain the first dielectric layer 211 and the initial second dielectric layer 221.

[0100] The first dielectric layer 211 covers a portion of the drift region 110 and a portion of the substrate 100 adjacent to the drift region 110 along the first direction F1, and the initial second dielectric layer 221 covers the first dielectric layer 211.

[0101] Specifically, forming the first dielectric layer 211 and the initial second dielectric layer 221 may include the following steps: forming a patterned mask layer (not shown in the figure) covering the area on the second dielectric material layer 220 corresponding to the initial second dielectric layer 221; using the mask layer as a mask, removing other second dielectric material layers 220 outside the area covered by the mask layer and other first dielectric material layers 210 outside the area covered by the initial second dielectric layer 221 to obtain the initial second dielectric layer 221 and the first dielectric layer 211.

[0102] Combined with reference Figure 3 and Figure 4 A portion of the initial second dielectric layer 221 is removed to obtain the second dielectric layer 222.

[0103] The second dielectric layer 222 covers part of the drift region 110 and exposes the first dielectric layer 211 located above the area adjacent to the drift region 110 and the substrate 100. The dielectric layer 200 composed of the second dielectric layer 222 and the first dielectric layer 211 is a multi-level stepped structure with the top surface height gradually decreasing along the first direction F1. The number of steps in the dielectric layer 200 is greater than or equal to three.

[0104] The dielectric layer 200 is a multi-level stepped structure with the top surface height gradually decreasing along the first direction F1. The corner position on the top surface of the dielectric layer 200 can introduce multiple electric field peaks distributed along the first direction F1 in the drift region 110, thus optimizing the lateral electric field distribution in the drift region 110 along the first direction F1 and improving the electrical performance of the semiconductor structure.

[0105] It should be noted that in this embodiment, the first direction F1 refers to the direction parallel to the surface of the drift region 110 and pointing from the drain region 140 to the source region 130.

[0106] Specifically, the initial second dielectric layer 221 has a first end and a second end, wherein the first end of the initial second dielectric layer 221 points to its second end along a first direction F1, and forming the second dielectric layer 222 may include:

[0107] Step S21: A patterned mask layer (not shown in the figure) is formed, which exposes the initial second dielectric layer 221 located above the area adjacent to the drift region 110 and the substrate 100. Using the mask layer as a mask, other initial second dielectric layers 221 outside the area covered by the mask layer are removed to expose the first dielectric layer 211 located above the area adjacent to the drift region 110 and the substrate 100.

[0108] Step S22: Remove the previous mask layer to form a new patterned mask layer (not shown in the figure). This mask layer exposes the area near the second end of the initial second dielectric layer 221. Using this mask layer as a mask, remove part of the thickness of the other initial second dielectric layer 221 outside the area covered by the mask layer to obtain the second dielectric layer 222.

[0109] It should be noted that the mask layer patterns used in different steps during the formation of the second dielectric layer 222 are different.

[0110] In some embodiments, refer to Figure 4 Step S22 is executed only once, and the resulting second dielectric layer 222 is a two-level stepped structure with two inflection points on its top surface. Correspondingly, the dielectric layer 200 composed of the second dielectric layer 222 and the first dielectric layer 211 is a three-level stepped structure with three inflection points on its top surface.

[0111] In other embodiments, step S22 can be performed multiple times, for example, three times, so that the second dielectric layer 222 has a four-level stepped structure with four inflection points on its top surface, and correspondingly, the dielectric layer 200 composed of the second dielectric layer 222 and the first dielectric layer 211 has a five-level stepped structure with five inflection points on its top surface.

[0112] It should be noted that when step S22 is executed multiple times, the area near its second end of the initial second dielectric layer 221 exposed by the mask layer each time is larger than the area near its second end of the initial second dielectric layer 221 exposed by the previous mask layer, so that the final second dielectric layer 222 is a multi-level stepped structure with the top surface height gradually decreasing along the first direction F1.

[0113] Continue to refer to Figure 4 This forms the gate body 310.

[0114] The gate body 310 is located on the first dielectric layer 211 exposed by the second dielectric layer 222, and is located above the partial drift region 110 and the portion of the substrate 100 adjacent to the partial drift region 110.

[0115] Continue to refer to Figure 4 This forms the gate sidewall 320.

[0116] The gate sidewalls 320 are located on both sides of the gate body 310, and the gate sidewalls 320 located near the second dielectric layer 222 cover the top surface of the first dielectric layer 211, while the gate sidewalls 320 located away from the second dielectric layer 222 cover the top surface of the substrate 100.

[0117] In this embodiment of the disclosure, the first dielectric layer 211 covered by the gate body 310 and the gate sidewall 320 is used as the gate dielectric layer 200, and the remaining first dielectric layer 211 and second dielectric layer 222, other than being used as the gate dielectric layer 200, are used as the field dielectric layer 200.

[0118] It is understandable that the remaining first dielectric layer 211, which is used as the gate dielectric layer 200, and the gate dielectric layer 200 both belong to the first dielectric layer 211. They are adjacent layer structures formed in the same process. The electrical characteristics on both sides of the interface are continuously distributed, and the interface will not cause electric field spikes at the corresponding positions on the substrate 100.

[0119] It should be noted that the first dielectric layer 211, by separating the gate body 310 and the substrate 100, can reduce the intensity of the electric field spike caused by the edge position of the gate body 310 at the corresponding position of the substrate 100, thereby optimizing the lateral electric field distribution in the substrate 100, where lateral refers to the direction parallel to the top surface of the substrate 100.

[0120] Continue to refer to Figure 4 , forming a body region of 120.

[0121] The doping type of the body region 120 is different from that of the drift region 110.

[0122] Specifically, the step of forming the body region 120 may include: forming a patterned mask layer (not shown in the figure) that exposes the substrate 100 near the first dielectric layer 211; and using the mask layer as a mask, doping the portion of the substrate 100 exposed by the mask layer to obtain the body region 120.

[0123] In some embodiments, after forming the body region 120, the semiconductor structure is annealed.

[0124] Annealing allows the body region 120 and the drift region 110 to diffuse relative to each other until they are adjacent, with their interface located below the gate body 310.

[0125] It should be noted that the first dielectric layer 211 and the second dielectric layer 222 are formed sequentially using different processes, and due to the difference in process temperature, there are a large number of defects at the interface between the first dielectric layer 211 and the second dielectric layer 222. These defects will capture and accumulate charge carriers, resulting in threshold voltage drift.

[0126] Annealing the semiconductor structure after forming the first dielectric layer 211 and the second dielectric layer 222 can promote atomic diffusion at the interface between the first dielectric layer 211 and the second dielectric layer 222, thereby reducing the amount of defects at the interface. This reduces the amount of charge carriers captured and accumulated at the interface between the first field dielectric layer 200 and the second field dielectric layer 200, and thus reduces the drift of the threshold voltage.

[0127] Continue to refer to Figure 4 A source region 130 is formed within the body region 120 exposed in the first dielectric layer 211, and a drain region 140 is formed within the drift region 110 exposed in the first dielectric layer 211.

[0128] Among them, the source region 130 and the body region 120 have different doping types, the drain region 140 has the same doping type as the source region 130 and the drift region 110, and the doping concentration of the drain region 140 is higher than that of the drift region 110.

[0129] In some embodiments, the source region 130 and the drain region 140 can be formed in various orders. For example, the drain region 140 may be formed during the formation of the source region 130. For example, the source region 130 may be formed after the drain region 140. For example, the source region 130 may be formed before the drain region 140.

[0130] Continue to refer to Figure 4 An extraction region 150 is formed within the source region 130.

[0131] The bottom surface of the extraction region 150 is adjacent to the body region 120. The extraction region 150 and the body region 120 have the same doping type, and the doping concentration of the extraction region 150 is higher than that of the body region 120. In this way, the extraction region 150 can extract the charge accumulated in the body region 120, thereby reducing the potential fluctuation of the body region 120.

[0132] In some embodiments, the number of second dielectric layers 222 can be one or more.

[0133] Figure 6 A top view schematic diagram of a semiconductor structure according to an embodiment of the present disclosure is shown.

[0134] As a specific example, in conjunction with reference Figure 4 and Figure 6 There are multiple second dielectric layers 222, and each second dielectric layer 222 is distributed at intervals along the second direction F2, wherein the second direction F2 is parallel to the surface of the drift region 110 and perpendicular to the first direction F1.

[0135] Compared to a single second dielectric layer 222, by providing multiple second dielectric layers 222 spaced apart along the second direction F2, the adjacent edges of each second dielectric layer 222 in the second direction F2 can introduce multiple new electric field peaks distributed along the second direction F2 in the drift region 110. This can optimize the distribution of the lateral electric field in the drift region 110 in the second direction F2, improve the breakdown voltage of the semiconductor structure, and thus improve the electrical performance of the semiconductor structure.

[0136] Continue to refer to Figure 6 Each of the second dielectric layers 222 has the same order, and at least one of the spacings between the same order step in each of the second dielectric layers 222 and the gate body 310 is different from the other spacings.

[0137] This increases the spacing between the electric field spikes introduced by the adjacent second dielectric layer 222 and reduces the superposition intensity between the corresponding adjacent electric field spikes. Therefore, it can simultaneously optimize the distribution of the lateral electric field in the drift region 110 in the first direction F1 and the second direction F2, improve the breakdown voltage of the semiconductor structure, and thus improve the electrical performance of the semiconductor structure.

[0138] Combined with reference Figure 4 and Figure 5 A field plate 400 is formed on the dielectric layer 200.

[0139] In practical use, the field plate 400 is used to connect external electrodes (not shown in the figure). By connecting with external electrodes, the field plate 400 can form an electric field perpendicular to the top surface of the substrate 100. This electric field can dissipate the charge carriers captured and accumulated at the interface between the first dielectric layer 211 and the second dielectric layer 222, thereby reducing the drift of the threshold voltage.

[0140] In addition, by connecting to external electrodes, the field plate 400 can also introduce a fixed potential, preventing the first field dielectric layer 200 and the second dielectric layer 222 from introducing random potentials due to the floating effect, ensuring that the first dielectric layer 211 and the second dielectric layer 222 are at a fixed potential, thereby stabilizing the transverse electric field within the substrate 100.

[0141] In some embodiments, the field plate 400 is a multi-level stepped structure in which the height of the top surface gradually decreases along the first direction F1.

[0142] In this way, the corner position on the top surface of the field plate 400 can introduce multiple electric field peaks distributed along the first direction F1 in the drift region 110, thereby optimizing the distribution of the lateral electric field in the drift region 110 along the first direction F1, improving the breakdown voltage of the semiconductor structure, and thus improving the electrical performance of the semiconductor structure.

[0143] In some embodiments, the projection position of the corner position on the top surface of the field plate 400 onto the surface of the drift region 110 does not overlap with the projection position of the corner position on the top surface of the dielectric layer 200 onto the surface of the drift region 110.

[0144] In this way, the positions of the multiple electric field peaks distributed along the first direction F1 introduced by the corner of the top surface of the field plate 400 in the drift region 110 do not overlap with the positions of the multiple electric field peaks distributed along the first direction F1 introduced by the corner of the top surface of the dielectric layer 200 in the drift region 110. Therefore, the positions of more electric field peaks distributed along the first direction F1 introduced in the drift region 110 can be optimized, thereby further optimizing the distribution of the transverse electric field in the first direction F1 within the drift region 110.

[0145] It should be noted that the aforementioned non-overlapping projection positions can include complete non-overlapping and partial non-overlapping.

[0146] In some examples, the projection of the corner position on the top surface of the field plate 400 onto the surface of the drift region 110 does not overlap with the projection of the corner position on the top surface of the dielectric layer 200 onto the surface of the drift region 110.

[0147] This avoids the superposition of the electric field spikes introduced in the drift region 110 at the corner of the top surface of the field plate 400 and the electric field spikes introduced in the drift region 110 at the corner of the top surface of the dielectric layer 200, thereby preventing the semiconductor structure from breaking down prematurely at the superposition location.

[0148] In other examples, the projection of the corner position on the top surface of the field plate 400 onto the surface of the drift region 110 may partially overlap with, but not partially overlap with, the projection of the corner position on the top surface of the dielectric layer 200 onto the surface of the drift region 110.

[0149] In some embodiments, the field plate 400 may be made of polycrystalline silicon.

[0150] Continue to refer to Figure 5 The second dielectric layer 222 in the three-step structure dielectric layer 200 is a two-step structure. As a specific example, forming a field plate 400 on the three-step structure dielectric layer 200 may include the following steps:

[0151] Step S31: A field plate material layer (not shown) is deposited on the dielectric layer 200; a patterned mask layer (not shown) is formed, which covers the field plate material layer above the first dielectric layer 211 located between the gate sidewall 320 and the second dielectric layer 222; using the mask layer as a mask, other field plate material layers outside the area covered by the mask layer are removed to form a bottom field plate unit 410, wherein the top surface of the bottom field plate unit 410 is flush with the top surface of the step with the lowest height on the top surface of the second dielectric layer 222.

[0152] The bottom field plate unit 410 has a first end and a second end, wherein the first end of the bottom field plate unit 410 points to its second end along a first direction F1, and in some embodiments, the second end of the bottom field plate unit 410 has a distance from the gate sidewall 320 along the first direction F1.

[0153] In this way, the position of the electric field peak introduced by the second end of the bottom field plate unit 410 in the drift region 110 will not overlap with the position of the electric field peak introduced by the gate sidewall 320 in the drift region 110. Therefore, the position of more electric field peaks distributed along the first direction F1 introduced in the drift region 110 can be optimized, thereby improving the breakdown voltage of the semiconductor structure and thus improving the electrical performance of the semiconductor structure.

[0154] Step S32: Remove the previous mask layer; deposit a new field plate material layer (not shown) on the second dielectric layer 222 and the bottom field plate unit 410; form a new patterned mask layer (not shown) that covers the field plate material layer above the step with the lowest top surface height of the second dielectric layer 222 and the field plate material layer above the bottom field plate unit 410 near the step; using the mask layer as a mask, remove other field plate material layers outside the area covered by the mask layer to form the middle field plate unit 420, wherein the top surface of the middle field plate unit 420 is flush with the top surface of the step with the highest top surface height of the second dielectric layer 222.

[0155] The middle field plate unit 420 has a first end and a second end, wherein the first end of the middle field plate unit 420 points to its second end along a first direction F1. In some embodiments, the projection position of the second end of the middle field plate unit 420 on the surface of the drift region 110 is spaced along the first direction F1 from the projection positions of the first end and the second end of the bottom field plate unit 410 on the surface of the drift region 110, and is located along the first direction F1 between the projection positions of the first end and the second end of the bottom field plate unit 410 on the surface of the drift region 110.

[0156] In this way, the position of the electric field peak introduced by the second end of the middle field plate unit 420 in the drift region 110 will not overlap with the position of the electric field peak introduced by the first end and the second end of the bottom field plate unit 410 in the drift region 110. Therefore, the position of more electric field peaks distributed along the first direction F1 introduced in the drift region 110 can be optimized, thereby further optimizing the electric field distribution along the first direction F1 in the drift region 110, improving the breakdown voltage of the semiconductor structure, and thus improving the electrical performance of the semiconductor structure.

[0157] Step S33: Remove the previous mask layer; deposit a new field plate material layer (not shown in the figure) on the second dielectric layer 222 and the middle field plate unit 420; form a new patterned mask layer (not shown in the figure), which covers the field plate material layer above the highest step on the top surface of the second dielectric layer 222 and the field plate material layer above the middle field plate unit 420 near the step; using the mask layer as a mask, remove other field plate material layers outside the area covered by the mask layer to form the top field plate unit 430, wherein the bottom field plate unit 410, the middle field plate unit 420 and the top field plate unit 430 together constitute the field plate 400.

[0158] The top field plate unit 430 has a first end and a second end, wherein the first end of the top field plate unit 430 points to its second end along a first direction F1. In some embodiments, the projection position of the second end of the top field plate unit 430 on the surface of the drift region 110 is spaced along the first direction F1 from the projection positions of the first end of the bottom field plate unit 410 and the middle field plate unit 420 on the surface of the drift region 110, and is located along the first direction F1 between the projection positions of the first end of the bottom field plate unit 410 and the middle field plate unit 420 on the surface of the drift region 110.

[0159] In this way, the position of the electric field peak introduced by the second end of the top field plate unit 430 in the drift region 110 will not overlap with the position of the electric field peak introduced by the first end and the second end of the bottom field plate unit 410 in the drift region 110. Therefore, the position of more electric field peaks distributed along the first direction F1 introduced in the drift region 110 can be optimized, thereby further optimizing the electric field distribution along the first direction F1 in the drift region 110, improving the breakdown voltage of the semiconductor structure, and thus improving the electrical performance of the semiconductor structure.

[0160] It should be noted that for a dielectric layer 200 with an order greater than three, the order of its corresponding second dielectric layer 222 is greater than two. Accordingly, during the formation of the field plate 400, multiple steps S32 will be executed to form multiple central field plate units 420 until the top surface of the last central field plate unit 420 formed is flush with the top surface of the step with the highest height of the top surface of the second dielectric layer 222.

[0161] In some embodiments, the number of field plates 400 can be one or more.

[0162] Figure 7 A top view schematic diagram of a semiconductor structure according to an embodiment of the present disclosure is shown.

[0163] As a specific example, in conjunction with reference Figure 5 and Figure 7 There are multiple field plates 400, and each field plate 400 is distributed at intervals along the second direction F2. Each field plate 400 corresponds to a second dielectric layer 222.

[0164] Compared to a single field plate 400, by setting multiple field plates 400 spaced apart along the second direction F2, the adjacent edges of each field plate 400 on the second direction F2 can introduce multiple new electric field peaks distributed along the second direction F2 in the drift region 110, thereby optimizing the distribution of the transverse electric field in the drift region 110 on the second direction F2.

[0165] In some embodiments, the order of each field plate 400 is the same, and at least one of the spacings between the same order step in each field plate 400 and the gate body 310 is different from the other spacings.

[0166] This increases the spacing between the electric field peaks introduced by adjacent field plates 400 and reduces the superposition intensity between the corresponding adjacent electric field peaks. Therefore, it can simultaneously optimize the distribution of the lateral electric field in the drift region 110 in the first direction F1 and the second direction F2, further improving the breakdown voltage of the semiconductor structure and thus improving the electrical performance of the semiconductor structure.

[0167] In some embodiments, along the second direction F2, the projection positions of each field plate 400 on the surface of the drift region 110 and the projection positions of the corresponding covered second dielectric layer 222 on the surface of the drift region 110 have a distance along the second direction F2.

[0168] In this way, the positions of the electric field peaks introduced by each field plate 400 in the drift region 110 will not overlap with the positions of the electric field peaks introduced by the corresponding covering second dielectric layer 222 in the drift region 110. Therefore, the positions of more electric field peaks distributed along the second direction F2 introduced in the drift region 110 can be further optimized, thereby improving the electric field distribution along the second direction F2 in the drift region 110, increasing the breakdown voltage of the semiconductor structure, and thus improving the electrical performance of the semiconductor structure.

[0169] In some embodiments, the semiconductor structure can be a symmetrical LDMOS device, which includes two symmetrical semiconductor units, with the body region 120 belonging to the semiconductor unit and the two semiconductor units sharing the same body region 120.

[0170] In some embodiments, the semiconductor structure may be an LDMOS device, which includes a semiconductor unit, wherein the semiconductor unit may include a drift region 110, a body region 120, a source region 130, a drain region 140, a pull-out region 150, a gate body 310, a gate sidewall 320, a dielectric layer 200, and a field plate 400.

[0171] Furthermore, the semiconductor structure can be a symmetrical LDMOS device, which includes two symmetrical semiconductor units that share a common body region 120, a source region 130, and a draw region 150.

[0172] Specifically, sharing the same bulk region 120, source region 130, and extraction region 150 can improve the current drive capability of LDMOS devices, while also simplifying the layout and increasing the integration density of the devices.

[0173] It should be noted that, apart from the shared body region 120, source region 130 and extraction region 150, each semiconductor unit in the symmetrical LDMOS device may have its own drift region 110, drain region 140, gate body 310, gate sidewall 320, dielectric layer 200 and field plate 400, and the above parts may be completely identical or not completely identical.

[0174] It should be noted that each semiconductor cell has its own first direction F1. The first direction F1 of each semiconductor cell refers to the direction from the source region 130 to the drain region 140 in that semiconductor cell. The first direction F1 of different semiconductor cells can be different, for example... Figures 4 to 7The first direction F1 of two semiconductor units under the same semiconductor structure can be opposite.

[0175] In this disclosure embodiment, a semiconductor structure may also be provided, in conjunction with reference to... Figures 2 to 7 The semiconductor structure may include: a substrate 100, a dielectric layer 200, a body region 120, a source region 130, a drain region 140, and a field plate 400.

[0176] The substrate 100 has a drift region 110, the doping type of which is different from that of the substrate 100. The dielectric layer 200 covers a portion of the drift region 110 and a portion of the substrate 100 adjacent to the drift region 110. The body region 120 is located on one side of the dielectric layer 200 and is adjacent to the drift region 110, the doping type of which is different from that of the drift region 110. The source region 130 is located within the body region 120, the doping type of which is different from that of the substrate 100. The drain region 140 is located within the drift region 110 exposed on the other side of the dielectric layer 200, the doping type of which is the same as that of the drift region 110. The field plate 400 covers the dielectric layer 200 and is a multi-level stepped structure with the top surface height gradually decreasing along a first direction F1, wherein the first direction F1 is parallel to the surface of the drift region 110 and points from the drain region 140 to the source region 130.

[0177] In some embodiments, the dielectric layer 200 is a multi-level stepped structure in which the height of the top surface gradually decreases along the first direction F1, wherein the number of steps in the dielectric layer 200 is greater than or equal to three.

[0178] In some embodiments, the dielectric layer 200 includes a first dielectric layer 211 and a second dielectric layer 222.

[0179] The first dielectric layer 211 covers a portion of the drift region 110 and a portion of the substrate 100 adjacent to the drift region 110 along the first direction F1; the second dielectric layer 222 covers a portion of the drift region 110 and exposes the first dielectric layer 211 located above the area adjacent to the drift region 110 and the substrate 100, and the top surface height of the multi-level stepped structure formed by the second dielectric layer 222 and the first dielectric layer 211 gradually decreases along the first direction F1.

[0180] In some embodiments, the second dielectric layer 222 is a multi-level stepped structure that gradually decreases along the first direction F1.

[0181] In some embodiments, the projection position of the corner position of the top surface of the field plate 400 onto the surface of the drift region 110 does not overlap with the projection position of the corner position of the top surface of the dielectric layer 200 onto the surface of the drift region 110.

[0182] In some embodiments, there are multiple second dielectric layers 222, and each second dielectric layer 222 is distributed at intervals along a second direction F2, wherein the second direction F2 is parallel to the surface of the drift region 110 and perpendicular to the first direction F1.

[0183] In some embodiments, the semiconductor structure further includes a gate body 310 and a gate sidewall 320.

[0184] The gate body 310 is located on the first dielectric layer 211 exposed by the second dielectric layer 222, and is located above the part of the drift region 110 and the part of the substrate 100 adjacent to the part of the drift region 110; the gate sidewall 320 is located on the sidewall of the gate body 310; it should be noted that the first dielectric layer 211 covered by the gate body 310 is used as the gate dielectric layer 200, and the remaining first dielectric layer 211 and the second dielectric layer 222, except for being used as the gate dielectric layer 200, are used as the field dielectric layer 200.

[0185] In some embodiments, the order of each second dielectric layer 222 is consistent, and at least one of the spacings between the same order of the steps in each second dielectric layer 222 and the gate body 310 is different from the other spacings.

[0186] In some embodiments, there are multiple field plates 400, and each field plate 400 is distributed at intervals along the second direction F2, with one field plate 400 corresponding to one second dielectric layer 222.

[0187] In some embodiments, the order of each field plate 400 is the same, and at least one of the spacings between the same order step in each field plate 400 and the gate body 310 is different in size from the other spacings.

[0188] It should be noted that for details regarding the principles, specific implementation, and beneficial effects of this semiconductor structure, please refer to the preceding text and... Figures 2 to 7 The description of the semiconductor structure formation method shown is not repeated here.

[0189] It is understandable that the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article indicates that the preceding and following related objects have an "or" relationship.

[0190] It is understood that "multiple" in this document refers to two or more. The descriptions of "first," "second," "third," etc., appearing in the embodiments of this application are for illustrative purposes and to distinguish the objects being described, and have no order, nor do they indicate a special limitation on the number of devices in the embodiments of this application, and cannot constitute any limitation on the embodiments of this application.

[0191] It is understood that multiple embodiments are described in this document, and the optional methods described in each embodiment can be combined and cross-referenced without conflict, thereby extending to a variety of possible embodiments. These can all be considered as embodiments disclosed in this publication.

[0192] While the embodiments disclosed herein are as described above, this disclosure is not limited thereto. Any person skilled in the art can make various alterations and modifications without departing from the spirit and scope of this disclosure; therefore, the scope of protection of this disclosure should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, wherein the substrate has a drift region, and the doping type of the drift region is different from the doping type of the substrate; A dielectric layer is formed, the dielectric layer covering a portion of the drift region and a portion of the substrate adjacent to the drift region; The dielectric layer includes a first dielectric layer and a second dielectric layer; the number of the second dielectric layers is multiple. A body region is formed within the substrate exposed on one side of the dielectric layer. The body region is adjacent to the drift region, and the doping type of the body region is different from that of the drift region. A source region is formed in the body region, and the doping type of the source region is different from the doping type of the substrate; A drain region is formed in the drift region exposed on the other side of the dielectric layer, and the doping type of the drain region is the same as that of the drift region; A field plate is formed on the dielectric layer. The field plate is a multi-level stepped structure with its top surface height gradually decreasing along a first direction, wherein the first direction is parallel to the surface of the drift region and points from the drain region to the source region. There are multiple field plates, which are spaced apart along a second direction, with one field plate corresponding to one second dielectric layer. The order of each field plate is the same, and at least one of the corresponding spacings between the steps of the same order in each field plate and the gate body is different from the other spacings. Before forming the field plate, the method further includes the steps of: forming a gate body on the first dielectric layer exposed by the second dielectric layer, the gate body being located above a portion of the drift region and a portion of the substrate adjacent to the portion of the drift region; and forming a gate sidewall on the sidewall of the gate body. The first dielectric layer covered by the gate body is used as the gate dielectric layer, and the remaining first dielectric layer and the second dielectric layer, excluding the gate dielectric layer, are used as field dielectric layers. Each second dielectric layer is spaced apart along a second direction, wherein the second direction is parallel to the surface of the drift region and perpendicular to the first direction; the second dielectric layer is a multi-level stepped structure with the top surface height gradually decreasing along the first direction, and the number of steps of each second dielectric layer is the same, and at least one of the spacings between the steps of the same number in each second dielectric layer and the gate body is different from the other spacings.

2. The forming method according to claim 1, characterized in that, The medium layer is a multi-level stepped structure with the top surface height gradually decreasing along the first direction, wherein the number of steps in the medium layer is greater than or equal to three.

3. The forming method according to claim 2, characterized in that, The steps for forming the dielectric layer include: A first dielectric material layer and a second dielectric material layer are formed on the substrate, wherein the second dielectric material layer covers the first dielectric material layer; A portion of the first dielectric material layer and a portion of the second dielectric material layer are removed to obtain a first dielectric layer and an initial second dielectric layer, wherein the first dielectric layer covers a portion of the drift region and a portion of the substrate adjacent to the portion of the drift region along a first direction, and the initial second dielectric layer covers the first dielectric layer; A portion of the initial second dielectric layer is removed to obtain a second dielectric layer, wherein the second dielectric layer covers a portion of the drift region and exposes a first dielectric layer located above the region adjacent to the substrate, and the top surface height of the multi-level stepped structure formed by the second dielectric layer and the first dielectric layer gradually decreases along the first direction.

4. The forming method according to claim 3, characterized in that, The projection of the corner position of the top surface of the field plate onto the surface of the drift region does not overlap with the projection of the corner position of the top surface of the dielectric layer onto the surface of the drift region.

5. A semiconductor structure, characterized in that, include: A substrate having a drift region, wherein the doping type of the drift region is different from the doping type of the substrate; A dielectric layer covers a portion of the drift region and a portion of the substrate adjacent to the drift region; the dielectric layer includes: a first dielectric layer and a second dielectric layer, wherein there are multiple second dielectric layers; The body region is located on one side of the dielectric layer and adjacent to the drift region. The doping type of the body region is different from that of the drift region. The source region is located within the body region, and the doping type of the source region is different from the doping type of the substrate; The drain region is located in the drift region exposed on the other side of the dielectric layer, and the doping type of the drain region is the same as that of the drift region. A field plate covers the dielectric layer, and the field plate has a multi-level stepped structure with the top surface height gradually decreasing along a first direction, wherein the first direction is parallel to the surface of the drift region and points from the drain region to the source region; there are multiple field plates, and each field plate is spaced apart along a second direction, with one field plate corresponding to one second dielectric layer; The gate body is located on the first dielectric layer exposed by the second dielectric layer, and above a portion of the drift region and a portion of the substrate adjacent to the drift region; the order of each field plate is consistent, and at least one of the spacings between the steps of the same order in each field plate and the gate body is different from the other spacings; Gate sidewall, located on the sidewall of the gate body; The first dielectric layer covered by the gate body is used as the gate dielectric layer, and the remaining first dielectric layer and the second dielectric layer, excluding the gate dielectric layer, are used as field dielectric layers. Each second dielectric layer is spaced apart along a second direction, wherein the second direction is parallel to the surface of the drift region and perpendicular to the first direction; each second dielectric layer has the same order, and at least one of the spacings between the steps of the same order in each second dielectric layer and the gate body is different from the other spacings.

6. The semiconductor structure according to claim 5, characterized in that, The medium layer is a multi-level stepped structure with the top surface height gradually decreasing along the first direction, wherein the number of steps in the medium layer is greater than or equal to three.

7. The semiconductor structure according to claim 6, characterized in that, A first dielectric layer covers a portion of the drift region and a portion of the substrate adjacent to the drift region along a first direction; The second dielectric layer covers part of the drift region and exposes the first dielectric layer located above the region adjacent to the substrate. The top surface height of the multi-level stepped structure formed by the second dielectric layer and the first dielectric layer gradually decreases along the first direction.

8. The semiconductor structure according to claim 7, characterized in that, The second dielectric layer is a multi-level stepped structure that gradually decreases in size along the first direction.

9. The semiconductor structure according to claim 8, characterized in that, The projection of the corner position of the top surface of the field plate onto the surface of the drift region does not overlap with the projection of the corner position of the top surface of the dielectric layer onto the surface of the drift region.

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