Transistor device and method of forming gate electrode and field plate in columnar trench

Abstract

Transistor devices and methods of forming gate electrodes and field plates in columnar trenches are disclosed. In an embodiment, a transistor device is provided, comprising: a semiconductor substrate, the semiconductor substrate comprising a first main surface; and a columnar trench disposed in the first main surface and including a lower surface and a sidewall extending from the lower surface to the first main surface. A gate electrode is positioned in the columnar trench and is electrically insulated from the semiconductor substrate by a gate dielectric. A field plate is positioned in the columnar trench below the gate electrode and is electrically insulated from the gate electrode and the semiconductor substrate by a field dielectric. The gate electrode is asymmetrical with respect to a longitudinal axis of the columnar trench. The field plate includes a field plate extension extending from the field plate toward the first major surface and laterally adjacent to the gate electrode.

Description

Background Art

[0001] Transistor devices used in power electronics applications are often manufactured using silicon (Si) semiconductor materials. Common transistor devices used in power applications include Si Si power MOSFETs and Si insulated gate bipolar transistors (IGBTs).

[0002] Transistor devices for power applications can be based on the charge compensation principle and can include an active cell field comprising a plurality of trenches, each trench including a field plate for charge compensation. In some designs, the trenches and the mesas formed between adjacent trenches each have an elongated strip-shaped structure. In some other designs, such as disclosed in DE 102014 112371A1, both the trenches and the field plates have a columnar, needle-like shape.

[0003] Further improvements would be desirable to further improve the performance of transistor devices having columnar field plates, for example by reducing the on-state resistance R DS(on).Area . Summary of the Invention

[0004] In an embodiment, a transistor device is provided, comprising: a semiconductor substrate including a first main surface; a columnar trench arranged in the first main surface and including a lower surface and sidewalls, the sidewalls extending from the lower surface to the first main surface. A gate electrode is positioned in the columnar trench and electrically insulated from the semiconductor substrate by a gate dielectric. A field plate is positioned in the columnar trench below the gate electrode and electrically insulated from the gate electrode and the semiconductor substrate by a field dielectric. The gate electrode is asymmetric about a longitudinal axis of the columnar trench. The field plate includes a field plate extension extending from the field plate toward the first main surface and laterally adjacent to the gate electrode.

[0005] In an embodiment, a method for forming a gate electrode and a field plate in a columnar trench is provided. The method includes providing a semiconductor substrate having a first main surface and a columnar trench, the columnar trench including a lower surface and sidewalls extending from the lower surface to the first main surface, wherein the sidewalls and the lower surface are lined with a field dielectric, and the columnar trench is filled with a first conductive material. The method further includes partially removing the field dielectric, partially removing the first conductive material from the columnar trench, and forming a gate recess located asymmetrically in the columnar trench about the longitudinal axis of the columnar trench. The method further includes forming a dielectric material on the wall of the gate recess and inserting a second conductive material into the gate recess to form a gate electrode. The remaining first conductive material forms a field plate and extends to the first main surface at a position adjacent to the gate electrode in the lateral direction.

[0006] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The elements of the drawings are not necessarily to scale with respect to each other. The same reference numerals designate corresponding similar parts. The features of the various illustrated embodiments may be combined unless they exclude each other. Exemplary embodiments are depicted in the drawings and are described in detail in the following description.

[0008] Figure 1 includes Figures 1A to 1E , and illustrates transistor devices according to various embodiments.

[0009] Figure 2 includes Figures 2A to 2L , and illustrates a method for fabricating a gate electrode and a field plate in a pillar-shaped trench.

[0010] Figure 3 includes Figures 3A to 3K , and illustrates a method for fabricating a gate electrode and a field plate in a pillar-shaped trench.

[0011] Figures 4A to 4H Illustrated is a top view of a metallization structure for a transistor device according to various embodiments. DETAILED DESCRIPTION

[0012] In the following detailed description, reference is made to the accompanying drawings, which form a part of the description and in which are shown by way of illustration specific embodiments in which the present invention may be put into practice. In this regard, directional terms such as "top", "bottom", "front", "back", "front end", "end", etc. are used with reference to the orientation of the (one or more) figures being described. Because the components of the embodiments can be positioned in many different orientations, the directional terms are used for illustrative purposes and are by no means limiting. It is understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description of the present invention is not taken in a limiting sense, and the scope of the present invention is defined by the appended claims.

[0013] A number of exemplary embodiments will be explained below. In this case, identical structural features are identified by identical or similar reference numerals in the various figures. In the context of this description, "lateral" or "lateral direction" should be understood to mean a direction or extent generally parallel to the lateral extent of the semiconductor material or semiconductor carrier. Therefore, the lateral direction generally extends parallel to these surfaces or sides. In contrast, the term "vertical" or "vertical direction" is understood to mean a direction generally perpendicular to these surfaces or sides and therefore perpendicular to the lateral direction. Therefore, the vertical direction extends in the thickness direction of the semiconductor material or semiconductor carrier.

[0014] As used in this specification, when an element such as a layer, region, or substrate is referred to as being "on" or "extending onto" another element, it can be directly on or directly extend onto the other element, or intervening elements may be present. In contrast, when an element is referred to as being "directly on" or "extending directly onto" another element, there are no intervening elements present.

[0015] As used in this specification, when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements.

[0016] As used herein, various device types and / or doped semiconductor regions may be identified as n-type or p-type, but this is merely for convenience of description and is not intended to be limiting, and such identification may be replaced by more general descriptions of a "first conductivity type" or an "opposite second conductivity type," where the first type may be n-type or p-type, and the second type is then p-type or n-type.

[0017] The figures indicate "-" or "-" next to the doping type "n" or "p". + ” to illustrate the relative doping concentration. For example, “n - ” means a doping concentration lower than the doping concentration of an “n”-doping region, and “n + The "n"-doped region has a higher doping concentration than the "n"-doped region. Doping regions with the same relative doping concentration do not necessarily have the same absolute doping concentration. For example, two different "n"-doped regions may have the same or different absolute doping concentrations.

[0018] In some embodiments, the transistor device is a vertical transistor device, i.e., having a vertical drift path extending perpendicular to two opposing main surfaces of the semiconductor substrate. The vertical transistor device can be a MOSFET (metal oxide semiconductor field effect transistor) device, an insulated gate bipolar transistor (IGBT) device, or a bipolar junction transistor (BJT).

[0019] The electrodes or terminals of a transistor device are referred to herein as source, drain, and gate. As used herein, these terms also encompass functionally equivalent terminals of other types of transistor devices, such as insulated gate bipolar transistors (IGBTs). For example, as used herein, the term "source" encompasses not only the source of a MOSFET device, but also the emitter of an insulated gate bipolar transistor (IGBT) device and the emitter of a bipolar junction transistor (BJT) device, the term "drain" encompasses not only the drain of a MOSFET device, but also the collector of an insulated gate bipolar transistor (IGBT) device and the collector of a BJT device, and the term "gate" encompasses not only the gate of a MOSFET device, but also the gate of an insulated gate bipolar transistor (IGBT) device and the base of a BJT device.

[0020] The present disclosure provides a transistor design concept for a columnar (such as a columnar) trench power transistor (e.g., a power MOSFET). In this design concept, it is proposed to integrate the gate and field plate in the same columnar trench. This design can be used in combination with a stepped field dielectric, which is a field dielectric having a greater thickness in the lower portion of the columnar trench than in the upper portion of the columnar trench. For example, in some embodiments, this can enable the pitch of the columnar (columnar) trench to be reduced.

[0021] Reducing the pitch in conventional pillar-trench MOSFET designs is challenging because the gate electrode and field plate are arranged in separate trenches, where the gate trench is positioned in a mesa formed between the pillar-trench where the field plate is located. Therefore, the minimum pitch between the pillar-trench is affected by process variations and integration schemes used to observe the minimum distance between the gate trench and the source mesa contact.

[0022] According to the present disclosure, a power transistor device, such as a MOSFET, having a columnar trench is provided, wherein a gate electrode and a field plate are located in the same columnar trench. In some embodiments, the gate and field plate are electrically isolated from each other, which can reduce gate-to-drain charge. The gate electrode and field plate electrode in the same trench are separately contacted with the gate potential and the source potential, respectively, at the die surface, i.e., at the upper open end of the columnar trench.

[0023] In an embodiment, a power transistor device with a pillared trench having a gate and a field plate electrode within the same trench further has a stepped field dielectric, wherein the field dielectric has a greater thickness on a lower portion of the pillared trench sidewall than on an upper portion of the pillared trench sidewall. The field plate has a smaller thickness in the lower portion of the pillared trench and a greater thickness in the upper portion of the pillared trench.

[0024] A single transistor device can have multiple columnar trenches arranged in a regular array. Different arrangements of the columnar trenches are possible, such as orthogonal and hexagonal layouts. The columnar shape can have any lateral shape, such as a circle, and any polygon with a side number n greater than or equal to 3 can be used for the columnar shape. Irregular polygons and elongated shapes are also possible.

[0025] Both the gate electrode and the field plate electrode are accessible at the top of the columnar trench and can be reached by their respective contacts. The use of a stepped field dielectric (e.g., a field oxide) can enable an increased area at the surface of the substrate that can be used to form contacts for the gate electrode and the field plate electrode that are positioned next to each other. In some embodiments, providing columnar trenches that include gate electrodes and field plate electrodes within the same trench can allow for pitch shrinkage and lower RDSonA. In the same or different embodiments, isolating the gate electrode and the field plate electrode using a dielectric material can reduce the gate to drain charge. Lower RdsonA can be provided by using a stepped field oxide. The trade-off between Rdson and gate charge Qg can be further adjusted by layout, for example by modifying the gate mask and contact mask.

[0026] Because the field plate reaches the top of the columnar trench and is positioned adjacent to the gate that also reaches the top of the columnar trench, the entire periphery of the columnar trench is not available for channel formation. The channel of the transistor device can be formed only adjacent to the gate. Since the gate is not positioned adjacent to the entire sidewall, that is, it does not extend 360° adjacent to the sidewall of the trench (because the field plate contacts the surface of the substrate), the size of the channel is correspondingly reduced. In other words, no channel is formed in the area along the columnar trench where the field plate electrode reaches the substrate surface and is positioned adjacent to the periphery of the columnar trench and adjacent to the periphery of the source region and body region. The percentage of available channel formed at each columnar trench can be adjusted by appropriate layout, for example by adjusting the gate mask. The percentage of the columnar trench periphery used for channel formation can be in the range of 15% to 85% of the total columnar trench periphery. Increasing the channel percentage improves Rdson at the expense of gate charge. Fine-tuning the Rdson-Qg trade-off can be achieved by designing the gate layout. For example, a layout with a 50% channel percentage (½ gate) and orthogonal and hexagonal pillar trench arrangements, or a layout with a 75% channel percentage (¾ gate) and orthogonal and hexagonal pillar trench arrangements may be used.

[0027] The integration scheme for gate and field plate in a single pillar trench is compatible with pillar trench technology including polysilicon or metal gate. Gate / source contacts and tungsten wire isolation are compatible with pillar trench and BEOL technology. Potential modulation of the output resistance Ross is provided by varying the thickness of the oxide in the upper part of the field plate in combination with the polysilicon resistor (to integrate buffer functionality to reduce oscillations during switching). The source contact layout can be optimized for device performance (Ron, Vth, DIBL, parasitic turn-on, etc.). Different contact arrangements and configurations are also possible.

[0028] In some designs, the gate charge of the proposed device can show 50% lower Qgd compared to a pillared trench device with a gate grid, while having a similar Ron A. Despite having a thinner gate oxide, the device has a better Ron*Qgd figure of merit (FOM), making the concept attractive for fast switching applications where a low FOM is required.

[0029] As a result of the possibility of reducing the pitch between the pillar trenches, a low voltage pillar trench MOSFET can be provided. The transistor device according to the present disclosure can enable low Rdson and low Qg(d) for low voltage pillar trench MOSFETs, where low voltage refers to a breakdown voltage (BV) <= 40V. The transistor device according to the present disclosure can also be used in higher voltage classes (BV>= 40V), for example for FOM (Figure of Merit) optimized products with low gate charge.

[0030] Figure 1 includes Figures 1A to 1E , and illustrates a transistor device 10 according to various embodiments. Figure 1A illustrates a cross-sectional view of a transistor device 10 according to an embodiment, and Figure 1B illustrates a top view of a transistor device 10 according to an embodiment, Figure 1C illustrates a cross-sectional view of a transistor device 10 according to another embodiment, and Figure 1D illustrates a top view of a transistor device 10 according to another embodiment, and Figure 1E Illustrated is a cross-sectional view of a transistor device 10 according to yet another embodiment.

[0031] Reference Figures 1A to 1E The transistor device 10 shown and described includes a semiconductor substrate 11 having a first main surface 12 and at least one pillar trench 13 arranged in the first main surface 12. The pillar trench 13 includes a lower surface 14, which may also be referred to as a bottom, and sidewalls 15 extending from the lower surface 14 to the first main surface 12.

[0032] The columnar groove 13 may also be referred to as a needle-shaped groove and has a small or narrow perimeter or width proportional to its height / depth in the substrate 11 perpendicular to the first major surface 12, in contrast to the elongated stripe-shaped groove, which has a length in a plane parallel to the first major surface 12 that is greater than its depth in the substrate 11. Using a Cartesian coordinate system, the first major surface 12 can be considered to be in the xy plane, and the height / depth is in the z direction.

[0033] The columnar (needle-shaped) groove 13 may have various shapes in a plan view, such as an octagon, a circle, a square, a hexagon, and a shape in a plan view. A columnar groove 13 that is circular in a plan view has a single continuous sidewall 15. A columnar groove 13 that is square in a plan view has a sidewall 15 having four subsections, with adjacent subsections arranged perpendicular to each other. A columnar groove 13 that is hexagonal in a plan view has a sidewall with six subsections, and so on.

[0034] The transistor device 10 may include a plurality of columnar trenches 13, which may be arranged in a regular array having substantially the same uniform pitch, such as a square grid array of rows and columns. Alternatively, for example, the plurality of columnar trenches 13 are an array of offset rows or a hexagonal array. The mesas 28 are formed by regions of the substrate 11 that laterally surround the columnar trenches 13, the regions being arranged, for example, between adjacent trenches of the plurality of columnar trenches 13. Each columnar trench 13 and its gate electrode 16 and field plate 18 may form part of a transistor cell 24 of the transistor device. Typically, the transistor device 10 includes a plurality of transistor cells 24 that are electrically coupled in parallel to switch a load.

[0035] The transistor device 10 further includes a gate electrode 16 positioned in the pillar trench 13 and electrically insulated from the semiconductor substrate 11 by a gate dielectric 17 positioned on the sidewalls 15 of the pillar trench 13. The transistor device 10 further includes a field plate 18, which may also be referred to as a field electrode. The field plate 18 is also positioned in the pillar trench 13. The field plate 18 is positioned in the pillar trench 13 below the gate electrode 16. The field plate 18 is electrically insulated from the gate electrode 16 and from the semiconductor substrate 11 by a field dielectric 19. The gate electrode 16 is asymmetric about the longitudinal axis 20 of the pillar trench 13.

[0036] The gate electrode 16 can be asymmetrically located within the columnar trench 13 about the longitudinal axis 20 of the columnar trench 13, where asymmetrically located refers to the asymmetrical position of the gate electrode 16 about the longitudinal axis 20 of the columnar trench in at least one plane parallel to the first main surface 12 and perpendicular to the longitudinal axis 10 in the columnar trench 13. In the at least one plane, the remaining portion of the columnar trench 13 is not occupied by the gate electrode 16. Since the gate electrode is asymmetrically located within the columnar trench 13 about the longitudinal axis 20 of the columnar trench 13, the columnar trench 13 has only one-fold rotational symmetry about the longitudinal axis 20 and no other n-fold rotational symmetry, where n is a natural number. For example, the gate electrode 16 can be located in only a single quadrant of a circular (cylindrical) columnar trench 13. In another example, the gate electrode can be located in only two or three adjacent quadrants of the circular columnar trench 13. The gate electrode 16 is provided by a single conductive member arranged in the columnar trench 13. The single conductive member is positioned asymmetrically in the pillar trench 13 about the longitudinal axis 20 .

[0037] The field plate 18 includes a field plate extension 21 extending from the field plate 18 below the gate electrode 16 toward the first main surface 12. The field plate extension 21 extends adjacent to the gate electrode 16 in a lateral direction, wherein the lateral direction designates the xy plane. Thus, the field plate extension 21 and the gate electrode 16 are positioned within a single pillar-shaped trench 13 and are located at or below the plane of the first main surface 12. This enables electrical contact to be made to the gate electrode 16 and the field plate extension 21, which enables electrical connection to be made to the field plate 18 located in the bottom of the pillar-shaped trench 13 at the first main surface 12. The first contact 22 and the second contact 23 of the pillar-shaped trench 13 are arranged adjacent to each other in the lateral direction and can be arranged at opposite sides of the pillar-shaped trench 13, for example, on opposite sides of the longitudinal axis 20.

[0038] In some embodiments, a first contact 22 to gate electrode 16 and a second contact 23 to field plate extension 21 and, thus, field plate 18 (which is located below gate electrode 16) can be positioned within a region of pillar trench 13 as defined by perimeter sidewalls 15 at first major surface 12. The first contact 22 and the second contact 23 of pillar trench 13 can be aligned in the x-direction.

[0039] The semiconductor substrate 11 may be formed of a Group IV semiconductor such as silicon and may be formed of a single crystal epitaxial layer or a single crystal (e.g., a single crystal silicon epitaxial layer or a single silicon crystal). The gate electrode 16 and the field plate 18 including its field plate extension 21 may comprise a conductive material such as polysilicon. The gate dielectric 17 and the field dielectric 19 may be formed of an oxide such as silicon oxide.

[0040] The semiconductor substrate 11 may be doped with a first conductivity type (e.g., n-type) and provide a drift region 25 of the transistor device. A body region 26 comprising a second conductivity type opposite to the first conductivity type (e.g., p-type if the first conductivity type is n-type) is formed on the drift region 25, and a source region 27 comprising the first conductivity type is arranged on and / or in the body region 26. A drain region 29 formed of the first conductivity type is formed at an opposite second surface 30 of the semiconductor substrate 11, such that a vertical drift path is formed between the opposite first surface 12 and the second surface 30. The source region 27 and the drain region 29 are more heavily doped than the drift region 25.

[0041] In some embodiments, the field plate 18 is electrically connected to the source potential. In some embodiments, the columnar trench 13 has a maximum area a in a plane parallel to the first main surface 12. t , and the gate electrode 16 is sized and configured so as to have a maximum area a in a plane parallel to the first major surface g , and make 10%≤(a g / a t ) * 100≤90% or 20%≤(a g / a t ) * 100≤80%, 25%≤(a g / a t ) * 100≤75%. In some embodiments, the field plate extension is sized and configured to have a maximum area a in a plane parallel to the first major surface. e , and make 10%≤(a e / a t ) * 100≤90% or 20%≤(a e / a t ) * 100≤80%, 25%≤(a e / a t ) * 100≤75%. In some embodiments, a e / a g The ratio is in the range of 1 / 9 to 9 / 1.

[0042] In some embodiments, the columnar trench 13 has an outer perimeter (circumference) A in a plane parallel to the first major surface 12. t , and the gate electrode 16 is sized and configured so as to have a maximum outer perimeter length (perimeter length) A in a plane parallel to the first major surface g , and make 10%≤(A g / A t ) * 100≤90% or 20%≤(A g / A t ) * 100≤80%, 25%≤(A g / A t ) * 100≤75%. In some embodiments, the field plate extension is sized and configured to have a maximum perimeter length A in a plane parallel to the first major surface. e , and make 10%≤(A e / A t )*100≤90%or20%≤(A e / A t )*100≤80%,25%≤(A e / A t )*100≤75%. In some embodiments, A e / A g The ratio is in the range of 1 / 9 to 9 / 1.

[0043] By placing the gate electrode 16 in the same trench as the field plate 18, the space within the mesa 28 is not occupied by the separation trench for the gate electrode. This makes it possible to reduce the pitch of the array of pillar trenches 13, i.e., the center-to-center pitch, and the width of the mesa 28, which can reduce RDS(on).Area.

[0044] The gate electrode 16 and the field plate 18 including its field plate extension 21 located in the pillar trench 13 may be electrically insulated from one another using various arrangements of electrically insulating and / or dielectric materials that together provide a field dielectric.

[0045] Figure 1A The diagram shows the Figure 1B A cross-sectional view along line AA is shown.

[0046] In some embodiments, the field dielectric 19 on the sidewalls 15 of the pillar trench has two or more different thicknesses. Figure 1A and Figure 1BField dielectric 19 has a first thickness t1 at a first distance from lower surface 14, where first thickness t1 is less than a second thickness t2 of field dielectric 19 at a second distance from lower surface 14, and has a third thickness t3 at a third distance from lower surface 14, wherein the first distance is greater than the second distance, which in turn is greater than the third distance. A first perimeter of columnar field plate 18 at the first distance is greater than a second perimeter of columnar field plate 18 at the second distance, and the second perimeter is greater than the third perimeter of field plate 18 at the third distance. The first distance may lie in a plane that separates field plate extension 21.

[0047] In some embodiments, the side of field plate 18 includes a step, such that the upper portion of the field plate has a width greater than the width of the lower portion of the field plate, and such that field dielectric 19 has a second thickness t2 in a first region of sidewall 15 of pillar trench 13 and a third thickness t3 in a second region of the sidewall of the pillar trench, where t2 ≤ 1.15t3, or t2 ≤ 1.2t3, or t1 ≤ 1.5t3. In some embodiments, t1 > t2. In some embodiments, t2 > t3. The difference between t2 and t3 is greater than the difference caused by process variations.

[0048] In some embodiments, the side of the field plate 18 includes a step at the transition to the field plate extension 21, so that the field dielectric 19 has a first thickness t1 in a first region of the sidewall 15 of the pillar trench 13 that intersects the field plate extension 21, and has a second thickness t2 in a second region of the sidewall 15 of the pillar trench 13 that intersects the upper portion of the field plate 18, where t1≤1.15t2 or t1≤1.2t2 or t1≤1.5t2.

[0049] Reference Figure 1A and Figure 1B In some embodiments, the intermediate electrically insulating layer 36 is centrally disposed along the longitudinal axis 20 of the pillar trench 13. For example, if the pillar trench 13 is substantially cylindrical, i.e., circular in plan view, the intermediate electrically insulating layer 36 may be cylindrical. The intermediate electrically insulating layer 36 extends vertically from the first major surface 12 into the trench 13 along the longitudinal axis 20 and is centrally positioned within the pillar trench 13 and extends from the first major surface 12 into the pillar trench 13 by a distance greater than the height of the gate electrode 16, i.e., a distance greater than the distance of the bottom (lower surface) of the gate electrode 16 from the first major surface 12. The intermediate electrically insulating layer 36 has a rod-like shape and is located between the inner sidewall of the gate electrode 16 and the field plate extension 21 positioned laterally adjacent to the gate electrode 16.

[0050] The gate electrode 16 is located in a gate recess 37, which is located in the pillar trench 13 adjacent to a section of the sidewall 15 and between the sidewall 15 and the intermediate electrically insulating layer 36. The intermediate electrically insulating layer 36 extends from the first main surface 12 beyond the bottom of the gate electrode 16 and the bottom of the gate recess 37, so that the upper region of the field plate 18 arranged below the gate recess 37 has an annular shape. The lower region of the field plate 18 is located below the intermediate electrically insulating layer 36, and the upper portion of the annular shape fills the remaining area of the pillar trench 13 that is not occupied by the field dielectric 19 on the sidewall 15 and the lower surface 14 of the pillar trench 13.

[0051] A gate recess 37 is positioned asymmetrically in the pillar trench 13 about the longitudinal axis 20. The gate recess 37 is bounded on its outer sidewalls by a gate dielectric 17 arranged on the upper portion of the sidewall 15 of the pillar trench 13, on its inner sidewalls by a central intermediate electrically insulating layer 36, on its lower surface by a lateral electrically insulating layer 38, and on two further sidewalls by vertical electrically insulating layers 39. Thus, the gate recess 37 is electrically isolated from the field plate 18 located below the gate recess 37 by the lateral electrically insulating layer 38, and from the field plate extension 21 positioned laterally adjacent to the inner sidewall of the gate recess 37 by the central intermediate electrically insulating layer 36 and the vertical electrically insulating layer 39. Thus, the gate electrode 16 is electrically isolated from the semiconductor substrate 11 by the gate dielectric 17, and from the field plate 18 and the field plate extension 21 by the intermediate electrically insulating layer 36 and the additional electrically insulating layers 38, 39.

[0052] In some embodiments, gate recess 37 and, therefore, gate electrode 16 have an arcuate shape. The arcuate shape can also be described as an open ring shape with a gap between the two distal ends of the open ring shape. Field plate extension 21 is located in the gap of gate electrode 16. Second contact 23 to field plate 18 is also located in the gap and is laterally adjacent to and separated from gate electrode 16 in pillar trench 13. Field plate extension 21 can also have an arcuate or open ring shape.

[0053] In some embodiments, the field plate 18 is electrically connected to the source potential. This electrical connection can be provided by various arrangements.

[0054] The area of second contact 23 may be smaller than the area of gate electrode 16. First contact 22 may be in direct physical contact with gate electrode 16, such that the bottom (lower surface) of first contact 22 is positioned below first major surface 12. The area of second contact 23 may be smaller than the area of field plate extension 21 at first major surface 12. Second contact 23 may also extend into and be in physical contact with field plate extension 21, and have a bottom (lower surface) positioned below first major surface 12.

[0055] In some embodiments, such as Figure 1A and Figure 1B As shown in FIG, transistor device 10 includes a third contact 31 for each of pillar trenches 13, extending into source region 27 and body region 26 in mesas 28 formed between adjacent pillar trenches in pillar trenches 13. Third contact 31 can be arranged laterally adjacent to second contact 23 for field plate 18, for example aligned in the x-direction. Third contact 31 can be electrically connected to second contact 23 to electrically connect field plate 18 to a source potential. In some embodiments, third contact 31 can be electrically connected to second contact 23 via a conductive trace 32 arranged on first main surface 12 of semiconductor substrate 11.

[0056] As in Figure 1A As shown in FIG, the transistor device 10 may include a metallization layer 33 on the first main surface, the metallization layer 33 including one or more dielectric layers 34 positioned directly on the first main surface 12 and through which the contacts 22, 23, 31 extend. The metallization layer 33 may include: a first electrically conductive redistribution structure 34 extending between and electrically connecting the first contact 22 and the gate electrode 16 to each other, one of the first contacts 22 being located in each of the regular array of pillar-shaped trenches 13; and a second electrically conductive structure 32 electrically connecting the second contact 23 and the third contact 31 to each other and thus electrically connecting the field plate 18 to the source region 27 and the source potential.

[0057] The first contact 22 and the second contact 23 associated with a particular cylindrical trench 13 may be arranged on opposite sides of the cylindrical trench 13, for example on opposite sides of the longitudinal axis 20, as in Figure 1B , as shown in the top view of FIG. This reflects the asymmetric positioning of gate electrode 16 within the region of pillar trench 13. In this embodiment, gate electrode 16 and field plate extension 21 have an open annular shape with a distal end. Gate electrode 16 and field plate extension 21 can be considered to have an arcuate segment of a cylindrical shape. A vertical electrically insulating layer 39 is disposed between the respective distal ends of the open annular shapes of gate electrode 16 and field plate 18 to electrically insulate gate electrode 16 and field plate 18 from each other. Both gate electrode 16 and field plate 18 have an outer perimeter that is slightly less than half the length of the perimeter or inner perimeter of sidewall 15 of pillar trench 13. Together, field plate extension 21 and the open annular shape of gate electrode 16 laterally surround intermediate electrically insulating layer 36, which has the shape of a substantially cylindrical member. In some embodiments, second contact 23 to field plate 18 and / or first contact 22 to gate electrode 16 also physically contact intermediate electrically insulating layer 36.

[0058] Field plate 18 is located below gate electrode 16 and is connected to field plate extension 21. The upper portion of field plate 18 includes a ring-shaped structure and is located between a central intermediate electrical insulating layer 36 and a field dielectric 19, which is positioned on the sidewalls 15 of pillar-shaped trench 13. The lower portion of field plate 18 is located below intermediate electrical insulating layer 36 and fills the area of pillar-shaped trench 13 defined by field dielectric 19, which lines the lower surface 14 and sidewalls 15 of pillar-shaped trench 13. For example, if the pillar-shaped trench has a substantially cylindrical shape, the lower portion of field plate 18 can have a cylindrical shape. A lateral electrically insulating intermediate layer 38 can also be arranged between the lower surface of gate electrode 16 and field plate 18.

[0059] Because the field plate extension 21 reaches the top of the columnar trench 13 and is positioned next to the gate electrode 16 that also reaches the top of the columnar trench 13, the channel of the transistor device 10 is not formed in the region along the columnar trench 12 where the field plate 18 reaches the perimeter of the first major surface 12. The percentage of the trench perimeter used to form the channel can be in the range of 15% to 85% of the total columnar trench perimeter. Increasing the channel percentage improves Rdson at the expense of gate charge. Fine tuning of the Rdson-Qg trade-off can be achieved by the design of the gate electrode 16. For example, a layout with a 50% channel percentage (1 / 2 gate) and an orthogonal and hexagonal columnar trench arrangement, or a layout with a 75% channel percentage (3 / 4 gate) can be used.

[0060] Figure 1C and Figure 1D The transistor device 10 according to another embodiment is shown in FIG. Figure 1D A cross-sectional view and a top view along line AA are shown. Figure 1C and Figure 1D transistor devices with Figure 1A and Figure 1B , differs from the transistor device illustrated in FIG, in that second contact 23 is sized, shaped, and positioned so as to be in direct contact with field plate extension 21 and with body region 26 and source region 27 formed in mesa 28. Second contact 23 can be considered to extend through sidewall 15 of pillar trench 13 so that its bottom (lower surface) is positioned in field plate extension 21 on field dielectric 19 and is also in contact with body region 26. Thus, a single contact 22 electrically connects field plate extension 21 and field plate 18 with body region 26 and source region 27, and thus electrically couples field plate 18 to the source potential.

[0061] exist Figure 1A and Figure 1BIn the transistor device 10 of the embodiment illustrated in FIG, an electrical connection of the field plate 18 to the source potential is provided by means of a second metallization structure 32, which is positioned on a dielectric layer 34 located on the first main surface 12 and extends between the separated second contact 23 and the third contact 31. The second metallization structure 32 may be formed from the same deposition layer as the contacts 23, 31 by patterning a portion of the deposition layer located on the dielectric layer 34 to form an electrically conductive trace. Figure 1C and Figure 1D The transistor device 10 of the embodiment shown in FIG. Figure 1A and Figure 1B The embodiment illustrated in FIG differs in that a single second contact 23 electrically connects the field plate 18 to the source region and is in direct contact with both the source region 27 and the field plate 18 . Figure 1C and Figure 1D Further features of the transistor device 10 of the embodiment illustrated in FIG. Figure 1A and Figure 1B The features of the transistor devices shown in FIG.

[0062] Figure 1E A transistor device 10 according to an embodiment is shown. Figures 1A to 1D The transistor device illustrated in FIG differs in the size, shape and position of an intermediate electrically insulating layer 36 located between the field plate extension 21 and the gate electrode 16 in the upper portion of the trench pillar trench 13 . Figure 1E Further features of the transistor device 10 of the embodiment illustrated in FIG. Figure 1A and Figure 1B The features of the transistor devices shown in FIG.

[0063] exist Figure 1E In the transistor device 10 of the embodiment illustrated in FIG, the intermediate electrically insulating layer 36 extends from the first main surface 12 into the pillar-shaped trench 13 by a distance so that its end is located between the lower surface of the gate electrode 16 and the field plate 18 and is aligned with the lateral electrically insulating layer 38 on the lower surface of the gate recess 37. The intermediate electrically insulating layer 36 forms the inner side of the gate recess 37 for the gate electrode 16, but is not aligned with the inner side of the gate recess 37. Figures 1A to 1D, the intermediate electrically insulating layer 36 does not extend further into the conductive material of the field plate 18 and beyond the lateral electrically insulating layer 38 on the bottom of the gate recess 37. The field plate 18 arranged below the gate electrode 16 fills the entire area of the pillar trench 13 that is not occupied by the field dielectric 19. The intermediate electrically insulating layer 36 can be arranged asymmetrically with respect to the longitudinal axis 20 of the pillar trench 13, for example, offset in the lateral direction from the longitudinal axis 20 toward the gate electrode 16. The intermediate electrically insulating layer 36 can also form two further sides of the gate recess 37, so that the gate electrode 16 in the gate recess 37 is electrically insulated from the field plate 18 and its field plate extension 21 also located in the pillar trench 13.

[0064] In some embodiments, field plate extension 21 can extend along longitudinal axis 20, with gate recess 37 laterally offset from longitudinal axis 20. The bottom of gate recess 37 is formed by lateral electrically insulating layer 38. Field plate 18 fills the region of pillar trench 13 below gate electrode 16 and below lateral electrically insulating layer 38 that is not occupied by field dielectric 19.

[0065] exist Figure 1E In the transistor device 10, the field dielectric 19 has two different thicknesses on the sidewall 15 of the pillar trench 13. The first thickness t1 of the field dielectric 19 at a first distance from the lower surface 14 is less than the second thickness t2 of the field dielectric at a second distance from the lower surface 14, where the first distance is greater than the second distance. The side of the field plate 18 includes a step, such that the field dielectric 19 has a first thickness t1 in a first region of the sidewall 15 of the pillar trench 13 adjacent to the field plate extension 21 and laterally adjacent to the gate electrode 16, and has a second thickness t2 in a second region of the sidewall 15 of the pillar trench 13 adjacent to the field plate 18 below the gate electrode 16, where t1≤1.15t2, t1≤1.2t2, or t1≤1.5t2. In some embodiments, t1>t2. In some embodiments, t2>t3. The difference between t1 and t2 is greater than the difference caused by process variations.

[0066] A method of manufacturing a gate electrode and a field plate in a pillar-shaped trench will now be described with reference to FIG. 2 , which includes Figures 2A to 2L The method described with reference to FIG. 2 can be used to manufacture Figures 1A to 1D The pillar trench 13 and the transistor device 10 are shown in FIG.

[0067] Reference Figure 2A, a semiconductor substrate 11 having a first main surface 12 and at least one columnar trench 13 is provided. The semiconductor substrate 11 may include a plurality of columnar trenches 13, the plurality of columnar trenches 13 being arranged in a regular array, such as an offset row or square grid array, each having substantially the same structure. The plurality of columnar trenches 13 may be processed using the same processing steps. The columnar trench 13 has a lower surface 14 and sidewalls 15, the lower surface 14 may also be referred to as the bottom of the trench, and the sidewalls 15 extend from the lower surface 14 to the first main surface 12. The sidewalls 15 and the lower surface 14 are lined with a field dielectric 19, and the remaining portion of the columnar trench 13, i.e., the central region defined by the field dielectric 19, is filled with a first conductive material 40.

[0068] The semiconductor substrate 11 may be formed of silicon, such as a single-crystal epitaxial silicon layer or a silicon single crystal. The body region 25 and the source region 27 may have been formed, for example, by implanting suitable dopants into the first main surface 12. The first conductive material 40 may be selected so as to be suitable for forming a field plate. For example, the first conductive material 40 may be polycrystalline silicon. The field dielectric 19 may be formed of an oxide, such as silicon oxide. The dielectric material 19 may also extend above the first main surface 12.

[0069] In one embodiment, the method is as described in reference Figure 2B In an alternative embodiment, the method is as described with reference to Figure 2C and Figure 2D Continue as described.

[0070] Reference Figure 2B , a portion of the first conductive material 40 is removed from the upper portion of the pillar trench 13, exposing the field dielectric 19 on the upper portion of the sidewall 15 of the pillar trench 13. The first conductive material 40 can be removed preferentially over the material of the field dielectric 19, for example, by selective etching (e.g., wet etching). The selectivity of the conductive material 40 over the material of the field dielectric 19 for etching can be approximately 100 to 1 (in some examples, it can also be less, such as 50 to 1). In some embodiments, a portion (e.g., the surface) of the exposed field dielectric 19 is also removed in this process (in other embodiments, this can be done in a separate process), thereby reducing the thickness of the field dielectric 19 in the upper portion of the pillar trench 13 and also on the first major surface 12. The upper portion of the sidewall 15 of the pillar trench 13 and the first major surface 12 remain covered with a thinner layer of field dielectric 19. The field dielectric 19 then has two different thicknesses on the sidewalls 15, a first greater thickness in a lower section in contact with the remainder of the first conductive material 40 and a second smaller thickness in an upper section exposed from the conductive material 40. The method may be as described with reference to Figures 2E to 2L Continue as described.

[0071] Reference Figure 2C In an alternative embodiment, for example, by selective etching (eg, wet etching) from the uppermost portion of the pillar trench 13 to the portion adjacent to the uppermost portion of the pillar trench 13. Figure 2B The embodiment illustrated in FIG. 1 removes the first conductive material 40 within the trench pillar trench 13 to a lesser depth, e.g., preferentially removes material of the field dielectric 19 over that of the field dielectric 19. The field dielectric 19 is also exposed to a lesser depth in the upper and middle portions of the sidewalls 15 of the pillar trench 13. The thickness of the exposed areas of the field dielectric 19 can also be slightly reduced by this process.

[0072] Reference Figure 2D , a further removal process is performed to remove a further section of the first conductive material 40 and a portion of the field oxide 19 on the sidewalls 15 in the uppermost portion of the pillared trench 13 and on the sidewalls 15 in the middle section of the pillared trench 13. In this embodiment, the field dielectric 19 includes three different thicknesses on the sidewalls 15 of the trench. The thickness is greatest in the lower portion of the trench where the field dielectric 19 is in contact with the remainder of the first conductive material 40. The field dielectric 19 has a second thickness slightly less than the first thickness in the middle portion that is not covered during the second etching process, and has a third thickness less than the second thickness in the uppermost portion of the trench 13, which is partially removed in both removal (e.g., etching) processes. This arrangement is similar to that in Figure 2B In contrast to the embodiment shown in FIG, in which the field dielectric has only two different thicknesses on the sidewalls 15. Then, an alternative approach is as described with reference to Figures 2E to 2L Continue as described.

[0073] Reference Figure 2E , a second conductive material 41 is deposited, extending over the exposed field dielectric 19 on the first main surface 12 and on the sidewalls 15 of the pillar trench 13. The second conductive material 41 may also cover the exposed upper surface of the first conductive material 40. The second conductive material 41 forms a conductive layer around a gap 42, which is centrally located in the pillar trench 13 and extends along the longitudinal axis 20 of the pillar trench 13. The first conductive material 40 and the second conductive material 41 may have the same or similar composition, such as polysilicon. The gap 42 is then filled with an electrically insulating material 43 (e.g., silicon oxide) and forms a central intermediate electrically insulating layer 36.

[0074] Reference Figure 2F A planarization process may be performed to remove the second conductive material 41 from the first main surface 12 and expose the remaining portion of the field dielectric layer 19 arranged on the first main surface 12 . The method continues by forming a gate recess 37 and a gate electrode 16 in an upper portion of the pillar trench 13 .

[0075] Reference Figure 2G A mask 44 is formed on the first major surface 12, the mask 44 including an opening 45 that is sized, configured, and arranged to form the gate recess 37. The opening 45 is sized, configured, and arranged to expose a region of the central electrically insulating material 43 and a region of the second conductive material 25, the region of the second conductive material 25 being positioned laterally asymmetrical about the longitudinal axis 20 of the pillar-shaped trench 13 and located within the pillar-shaped trench 13. For example, the opening 45 in the mask 44 can have an arcuate shape, which can also be described as an open annular shape having a gap between its two distal ends. The remaining portion of the second conductive material 41 within the pillar-shaped trench 13 and, optionally, the region of the electrically insulating layer material 43 are covered by the mask 44. The exposed region of the second conductive layer 41 is removed to form a single gate recess 37 located in a section of the region of the pillar-shaped trench 13. The intermediate electrically insulating layer 36 in combination with the mask 44 acts as an etch stop and at least partially assists in self-aligning the position of the gate recess 37 within the pillar trench 13. The gate recess 37 is lined on its outer side by the field dielectric 19 located on the sidewalls 15 of the trench 13 and on its inner side by the exposed portion of the intermediate electrically insulating layer 36. At this stage of the method, the lower surface of the gate recess 37 and two further sidewall sections are formed by the exposed second conductive material 41.

[0076] Reference Figure 2H , the mask 44 is removed. The exposed region of the field dielectric 19 is removed, and the upper section of the sidewall 15 of the pillar trench 13 and the first main surface 12 are exposed. Figure 2IA further electrically insulating layer 17 is deposited or grown, for example by thermal oxidation, covering the lower surface and sidewall sections of the gate recess 37 so that the gate recess 37 is lined with an electrically insulating and / or dielectric material. The thickness of the electrically insulating layer 17 on the sidewalls 15 of the pillar trench 13 is suitable for providing the gate dielectric 17 of the transistor device 10. The thickness of the electrically insulating layer 17 can be greater on the lower surface and other sidewall sections of the gate recess 37. If the gate dielectric is deposited, then the thickness of the gate dielectric on the lower surface and sidewalls (i.e., sections 17, 38, and 39) can be the same. If the gate dielectric is thermally grown, the regions on the lower surface and sidewalls formed of polysilicon, i.e., sections 38, 39, can have a greater thickness than the section 17 formed on the sidewalls formed of silicon. For example, for thermally grown silicon oxide, the thickness of the gate dielectric thermally grown in sections 38, 39 can be two to three times greater than in section 17 because silicon oxide grows faster on polysilicon than on silicon. A conductive material 47 (e.g., polysilicon) is then inserted into gate recess 37 to form gate electrode 16, which is electrically insulated from second conductive material 41 in pillar trench 13, which forms field plate 18 and field plate extension 21, and from semiconductor substrate 11 by electrically insulating material 17.

[0077] Reference Figure 2J The method may continue by depositing one or more dielectric layers 48 on the first main surface 12, the one or more dielectric layers 48 covering the pillar trenches 13 and the gate electrodes 16 and the field plate extensions 21. Figure 2K For at least one of the pillar trenches 13, a first opening 49 exposing the gate electrode 16 can be formed in the dielectric layer 48, and a second opening 50 exposing the second conductive material 41 can be formed in a position laterally adjacent to the gate electrode 16. In some embodiments, the second opening 50 also exposes a region of the mesa 28 formed adjacent to the sidewall 15 of the pillar trench 13. An etching process can then be performed to remove a portion of the second conductive material 41 and the material of the gate electrode 16, and if exposed, to remove the adjacent portion of the mesa 28 to form a first contact opening 51 and a second contact opening 52. The etching process can also be used to form a third opening for the contact 31 to the mesa 28.

[0078] Reference Figure 2L2 , a conductive material 53 may then be inserted into the first opening 51 and the second opening 52 to form a first contact 22 to the gate electrode and a second contact 23 to the second conductive material 41. The second conductive material 41 forms the field plate extension 21 and is electrically connected to the first conductive material 40 in the lower portion of the pillar trench 13, which forms the field plate 18 within the lower portion of the pillar trench 13. In a plane not shown in FIG2 , the conductive material 53 is also inserted into the third opening to form a contact 31 to the mesa 28. The conductive material 53 may be polysilicon or a metal and may include two or more sublayers of different compositions, such as different metals or alloys.

[0079] In some embodiments, a first lateral redistribution structure 56 may be formed, extending between the first contacts 22 and electrically connecting the gate electrodes 16 in different pillar trenches 13. A second lateral redistribution structure 32 may be formed, extending between the second contacts 23 and electrically connecting the field plate 18, the body region 26, and the source region 27.

[0080] The first lateral redistribution structure 56 and the second lateral redistribution structure 32 may be formed simultaneously with the insertion of the conductive material 53 into the first and second openings 51, 52, and the third opening for the mesa contact 31. The conductive material is further formed on the first main surface and then patterned to form separate lateral redistribution structures 56, 32. The lateral redistribution structure 56 is used to electrically connect the first contact 22 and the gate electrode 16 to each other. The second lateral redistribution structure 32 is used to electrically connect the second contact 23 and the field plate 18, and the contact 31 and the mesa 28 to each other.

[0081] A method for forming a gate electrode and a field plate in a pillar-shaped trench according to another embodiment will now be described with reference to FIG. 3 . FIG. 3 includes Figures 3A to 3K The method described with reference to FIG. 3 can be used to manufacture Figure 1E The pillar trench 13 and the transistor device 10 are shown in FIG.

[0082] Reference Figure 3A , as referenced Figure 2A As described, a semiconductor substrate 11 having a first main surface 12 and at least one pillar trench 13 is provided. Each of the pillar trenches 13 has a lower surface 14 and a sidewall 15 extending from the lower surface 14 to the first main surface 12. The first main surface 12, the sidewall 15, and the lower surface 14 of the pillar trench 13 are covered with a dielectric layer 19, which surrounds a gap in the center of each of the pillar trenches 13. The gap is filled with a first conductive material 40 for forming a field plate.

[0083] Reference Figure 3BThe first conductive material 40 is removed from the upper portion of the pillar trench 13, exposing a section of the field dielectric 19 located on the sidewall 15 of the pillar trench 13. For example, the first conductive material 40 (e.g., polysilicon) is removed preferentially over the material of the field dielectric 19 (e.g., SiO2) by selective etching.

[0084] Reference Figure 3C , a portion of the exposed field dielectric 19 is removed, reducing the thickness of the field dielectric 19 on the sidewalls 14 of the upper portion of the pillar trench 13 and on the first major surface 12, so that the field dielectric 19 has a smaller thickness on the sidewalls 15 in the upper portion of the pillar trench 13 and a larger thickness in the lower portion of the pillar trench 13. In this embodiment, the field dielectric 19 has two different thicknesses on the sidewalls 15, a first larger thickness in the lower section that is in contact with the remaining portion of the first conductive material 40 and a second smaller thickness in the upper section that is exposed from the conductive material 40.

[0085] Reference Figure 3D A second conductive material 41, such as polysilicon, is then inserted into the pillar trench 13 to fill the trench, thereby forming a structure for a field plate 18 having a larger width in the upper portion of the pillar trench 13 and a smaller width in the lower portion of the pillar trench 13. One or more further dielectric materials 48 are then deposited on the first main surface 12, the one or more further dielectric materials 48 covering the pillar trench 13 and the second conductive material 41 within the pillar trench 13.

[0086] Reference Figure 3E A gate recess 37 is formed in an upper portion of the pillar trench 13 by removing a section of the second conductive material 41 so as to expose the field dielectric 19 of the sidewalls 15 of the pillar trench 13. The gate recess 37 is defined on its outer surface by the field dielectric 19 and on its inner sidewalls and remaining sidewalls by the second conductive material 41. The gate recess 37 is positioned asymmetrically in the laterally direction about the longitudinal axis 20 of the pillar trench.

[0087] The thickness of the exposed region of the field dielectric 19 on the uppermost section 15 of the sidewall 15 of the pillar trench 13 may be further reduced, as in Figure 3F and can be completely removed. Figure 3G, an electrically insulating layer 17 is then deposited into the gate recess 37, the electrically insulating layer 17 lining the lower surface and sidewalls of the gate recess 37, including the sidewalls 15 of the pillared trench 13, where it forms isolation regions 38 and 39 between the gate electrode 16 and the field plate electrode 18 of the transistor device 10, and the gate dielectric 17, as well as the sidewalls of the gate recess 37 formed by the second conductive material 41. Alternatively, the electrically insulating layer 17 can be grown, for example, by thermal oxidation of the sidewalls and lower surface of the gate recess 37, including the sidewalls 15 of the pillared trench 13, to form the gate dielectric 17 and the isolation regions 38 and 39 between the gate electrode 16 and the field plate electrode 18 of the transistor device 10, and between the gate electrode 16 and the sidewalls of the gate recess 37 formed by the second conductive material 41.

[0088] Reference Figure 3H , a conductive material 47 is then inserted into the dielectric-lined gate recess 37 to form the gate electrode 16. The gate electrode 16 is electrically insulated from the second conductive material 41 by the dielectric layer 17, which lines the sidewalls and lower surface of the gate recess 37 and also forms the gate dielectric 17 on the sidewalls 15 of the pillar-shaped trench 13. The second conductive material 41 forms the field plate extension 21, which is located in the upper portion of the trench 13 and is laterally adjacent to the height of the gate electrode 16 and substantially parallel to the gate dielectric 17. The second conductive material 41 also forms the upper portion of the field plate 18 that is partially located below the gate electrode 16.

[0089] Reference Figure 3I A planarization process may be performed to expose the first main surface 12, and then one or more dielectric layers 48 may be deposited on the planarized surface, the one or more dielectric layers 48 also covering the pillar trenches 13. Contacts to the gate electrode 16 and the field plate 18 may be made with reference to Figure 2K and Figure 2L The diagram is formed in a similar manner.

[0090] Reference Figure 3J , forming a first opening 51 through dielectric layer 48, the first opening 51 exposing gate electrode 16 and extending into gate electrode 16. Forming a second opening 52, the second opening 52 exposing second conductive material 41 and sized and configured to extend into mesa 28 in a region adjacent to sidewall 15 of pillar trench 13. Figure 3KConductive material 53 is inserted into the openings 51 and 52 to form first contacts 22 to the gate electrode 16 and second contacts 23 to the field plate extension 21 and the mesa 28. One first contact 22 and one second contact 23 are formed in each of the pillar trenches 13. The first contacts 22 can be positioned on the dielectric layer 48 or laterally connected together by a lateral redistribution structure 56 in the dielectric layer 48, and the second contacts 23 can be electrically connected to each other by a second lateral redistribution structure 32 extending on the upper surface of the dielectric layer 48. The first lateral redistribution structure 56 and the second lateral redistribution structure 32 can extend substantially parallel to each other and can be positioned on opposite sides of the pillar trench 13.

[0091] include Figures 4A to 4H FIG. 4 illustrates a view of a metallization layer 60 according to various embodiments, which may be located on the first main surface 12 of the semiconductor substrate 11 of the transistor device 10 .

[0092] Figure 4A illustrates a top view of a transistor device 10 having a metallization layer 60 according to an embodiment, and Figure 4B Illustrated is a cross-sectional view of a transistor device 10 having a metallization layer 60 according to an embodiment. Figure 4A The top view shows the Figure 1C A top view of the transistor device 10, and Figure 4B The cross-sectional view shows the Figure 1D 1. A cross-sectional view of the transistor device 10.

[0093] In this embodiment, gate electrode 16 has an open ring-type shape with an outer periphery corresponding to slightly less than 50% of the outer periphery of sidewall 15 of pillar-shaped trench 13. Field plate extension 21 also has an open ring-type structure and has an outer periphery slightly less than 50% of the inner periphery of sidewall 15 of pillar-shaped trench 13 due to an electrically insulating layer 39 arranged between gate electrode 16 and the distal end of field plate extension 21. One first contact 22 for the gate electrode and one second contact 23 for field plate 18 are provided for each pillar-shaped trench 13.

[0094] The columnar trenches 13 are arranged in a square grid array or rows and columns so that the distances between the columnar trenches 13 in two perpendicular directions (the x-direction and the y-direction using a Cartesian coordinate system) are substantially the same. The columnar trenches 13 can be considered to be arranged in a plurality of columns, each extending in the y-direction. The first contacts 22 electrically connected to the corresponding gate electrodes 16 in the columnar trenches 13 of the columns are electrically connected to each other by strip-shaped conductive traces 61 of the metallization layer 60 extending in the y-direction. The conductive traces 61 are positioned on each of the first contacts 22 and are in electrical contact with each of the first contacts 22, and are electrically insulated from the mesas 28 located between the columnar trenches 13.

[0095] In this embodiment, second contact 23 is sized, shaped, and positioned to contact field plate 18 and mesa 28, and in particular, to contact body region 26 and source region 27 located in mesa 28 adjacent to the columnar trench. A fourth contact 62 is provided, one located in mesa 28 between adjacent columnar trenches formed in a column of columnar trenches 13. Fourth contact 62 is electrically connected to source region 27 and, optionally, also to body region 26. Fourth contact 62 may have a depth from first main surface 12 into semiconductor substrate 11 so as to extend into source region 27 and body region 26. Fourth contact 62 may be arranged in a column with second contact 23, the column extending in the y-direction and substantially extending to the column of first contact 22 for the gate electrode. Second contact 23 and fourth contact 62 are electrically connected to each other via a conductive metallization structure 63 in first main surface 12. Conductive metallization structure 63 may be strip-like and extend in the y-direction and is parallel to and spaced apart from conductive trace 61 connecting gate electrode 16. Conductive trace 63 is electrically connected to field plates 18 of the column and source and body regions 27 and 26 in mesas 28.

[0096] The metallization structure 60 includes further conductive traces 64, which are located on the dielectric layer on the first main surface 12 and are electrically connected to the contacts 23, 62 and the metallization structure 63 located in the semiconductor substrate 11. The conductive trace 61 is located on the dielectric layer 34 on the first main surface 12 and electrically connects the first contact 22 to the gate electrode 16. The conductive trace 64 extends substantially parallel to the conductive trace 61. The conductive trace 64 can be wider than the conductive trace 61. Since the pillar-shaped trenches 13 are arranged in a plurality of columns extending substantially parallel to each other in the y-direction, two conductive traces 61, 64 are provided for each column of pillar-shaped trenches 13, so that the traces 61, 64 are alternately connected to the gate and source potentials. The traces 61, 64 can be arranged in a layer of the metallization layer 60, which is integrated with the conductive material forming the contacts 22, 23, 62 and the conductive connection 63 and is formed at the same time.

[0097] Figure 4C illustrates a top view of a transistor device 10 including a metallization layer according to another embodiment, and Figure 4D 1 shows a cross-sectional view of a transistor device 10 including a metallization layer according to another embodiment. Figure 4C and Figure 4D The transistor device 10 shown in FIG. Figure 4A and Figure 4B The transistor device 10 shown in FIG. 1 differs in the ratio between the area of the gate electrode 16 at the first main surface 12 within one pillar-shaped trench 13 and the area of the field plate extension 21, as well as the ratio between the length of the perimeter of the gate electrode 16 and the length of the perimeter of the field plate 18 at the first main surface 12 within one pillar-shaped trench 13. In this embodiment, the gate electrode 16 has an open-ring-type shape with an outer perimeter corresponding to slightly less than 75% of the outer perimeter of the sidewall 15 of the pillar-shaped trench 13. The field plate extension 21 also has an open-ring-type structure and, due to the electrically insulating layer 39 disposed between the respective distal ends of the gate electrode 16 and the field plate extension 21, has an outer perimeter slightly less than 25% of the inner perimeter of the sidewall 15 of the pillar-shaped trench 13. The open-ring-shaped gate electrode 16 and the open-ring-shaped field plate extension 21, together with the electrically insulating layer 39, laterally surround the central, rod-shaped intermediate electrically insulating layer 36 within the pillar-shaped trench 13.

[0098] The positioning of the second contact 23 of the field plate 18 is similar to Figure 4A The difference in FIG. 1 is that it is no longer aligned in the x-direction with the first contact 22 of the gate electrode 16 for this columnar trench 13, but is offset in the y-direction. A fourth contact 62 is also provided, which is located between the mesas 28 between two adjacent columnar trenches 13 of a column of columnar trenches 13 extending in the y-direction. The second contact 23 and the fourth contact 62 are electrically connected by a conductive connection 63, as in FIG. Figure 4A . Metallization layer 60 also includes strip-like conductive traces 64 located on dielectric layer 34 on first major surface 12. Conductive traces 64 are located on and electrically connected to conductive connections 63 formed in dielectric layer 34, and are also electrically connected to mesas 28 and field plates 18. Conductive traces 64 extend substantially parallel to conductive traces 61 in the y-direction, which are located on dielectric layer 34 and electrically connected to gate contacts 22 of a particular column of pillar-shaped trenches 13. Conductive traces 64 can be integrated with conductive connections 63 and contacts 23, 61, and conductive traces 61 can be integrated with contacts 22. Conductive traces 61 and 64 are substantially coplanar.

[0099] Figure 4E illustrates a top view of a metallization layer 60 and a transistor device 10 according to another embodiment, and Figure 4F A cross-sectional view of a metallization layer 60 and a transistor device 10 is shown according to another embodiment, which is similar to the embodiment shown in FIG. Figure 4A and Figure 4B The embodiment illustrated in FIG. 1 differs in that the columnar trenches 13 are arranged in columns that are offset from one another, ie, offset in the Y direction, so that the columnar trenches 13 have a hexagonal arrangement.

[0100] Each of the columnar trenches 16 has an open ring-shaped gate electrode 16 and an open ring-shaped field plate 18, which are substantially semicircular, as shown in FIG. Figure 4A As in the embodiment shown in FIG. Figure 4A , each of the pillar trenches 13 is associated with a first contact 22 for the gate electrode 16 and a second contact 23 for the field plate 18 in the pillar trench 13. The second contact 23 extends into the adjacent region of the mesa 28 to electrically connect the field plate to the body region 26 and the source region 27. In this embodiment, the shape of the conductive trace 63 extending between the second contacts 23 is different from Figure 4A In this embodiment, the conductive traces 63 have a zigzag structure such that they are positioned substantially equidistantly between the columnar trenches 13 within a column (in the y-direction) and between the columnar trenches 13 of the column and the adjacent column. The first contacts 22 and the second contacts 23 of a columnar trench 13 of a column are aligned in the x-direction, but are offset in the y-direction from the first contacts 22 and the second contacts 23 of a columnar trench 13 of an adjacent column.

[0101] The metallization layer 60 further includes: a strip-like conductive trace 61, which is electrically connected to the gate electrode 16 of the pillar trench 13 and the plurality of first contacts ss; and a conductive trace 64, which extends substantially parallel to the conductive trace 61 and is electrically connected to the second contacts 23, and thus to the source region 27 and the field plate 18.

[0102] Figure 4G illustrates a top view of a metallization layer 60 and a transistor device 10 according to another embodiment, and Figure 4H 1 shows a cross-sectional view of a metallization layer 60 and a transistor device 10 according to another embodiment. Figure 4E As shown in the top view of FIG, the columnar trenches 13 are arranged in offset columns. Each columnar trench 13 includes a gate electrode 16 and a field plate 18, having a Figure 4C. Gate electrode 16 has an open ring type shape having an outer periphery corresponding to slightly less than 75% of the outer periphery of sidewall 15 of pillar-shaped trench 13, and field plate extension 21 also has an open ring type structure and has an outer periphery slightly less than 25% of the inner periphery of sidewall 15 of pillar-shaped trench 13 due to the arrangement of electrical insulating layer 39 between respective distal ends of gate electrode 16 and field plate extension 21.

[0103] In this embodiment, the second contacts 23 for the field plate extensions 21 are arranged offset from the first contacts 22 for the gate electrodes 16 of a particular pillar trench 13. The conductive traces 63 extending between the second contacts 23 also have a zigzag or meandering structure such that they are substantially equidistant between adjacent pillar trenches 13 in one column of the array and between pillar trenches 13 in an adjacent column.

[0104] In summary, a power MOSFET having a columnar trench is provided, wherein a gate electrode and a columnar field plate are located in the same columnar trench. The gate electrode and the columnar field plate are electrically isolated from each other to reduce gate-to-drain charge. The gate electrode and the field plate in the same trench can be separately contacted at the die surface, i.e., at the upper end of the columnar trench to contact the gate potential and the source potential, respectively.

[0105] By placing the gate electrode and field plate electrode in the same trench, pitch shrinkage and lower RDSonA can be achieved. By isolating the gate electrode and field plate electrode with dielectric material, low gate-to-drain charge can be achieved. Using a stepped field oxide can also provide lower RdsonA.

[0106] Due to the possibility of reducing the pitch between the pillar trenches, a low voltage pillar trench MOSFET can be provided. The transistor device according to the present disclosure can enable low Rdson and low Qg(d) for low voltage pillar trench MOSFETs, where the low voltage is BV≤40V. The transistor device according to the present disclosure can also be used in higher voltage classes (BV≥40V), for example for FOM (Figure of Merit) optimized products with very low gate charge.

[0107] Although the present disclosure is not so limited, the following numbered examples illustrate one or more aspects of the present disclosure.

[0108] Example

[0109] Example 1. A transistor device comprising:

[0110] a semiconductor substrate comprising a first major surface;

[0111] a columnar trench disposed in the first major surface and comprising a lower surface and a sidewall extending from the lower surface to the first major surface;

[0112] a gate electrode located in the pillar-shaped trench and electrically insulated from the semiconductor substrate by a gate dielectric,

[0113] a field plate, which is positioned in the pillar-shaped trench below the gate electrode and is electrically insulated from the gate electrode and the semiconductor substrate by a field dielectric,

[0114] wherein the gate electrode is asymmetric about the longitudinal axis of the columnar trench, and

[0115] The field plate includes a field plate extension extending from the field plate toward the first main surface and adjacent to the gate electrode in a laterally direction.

[0116] Example 2. The transistor device according to Example 1, further comprising:

[0117] a first contact extending from the first main surface into the pillar-shaped trench, the first contact being electrically connected to the gate electrode, and

[0118] a second contact extending from the first main surface into the pillar-shaped trench, the second contact being electrically connected to the field plate,

[0119] Wherein the first contact and the second contact are arranged laterally adjacent to each other.

[0120] Example 3. The transistor device of Example 2, wherein the first contact and the second contact are located on opposite sides of the pillar-shaped trench.

[0121] Example 4. The transistor device of any of Examples 1 to 3, wherein the field plate extension is laterally electrically insulated from the gate electrode by an intervening dielectric.

[0122] Example 5. The transistor device of Example 4, wherein the intervening dielectric is centered in the pillar-shaped trench and extends from the first major surface to the field plate.

[0123] Example 6. The transistor device of any one of Examples 1 to 5, wherein the field plate extension and the gate electrode both comprise an arc shape.

[0124] Example 7. The transistor device of any one of Examples 1 to 6, wherein the gate electrode is provided by a single conductive portion having an open annular shape with a gap between two distal ends of the open annular shape.

[0125] Example 8. The transistor device of Example 6, wherein the field plate extension is located in the gap of the gate electrode.

[0126] Example 9. A transistor device according to any one of Examples 1 to 8, wherein a first thickness of the field dielectric at a first distance from the lower surface is less than a second thickness of the field dielectric at a second distance from the lower surface, wherein the first distance is greater than the second distance, and wherein a first perimeter of the columnar field plate at the first distance is greater than a second perimeter of the columnar field plate at the second distance.

[0127] Example 10. A transistor device according to Example 9, wherein the side of the field plate includes a step so that the upper portion of the field plate has a width greater than the width of the lower portion of the field plate, and so that the field dielectric has a first thickness t1 in a first region of the sidewall of the pillar trench and a second thickness t2 in a second region of the sidewall of the pillar trench, wherein t1≤1.15t2 or t1≤1.2t2 or t1≤1.5t2.

[0128] Example 11. The transistor device of any of Examples 7 to 10, wherein the second contact is positioned at least partially in the gap.

[0129] Example 12. The transistor device of any one of Examples 1 to 11, wherein the field plate extension extends to the first major surface.

[0130] Example 13. The transistor device of any one of Examples 1 to 12, wherein

[0131] The columnar groove has a maximum area a in a plane parallel to the first major surface. t , and the gate electrode is sized and configured so as to have a maximum area a in a plane parallel to the first major surface g , and make 10%≤(a g / a t )*100≤90%or20%≤(a g / a t )*100≤80%,25%≤(a g / a t )*100≤75% and / or

[0132] The field plate extension is sized and shaped so as to have a maximum area a in a plane parallel to the first major surface. e , and make 10%≤(a e / a t )*100≤90%or20%≤(a e / a t )*100≤80%,25%≤(a e / a t )*100≤75% and / or

[0133] a e / ag The ratio is in the range of 1 / 9 to 9 / 1, and / or

[0134] in

[0135] The columnar groove has an outer perimeter length A in a plane parallel to the first major surface. t , and the gate electrode is sized and configured to have a maximum outer perimeter length A in a plane parallel to the first major surface g , and make 10%≤(A g / A t )*100≤90%or20%≤(A g / A t )*100≤80%,25%≤(A g / A t )*100≤75% and / or

[0136] The field plate extension is sized and configured to have a maximum outer perimeter length A in a plane parallel to the first major surface. e , and make 10%≤(A e / A t )*100≤90%or20%≤(A e / A t )*100≤80%,25%≤(A e / A t )*100≤75% and / or

[0137] A e / A g The ratio is in the range of 1 / 9 to 9 / 1.

[0138] Example 14. The transistor device of any one of Examples 1 to 13, wherein the field plate includes a lower portion and an upper portion located below the gate electrode, wherein the lower portion has a smaller area than the upper portion.

[0139] Example 15. A transistor device according to any one of Examples 1 to 14, wherein the semiconductor substrate includes a drain region of a first conductivity type formed at the second surface, a drift region of the first conductivity type formed on the drain region, a body region of a second conductivity type opposite to the first conductivity type formed on the drift region, and a source region of the first conductivity type formed on and / or in the body region.

[0140] Example 16. The transistor device of any one of Examples 1 to 15, wherein the transistor device comprises a plurality of pillar-shaped trenches arranged in an array, and further comprising a metallization layer on the first major surface, wherein the metallization structure comprises:

[0141] a first metallization structure extending between the first contacts of the pillar trenches, and

[0142] a second metallization structure extending between the second contacts of the pillar trenches,

[0143] The first metallization structure and the second metallization structure extend substantially parallel to each other.

[0144] Example 17. The transistor device of Example 16, wherein the second metallization structure electrically connects the field plate to the source region.

[0145] Example 18. The transistor device of Example 16 or Example 17, wherein the second contact extends between and contacts the field plate and the source region.

[0146] Example 19. A method of forming a gate electrode and a field plate in a pillar-shaped trench, the method comprising:

[0147] Providing a semiconductor substrate having a first main surface and a pillar trench, the pillar trench including a lower surface and sidewalls extending from the lower surface to the first main surface, wherein the sidewalls and the lower surface are lined with a field dielectric, and the pillar trench is filled with a first conductive material;

[0148] partially removing the field dielectric and the conductive material from the pillar trench and forming a gate recess asymmetrically located in the pillar trench about a longitudinal axis of the pillar trench;

[0149] forming a dielectric on a wall of the recess;

[0150] inserting a second conductive material into the gate recess to form a gate electrode,

[0151] The first conductive material extends to the first main surface laterally adjacent to the gate electrode and forms a field plate.

[0152] Example 20. The method of Example 19, wherein partially removing the dielectric and conductive material from the pillar trench comprises:

[0153] exposing the field dielectric at the top of the pillared trench, forming a conductive layer on the exposed field dielectric and on the conductive material in the lower surface of the trench, wherein the conductive layer extends to the first major surface and surrounds the central gap;

[0154] forming an intermediate electrically insulating layer in the central gap;

[0155] The conductive layer is partially removed and the field dielectric and the intermediate electrical insulating layer on the sidewalls are exposed to form a gate recess.

[0156] Example 21. The method of Example 20, further comprising:

[0157] applying a mask to the first main surface, the mask covering a first portion of the conductive layer and exposing a second portion of the conductive layer, and partially covering the intermediate electrically insulating layer within the pillar-shaped trenches,

[0158] removing the exposed second portion of the conductive layer and forming a gate recess,

[0159] Remove the mask.

[0160] Example 22. The method according to any one of Examples 19 to 21, further comprising:

[0161] applying an electrically insulating layer to the first main surface, which covers the trench, forming a first opening exposing the gate electrode,

[0162] forming a second opening exposing the field plate electrode;

[0163] Conductive material is inserted into the first opening and the second opening to form a first contact to the gate electrode and a second contact to the field plate.

[0164] Example 23. The method of Example 22, wherein the second opening further exposes the source region and the body region, and the second contact is further connected to the source region and the body region.

[0165] Example 24. The method of Example 22, further comprising forming a third opening exposing the body region and the source region, and inserting a conductive material into the third opening to form a third contact to the source region and the body region, the third contact being separate from the second contact to the field plate.

[0166] For ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," and the like are used to explain the positioning of one element relative to a second element. These terms are intended to encompass different orientations of the device in addition to those depicted in the figures. Further, terms such as "first," "second," and the like are also used to describe various elements, regions, sections, and the like, and are not intended to be limiting. Throughout the description, like terms refer to like elements.

[0167] As used herein, the terms "having," "comprising," "including," "comprising," and the like are open-ended terms that indicate the presence of stated elements or features, but do not exclude additional elements or features. The quantifiers "a," "an," and the pronoun "the" are intended to include the plural as well as the singular, unless the context clearly indicates otherwise. It is understood that the features of the various embodiments described herein can be combined with each other unless specifically noted otherwise.

[0168] Although specific embodiments have been illustrated and described herein, it will be appreciated by those skilled in the art that various alternative and / or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptation or variation of the specific embodiments discussed herein. Therefore, the present invention is intended to be limited only by the claims and their equivalents.

Claims

1. A transistor device comprising: a semiconductor substrate comprising a first major surface; a columnar trench disposed in the first major surface and comprising a lower surface and a sidewall extending from the lower surface to the first major surface; a gate electrode positioned in the pillar-shaped trench and electrically insulated from the semiconductor substrate by a gate dielectric, a field plate, which is positioned in the pillar-shaped trench below the gate electrode and is electrically insulated from the gate electrode and the semiconductor substrate by a field dielectric, wherein the gate electrode is asymmetric about the longitudinal axis of the columnar trench, and The field plate includes a field plate extension extending from the field plate toward the first main surface and adjacent to the gate electrode in a laterally direction.

2. The transistor device according to claim 1 , further comprising: a first contact extending from the first main surface into the pillar-shaped trench, the first contact being electrically connected to the gate electrode, and a second contact extending from the first main surface into the pillar-shaped trench, the second contact being electrically connected to the field plate, Wherein the first contact and the second contact are arranged laterally adjacent to each other. The transistor device of claim 2 , wherein the first contact and the second contact are located on opposite sides of the pillar-shaped trench. 4 . The transistor device of claim 1 , wherein the field plate extension is laterally electrically insulated from the gate electrode by an intervening dielectric. The transistor device of claim 4 , wherein the interlayer dielectric is centrally located in the pillar-shaped trench and extends from the first major surface to the field plate.

6. A transistor device according to any one of claims 1 to 5, wherein the gate electrode is provided by a single conductive portion, the single conductive portion having an open annular shape with a gap between two distal ends of the open annular shape.

7. The transistor device of claim 1 , wherein a first thickness of the field dielectric at a first distance from the lower surface is less than a second thickness of the field dielectric at a second distance from the lower surface, wherein the first distance is greater than the second distance, and wherein a first perimeter of the columnar field plate at the first distance is greater than a second perimeter of the columnar field plate at the second distance.

8. The transistor device according to any one of claims 1 to 7, wherein The columnar groove has a maximum periphery A in a plane parallel to the first main surface. t , and the gate electrode is sized and configured to have a maximum outer perimeter length A in a plane parallel to the first major surface g , and make 10%≤(A g / A t )*100≤90% or 20%≤(Ag / At)*100≤80%, 25%≤(Ag / At)*100≤75% and / or The field plate extension is sized and configured to have a maximum outer perimeter length A in a plane parallel to the first major surface. e , and make 10%≤(A e / A t )*100≤90%or20%≤(A e / A t )*100≤80%,25%≤(A e / A t )*100≤75% and / or A e / A g The ratio is in the range of 1 / 9 to 9 / 1.

9. The transistor device according to any one of claims 1 to 8, wherein the transistor device comprises a plurality of pillar-shaped trenches arranged in an array, and further comprising a metallization layer on the first major surface, wherein the metallization layer comprises: a first metallization structure extending between the first contacts of the pillar trenches, and a second metallization structure extending between the second contacts of the pillar trenches, The first metallization structure and the second metallization structure extend substantially parallel to each other.

10. A method for forming a gate electrode and a field plate in a columnar trench, the method comprising: providing a semiconductor substrate having a first main surface and a pillar trench, the pillar trench including a lower surface and sidewalls extending from the lower surface to the first main surface, wherein the sidewalls and the lower surface are lined with a field dielectric, and the pillar trench is filled with a first conductive material; partially removing the field dielectric and partially removing the first conductive material from the pillar trench and forming a gate recess asymmetrically located in the pillar trench about a longitudinal axis of the pillar trench; forming a dielectric on a wall of the recess; inserting a second conductive material into the gate recess to form a gate electrode, The first conductive material extends to the first main surface laterally adjacent to the gate electrode and forms a field plate.

11. The method of claim 10 , wherein partially removing the field dielectric and the conductive material from the pillar trench comprises: recessing the first conductive material at the top of the pillar-shaped trench, exposing the field dielectric at the top of the pillar-shaped trench, and forming a conductive layer on the exposed field dielectric and on the conductive material in the lower surface of the trench, wherein the conductive layer extends to the first major surface and surrounds the central gap; forming an intermediate electrically insulating layer in the central gap; The conductive layer is partially removed to expose the field dielectric and the intermediate electrical insulating layer on the sidewalls to form a gate recess.

12. The method according to claim 11, further comprising: applying a mask to the first main surface, the mask covering a first portion of the conductive layer and exposing a second portion of the conductive layer, and partially covering the intermediate electrically insulating layer within the pillar-shaped trenches, removing the exposed second portion of the conductive layer and forming a gate recess, Remove the mask.

13. The method according to any one of claims 10 to 12, further comprising: applying an electrically insulating layer to the first main surface, which covers the trench, forming a first opening exposing the gate electrode, forming a second opening exposing the field plate; Conductive material is inserted into the first opening and the second opening to form a first contact to the gate electrode and a second contact to the field plate. The method according to claim 13 , wherein the second opening further exposes the source region and the body region, and the second contact is further connected to the source region and the body region. 15 . The method of claim 13 , further comprising forming a third opening exposing the body region and the source region, and inserting a conductive material into the third opening to form a third contact to the source region and the body region, the third contact being separated from the second contact to the field plate.

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