Semiconductor structure and manufacturing method thereof

Abstract

A semiconductor structure includes a semiconductor substrate, an insulator fin over the semiconductor substrate, the insulator fin having a main dimension perpendicular to a top surface of the semiconductor substrate as viewed in cross-section, and a semiconductor capping layer covering the insulator fin along the main dimension. The invention also discloses a method for manufacturing the semiconductor structure.

Description

[0001] Divisional application

[0002] This application is a divisional application of the patent application entitled “Semiconductor Structure and Manufacturing Method Thereof” filed on November 28, 2019, with patent application number 201911192138.5. Technical Field

[0003] Embodiments of the present invention relate to semiconductor structures and methods of manufacturing the same. Background Art

[0004] To achieve increased circuit density in integrated circuits, the size of semiconductor devices, such as field-effect transistors, within such integrated circuits has been reduced. However, reducing the size of semiconductor devices may result in a reduction in the length of the semiconductor device's channel. Reducing the channel length may result in the source and drain regions of the semiconductor device being closer together, which may allow the source and drain regions to exert an undue influence on the channel or on carriers within the channel, which is commonly referred to as the short channel effect. Consequently, the gate of a semiconductor device subject to the short channel effect has reduced control over the channel, which, in particular, inhibits the gate's ability to control the on and / or off state of the semiconductor device. Summary of the Invention

[0005] An embodiment of the present invention provides a semiconductor structure, comprising: a semiconductor substrate; an insulator fin located above the semiconductor substrate, wherein, as viewed from a cross-sectional view, the insulator fin has a main dimension perpendicular to a top surface of the semiconductor substrate; and a semiconductor covering layer covering the insulator fin along the main dimension.

[0006] Another embodiment of the present invention provides a semiconductor structure comprising: a semiconductor substrate; a first strip extending along a first direction, the first strip comprising: an insulator core; and a semiconductor cap covering the top surface and side walls of the insulator core; and a second strip extending along a second direction substantially perpendicular to the first direction and in contact with the semiconductor cap of the first strip.

[0007] Yet another embodiment of the present invention provides a method for manufacturing a semiconductor structure, comprising: patterning insulator strips above the semiconductor substrate; continuously depositing a semiconductor capping layer above the insulator strips; and cutting away the semiconductor capping layer between the insulator strips. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Various aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion.

[0009] Figure 1 is a perspective view of a FinFET structure according to some embodiments of the present invention.

[0010] Figure 2A is a cross-sectional view of a FinFET structure according to some embodiments of the present invention.

[0011] Figure 2B is a cross-sectional view of a FinFET structure according to some embodiments of the present invention.

[0012] Figure 3 is a perspective view of a FinFET structure according to some embodiments of the present invention.

[0013] Figure 4 is a cross-sectional view of a FinFET structure according to some embodiments of the present invention.

[0014] Figure 5A are cross-sectional views of FinFET structures according to some comparative embodiments of the present invention.

[0015] Figure 5B are cross-sectional views of FinFET structures according to some comparative embodiments of the present invention.

[0016] Figures 6 to 16 Depicted is a cross-sectional view of an intermediate stage in an example fabrication process for forming a FinFET structure, according to some embodiments of the present invention.

[0017] Figure 17A are cross-sectional views of a FinFET at various fabrication operations according to some embodiments of the present invention.

[0018] Figure 17B to Figure 17B' are cross-sectional views of a FinFET at various fabrication operations according to some embodiments of the present invention.

[0019] Figure 17C to Figure 17C' are cross-sectional views of a FinFET at various fabrication operations according to some embodiments of the present invention.

[0020] Figure 18A are cross-sectional views of FinFETs according to some comparative embodiments of the present invention.

[0021] Figure 18B is a cross-sectional view of a FinFET according to some embodiments of the present invention.

[0022] Figure 19A are cross-sectional views of FinFETs according to some comparative embodiments of the present invention.

[0023] Figure 19B is a cross-sectional view of a FinFET according to some embodiments of the present invention. DETAILED DESCRIPTION

[0024] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component may include embodiments in which the first component and the second component are directly in contact, and may also include embodiments in which additional components may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numerals and / or characters in various embodiments. This repetition is for the purpose of simplicity and clarity and does not, in itself, indicate a relationship between the various embodiments and / or configurations discussed.

[0025] Furthermore, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," and "upper" may be used herein to describe the relationship of one element or component to another (or additional) elements or components as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0026] Although the numerical ranges and parameters setting forth the broad scope of the present invention are approximate, the numerical values set forth in the specific examples are reported as accurately as possible. However, any numerical value inherently contains certain errors, which are necessarily caused by the standard deviation found in the corresponding test measurements. Similarly, as used herein, the term "about" generally refers to within 10%, 5%, 1% or 0.5% of a given value or range. Alternatively, the term "about" refers to within an acceptable standard error of the mean value when considered by one of ordinary skill in the art. Except in the operating / working examples, or unless otherwise expressly stated, all numerical ranges, quantities, values and percentages (such as those used for the material quantities, durations, temperatures, operating conditions, quantity ratios, etc. disclosed herein) should be understood to be modified by the term "about" in all cases. Therefore, unless otherwise indicated, the numerical parameters set forth in the present invention and the appended claims are approximate values that can be varied as needed. At a minimum, each numerical parameter should at least be interpreted based on the number of reported significant figures and by applying ordinary rounding techniques. Ranges can be expressed herein as from one endpoint to the other or between two endpoints. Unless otherwise stated, all ranges disclosed herein are inclusive of the endpoints.

[0027] This article provides one or more semiconductor devices and techniques for forming such semiconductor devices. A semiconductor device such as a fin field effect transistor (FinFET) includes a fin formed on a semiconductor substrate. A gate structure surrounds at least a portion of the fin, such as a channel within the top fin portion of the fin. A source region is formed within a first portion of the fin on a first side of the channel, and a drain region is formed within a second portion of the fin on a second side of the channel. For example, because the gate structure is formed around the channel or on multiple sides, the gate structure has relatively greater control over the channel and the carriers therein relative to a gate structure formed only above the channel. As the line width decreases, a FinFET with a channel length comparable to the depletion layer width can achieve complete depletion. However, a FinFET with a channel length greater than the depletion layer width may still suffer from incomplete depletion at or above the threshold voltage during operation. Therefore, leakage current may be caused due to the short channel effect. Conventionally, the fin width of a FinFET with a channel length longer than the depletion layer width can be reduced to achieve complete depletion at the channel during operation. However, due to the reduced size of the gate-channel interface, the carrier mobility decreases.

[0028] Thus, the present invention provides a FinFET device that achieves full depletion in the active region or channel during operation. This effect does not come at the expense of shortening the channel length or reducing the fin width.

[0029] Silicon-on-insulator (SOI) technology effectively reduces parasitic device capacitance, thereby improving performance. To fully utilize the advantages of SOI technology when manufacturing FinFET devices, a fin-shaped insulator is designed on the substrate, and a semiconductor film is constructed as a cap on top of the fin. In this invention, a new structure of FinFET on a fin-on-insulator on a substrate is proposed to more fully combine the advantages of FinFET and SOI.

[0030] Reference Figure 1 , Figure 1 FIG is a perspective view of a FinFET structure 10 according to some embodiments of the present invention. FIG shows a substrate 101 on which a dielectric layer 103 is formed. The substrate 101 may be formed, for example, of silicon. Although the substrate 101 may be Figure 1 1 is shown as a bulk wafer comprising a single material (e.g., a bulk silicon wafer), but in other examples, a semiconductor on insulator or silicon on insulator (SOI) wafer or a glass substrate may be used instead. In the case of using such an SOI wafer, the dielectric layer 103 may be formed on the top silicon layer ( Figure 1 an insulating layer (eg, an oxide layer) between the silicon-based layer (eg, a bottom silicon layer) and the silicon-based layer (eg, a bottom silicon layer).

[0031] Any suitable material for substrate 101 may be used, and the material for substrate 101 is not limited to silicon. For example, substrate 101 may be a bulk substrate that may include gallium arsenide, germanium, or any other material or combination of materials. In addition, substrate 101 may include other components or structures formed on or in substrate 101. Dielectric layer 103 may include a dielectric material capable of etching substrate 101. In one example, substrate 101 may be single crystal silicon, and dielectric layer 103 may include silicon nitride deposited substantially above substrate 101.

[0032] From a perspective view, a plurality of insulator fins 105 positioned above the dielectric layer 103 extend along a long first direction 11 above the substrate 101. Figure 1 As shown, the plurality of insulator fins 105 can be the core of a first strip, wherein the core is wrapped at least from the top surface 105t and / or sidewalls 105s of the insulator fins 105 by an insulating cap or cover layer 107. The insulator fins 105 and cover layer 107 combine to form a first strip extending along a first direction 11 above the substrate 101. A gate 109 spans the plurality of insulator fins 105 along a second direction 12 above the substrate 101. In some embodiments, the second direction 12 is substantially perpendicular to the first direction 11. The gate 109 forms a second strip extending along the second direction above the semiconductor substrate 101. The second strip is in contact with at least the cover layer 107 of the first strip. In other words, the gate 109 is in contact with the portion of the cover layer 107 that wraps around the top surface 105t and sidewalls 105s of each of the plurality of insulator fins 105. In some embodiments, the insulator fins 105 and the dielectric layer 103 can be a continuous region patterned from the insulating layer of an SOI wafer. In some embodiments, the insulator fin 105 and the dielectric layer 103 may be composed of an insulating material such as SiO 2 , HfO 2 , SiOCN, or GeO, a high-k dielectric material, or a semiconductor derivative.

[0033] In some embodiments, the capping layer may be composed of a crystalline, polycrystalline, or semicrystalline semiconductor material such as Si, SiGe, Ge, other III-V materials, or two-dimensional materials such as graphene, MoS2, WSe2, or HfTe2.

[0034] exist Figure 1 In the embodiment of the present invention, the combination of the first strip or insulator fin 105 and the capping layer 107 exposed from the second strip or gate 109 comprises a source or drain (hereinafter referred to as an S / D region). In some embodiments, the S / D region can be a portion of the capping layer 107 exposed from the gate 109 and laterally adjacent to the gate 109. In some embodiments, the S / D region can be formed by an ion implantation operation or an etching operation followed by an epitaxial regrowth operation, as will be discussed later in the present invention.

[0035] Reference Figure 2A , Figure 2A is a cross-sectional view of the FinFET structure 10 taken along line AA according to some embodiments of the present invention. In some embodiments, Figure 2A The capping layer 107 shown in FIG is the S / D region of the FinFET structure 10. Each of the plurality of insulator fins 105 has a major dimension A opposite to a minor dimension B, as shown in FIG. Figure 2A As shown. The major dimension A is substantially perpendicular to the top surface 101t of the substrate 101. The capping layer 107 wraps around the top surface 105t at least along the minor dimension B and wraps around the sidewall 105s along the major dimension A of the insulator fin 105. The value of the major dimension A is measured from the top surface 105t to the bottom of the insulator fin 105, and the value of the minor dimension B is measured from one sidewall to the opposite sidewall of the insulator fin 105. In some embodiments, the major dimension A is in a range from about 5 nm to about 100 nm, and the minor dimension B is in a range from about 2 nm to about 30 nm. When the major dimension A is greater than 100 nm and the minor dimension B is within the above range, the insulator fin 105 has a high aspect ratio, thereby making the insulator fin 105 susceptible to deformation or collapse during subsequent manufacturing operations (for example, forming a polysilicon gate over the plurality of insulator fins 105). When major dimension A is less than 5 nm and minor dimension B is within the above range, the contact area between capping layer 107 and insulator fin 105 is too small to provide a reasonable channel size in a FinFET device. When minor dimension B is greater than 30 nm and major dimension A is within the above range, the number of transistors per unit chip area is significantly reduced. When minor dimension B is less than 2 nm and major dimension A is within the above range, the high aspect ratio again makes insulator fin 105 susceptible to deformation or collapse during subsequent manufacturing operations.

[0036] like Figure 2A As shown, the thickness C of the capping layer 107 is determined to allow a fully depleted region to be formed in the capping layer 107 under a predetermined operating bias. In some embodiments, the thickness C of the capping layer 107 may be in a range from about 40 nm to about 20 nm. When the thickness C of the capping layer 107 is thicker than 20 nm, the number of transistors per unit chip area is significantly reduced. When the thickness C of the capping layer 107 is thinner than 20 nm, the number of transistors per unit chip area is significantly reduced. When the crystallinity of the capping layer 107 (in some embodiments, a single crystal epitaxial layer) is degraded. Figure 14 and Figure 15 Further discussed in The cover layer 107 may increase manufacturing difficulties in subsequent manufacturing operations.

[0037] The dielectric layer 103 is located between the bottom of the insulator fin 105 and the top surface of the substrate 101. In some embodiments, the dielectric layer 103 does not surround the sidewalls of the insulator fin 105. The dielectric layer 103 is positioned between the subsequently formed metal gate in contact with the capping layer 107 and the substrate 101. In other words, the capping layer 107 does not contact the substrate 101, thereby effectively reducing leakage current flowing to the substrate 101.

[0038] Reference Figure 2B , Figure 2B is a cross-sectional view of the FinFET structure 10 taken along line AA according to some embodiments of the present invention. In some embodiments, Figure 2B The capping layer 107 shown in FIG is the S / D region of the FinFET structure 10. Figure 2B As shown, the capping layer 107 is wrapped around the top surface 105t at least along the minor dimension B of the insulator fin 105 and is wrapped around the sidewall 105s along the major dimension A of the insulator fin 105. The values of the major dimension A, the minor dimension B and the thickness C of the capping layer 107 can be referred to Figure 2A , and for the sake of simplicity, the description is not repeated here. The deposition of the capping layer 107 may not have equal thickness everywhere along the top surface 105t and sidewalls 105s of the insulator fin 105. For example, rounded features of the capping layer 107 may be observed at the corners of the insulator fin 105. The thickness C of the capping layer 107 under this condition can be measured at the bottom of the capping layer 105 where the capping layer 105 contacts the dielectric layer 103.

[0039] Figure 3 is a perspective view of a FinFET structure according to some embodiments of the present invention. Figure 3 and Figure 1 The same reference numerals in the drawings refer to substantially the same elements and their equivalents and may be referenced thereto. Figure 3 In FIG, the insulator fin 105 and the capping layer 107 are covered under the gate 109. Figure 1 In contrast, portions of the insulator fin 105 and capping layer 107 exposed from the gate 109 are now removed and replaced by conductive regions 110 configured as S / D regions of the FinFET structure 10. The conductive regions 110 are disposed along the first 11 over the substrate and laterally adjoin the gate 109.

[0040] Reference Figure 4 , Figure 4 is a cross-sectional view of a FinFET structure 10 according to some embodiments of the present invention. Figure 3 The portion of the insulator fin 105 and capping layer 107 shown covering the gate 109 has the same Figure 2A or Figure 2BThe cross-sectional views mentioned in the previous section are not repeated here for the sake of simplicity. Figure 3 The conductive region 110 configured as the S / D region has Figure 4 In some embodiments, the conductive region 110 may be in contact with the top surface of the substrate 101 . In some embodiments, the dielectric layer 103 may separate the conductive region 110 from the top surface of the substrate 101 .

[0041] Reference Figure 5A and Figure 5B , Figure 5A is a cross-sectional view of a comparative FinFET structure according to a comparative embodiment of the present invention, and Figure 5B This is a cross-sectional view of a comparative FinFET structure. Compared with the currently disclosed FinFET structure, Figure 5A and Figure 5B The FinFET structures shown in FIG. 5 include a plurality of semiconductor fins 505 and a dielectric layer 503. Figure 5A The semiconductor fin 505 is formed in the semiconductor substrate 501, so that the semiconductor fin 505 and the semiconductor substrate 501 form a continuous semiconductor region. The dielectric layer 503 is formed above the top surface of the semiconductor substrate 501 and partially surrounds the semiconductor fin 505. However, the upper semiconductor layer patterning from the SOI wafer Figure 5B The semiconductor fin 505 is formed in the SOI wafer. The dielectric layer 503 of the SOI wafer is disposed between the semiconductor fin 505 and the lower semiconductor layer of the SOI wafer to electrically isolate the semiconductor fin 505 from the semiconductor substrate 501.

[0042] Figure 5A and Figure 5B The two comparative embodiments shown differ from the embodiments of the present invention at least in that the semiconductor fins 505 are made of semiconductor material rather than an insulator. The semiconductor fins 505 are bulk structures without a core and a capping layer, as previously mentioned in the embodiments of the present invention.

[0043] The present invention provides a method for fabricating the FinFET structure described herein. Figures 6 to 16 , Figures 6 to 16 1 shows a cross-sectional view of an intermediate stage of an example fabrication process for forming a FinFET structure according to some embodiments of the present invention. Figure 6 , the semiconductor substrate 60 is provided with an insulating layer 62 thereon. In some embodiments, the semiconductor substrate 60 and the insulating layer 62 may be part of an SOI wafer. In other embodiments, the insulating layer 62 is deposited over the surface of the semiconductor substrate 60 during the manufacturing operation. A hard mask layer 64 and an anti-reflective layer 66 are positioned over the insulating layer 62 for subsequent patterning of the insulating layer 62 into Figure 1The insulator fin 105 is formed on the semiconductor substrate 60. The mask pattern layer 68 is positioned over the anti-reflective layer 66, and features of the mask pattern layer 68 are aligned with predetermined locations of the insulator fin on the semiconductor substrate 60.

[0044] In some embodiments, the insulating layer 62 may be composed of an insulating material, such as SiO2, HfO2, SiOCN, or GeO, a high-k dielectric material, or a semiconductor derivative. In some embodiments, the hard mask layer 64 may be composed of a material having different physical and / or chemical properties than the underlying insulating layer 62, such as a silicon nitride layer. In some embodiments, the anti-reflective layer 66 may include an improved patterning film (APF) 66A, a silicon oxynitride layer 66B, and an anti-reflective coating 66C stacked from the hard mask layer 64 to the mask pattern layer 68. In some embodiments, the mask pattern layer 68 may be a photoresist layer patterned using conventional techniques.

[0045] exist Figure 7 In the embodiment, an etching operation is performed to pattern the hard mask layer 64. The remaining features of the hard mask layer 64 follow the features of the mask pattern layer 68. Subsequently, the mask pattern layer 68 is removed along with the APF 66A, the silicon oxynitride layer 66B, and the anti-reflective coating 66C. Figure 8 In the embodiment of the present invention, the patterned hard mask layer 64' is used in another etching operation, such as a dry etching operation, a wet etching operation, or a combination thereof, to pattern the insulating layer 62 into the insulating fins 63 and the dielectric layer 603. The etching operation performed to obtain the insulating fins 63 does not consume the entire thickness of the insulating layer 62 at the masked locations. Moreover, by performing a time-mode etching, a continuous insulating material layer is intentionally retained to form the dielectric layer 603, or as previously discussed, to form the dielectric layer 603. Figure 1 The dielectric layer 103 in the FinFET device 10 is then removed. The patterned hard mask layer 64' is then removed. Figure 9 shown.

[0046] exist Figure 9 In the embodiment, each of the plurality of insulator fins 63 has a major dimension A opposite to a minor dimension B. The major dimension A is substantially perpendicular to the top surface of the substrate 60. In some embodiments, the major dimension A is in a range from about 5 nm to about 100 nm, and the minor dimension B is in a range from about 2 nm to about 30 nm. The critical values of the major dimension A and the minor dimension B within the above ranges can be referred to. Figure 2A , and for the sake of simplicity, it will not be repeated here. From the perspective of the stereogram, Figure 9 The insulator fin 63 is arranged above the semiconductor substrate 60 along the first direction 11 (see FIG. Figure 1 ) extends and forms an insulator strip.

[0047] exist Figure 10In the perspective view, the capping layer 507 is continuously formed above the insulator fin 63, or alternatively, above the insulator strip. The top surface 63t and sidewalls 63s of the insulator fin 63 and the top surface 603t of the dielectric layer 603 are covered by the deposited capping layer 507. In some embodiments, the capping layer 507 can be composed of a crystalline, polycrystalline, or semicrystalline semiconductor material such as Si, SiGe, Ge, other III-V materials, or two-dimensional materials such as graphene, MoS2, WSe2, or HfTe2. In some embodiments, before depositing the capping layer material, the insulator fin 63 and the dielectric layer 603 are subjected to an annealing operation, and then the crystalline, polycrystalline, or semicrystalline semiconductor material is deposited as the capping layer 507. Alternatively, in some embodiments, the capping layer material is first deposited above the insulator fin 63 and the dielectric layer 603, regardless of their crystalline state, and then an annealing operation is performed to crystallize the capping layer material into a crystalline, polycrystalline, or semicrystalline phase.

[0048] Figures 11 to 16 An operation for interrupting or cutting away the capping layer 507 between adjacent insulator fins 63 is shown. Figure 11 In the embodiment, an insulating layer 1101 is blanket formed over the capping layer 507 covering the insulating fins 63. The insulating layer 1101 may conform to the topography of the underlying insulating fins 63. A planarization operation such as chemical mechanical polishing (CMP) is performed to obtain a horizontal top surface 1103 between the insulating layer 1101 and the portion of the capping layer 507 deposited above the top surface 63t of the insulating fins 63. In some embodiments, the insulating layer 1101 deposited herein may consist essentially of the same Figure 6 The insulating layer 62 is made of the same material.

[0049] exist Figure 12 , a hard mask layer 1204, an anti-reflective layer 1206, and a mask layer 1208 are formed over the horizontal top surface 1103 for subsequent patterning of the capping layer 507. The mask pattern layer 1208 is positioned over the anti-reflective layer 1206, with features of the mask pattern layer 1208 aligned with positions of the insulator fins 63 over the semiconductor substrate 60.

[0050] In some embodiments, the hard mask layer 1204 may be composed of a material having different physical and / or chemical properties than the underlying insulating layer 1101, such as a silicon nitride layer. In some embodiments, the anti-reflective layer 1206 may include an advanced patterning film (APF) 1206A, a silicon oxynitride layer 1206B, and an anti-reflective coating layer 1206C stacked from the hard mask layer 1204 to the mask pattern layer 1208. In some embodiments, the mask pattern layer 1208 may be a photoresist layer patterned using conventional techniques.

[0051] exist Figure 13In , an etching operation is performed to pattern the hard mask layer 1204. The remaining features of the hard mask layer 1204 follow the features of the mask pattern layer 1208. Subsequently, the mask pattern layer 1208 is removed along with the APF 1206A, the oxynitride layer 1206B, and the anti-reflective coating 1206C. Figure 14 In the embodiment of the present invention, the patterned hard mask layer 1204' is used in another etching operation, such as a dry etching operation, a wet etching operation, or a combination thereof, to remove the insulating layer 1101. The etching operation stops until the capping layer 507 previously covered by the insulating layer 1101 is exposed. An etching chemistry having sufficient material selectivity between the insulating layer 1101 and the capping layer 507 can be used. For example, in Figure 14 The etching operation may use an etchant that removes oxide material at a rate at least ten times faster than the semiconductor material is removed.

[0052] As previously in Figure 2A As discussed in The covering layer will increase the manufacturing difficulty during the subsequent manufacturing operations. Figure 14 In the operation described in When the etchant selectivity is too low, the etchant selectivity may not be sufficient to perform the etching operation without consuming a relatively large amount of the thin capping layer 507. Therefore, the thin capping layer 507 may be completely consumed at various locations along the top surface 63t and sidewalls 63s of the insulator fin 63, thereby damaging the active area or channel of the FinFET device. Therefore, considering the etching process window or selectivity, it is necessary to deposit a lithographic layer having, for example, greater than 100 nm. A covering layer 507 of suitable thickness is provided.

[0053] exist Figure 15 In the embodiment of the present invention, the patterned hard mask layer 1204' is used in another etching operation, such as a dry etching operation, a wet etching operation, or a combination thereof, to remove a portion of the capping layer disposed on the top surface 603t of the dielectric layer 603. The etching operation is stopped until the dielectric layer 603 previously covered by the capping layer 507 is exposed. An etching chemistry having sufficient material selectivity between the dielectric layer 603 and the capping layer 507 can be used. For example, in Figure 15 The etching operation may use an etchant that removes semiconductor material at a rate at least ten times faster than the dielectric material. The patterned hard mask layer 1204' is then removed, as shown in FIG. Figure 16 As shown. A gate 609 is formed, which spans over the plurality of insulator fins 63 after the capping layer 507 between adjacent insulator fins 63 is removed. From a perspective view, the gate 609 appears as a gate strip extending along the second direction above the semiconductor. The gate 609 may include a polysilicon gate or a replacement gate (e.g., a metal gate). The second direction 12 may be substantially perpendicular to the first direction 11, as previously described. Figure 1 As shown in .

[0054] Figure 17A 、 Figure 17B 、 Figure 17B' 、 Figure 17C and Figure 17C' is a cross-sectional view of a FinFET during various fabrication operations according to some embodiments of the present invention. Figure 17A 6. In FIG. 5, a conductive region 1701 is formed by an ion implantation operation 1703, which represents a portion of the capping layer 507 that is not covered by the gate 609 and laterally adjacent to the gate 609. For example, the portion of the capping layer 507 receives a sufficient dose of ion implantation to form a source or drain region above the insulator fin 63. An appropriate annealing operation may be performed on a portion of the capping layer 507 after the implantation operation.

[0055] exist Figure 17B and Figure 17B' In the absence of a patterned hard mask layer 1204', a process similar to Figure 15 The etching operation disclosed in removes the originally deposited capping layer 507, followed by an epitaxial regrowth operation to form a conductive region 1701 having the desired regrowth material or conductive material. The regrowth material or conductive material may be different from the original capping material. The regrowth material or conductive material includes, but is not limited to, SiGe, SiC, Ge, graphene, MoS2, WSe2, or HfTe2, or a combination thereof. In some embodiments, prior to depositing the regrowth material or conductive material, the insulator fin 63 and the dielectric layer 603 are subjected to an annealing operation, followed by deposition of a crystalline, polycrystalline, or semicrystalline semiconductor material as the conductive region. Alternatively, in some embodiments, regardless of its crystallization state, the regrowth material or conductive material is first deposited over the insulator fin 63 and the dielectric layer 603, and then an annealing operation is performed to crystallize the regrowth material or conductive material into a crystalline, polycrystalline, or semicrystalline phase. If the regrowth material or conductive material merges, a suitable etching operation may be performed to remove the regrowth material or conductive material at adjacent insulator fins 63. The conductive region 1701' may be grown to have several facets (not shown) or to have a Figure 17B' The rounded surface shown.

[0056] exist Figure 17C and Figure 17C' In the embodiment, the originally deposited capping layer 507 and the original insulator fin 63 are removed by an etching operation, followed by epitaxial regrowth to form the conductive region 1701 with the desired regrowth material or conductive material. The capping layer 507 and the insulator fin 63 may be partially or completely removed. Figure 17CAs shown, the removed portion of the capping layer 507 and the insulator fin 63 forms a groove 1705 depicted by a dotted line, or the groove 1705 can be seen along the insulator strip from a perspective view. Then, a regrown material or a conductive material is deposited in the groove 1705 and fills the groove 1705 to obtain a conductive region 1701 ', as shown in FIG. Figure 17C' In some embodiments, the dielectric layer 603 below the recess 1705 may also be removed in another photolithography operation to expose the underlying semiconductor substrate 60. The regrown material or conductive material may then be epitaxially grown over the exposed semiconductor substrate 60.

[0057] The regrowth material or conductive material may be different from the original capping material. The regrowth material or conductive material includes, but is not limited to, SiGe, SiC, Ge, graphene, MoS2, WSe2, or HfTe2, or a combination thereof. In some embodiments, when the dielectric layer 603 located below the groove 1705 is not removed prior to the regrowth operation, the dielectric layer 603 is subjected to an annealing operation, followed by deposition of a crystalline, polycrystalline, or semicrystalline semiconductor material as the conductive region 1701. Alternatively, in some embodiments, regardless of its crystalline state, the regrowth material or conductive material is first deposited over the dielectric layer 603, and then an annealing operation is performed to crystallize the regrowth material or conductive material into a crystalline, polycrystalline, or semicrystalline phase. If the regrowth material or conductive material merges, a suitable etching operation may be performed to cut off the regrowth material or conductive material at adjacent conductive regions 1701. The conductive region 1701 may be grown to have a Figure 17C' Several small planes as shown, or with Figure 17B' The rounded surface shown.

[0058] Reference Figure 18A and Figure 18B , Figure 18A is a cross-sectional view of the FinFET structure. Figure 18Bis a cross-sectional view of the FinFET structure of this embodiment. By utilizing the FinFET structure of the present invention, FinFET structures 180A and 180B having the same fin width F1 (e.g., 8 nm) can have different threshold voltages. The shaded areas associated with the fin structures 1805 and 1805' indicate the depletion regions generated under the corresponding threshold biases. In order to achieve complete depletion in the FinFET structure 180A, for example, a threshold voltage Vt1 is required to deplete carriers from the entire semiconductor fin 1805 having the fin width F1. For example, in order to achieve complete depletion in the FinFET structure 180B, a threshold voltage Vt2 is required to deplete carriers from the capping layer 1807' above the insulator fin 1805', the width of the capping layer 1807' and the insulator fin 1805' constituting the fin width F1. The threshold voltage Vt2 applied to the FinFET structure 180B is substantially lower than the threshold voltage Vt1 applied to the FinFET structure 180A.

[0059] Reference Figure 19A and Figure 19B , Figure 19A is a cross-sectional view of the FinFET structure. Figure 19B : is a cross-sectional view of the FinFET structure of this embodiment. By utilizing the FinFET structure of the present invention, FinFET structures 190A and 190B having the same fin width F2 (e.g., 16 nm) can have different depletion degrees. The shaded area associated with the fin structures 1905 and 1905' represents the depletion region generated under a predetermined bias. When a predetermined bias is applied to the FinFET structure 190A, the semiconductor fin 1905 generates a depletion region at the top surface and sidewalls of the semiconductor fin 1905, but the semiconductor fin 1905 is not completely depleted, and therefore, possible leakage may occur due to the short channel effect. When a predetermined bias is applied to the FinFET structure 190B, the semiconductor fin 1905' generates a depletion region in the capping layer 1907' above the insulator fin 1905', and the capping layer is completely depleted, thereby preventing the occurrence of leakage.

[0060] Some embodiments of the present invention provide a semiconductor structure including a semiconductor substrate, an insulator fin located above the semiconductor substrate, wherein, from a cross-sectional view, the insulator fin has a main dimension perpendicular to a top surface of the semiconductor substrate, and a semiconductor covering layer covering the insulator fin along the main dimension.

[0061] In some embodiments, the semiconductor capping layer also covers the top surface of the insulator fin. In some embodiments, the semiconductor structure further comprises a gate contacting the semiconductor capping layer at the top surface of the insulator fin and along the main dimension of the insulator fin. In some embodiments, the semiconductor structure further comprises an insulator layer located between the insulator fin and the semiconductor substrate. In some embodiments, the insulator fin comprises SiO2, HfO2, SiOCN or GeO. In some embodiments, the semiconductor capping layer comprises Si, Ge, SiGe, graphene, MoS2, WSe2 or HfTe2. Some embodiments of the present invention provide a semiconductor structure comprising a semiconductor substrate, a first strip extending along a first direction, and a second strip extending along a second direction substantially perpendicular to the first direction. The first strip comprises an insulator core and a semiconductor cap covering the top surface and sidewalls of the insulator core. The second strip contacts the semiconductor cap of the first strip.

[0062] In some embodiments, the semiconductor cap has a thickness that allows for the formation of a fully depleted region in the semiconductor cap under a predetermined bias voltage. In some embodiments, the semiconductor cap comprises a crystalline material. In some embodiments, the semiconductor structure further comprises an insulating layer positioned between the first strip and the semiconductor substrate. In some embodiments, the semiconductor structure further comprises a conductive region positioned in the semiconductor cap of the first strip, the conductive region being adjacent to the second strip.

[0063] Some embodiments of the present invention further provide a method for fabricating a semiconductor structure, comprising: patterning insulator strips on a semiconductor substrate, continuously depositing a semiconductor capping layer on the insulator strips, and removing the semiconductor capping layer between the insulator strips.

[0064] In some embodiments, the method further comprises annealing the semiconductor strips before depositing the semiconductor capping layer. In some embodiments, the method further comprises annealing the semiconductor capping layer after depositing the semiconductor capping layer over the insulator strips. In some embodiments, removing the semiconductor capping layer further comprises: forming an insulating layer over the semiconductor capping layer; making the insulating layer flush with a top surface of the semiconductor capping layer; and removing the insulating layer until the semiconductor capping layer between the insulator strips is exposed. In some embodiments, the method further comprises: patterning the insulator strips and the gate strips over the semiconductor capping layer after removing the semiconductor capping layer. In some embodiments, the method further comprises: forming a conductive region at a portion of the semiconductor capping layer not covered by the gate strips by an implantation operation. In some embodiments, the method further comprises: forming a conductive region at a portion of the insulator strip not covered by the gate strips by a regrowth operation. In some embodiments, the regrowth operation comprises: removing a portion of the semiconductor capping layer to expose the insulator strips; and forming a conductive layer covering the exposed insulator strips. In some embodiments, the regrowth operation comprises: removing a portion of the semiconductor capping layer and a portion of the insulator strips and forming a recess; and forming the conductive layer in the recess.

[0065] The parts of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art will appreciate that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art will also appreciate that such equivalent constructions do not depart from the spirit and scope of the present invention, and that they may make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present invention.

[0066] Furthermore, the scope of this application is not intended to be limited to the particular embodiments of the processes, machines, manufactures, compositions of matter, means, methods, and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure herein, according to the present invention, processes, machines, manufactures, compositions of matter, means, methods, or steps, now existing or later developed, that perform substantially the same functions or can achieve substantially the same results as the corresponding embodiments described herein may be utilized. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufactures, compositions of matter, means, methods, or steps.

Claims

1. A semiconductor structure comprising: a semiconductor substrate having a gate region; an insulator fin located above the semiconductor substrate, wherein the insulator fin has a main dimension perpendicular to a top surface of the semiconductor substrate when viewed in a cross-sectional view; a semiconductor capping layer covering the insulator fin along the major dimension and covering a top surface of the insulator fin; a gate extending in a first direction and directly contacting a top surface of the semiconductor capping layer and growing along a sidewall of the main dimension of the insulator fin, wherein the semiconductor capping layer has a first portion covered by the gate, the first portion constituting a channel structure; a source / drain formed of a conductive material and adjacent to the gate in a second direction, wherein a top surface and sidewalls of the source / drain are not covered by the semiconductor covering layer, wherein the second direction is perpendicular to the first direction; and an insulator layer located between the insulator fin and the semiconductor substrate, wherein at least a portion of the insulator layer is exposed from the semiconductor cap layer, and the semiconductor cap layer is not in contact with the semiconductor substrate, and the insulator fin and the insulator layer are composed of the same material, The bottom surface of the semiconductor cover layer is flush with the bottom surface of the gate and the bottom surface of the insulator fin.

2. The semiconductor structure according to claim 1, wherein The bottom surfaces of the source / drain directly contact the surface of the semiconductor substrate.

3. The semiconductor structure according to claim 1, wherein The thickness of the semiconductor covering layer is to 20nm range.

4. A semiconductor structure comprising: a semiconductor substrate having a gate region; A first belt extends along a first direction, the first belt comprising: an insulator core; and a semiconductor cap covering a top surface and side walls of the insulator core; and a second strip extending along a second direction perpendicular to the first direction and directly contacting a top surface of the semiconductor cap of the first strip, the semiconductor cap having a first portion covered by the second strip, the first portion constituting a channel structure, the first strip forming a source / drain; a conductive region located in a portion of the first strip not covered by the second strip, the conductive region being adjacent to the second strip, and having a top surface and sidewalls not covered by the semiconductor cap; an insulating layer located between the first strip and the semiconductor substrate, wherein at least a portion of the insulating layer is exposed from the semiconductor cap and the semiconductor cap is not in contact with the semiconductor substrate, the insulator core and the insulating layer being composed of the same material, The bottom surface of the semiconductor cover is flush with the bottom surface of the second strip and the bottom surface of the insulator core.

5. The semiconductor structure according to claim 4, wherein The semiconductor cap has a thickness that allows a fully depleted region to be formed in the semiconductor cap at the predetermined bias voltage.

6. A method for manufacturing a semiconductor structure, comprising: forming a dielectric layer on a semiconductor substrate; patterning an insulator strip over the semiconductor substrate, the dielectric layer being located between the semiconductor substrate and the insulator strip, wherein the insulator strip and the dielectric layer are a continuous region formed by patterning the insulating layer; continuously depositing a semiconductor capping layer over the insulator strip, the semiconductor capping layer not contacting the semiconductor substrate; and cutting away the semiconductor capping layer between the insulator strips, wherein at least a portion of the dielectric layer is exposed from the semiconductor capping layer; forming a gate electrode that directly contacts a top surface of the semiconductor capping layer and grows along a sidewall of a long dimension of the insulator strip, the semiconductor capping layer having a first portion covered by the gate electrode, the first portion constituting a channel structure; and forming a conductive region at a portion of the insulator strip not covered by the gate, The step of forming the conductive region at a portion of the insulator strip not covered by the gate strip by a regrowth operation comprises: removing portions of the semiconductor cap layer and portions of the insulator strip and forming grooves; and forming a conductive layer in the groove, The bottom surface of the semiconductor cover layer is flush with the bottom surface of the gate and the bottom surface of the insulator fin.

7. The method of claim 6, further comprising annealing the insulator strip prior to depositing the semiconductor capping layer. 8 . The method of claim 6 , further comprising, after depositing the semiconductor capping layer over the insulator strip, annealing the semiconductor capping layer.

9. The method according to claim 6, wherein: Removing the semiconductor cover layer further comprises: forming an insulating layer over the semiconductor cap layer; making the insulating layer flush with the top surface of the semiconductor cap layer; and The insulating layer is removed until the semiconductor capping layer between the insulator strips is exposed.

10. The method according to claim 6, further comprising: After cutting away the semiconductor capping layer, the insulator strips and the gate strips over the semiconductor capping layer are patterned.

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