Gallium oxide MOSFET (Metal Oxide Semiconductor Field Effect Transistor) structure with p-type buried layer and preparation method thereof
By introducing p-type buried layer and heterojunction diode structure into the gallium oxide MOSFET structure, the gate dielectric premature breakdown problem of gallium oxide-based vertical field effect transistor is solved, and the voltage withstandness and reverse conduction characteristics of the device are improved.
Patent Information
- Application Number
- CN202510598945.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-09
- Publication Date
- 2025-08-08
AI Technical Summary
Due to the lack of effective p-type doping schemes, existing gallium oxide-based vertical field effect transistors cause device gate dielectric to break down ahead of schedule at high voltage, affecting the device's withstand voltage level and reverse power consumption.
A gallium oxide MOSFET structure with a p-type buried layer is designed. By introducing a p-type buried layer at the device terminal, the electric field peak at the corner of the gate dielectric is transferred to the p-type buried layer, and combined with a heterojunction diode structure, reverse current transmission is achieved and reverse conduction power consumption is reduced.
The blocking characteristics of gallium oxide vertical MOSFET are improved, prevent gate dielectric breakdown, reduce reverse conduction power consumption, and enhance the device's voltage resistance.
Smart Images
Figure CN120456594A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor devices, and in particular to a gallium oxide MOSFET structure with a p-type buried layer and a preparation method thereof. Background Art
[0002] Gallium oxide (Ga2O3) materials can significantly improve the performance of power devices. For example, an ultra-high critical breakdown field strength of approximately 8 MV / cm can significantly increase the breakdown voltage of power devices; an ultra-wide bandgap of approximately 4.8 eV can improve the reliability of power devices in extreme environments such as high temperature and strong radiation; and melt-grown substrate materials can reduce the material cost of power devices. Enhancement-mode transistors are favored in many power electronics applications because they ensure safe operation in the event of faults and simplify circuit design. Compared to horizontal transistors, vertical transistors can support higher voltages without sacrificing chip area by increasing the thickness of the drift layer.
[0003] Due to the lack of an effective p-type doping scheme for gallium oxide materials, Ga2O3-based vertical field-effect transistors (VFETs) currently cannot achieve enhancement-mode characteristics using a p-well structure like Si / SiC-based VFETs. Solutions can be divided into two categories. One involves modifying the surface structure of the epitaxial layer, such as using vertical FinFET technology to achieve enhancement-mode operation by fully depleting carriers in the channel at zero gate bias through an ultra-thin Fin channel. The other involves directly blocking carrier flow in the channel at zero gate bias by introducing a deep acceptor in the conductive channel region to compensate for free carriers. This can be achieved by using a high-resistance current blocking layer (CBL) formed by Mg / N ion implantation or oxygen annealing. However, both CBLs and Fin channels, due to the high electric field strength material properties of gallium oxide and the electric field curvature effect generated by their inherent structure, can cause premature breakdown of the device gate dielectric when subjected to high withstand voltages, resulting in a low overall withstand voltage. Therefore, based on the unique material properties of gallium oxide, developing terminal technology and preparation processes suitable for Ga2O3-based vertical field-effect transistors is of great significance to improving device performance.
[0004] Therefore, the existing technology still needs to be improved and developed. Summary of the Invention
[0005] The present invention aims to provide a gallium oxide MOSFET structure with a p-type buried layer and a preparation method thereof, which can improve the premature breakdown of the device gate dielectric and enhance the blocking characteristics of the gallium oxide vertical field-effect transistor.
[0006] To achieve the above objectives, the present invention adopts the following technical solution: a gallium oxide MOSFET structure with a p-type buried layer, comprising a MOSFET region and a heterojunction diode region alternately arranged in a laterally direction, wherein the MOSFET region includes a drain metal layer, a highly doped n-type gallium oxide substrate, a low-doped n-type gallium oxide epitaxial layer, a current blocking layer, a highly doped n-type gallium oxide epitaxial layer, a p-type semiconductor layer, a gate dielectric layer, a gate metal layer, an oxide dielectric layer, and a source metal layer; The highly doped n-type gallium oxide substrate is located above the drain metal layer, and the drain metal layer forms an ohmic contact with the highly doped n-type gallium oxide substrate; The low-doped n-type gallium oxide epitaxial layer is a convex structure with an upper convex table in the middle and is located above the high-doped n-type gallium oxide substrate; The current blocking layer is located above the mesa of the low-doped n-type gallium oxide epitaxial layer; The highly doped n-type gallium oxide epitaxial layer is located above the current blocking layer; The p-type semiconductor layer is located on the left and right sides of the upper convex mesa of the low-doped n-type gallium oxide epitaxial layer. The p-type semiconductor layer on one side has an L-shaped structure and covers the upper surface of the non-mesa portion of the low-doped n-type gallium oxide epitaxial layer and part of the sidewall of the upper convex mesa. The gate dielectric layer is located above the p-type semiconductor layer, and the portion of the gate dielectric layer adjacent to the sidewall of the raised mesa of the low-doped n-type gallium oxide epitaxial layer extends upward and covers the remaining sidewalls of the raised mesa of the low-doped n-type gallium oxide epitaxial layer, the sidewalls of the current blocking layer, and the sidewalls and a portion of the upper surface of the highly doped n-type gallium oxide epitaxial layer; The gate metal layer is located above the gate dielectric layer, and its upper and lower ends do not completely cover the upper surface of the gate dielectric layer; The oxide dielectric layer is located above the gate metal layer and covers the upper surface of the gate metal layer and the upper surface of the gate dielectric layer not covered by the gate metal layer; The source metal layer is located above the oxide dielectric layer and covers the upper surface of the oxide dielectric layer and the remaining upper surface of the highly doped n-type gallium oxide epitaxial layer, and the source metal layer forms an ohmic contact with the highly doped n-type gallium oxide epitaxial layer; The heterojunction diode region includes, from bottom to top, a drain metal layer, a highly doped n-type gallium oxide substrate, a low doped n-type gallium oxide epitaxial layer, a p-type semiconductor layer, and a source metal layer. The drain metal layer, highly doped n-type gallium oxide substrate, low doped n-type gallium oxide epitaxial layer, p-type semiconductor layer, and source metal layer of the heterojunction diode region are respectively connected to the drain metal layer, highly doped n-type gallium oxide substrate, low doped n-type gallium oxide epitaxial layer, p-type semiconductor layer, and source metal layer of the MOSFET region as a whole; The MOSFET region and the heterojunction diode region share a drain metal layer and a source metal layer. The drain metal layer serves as both the drain electrode of the MOSFET region and the cathode electrode of the heterojunction diode region. The source metal layer serves as both the source electrode of the MOSFET region and the anode electrode of the heterojunction diode region.
[0007] Furthermore, the thickness of the highly doped n-type gallium oxide substrate is 50-650 μm, and the doping concentration is 10 18 ~10 20 cm ~3 The thickness of the low-doped n-type gallium oxide epitaxial layer is 2~20μm, and the doping concentration is 10 15 ~10 17 cm ~3 .
[0008] Furthermore, the gate dielectric layer is made of at least one of aluminum oxide (Al2O3), silicon nitride (Si3N4), hafnium oxide (HfO2) and silicon dioxide (SiO2), and the thickness of the gate dielectric layer is 0.01-1 μm; The gate metal layer is made of at least one of platinum (Pt), nickel (Ni), molybdenum (Mo), gold (Au) and copper (Cu), and the thickness of the gate metal layer is 0.01-3 μm; The material used for the oxide dielectric layer is at least one of aluminum oxide (Al2O3), silicon nitride (Si3N4), hafnium oxide (HfO2) and silicon dioxide (SiO2), and the thickness of the oxide dielectric layer is 0.01-5 μm.
[0009] Furthermore, the thickness of the current blocking layer is 0.1-3 μm, and the material used is a nitrogen doping concentration of 10 16 ~10 20 cm ~3 gallium oxide materials.
[0010] Furthermore, the thickness of the highly doped n-type gallium oxide epitaxial layer is 0.1-3 μm, and the material used is a doping concentration of 10 18 ~10 20 cm ~3 gallium oxide materials.
[0011] Furthermore, the material used for the p-type semiconductor layer is at least one of p-type NiO, p-type Cu2O and p-type diamond, and the doping concentration is 10 17 ~10 20 cm ~3The thickness of the p-type semiconductor layer extending in the horizontal direction is 0.1-2 μm, and the height of the p-type semiconductor layer extending in the vertical direction and adjacent to the side wall of the convex mesa on the low-doped n-type gallium oxide epitaxial layer is 0.1-3 μm.
[0012] Furthermore, the width of the raised mesa on the low-doped n-type gallium oxide epitaxial layer is 0.1-4 μm, and the height of the raised mesa on the low-doped n-type gallium oxide epitaxial layer is 0.15-4 μm.
[0013] Furthermore, the overall width of the heterojunction diode region is 0.1-5 μm.
[0014] Furthermore, the material of the drain metal layer is at least one of titanium (Ti), nickel (Ni), silver (Ag) and gold (Au), and the thickness of the drain metal layer is 0.1-5 μm; The material of the source metal layer is at least one of titanium (Ti), nickel (Ni), silver (Ag) and gold (Au), and the thickness of the source metal layer is 0.1-5 μm.
[0015] The present invention also provides a method for preparing the above-mentioned gallium oxide MOSFET structure with a p-type buried layer, comprising the following steps: Providing a highly doped n-type gallium oxide substrate; forming a low-doped n-type gallium oxide epitaxial layer on a high-doped n-type gallium oxide substrate; forming a current blocking layer on the low-doped n-type gallium oxide epitaxial layer; forming a highly doped n-type gallium oxide epitaxial layer on the current blocking layer; Performing interval etching on the stacked structure formed above, etching partially to a set depth below the low-doped n-type gallium oxide epitaxial layer, so that the low-doped n-type gallium oxide epitaxial layer has interval upper convex mesas, and the current blocking layer and the high-doped n-type gallium oxide epitaxial layer are retained on the upper convex mesas; forming a p-type semiconductor layer on the low-doped n-type gallium oxide epitaxial layer, wherein the p-type semiconductor layer covers the upper surface of the non-mesa portion of the low-doped n-type gallium oxide epitaxial layer and part of the sidewalls of the upper convex mesas on the left and right sides; forming a gate dielectric layer on the p-type semiconductor layer, on the sidewall of the low-doped n-type gallium oxide epitaxial layer, on the sidewall of the current blocking layer, and on the high-doped n-type gallium oxide epitaxial layer; forming a gate metal layer on a portion of the surface of the gate dielectric layer; forming an oxide dielectric layer on the remaining surface of the gate dielectric layer and on the gate metal layer; forming electrode contact windows on a portion of the surface of the oxide dielectric layer and the gate dielectric layer, exposing a portion of the surface of the p-type semiconductor layer, a portion of the surface of the gate dielectric layer, and a portion of the upper surface of the highly doped n-type gallium oxide epitaxial layer; forming a source metal layer on a portion of the surface of the p-type semiconductor layer, a portion of the surface of the gate dielectric layer, a portion of the surface of the oxide dielectric layer, and a portion of the upper surface of the highly doped n-type gallium oxide epitaxial layer; A drain metal layer is formed on the side of the highly doped n-type gallium oxide substrate facing away from the low-doped n-type gallium oxide epitaxial layer to obtain a gallium oxide MOSFET with a p-type buried layer, wherein the area covered with the oxide dielectric layer is the MOSFET area, and the area between adjacent MOSFET areas is the heterojunction diode area.
[0016] Compared with existing technologies, the present invention has the following beneficial effects: By introducing a p-type buried layer at the device terminal, the present invention transfers the electric field peak located at the corner of the gate dielectric at the bottom of the gallium oxide vertical MOSFET device mesa to the p-type buried layer, thereby avoiding the negative impact of premature gate dielectric breakdown when the gallium oxide vertical MOSFET is subjected to high withstand voltage, thereby improving the MOSFET's blocking characteristics. Furthermore, the p-type buried layer designed between the gate dielectric layer and the low-doped n-type gallium oxide epitaxial layer in the MOSFET region can also achieve reverse conduction of the MOSFET. Because the p-type buried layer can form a heterojunction diode with the gallium oxide n-type epitaxial layer, the gallium oxide MOSFET with the p-type buried layer can transmit reverse current through the internal heterojunction diode structure, reducing reverse conduction power consumption. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] Figure 1 Schematic diagram of the structure of a gallium oxide MOSFET with a p-type buried layer in an embodiment of the present invention.
[0018] Figure 2 Schematic diagram of the preparation process of a gallium oxide MOSFET with a p-type buried layer in an embodiment of the present invention, wherein (a) is a schematic diagram of sequentially forming a gallium oxide epitaxial layer, a current blocking layer, and a highly doped n-type gallium oxide epitaxial layer on the surface of a gallium oxide substrate, (b) is a schematic diagram of forming a mesa on the surface of the gallium oxide epitaxial layer, (c) is a schematic diagram of forming a p-type semiconductor layer on the surface of the gallium oxide epitaxial layer, (d) is a schematic diagram of forming a gate dielectric layer on the surface of the p-type semiconductor layer, on a portion of the sidewall of the gallium oxide epitaxial layer, on the sidewall of the gallium oxide current blocking layer, and on the surface of the highly doped n-type gallium oxide epitaxial layer, (e) is a schematic diagram of forming a gate metal layer on a portion of the surface of the gate dielectric layer, (f) is a schematic diagram of forming an oxide dielectric layer on a portion of the surface of the gate dielectric layer and on the surface of the gate metal layer, (g) is a schematic diagram of forming electrode contact windows on a portion of the surface of the oxide dielectric layer and on the surface of the gate dielectric layer, (h) is a schematic diagram of forming a source metal layer on a portion of the surface of the p-type semiconductor layer, on the surface of the oxide dielectric layer, and on the surface of the highly doped n-type gallium oxide epitaxial layer, and (i) is a schematic diagram of forming a drain metal layer on a side of the gallium oxide substrate facing away from the gallium oxide epitaxial layer.
[0019] Figure 3 This is a schematic diagram of the structure of a conventional gallium oxide MOSFET that introduces a current blocking layer structure.
[0020] Figure 4 The two-dimensional electric field distribution and maximum electric field position results of the conventional gallium oxide MOSFET with a current blocking layer structure and the gallium oxide MOSFET with a p-type buried layer in Example 1 are shown.
[0021] Figure 5 The reverse current curves of the conventional gallium oxide MOSFET with a current blocking layer structure and the gallium oxide MOSFET with a p-type buried layer in Example 1, as well as the two-dimensional reverse current distribution of the gallium oxide MOSFET with a p-type buried layer in Example 1 are shown.
[0022] Reference numerals in the accompanying drawings: 1. MOSFET region; 2. Drain metal layer; 3. Highly doped n-type gallium oxide substrate; 4. Low-doped n-type gallium oxide epitaxial layer; 5. P-type semiconductor layer; 6. Gate dielectric layer; 7. Gate metal layer; 8. Oxide dielectric layer; 9. Highly doped n-type gallium oxide epitaxial layer; 10. Source metal layer; 11. Heterojunction diode region; 12. Current blocking layer. DETAILED DESCRIPTION
[0023] The present invention provides a gallium oxide MOSFET structure with a p-type buried layer and a method for fabricating the same. To clarify the objectives, technical solutions, and advantages of the present invention, the present invention is described in further detail below. It should be understood that the specific embodiments described herein are intended only to illustrate the present invention and are not intended to limit the present invention.
[0024] Unless otherwise defined, all technical terms and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention.
[0025] Terms such as “vertical,” “horizontal,” “upper,” “lower,” “left,” “right,” and similar expressions used herein are for illustrative purposes only and are not intended to be the only implementations.
[0026] In the present invention, unless otherwise expressly specified or limited, when a first feature is "above" or "below" a second feature, it may mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediary. Furthermore, when a first feature is "above," "above," or "above" a second feature, it may mean that the first feature is directly above or diagonally above the second feature, or simply means that the first feature is at a higher level than the second feature. When a first feature is "below," "below," or "below" a second feature, it may mean that the first feature is directly below or diagonally below the second feature, or simply means that the first feature is at a lower level than the second feature.
[0027] This embodiment provides a gallium oxide MOSFET structure with a p-type buried layer, which is composed of a MOSFET region and a heterojunction diode region alternately arranged in the transverse direction. The structure can be divided into two parts: the MOSFET region and the heterojunction diode region. Figure 1 shown.
[0028] The MOSFET region 1 includes a drain metal layer 2, a highly doped n-type gallium oxide substrate 3, a low-doped n-type gallium oxide epitaxial layer 4, a current blocking layer 12, a highly doped n-type gallium oxide epitaxial layer 9, a p-type semiconductor layer 5, a gate dielectric layer 6, a gate metal layer 7, an oxide dielectric layer 8, and a source metal layer 10.
[0029] The highly doped n-type gallium oxide substrate 3 is located above the drain metal layer 2 , and the drain metal layer 2 forms an ohmic contact with the highly doped n-type gallium oxide substrate 3 .
[0030] The low-doped n-type gallium oxide epitaxial layer 4 is a convex structure with an upper convex terrace in the middle and is located above the high-doped n-type gallium oxide substrate 3 .
[0031] The current blocking layer 12 is located above the mesa of the low-doped n-type gallium oxide epitaxial layer 4 .
[0032] The highly doped n-type gallium oxide epitaxial layer 9 is located above the current blocking layer 12 .
[0033] The p-type semiconductor layer 5 is located on the left and right sides of the raised mesa of the low-doped n-type gallium oxide epitaxial layer 4. The p-type semiconductor layer on one side has an L-shaped structure and covers the upper surface of the non-mesa portion of the low-doped n-type gallium oxide epitaxial layer 4 and part of the sidewall of the raised mesa.
[0034] The gate dielectric layer 6 is located above the p-type semiconductor layer 5, and extends upward from the sidewall of the raised mesa on the low-doped n-type gallium oxide epitaxial layer 4 and covers the remaining sidewalls of the raised mesa on the low-doped n-type gallium oxide epitaxial layer 4, the sidewalls of the current blocking layer 12, and the sidewalls and a portion of the upper surface of the highly doped n-type gallium oxide epitaxial layer 9.
[0035] The gate metal layer 7 is located above the gate dielectric layer 6 , and the upper and lower ends of the gate metal layer 7 do not completely cover the upper surface of the gate dielectric layer 6 .
[0036] The oxide dielectric layer 8 is located above the gate metal layer 7 and covers the upper surface of the gate metal layer 7 and the upper surface of the gate dielectric layer 6 not covered by the gate metal layer.
[0037] The source metal layer 10 is located above the oxide dielectric layer 8 and covers the upper surface of the oxide dielectric layer 8 and the remaining upper surface of the highly doped n-type gallium oxide epitaxial layer 9 . The source metal layer 10 forms an ohmic contact with the highly doped n-type gallium oxide epitaxial layer 9 .
[0038] The heterojunction diode region 11 includes, from bottom to top, a drain metal layer 2, a highly doped n-type gallium oxide substrate 3, a low-doped n-type gallium oxide epitaxial layer 4, a p-type semiconductor layer 5, and a source metal layer 10. The drain metal layer 2, the highly doped n-type gallium oxide substrate 3, the low-doped n-type gallium oxide epitaxial layer 4, the p-type semiconductor layer 5, and the source metal layer 10 of the heterojunction diode region 11 are respectively connected as a whole with the drain metal layer 2, the highly doped n-type gallium oxide substrate 3, the low-doped n-type gallium oxide epitaxial layer 4, the p-type semiconductor layer 5, and the source metal layer 10 of the MOSFET region 1.
[0039] The MOSFET region 1 and the heterojunction diode region 11 share the drain metal layer 2 and the source metal layer 10. The drain metal layer 2 serves as both the drain electrode of the MOSFET region 1 and the cathode electrode of the heterojunction diode region 11. The source metal layer 10 serves as both the source electrode of the MOSFET region 1 and the anode electrode of the heterojunction diode region 11.
[0040] The present invention introduces a p-type buried layer at the device terminal to transfer the electric field peak at the corner of the gate dielectric at the bottom of the gallium oxide vertical MOSFET device mesa to the p-type buried layer. This prevents the negative impact of premature gate dielectric breakdown when the gallium oxide vertical MOSFET is subjected to high withstand voltages, thereby improving the MOSFET's blocking characteristics. Furthermore, the p-type buried layer designed between the gate dielectric layer and the low-doped n-type gallium oxide epitaxial layer within the MOSFET region can also enable reverse conduction of the MOSFET. Because the p-type buried layer can form a heterojunction diode with the gallium oxide n-type epitaxial layer, the gallium oxide MOSFET with the p-type buried layer can transmit reverse current through the internal heterojunction diode structure, reducing reverse conduction power consumption.
[0041] In this embodiment, the thickness of the gallium oxide substrate is 50-650 μm, for example, 50 μm, 100 μm, 150 μm, 200 μm, 250 μm, 300 μm, 350 μm, 400 μm, 450 μm, 500 μm, 550 μm, 600 μm or 650 μm.
[0042] In this embodiment, the gallium oxide substrate is a highly doped n-type gallium oxide substrate with a doping concentration (ie, electron concentration) of 10 18 ~10 20 cm ~3 , the doping element is at least one of Si and Sn.
[0043] In this embodiment, the thickness of the gallium oxide epitaxial layer is 2-20 μm, for example, 2 μm, 3 μm, 5 μm, 8 μm, 10 μm, 12 μm, 15 μm, 18 μm or 20 μm.
[0044] In this embodiment, the gallium oxide epitaxial layer is a low-doped n-type gallium oxide epitaxial layer, and the doping concentration (ie, electron concentration) is 10 15 ~10 17 cm ~3 , the doping element is at least one of Si and Sn.
[0045] In this embodiment, the thickness of the gate dielectric layer is 10 nm to 1 μm, for example, 10 nm, 200 nm, 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm or 1 μm, etc. Figure 1 The thickness in the vertical direction shown in the figure is as follows: Figure 1 Thickness in the up and down directions shown.
[0046] In this embodiment, the material of the gate dielectric layer includes, but is not limited to, at least one of aluminum oxide (Al2O3), silicon nitride (Si3N4), hafnium oxide (HfO2), and silicon dioxide (SiO2). The thickness of the gate dielectric layer is 0.01 to 1 μm. For example, the thickness may be 10 nm, 200 nm, 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm, or 1 μm.
[0047] In this embodiment, the material of the gate metal layer includes, but is not limited to, at least one of platinum (Pt), nickel (Ni), molybdenum (Mo), gold (Au), and copper (Cu). The thickness of the gate metal layer is 0.01 to 3 μm. For example, the thickness may be 10 nm, 200 nm, 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 1 μm, 2 μm, or 3 μm.
[0048] In this embodiment, the material of the oxide dielectric layer includes, but is not limited to, at least one of aluminum oxide (Al2O3), silicon nitride (Si3N4), hafnium oxide (HfO2), and silicon dioxide (SiO2). The thickness of the oxide dielectric layer is 0.01 to 5 μm, for example, 10 nm, 100 nm, 1 μm, 2 μm, 3 μm, 4 μm, or 5 μm.
[0049] In this embodiment, the material of the source metal layer includes, but is not limited to, at least one of titanium (Ti), nickel (Ni), silver (Ag), and gold (Au). The thickness of the source metal layer is 0.1 to 5 μm, for example, 100 nm, 500 nm, 1 μm, 2 μm, 3 μm, or 5 μm.
[0050] In this embodiment, the thickness of the current blocking layer is 0.1-3 μm, and the nitrogen doping concentration is 10 16 ~10 20 cm -3 For example, the thickness may be 100 nm, 500 nm, 1 μm, 2 μm, or 3 μm.
[0051] In this embodiment, the thickness of the highly doped n-type gallium oxide epitaxial layer is 0.1-3 μm, and the doping concentration is 10 18 ~10 20 cm -3 For example, the thickness may be 100 nm, 200 nm, 300 nm, 400 nm, 500 nm, 1 μm, 2 μm, or 3 μm.
[0052] In this embodiment, the p-type semiconductor layer includes but is not limited to at least one of p-type NiO, p-type Cu2O and p-type diamond, and the doping concentration is 10 17 ~10 20 cm -3， The thickness of the p-type semiconductor layer is 0.1 to 2 μm, for example, 100 nm, 200 nm, 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 1 μm, or 2 μm.
[0053] In this embodiment, the material of the drain metal layer includes, but is not limited to, at least one of titanium (Ti), nickel (Ni), silver (Ag), and gold (Au). The thickness of the drain metal layer is 0.1 to 5 μm, for example, 100 nm, 1 μm, 2 μm, 3 μm, 4 μm, or 5 μm.
[0054] In this embodiment, the height of the sidewall portion of the raised mesa of the p-type semiconductor layer extending vertically and adjacent to the low-doped n-type gallium oxide epitaxial layer is 0.1 to 3 μm. For example, it can be 100 nm, 200 nm, 300 nm, 400 nm, 500 nm, 1 μm, 2 μm, or 3 μm. The mesa width of the low-doped n-type gallium oxide epitaxial layer is 0.1 to 4 μm. For example, it can be 100 nm, 500 nm, 1 μm, 2 μm, 3 μm, or 4 μm. The mesa height of the low-doped n-type gallium oxide epitaxial layer is 0.15 to 4 μm. For example, it can be 150 nm, 500 nm, 1 μm, 2 μm, 3 μm, or 4 μm.
[0055] In this embodiment, the overall width of the heterojunction diode region is 0.1-5 μm, for example, 100 nm, 200 nm, 300 nm, 400 nm, 500 nm, 1 μm, 2 μm, 3 μm, 4 μm, or 5 μm.
[0056] This embodiment also provides a method for preparing the gallium oxide MOSFET structure with a p-type buried layer, such as Figure 2 As shown, the following steps are included: S1, such as Figure 2 As shown in (a), a highly doped n-type gallium oxide substrate 3 is provided, and then a low-doped n-type gallium oxide epitaxial layer 4, a current blocking layer 12 and a highly doped n-type gallium oxide epitaxial layer 9 are sequentially formed on the highly doped n-type gallium oxide substrate; S2, such as Figure 2 As shown in (b), the stacked structure formed above is subjected to interval etching, and the etching portion is etched to a set depth below the low-doped n-type gallium oxide epitaxial layer, so that the low-doped n-type gallium oxide epitaxial layer 4 has an interval upper convex mesa, and the current blocking layer 12 and the high-doped n-type gallium oxide epitaxial layer 9 are retained on the upper convex mesa; S3, such as Figure 2 As shown in (c), a p-type semiconductor layer 5 is formed on the low-doped n-type gallium oxide epitaxial layer 4. The p-type semiconductor layer 5 covers the upper surface of the non-mesa portion of the low-doped n-type gallium oxide epitaxial layer 4 and part of the sidewalls of the upper convex mesas on the left and right sides. S4, such as Figure 2 As shown in (d), a gate dielectric layer 6 is formed on the p-type semiconductor layer 5, the sidewalls of the low-doped n-type gallium oxide epitaxial layer 4, the sidewalls of the current blocking layer 12, and the high-doped n-type gallium oxide epitaxial layer 9; S5, such as Figure 2 As shown in (e), a gate metal layer 7 is formed on a portion of the surface of the gate dielectric layer 6; S6, such as Figure 2 As shown in (f), an oxide dielectric layer 8 is formed on the remaining surface of the gate dielectric layer 6 and on the gate metal layer 7; S7, such as Figure 2 As shown in (g), electrode contact windows are formed on portions of the surfaces of the oxide dielectric layer 8 and the gate dielectric layer 6, exposing portions of the surface of the p-type semiconductor layer, portions of the surface of the gate dielectric layer, and portions of the upper surface of the highly doped n-type gallium oxide epitaxial layer; S8, such as Figure 2 As shown in (h), a source metal layer is formed on a portion of the surface of the p-type semiconductor layer 5, a portion of the surface of the gate dielectric layer 6, a portion of the surface of the oxide dielectric layer 8, and a portion of the upper surface of the highly doped n-type gallium oxide epitaxial layer 9; S9, such as Figure 2 As shown in (i), a drain metal layer 2 is formed on the side of the highly doped n-type gallium oxide substrate 3 facing away from the low-doped n-type gallium oxide epitaxial layer 4, thereby obtaining a gallium oxide MOSFET with a p-type buried layer, wherein the area covered with the oxide dielectric layer is the MOSFET region 1, and the area between adjacent MOSFET regions is the heterojunction diode region 11.
[0057] In the present invention, in step S1, a gallium oxide substrate having a gallium oxide epitaxial layer on its surface may be directly provided, and then inorganic and organic cleaning is performed before the subsequent steps are performed.
[0058] In step S1 , the selection of the gallium oxide substrate is specifically described above and will not be repeated here.
[0059] In step S1 , the material and thickness of the gallium oxide epitaxial layer are as described above and will not be described again here.
[0060] In step S1, the material and thickness of the gallium oxide current blocking layer are as described above and will not be repeated here. In some embodiments, the current blocking layer can be formed by metal organic chemical vapor deposition and ion implantation; In step S1 , the material, thickness, etc. of the highly-doped n-type gallium oxide epitaxial layer of gallium oxide are as described above and will not be described again here.
[0061] In step S2, the width and height of the table are as described above and will not be repeated here.
[0062] In some embodiments, the step of forming a mesa on the surface of the gallium oxide epitaxial layer specifically includes: like Figure 2 As shown in (b), a mesa is prepared on the gallium oxide epitaxial layer by dry etching; wherein the dry etching method includes but is not limited to one of capacitive plasma etching (CCP), inductive plasma etching (ICP), electron cyclotron oscillation (ECR) and ion beam etching (IBE).
[0063] In step S3 , the material and thickness of the p-type semiconductor layer are as described above and will not be described again here.
[0064] In some embodiments, the p-type semiconductor layer may be formed by a deposition method (including but not limited to magnetron sputtering deposition, pulsed laser deposition, metal organic chemical vapor deposition, metal thermal oxidation, etc.); Then, the sidewall of the p-type semiconductor layer is patterned by a stripping or etching method to obtain the p-type semiconductor layer.
[0065] For example, when the material of the p-type semiconductor layer is p-type NiO, the p-type NiO layer can be prepared by using a Ni metal thermal oxidation method.
[0066] In step S4 , the material and thickness of the gate dielectric layer are as described above and will not be described again here.
[0067] In some embodiments, the gate dielectric layer may be formed by a deposition method (including but not limited to plasma enhanced chemical vapor deposition, atomic layer deposition, low pressure chemical vapor deposition, inductively coupled plasma chemical vapor deposition, magnetron sputtering, etc.).
[0068] In step S5 , the material and thickness of the gate metal layer are as described above and will not be described again here.
[0069] Specifically, an electron beam evaporation method or a magnetron sputtering method is used for deposition, and a lift-off process is used to form the gate metal layer.
[0070] In step S6 , the material and thickness of the oxide dielectric layer are as described above and will not be described again here.
[0071] In some embodiments, the oxide dielectric layer may be formed by a deposition method (including but not limited to plasma enhanced chemical vapor deposition, atomic layer deposition, low pressure chemical vapor deposition, inductively coupled plasma chemical vapor deposition, magnetron sputtering, etc.).
[0072] In step S7 , the overall width of the heterojunction diode region is as described above and will not be described again here.
[0073] In some embodiments, photolithography is performed on the surface of the oxide dielectric layer, and then the oxide dielectric layer and the gate dielectric layer are patterned by dry-wet combined etching or wet etching to obtain an electrode contact window.
[0074] In step S8 , the material and thickness of the source metal layer are as described above and will not be repeated here.
[0075] The method for forming the source metal layer refers to the method for forming the gate metal layer.
[0076] In step S9 , the material and thickness of the drain metal layer are as described above and will not be described again here.
[0077] The method for forming the drain metal layer refers to the method for forming the gate metal layer.
[0078] The present invention will be further described below with reference to specific examples.
[0079] Example 1 An embodiment of the present invention provides a gallium oxide MOSFET device with a p-type buried layer. Its structure consists of MOSFETs and heterojunction diodes arranged alternately in a laterally direction. According to the structure, it can be divided into two parts: a MOSFET region and a heterojunction diode region. The MOSFET region 1 includes, from bottom to top, a drain metal layer 2, a highly doped n-type gallium oxide substrate 3, a low-doped n-type gallium oxide epitaxial layer 4, a p-type semiconductor layer 5, a current blocking layer 12, a gate dielectric layer 6, a gate metal layer 7, an oxide dielectric layer 8, a highly doped n-type gallium oxide epitaxial layer 9, and a source metal layer 10.
[0080] The device is characterized in that the drain metal layer 2 is deposited below the highly doped n-type gallium oxide substrate 3 to form an ohmic contact with the highly doped n-type gallium oxide substrate 3; the drain electrode layer includes a Ti layer (100 nm thick), a Ni layer (300 nm thick), and an Ag layer (1 μm thick) stacked in sequence, with the Ti layer side being bonded to the gallium oxide substrate; The low-doped n-type gallium oxide epitaxial layer 4 is deposited on the high-doped n-type gallium oxide substrate 3; the thickness of the gallium oxide substrate is 500 μm, the gallium oxide substrate is a Sn-doped gallium oxide substrate, and the electron concentration is 10 20 cm ~3 The thickness of the gallium oxide epitaxial layer is 10 μm, and the gallium oxide epitaxial layer is a Si-doped gallium oxide epitaxial layer with an electron concentration of 10 16 cm ~3 ; The p-type semiconductor layer 5 is deposited on the upper surface of the low-doped n-type gallium oxide epitaxial layer 4; the thickness of the p-type semiconductor layer is 400 nm, and the height of the mesa sidewall of the p-type semiconductor layer close to the low-doped n-type gallium oxide epitaxial layer is 1 μm; the mesa width of the low-doped n-type gallium oxide epitaxial layer is 500 nm, and the mesa height of the low-doped n-type gallium oxide epitaxial layer is 2 μm.
[0081] The gate dielectric layer 6 is deposited on the sidewalls of the low-doped n-type gallium oxide epitaxial layer 4, the sidewalls of the current blocking layer 12, the surface of the highly-doped n-type gallium oxide epitaxial layer 9, and the upper surface of the p-type semiconductor layer 5; the thickness of the gate dielectric layer is 100 nm; The gate metal layer 7 is deposited on the surface of the gate dielectric layer 6; the thickness of the gate metal layer 7 is 200 nm, and the material of the gate metal layer is Cu (grown by electron beam evaporation); The current blocking layer 12 is deposited on the upper surface of the low-doped n-type gallium oxide epitaxial layer 4; the thickness of the current blocking layer is 1 μm; the current blocking layer 12 is formed by n-injection, and the n-doping concentration is 10 18 cm ~3 ; The highly doped n-type gallium oxide epitaxial layer 8 is deposited on the upper surface of the current blocking layer 12; the highly doped n-type gallium oxide epitaxial layer 8 is formed by Si injection, and the electron concentration is 10 18 cm ~3 ; The oxide dielectric layer 8 is deposited on the upper surface of the gate dielectric layer 6 and the surface of the gate metal layer 7; the thickness of the oxide dielectric layer is 600 nm, and the material of the oxide dielectric layer is silicon oxide (grown by PECVD); The source metal layer 10 is deposited on the upper surface of the highly doped n-type gallium oxide epitaxial layer 9 and the upper surface of the oxide dielectric layer 8, and the source metal layer 10 forms an ohmic contact with the highly doped n-type gallium oxide epitaxial layer 9. The source electrode layer includes a Ti layer (100 nm thick) and an Au layer (500 nm thick) stacked in sequence, with the Ti layer side bonded to the highly doped n-type gallium oxide epitaxial layer (grown by electron beam evaporation). On the basis of the MOSFET region 1, the drain metal layer 2, the highly doped n-type gallium oxide substrate 3, the low doped n-type gallium oxide epitaxial layer 4, the p-type semiconductor layer 5 and the source metal layer 10 are extended on the left and right sides of the gallium oxide MOSFET to form the drain metal layer 2, the highly doped n-type gallium oxide substrate 3, the low doped n-type gallium oxide epitaxial layer 4, the p-type semiconductor layer 5 and the source metal layer 10 of the heterojunction diode region 11; The heterojunction diode region 11 includes, from bottom to top, a drain metal layer 2, a highly doped n-type gallium oxide substrate 3, a low doped n-type gallium oxide epitaxial layer 4, a p-type semiconductor layer 5, and a source metal layer 10; the extended width is 800 nm; The device is characterized in that the drain electrode of the MOSFET region and the cathode electrode of the heterojunction diode region share the drain metal layer 2; the drain metal layer 2 is deposited on the side of the highly doped n-type gallium oxide substrate 3 away from the low-doped n-type gallium oxide epitaxial layer 4, forms an ohmic contact with the highly doped n-type gallium oxide substrate 3, and serves as the cathode of the heterojunction diode region 11; the cathode electrode layer includes a Ti layer (with a thickness of 100 nm), a Ni layer (with a thickness of 300 nm), and an Ag layer (with a thickness of 1 μm) stacked in sequence, with the Ti layer side being bonded to the gallium oxide substrate; It is characterized in that the source electrode of the MOSFET region and the anode electrode of the heterojunction diode region share the drain metal layer 2; the source metal layer 10 is deposited above the p-type semiconductor layer 5, forming an ohmic contact with the p-type semiconductor layer 5, serving as the anode of the heterojunction diode region 11; the anode electrode layer includes a Ti layer (with a thickness of 100 nm) and an Au layer (with a thickness of 500 nm) stacked in sequence, and the Ti layer side is arranged in contact with the p-type semiconductor layer.
[0082] In Example 1, a gallium oxide MOSFET with a p-type buried layer and a conventional gallium oxide MOSFET with a current blocking layer structure are introduced (its structural diagram is shown in FIG. Figure 3 The surface electric field distribution at breakdown is shown in the figure below Figure 4 As shown, the current distribution during reverse conduction is as follows Figure 5 shown.
[0083] like Figure 4 As shown, compared with the gallium oxide MOSFET with a conventional current blocking layer structure, the P-type semiconductor layer introduced in Example 1 transfers the peak electric field from the corner of the bottom gate dielectric layer to the corner of the P-type semiconductor layer, avoiding premature breakdown of the gate dielectric layer, thereby achieving a higher breakdown voltage. Figure 5 The reverse current curves of the two MOSFET structures during reverse conduction and the two-dimensional reverse current distribution of the gallium oxide MOSFET with a p-type buried layer in Example 1 are shown. It can be seen that when the gallium oxide MOSFET structure with a p-type buried layer and the gallium oxide MOSFET structure with a conventional current blocking layer structure are reverse-conducted, the gallium oxide MOSFET structure with a conventional current blocking layer structure cannot rely on the conductive channel generated by the current blocking layer at zero gate voltage to conduct current, and the reverse conduction power consumption is extremely high. In the structure of the gallium oxide MOSFET with a p-type buried layer provided in Example 1 of the present invention, when reverse-conducting, the heterojunction diode region can pass a large area of current, thereby giving full play to the advantages of the heterojunction diode region structure. Therefore, this fully demonstrates that the structure provided by the present invention achieves an effective reverse conduction path while avoiding premature breakdown of the gate dielectric and thereby increasing the breakdown voltage of the device.
[0084] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any other manner. Any person skilled in the art may utilize the above-disclosed technical content to modify or modify the present invention into equivalent embodiments. However, any simple modifications, equivalent variations, and modifications to the above embodiments that do not depart from the technical content of the present invention and are based on the technical essence of the present invention remain within the scope of protection of the present invention.
Claims
1. A gallium oxide MOSFET structure with a p-type buried layer, characterized in that: It consists of a MOSFET region and a heterojunction diode region alternately arranged in the transverse direction, wherein the MOSFET region includes a drain metal layer, a highly doped n-type gallium oxide substrate, a low-doped n-type gallium oxide epitaxial layer, a current blocking layer, a highly doped n-type gallium oxide epitaxial layer, a p-type semiconductor layer, a gate dielectric layer, a gate metal layer, an oxide dielectric layer, and a source metal layer; The highly doped n-type gallium oxide substrate is located above the drain metal layer, and the drain metal layer forms an ohmic contact with the highly doped n-type gallium oxide substrate; The low-doped n-type gallium oxide epitaxial layer is a convex structure with an upper convex table in the middle and is located above the high-doped n-type gallium oxide substrate; The current blocking layer is located above the mesa of the low-doped n-type gallium oxide epitaxial layer; The highly doped n-type gallium oxide epitaxial layer is located above the current blocking layer; The p-type semiconductor layer is located on the left and right sides of the upper convex mesa of the low-doped n-type gallium oxide epitaxial layer. The p-type semiconductor layer on one side has an L-shaped structure and covers the upper surface of the non-mesa portion of the low-doped n-type gallium oxide epitaxial layer and part of the sidewall of the upper convex mesa. The gate dielectric layer is located above the p-type semiconductor layer, and the portion of the gate dielectric layer adjacent to the sidewall of the raised mesa of the low-doped n-type gallium oxide epitaxial layer extends upward and covers the remaining sidewalls of the raised mesa of the low-doped n-type gallium oxide epitaxial layer, the sidewalls of the current blocking layer, and the sidewalls and a portion of the upper surface of the highly doped n-type gallium oxide epitaxial layer; The gate metal layer is located above the gate dielectric layer, and its upper and lower ends do not completely cover the upper surface of the gate dielectric layer; The oxide dielectric layer is located above the gate metal layer and covers the upper surface of the gate metal layer and the upper surface of the gate dielectric layer not covered by the gate metal layer; The source metal layer is located above the oxide dielectric layer and covers the upper surface of the oxide dielectric layer and the remaining upper surface of the highly doped n-type gallium oxide epitaxial layer, and the source metal layer forms an ohmic contact with the highly doped n-type gallium oxide epitaxial layer; The heterojunction diode region includes, from bottom to top, a drain metal layer, a highly doped n-type gallium oxide substrate, a low doped n-type gallium oxide epitaxial layer, a p-type semiconductor layer, and a source metal layer. The drain metal layer, highly doped n-type gallium oxide substrate, low doped n-type gallium oxide epitaxial layer, p-type semiconductor layer, and source metal layer of the heterojunction diode region are respectively connected to the drain metal layer, highly doped n-type gallium oxide substrate, low doped n-type gallium oxide epitaxial layer, p-type semiconductor layer, and source metal layer of the MOSFET region as a whole; The MOSFET region and the heterojunction diode region share a drain metal layer and a source metal layer. The drain metal layer serves as both the drain electrode of the MOSFET region and the cathode electrode of the heterojunction diode region. The source metal layer serves as both the source electrode of the MOSFET region and the anode electrode of the heterojunction diode region.
2. The gallium oxide MOSFET structure with a p-type buried layer according to claim 1, characterized in that: The thickness of the highly doped n-type gallium oxide substrate is 50-650 μm, and the doping concentration is 10 18 ~10 20 cm ~3 The thickness of the low-doped n-type gallium oxide epitaxial layer is 2~20μm, and the doping concentration is 10 15 ~10 17 cm ~3 .
3. The gallium oxide MOSFET structure with a p-type buried layer according to claim 1, characterized in that: The gate dielectric layer is made of at least one of aluminum oxide (Al2O3), silicon nitride (Si3N4), hafnium oxide (HfO2) and silicon dioxide (SiO2), and the thickness of the gate dielectric layer is 0.01-1 μm; The gate metal layer is made of at least one of platinum (Pt), nickel (Ni), molybdenum (Mo), gold (Au) and copper (Cu), and the thickness of the gate metal layer is 0.01-3 μm; The material used for the oxide dielectric layer is at least one of aluminum oxide (Al2O3), silicon nitride (Si3N4), hafnium oxide (HfO2) and silicon dioxide (SiO2), and the thickness of the oxide dielectric layer is 0.01-5 μm.
4. The gallium oxide MOSFET structure with a p-type buried layer according to claim 1, characterized in that: The thickness of the current blocking layer is 0.1-3 μm, and the material used is a nitrogen doping concentration of 10 16 ~10 20 cm ~3 gallium oxide materials.
5. The gallium oxide MOSFET structure with a p-type buried layer according to claim 1, characterized in that: The thickness of the highly doped n-type gallium oxide epitaxial layer is 0.1-3 μm, and the material used is a doping concentration of 10 18 ~10 20 cm ~3 gallium oxide materials.
6. The gallium oxide MOSFET structure with a p-type buried layer according to claim 1, characterized in that: The material used for the p-type semiconductor layer is at least one of p-type NiO, p-type Cu2O and p-type diamond, and the doping concentration is 10 17 ~10 20 cm ~3 The thickness of the p-type semiconductor layer extending in the horizontal direction is 0.1-2 μm, and the height of the p-type semiconductor layer extending in the vertical direction and adjacent to the side wall of the convex mesa on the low-doped n-type gallium oxide epitaxial layer is 0.1-3 μm.
7. The gallium oxide MOSFET structure with a p-type buried layer according to claim 1, characterized in that: The width of the convex mesa on the low-doped n-type gallium oxide epitaxial layer is 0.1-4 μm, and the height of the convex mesa on the low-doped n-type gallium oxide epitaxial layer is 0.15-4 μm.
8. The gallium oxide MOSFET structure with a p-type buried layer according to claim 1, characterized in that: The overall width of the heterojunction diode region is 0.1-5 μm.
9. The gallium oxide MOSFET structure with a p-type buried layer according to claim 1, characterized in that: The material of the drain metal layer is at least one of titanium (Ti), nickel (Ni), silver (Ag) and gold (Au), and the thickness of the drain metal layer is 0.1-5 μm; The material of the source metal layer is at least one of titanium (Ti), nickel (Ni), silver (Ag) and gold (Au), and the thickness of the source metal layer is 0.1-5 μm.
10. The method for preparing a gallium oxide MOSFET structure with a p-type buried layer according to any one of claims 1 to 9, characterized in that: The steps include: Providing a highly doped n-type gallium oxide substrate; forming a low-doped n-type gallium oxide epitaxial layer on a high-doped n-type gallium oxide substrate; forming a current blocking layer on the low-doped n-type gallium oxide epitaxial layer; forming a highly doped n-type gallium oxide epitaxial layer on the current blocking layer; Performing interval etching on the stacked structure formed above, etching partially to a set depth below the low-doped n-type gallium oxide epitaxial layer, so that the low-doped n-type gallium oxide epitaxial layer has interval upper convex mesas, and the current blocking layer and the high-doped n-type gallium oxide epitaxial layer are retained on the upper convex mesas; forming a p-type semiconductor layer on the low-doped n-type gallium oxide epitaxial layer, wherein the p-type semiconductor layer covers the upper surface of the non-mesa portion of the low-doped n-type gallium oxide epitaxial layer and part of the sidewalls of the upper convex mesas on the left and right sides; forming a gate dielectric layer on the p-type semiconductor layer, on the sidewall of the low-doped n-type gallium oxide epitaxial layer, on the sidewall of the current blocking layer, and on the high-doped n-type gallium oxide epitaxial layer; forming a gate metal layer on a portion of the surface of the gate dielectric layer; forming an oxide dielectric layer on the remaining surface of the gate dielectric layer and on the gate metal layer; forming electrode contact windows on a portion of the surface of the oxide dielectric layer and the gate dielectric layer, exposing a portion of the surface of the p-type semiconductor layer, a portion of the surface of the gate dielectric layer, and a portion of the upper surface of the highly doped n-type gallium oxide epitaxial layer; forming a source metal layer on a portion of the surface of the p-type semiconductor layer, a portion of the surface of the gate dielectric layer, a portion of the surface of the oxide dielectric layer, and a portion of the upper surface of the highly doped n-type gallium oxide epitaxial layer; A drain metal layer is formed on the side of the highly doped n-type gallium oxide substrate facing away from the low-doped n-type gallium oxide epitaxial layer to obtain a gallium oxide MOSFET with a p-type buried layer, wherein the area covered with the oxide dielectric layer is the MOSFET area, and the area between adjacent MOSFET areas is the heterojunction diode area.