Semiconductor device and method of manufacturing the same

Abstract

The present disclosure relates to the technical field of semiconductor chip, and particularly relates to a semiconductor device and a preparation method thereof. The semiconductor device comprises a first region and a second region surrounding the first region, and the semiconductor device comprises a substrate, a functional layer and a drift layer, the functional layer is arranged on the substrate, the drift layer is arranged on the side of the functional layer away from the substrate, the doping type of the drift layer is the same as the doping type of the functional layer, wherein the functional layer comprises a first sub-functional layer and a second sub-functional layer, the first sub-functional layer is arranged in the second region, the second sub-functional layer is arranged in the first region, and the doping concentration of the second sub-functional layer is greater than the doping concentration of the first sub-functional layer.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor chip, and particularly relates to a semiconductor device and a preparation method thereof. BACKGROUND

[0002] As one of the core components of modern power electronic systems, power semiconductor devices bear key functions such as conversion, control and management of electric energy, and are widely used in new energy vehicles and rail transit electric drive, power systems, communication and data center infrastructure power supply, consumer electronics and general power supply, special equipment and other fields.

[0003] According to the main flow direction of the current inside the device, the power semiconductor device can be divided into a lateral power semiconductor device and a vertical power semiconductor device. The vertical power semiconductor device has many advantages such as high blocking voltage, small conduction loss and strong heat dissipation capacity, and has been widely applied and developed in medium and high power application scenarios.

[0004] However, in actual device design and manufacturing, the voltage resistance performance is often limited by many factors. Therefore, an improved semiconductor device is expected to solve the above problems. SUMMARY

[0005] Embodiments of the present disclosure provide a semiconductor device and a preparation method thereof, aiming to solve the problem of voltage resistance of the semiconductor device.

[0006] To achieve the above-mentioned purpose, the embodiments of the present disclosure adopt the following technical solutions:

[0007] On the one hand, a semiconductor device is provided, comprising a first region and a second region around the first region. The semiconductor device comprises a substrate, a functional layer and a drift layer. The functional layer is arranged on the substrate. The drift layer is arranged on the side of the functional layer away from the substrate, and the doping type of the drift layer is the same as that of the functional layer. The functional layer comprises a first sub-functional layer and a second sub-functional layer, the first sub-functional layer is arranged in the second region, and the second sub-functional layer is arranged in the first region. The doping concentration of the second sub-functional layer is greater than that of the first sub-functional layer.

[0008] The semiconductor device comprises a first region and a second region surrounding the first region, and a functional layer is arranged in the semiconductor device, the functional layer comprises a second sub-functional layer in the first region and a first sub-functional layer in the second region, the first sub-functional layer can affect the size of the depletion region of the second region in the third direction, the doping concentration of the first sub-functional layer is lower than the doping concentration of the second sub-functional layer, so as to increase the thickness of the effective drift region of the second region, thereby increasing the size of the depletion region of the second region in the third direction, which can effectively reduce the surface electric field of the second region and improve the withstand voltage capability of the second region of the semiconductor device.

[0009] The thickness and / or doping concentration of the second sub-functional layer can affect the size of the depletion region of the first region in the third direction, the existence of the second sub-functional layer increases the sum of the sizes of the second sub-functional layer and the drift layer in the third direction, which also increases the size of the depletion region of the first region in the third direction, in this case, by increasing the doping concentration of the second sub-functional layer, the doping concentration of the second sub-functional layer is greater than the doping concentration of the first sub-functional layer, which can effectively reduce the size of the depletion region of the first region in the third direction. And the doping concentration of the second sub-functional layer is greater than the doping concentration of the drift layer, which can further reduce the thickness of the effective drift region of the first region, thereby reducing the size of the depletion region of the first region in the third direction, which can effectively improve the on-state performance of the first region.

[0010] In a feasible embodiment, the functional layer further comprises at least one third sub-functional layer arranged in the first region, and the doping concentration of the third sub-functional layer is less than the doping concentration of the second sub-functional layer; the functional layer comprises a plurality of second sub-functional layers, and the third sub-functional layer is arranged between at least two adjacent second sub-functional layers.

[0011] In the process of forming the second sub-functional layer, ion implantation and other processes can be used, which may cause lattice damage of the second sub-functional layer, thereby affecting the epitaxial quality of the drift layer. By reducing the area of the second sub-functional layer, the lattice damage of the functional layer can be effectively reduced, the growth quality of the drift layer can be improved, and the electrical performance of the semiconductor device can be improved.

[0012] In a feasible embodiment, the second sub-functional layer and the third sub-functional layer extend along the first direction, and the second sub-functional layer and the third sub-functional layer are arranged alternately along the second direction; the first direction and the second direction are perpendicular to the thickness direction of the substrate, and the first direction and the second direction are perpendicular to each other.

[0013] In an embodiment, a plurality of the second sub-functional layers, a part of the second sub-functional layers extend along a first direction, another part of the second sub-functional layers extend along a second direction, the part of the second sub-functional layers and the another part of the second sub-functional layers intersect each other to form a mesh structure; the third sub-functional layer is located in an opening of the mesh structure.

[0014] In an embodiment, the second sub-functional layer is a ring structure, and a plurality of the second sub-functional layers are sequentially arranged and spaced apart; the third sub-functional layer is located between two second sub-functional layers adjacent in a radial direction of the second sub-functional layer.

[0015] In an embodiment, the first sub-functional layer is also arranged in the first region, and the first sub-functional layer is located around the second sub-functional layer.

[0016] In an embodiment, the first sub-functional layer can also be located in the first region, that is, the area of the first sub-functional layer is greater than the area of the second region, in which case, a part of the first sub-functional layer can extend to the first region.

[0017] In an embodiment, the doping concentration of the second sub-functional layer is greater than or equal to the doping concentration of the drift layer.

[0018] In an embodiment, a buffer layer is further arranged between the substrate and the functional layer, the buffer layer has the same doping type as the functional layer, and the buffer layer is in contact with the functional layer.

[0019] The buffer layer can prevent the extension of the depletion layer of the semiconductor device to the substrate in the reverse blocking state, and avoid the influence of the substrate defects on the long-term reliability of the semiconductor device.

[0020] In an embodiment, at least one junction termination structure and a passivation layer are further included, the junction termination structure is arranged on the side of the drift layer away from the substrate; the junction termination structure is arranged in the second region and surrounds the first region; the passivation layer is arranged on the side of the drift layer away from the substrate and located in the second region; and the passivation layer covers the at least one junction termination structure.

[0021] The junction termination structure can reduce the surface electric field of the second region of the semiconductor device, alleviate the electric field concentration phenomenon of the second region, reduce the risk of breakdown of the second region, and improve the withstand voltage of the semiconductor device.

[0022] The passivation layer can electrically isolate the junction termination structure and the second metal layer to avoid short circuit damage of the semiconductor device, and the passivation layer can adjust the electric field and improve the withstand voltage of the second region of the semiconductor device to a certain extent.

[0023] In an implementation, the semiconductor power device further comprises: a first doped region, located on the side of the drift layer away from the substrate and in the first region; the first doped region has a different doping type from the drift layer; a first metal layer, located on the side of the substrate away from the drift layer; and a second metal layer, located on the side of the first doped layer away from the substrate and in contact with the first doped region.

[0024] As a possible implementation, the semiconductor power device can be a diode.

[0025] In an implementation, the semiconductor power device further comprises: a source region, located on the side of the drift layer away from the substrate and in the first region; at least part of the source region has a different doping type from the drift layer; a gate, located in the first region and on the side of the drift layer away from the substrate and in contact with part of the source region; and a drain, located on the side of the substrate away from the drift layer.

[0026] As a possible implementation, the semiconductor power device can be a field effect transistor.

[0027] In another aspect, a method for manufacturing a semiconductor device is provided, which comprises: forming an initial functional layer on one side of a substrate; performing ion implantation on a target region of the initial functional layer to form a second sub-functional layer, the initial functional layer excluding the target region forms a first sub-functional layer; the first sub-functional layer surrounds the second sub-functional layer, and the first sub-functional layer and the second sub-functional layer form a functional layer; and forming a drift layer on the side of the functional layer away from the substrate.

[0028] It can be understood that the method for manufacturing a semiconductor device provided by the above-mentioned embodiments of the present disclosure can achieve the beneficial effects of the semiconductor device, which are described above and will not be repeated here. BRIEF DESCRIPTION OF DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the present disclosure, the following will briefly introduce the drawings needed to be used in some embodiments of the present disclosure. Obviously, the drawings described below are only some of the drawings of the embodiments of the present disclosure, and other drawings can also be obtained by those skilled in the art according to these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limited to the actual size, actual process, actual time sequence, etc. of the product involved in the embodiments of the present disclosure.

[0030] Figure 1 a structural diagram of an electronic device according to some embodiments;

[0031] Figure 2 A structure diagram of a chip according to some embodiments;

[0032] Figure 3 A structure diagram of a semiconductor device according to some embodiments;

[0033] Figure 4 A structure diagram of another semiconductor device according to some embodiments;

[0034] Figure 5 A Figure 4 An AA direction view of the functional layer in the middle;

[0035] Figure 6 A Figure 3 A partial doping concentration distribution diagram of the B region of the semiconductor device shown;

[0036] Figure 7 A Figure 4 A partial doping concentration distribution diagram of the B region of the semiconductor device shown;

[0037] Figure 8 A cathode voltage-cathode current curve diagram of the semiconductor device;

[0038] Figure 9 A Figure 3 An electric field distribution diagram of the B region of the semiconductor device shown;

[0039] Figure 10 A Figure 4 An electric field distribution diagram of the B region of the semiconductor device shown;

[0040] Figure 11 A lateral electric field distribution curve diagram of the semiconductor device;

[0041] Figure 12 A longitudinal electric field distribution curve diagram of the semiconductor device;

[0042] Figure 13 A Figure 3 An avalanche breakdown impact ionization rate distribution diagram of the semiconductor device shown;

[0043] Figure 14 A Figure 4 An avalanche breakdown impact ionization rate distribution diagram of the semiconductor device shown;

[0044] Figure 15 A structure diagram of another semiconductor device according to some embodiments;

[0045] Figure 16 A Figure 15 An AA direction view of the functional layer in the middle;

[0046] Figure 17 FIG. 6 is another AA-direction view of the functional layer in FIG. 5; Figure 15 FIG. 7 is another AA-direction view of the functional layer in FIG. 5;

[0047] Figure 18 FIG. 8 is another AA-direction view of the functional layer in FIG. 5; Figure 15 FIG. 9 is another AA-direction view of the functional layer in FIG. 5;

[0048] Figure 19 FIG. 10 is another AA-direction view of the functional layer in FIG. 5; Figure 15 FIG. 11 is another AA-direction view of the functional layer in FIG. 5;

[0049] Figure 20 FIG. 12 is a structural diagram of a semiconductor device according to some embodiments;

[0050] Figure 21 FIG. 13 is a flowchart of a method for manufacturing a semiconductor device according to some embodiments;

[0051] Figure 22 FIG. 14 is a flowchart of another method for manufacturing a semiconductor device according to some embodiments;

[0052] Figures 23-27 FIG. 15 is a structural diagram of a semiconductor structure corresponding to different steps in the manufacturing method shown in FIG. 14. Figure 22 DETAILED DESCRIPTION

[0053] The technical solutions in some embodiments of the present disclosure will be clearly and completely described below with reference to the drawings. Obviously, the described embodiments are only some of the embodiments of the present disclosure, but not all the embodiments. Based on the embodiments provided in the present disclosure, all other embodiments obtained by those of ordinary skill in the art belong to the scope of protection of the present disclosure.

[0054] In the description of the present disclosure, it should be understood that the terms "center", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like indicate the orientation or positional relationship shown in the drawings, and are only used to facilitate the description of the present disclosure and simplify the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation to the present disclosure.

[0055] ​Unless the context clearly requires otherwise, throughout the description and the claims, the term "comprise," "comprising," and the like are to be construed in an open, inclusive sense as "including, but not limited to." In describing the description, the terms "a," "an," "some," "some," "exemplary" or "some examples" are intended to mean that a certain feature, structure, material, or characteristic is included in at least one embodiment or example of the disclosure. The illustrative representations of the above terms are not necessarily meant to refer to the same embodiment or example. In addition, the specific features, structures, materials, or characteristics described can be included in any suitable way in one or more embodiments or examples.

[0056] Hereinafter, the terms "first", "second" are used only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the embodiments of the disclosure, unless otherwise stated, the meaning of "a plurality of" is two or more.

[0057] In describing some embodiments, "connected" and / or its derivatives can be used. For example, the term "connected" can be used to describe some embodiments in which two or more components are in direct physical or electrical contact with each other.

[0058] "A and / or B" includes the following three combinations: only A, only B, and a combination of A and B.

[0059] The use of "adapted for" or "configured for" herein means open and inclusive language that does not exclude devices adapted for or configured for performing additional tasks or steps.

[0060] In addition, the use of "based on" means open and inclusive, because the process, step, calculation or other action "based on" one or more stated conditions or values can be based on additional conditions or values beyond those stated in practice.

[0061] As used herein, "about," "approximately," or "almost" includes the stated value and the average value within an acceptable deviation range of the specific value, wherein the acceptable deviation range is determined by the person of ordinary skill in the art considering the measurement being discussed and the error related to the measurement of the specific quantity (i.e., the limitations of the measurement system).

[0062] In the present disclosure, the meaning of "on," "over," and "above" should be interpreted in the broadest context possible such that "on" means not only "directly on" but also "on" with an intervening feature or layer therebetween, and "over" or "above" means not only "over" or "above" but also "over" or "above" with no intervening feature or layer therebetween (i.e., directly on).

[0063] Exemplary embodiments are described herein with reference to cross-sectional and / or plan view illustrations that are schematic illustrations of idealized embodiments. In this regard, the thicknesses of layers and regions are exaggerated in the drawings for clarity. Thus, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Therefore, exemplary embodiments should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region illustrated as a rectangle will typically have rounded or curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of exemplary embodiments.

[0064] As used herein, the term "substrate" refers to a material on which a subsequent layer of material can be added. The substrate itself can be patterned. The material added on the substrate can be patterned or can remain unpatterned. Further, the substrate can include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of a non-conductive material such as glass, plastic, or sapphire wafer.

[0065] It should be noted that in this disclosure, the terms "exemplary" or "for example" are used as indicative of a possible embodiment, or to present an example, instance or illustration. The use of these terms is intended to be illustrative, and not to be construed as being superior or inferior, or as having any other connotation. In other words, the embodiments described as "exemplary" or "for example" are not necessarily more than other embodiments, and all embodiments are intended to be within the scope of the present disclosure.

[0066] Figure 1 A structural diagram of an electronic device according to some embodiments is provided. As Figure 1As shown, the electronic device 1000 can be a product or component with power conversion function, such as a power conversion system of an electric vehicle, a charging device of a mobile phone, a power supply adaptation device of a notebook computer, etc. The electronic device 1000 can also be a user device or terminal device of different types, such as a notebook computer, a tablet computer, a mobile phone, a wearable device, and a vehicle-mounted device, etc. The electronic device 1000 can also be a power amplification device applied in the above electronic devices. It should be understood that the electronic device 1000 can also be a device or component with signal receiving / transmitting function in an amplifier, a modulator, a base station, a radar, etc. The specific form of the electronic device 1000 is not specially limited in the embodiments of the present application.

[0067] The electronic device 1000 with power conversion function is taken as an example below to illustrate some embodiments of the present disclosure, but the embodiments of the present disclosure are not limited thereto, and any other display device can also be considered as long as the same technical idea is applied.

[0068] In Figure 1 , the electronic device 1000 includes a chip 1001 and a circuit board 1002, for example. The chip 1001 is coupled to the circuit board 1002, and the circuit board 1002 is configured to supply power and transmit signals to the chip 1001. For example, the chip 1001 is coupled to the circuit board 1002 through a plurality of pins. Figure 2 , Figure 2 is a structural diagram of a chip according to some embodiments. The chip 1001 includes a semiconductor device 100 and a packaging substrate 200, and the semiconductor device 100 is coupled to the packaging substrate 200.

[0069] Figure 3 is a structural diagram of a semiconductor device according to some embodiments. The semiconductor device 100 can be a diode. The semiconductor device 100 includes a substrate 101, a buffer layer 102, a drift layer 104, and a first doped layer 105.

[0070] The buffer layer 102 is disposed on one side of the substrate 101, the drift layer 104 is disposed on a side of the buffer layer 102 away from the substrate 101, and the first doped layer 105 is disposed on a side of the drift layer 104 away from the drift layer 104.

[0071] In some possible embodiments, the semiconductor device 100 further includes a first doped layer 105, a first metal layer 201, and a second metal layer 202. The first doped layer 105 is disposed on a side of the drift layer 104 away from the substrate 101 and in the first region Q1, and the first doped layer 105 has a doping type different from that of the drift layer 104. The first metal layer 201 is disposed on a side of the substrate 101 away from the drift layer 104 and in contact with the substrate 101. The second metal layer 202 is disposed on a side of the first doped layer 105 away from the substrate 101 and in contact with the first doped layer 105.

[0072] In some possible embodiments, the semiconductor device 100 further includes a passivation layer 203 disposed on a side of the drift layer 104 away from the substrate 101 and in the second region Q2. The passivation layer 203 is in contact with the second metal layer 202.

[0073] The first region Q1 can be an active region of the power device, and the second region Q2 can be a termination region of the power device. The first region Q1 mainly functions to conduct current and withstand voltage, so as to realize the electrical function of the semiconductor device 100.

[0074] In some possible embodiments, the semiconductor device 100 further includes a transition region between the first region Q1 and the second region Q2. The transition region functions to connect the termination region and the active region, so that the first region Q1 can be smoothly connected to the second region Q2.

[0075] The withstand voltage of the semiconductor device 100 is limited by many factors. The applicant has found that the longitudinal withstand voltage characteristics of the first region Q1 and the second region Q2 are basically the same, but the second region Q2 is located at the edge of the chip and is affected by the transverse voltage. Under the superposition of the longitudinal voltage and the transverse voltage, the second region Q2 bears a larger electric field and is more likely to cause breakdown and other problems. In view of this, the present disclosure proposes an improved semiconductor device 100 to improve the withstand voltage of the semiconductor device 100.

[0076] Figure 4 FIG. 2 shows a structure of another semiconductor device according to some embodiments. The semiconductor device 100 includes a substrate 101, a functional layer 103, and a drift layer 104. The semiconductor device 100 can include a first region Q1 and a second region Q2 located around the first region Q1.

[0077] The material of the substrate 101 includes any one of silicon (Si), silicon carbide (SiC), or gallium nitride (GaN). For example, the substrate 101 has an N-type doping type.

[0078] The functional layer 103 is disposed on one side of the substrate 101. The functional layer 103 includes a first sub-functional layer 103a disposed in the second region Q2 and a second sub-functional layer 103b disposed in the first region Q1, and the second sub-functional layer 103b has a larger doping concentration than the first sub-functional layer 103a. For example, the functional layer 103 is of an N-type.

[0079] Referring to Figure 5 , Figure 5 For example, the functional layer 103 is of an N-type. Figure 4 The AA direction view of the functional layer in FIG. 10. The area of the second sub-functional layer 103b can be less than or equal to the area of the first region Q1. In the case where the area of the second sub-functional layer 103b is less than the area of the first region Q1, part of the first sub-functional layer 103a can extend to the first region Q1.

[0080] The drift layer 104 is disposed on the side of the functional layer 103 away from the substrate 101, and the drift layer 104 is of the same doping type as the functional layer 103. For example, the drift layer 104 is of an N-type.

[0081] Referring to Figure 6 and Figure 7 , Figure 6 For example, the functional layer 103 is of an N-type. Figure 3 The partial doping concentration distribution of the semiconductor device B region shown in FIG. 11, Figure 7 The partial doping concentration distribution of the semiconductor device B region shown in FIG. 12. Figure 4 The partial doping concentration distribution of the semiconductor device B region shown in FIG. 11, Figure 6 and Figure 7 In FIG. 13, the ordinate is the dimension of the semiconductor device 100 in the third direction z, in micrometers, with the surface of the drift layer 104 away from the substrate 101 as the zero point. It can be seen that, in combination with Figure 3 and Figure 6 It can be seen that the dimension of the drift layer 104 in the third direction z of the first region Q1 is about 4.7 nanometers, and the dimension of the drift layer 104 in the third direction z of the second region Q2 is about 4.7 nanometers. In combination with Figure 4 and Figure 7 It can be seen that the dimension of the drift layer 104 in the third direction z of the first region Q1 is about 4.7 nanometers, and the sum of the dimensions of the drift layer 104 in the third direction z of the second region Q2 and the first sub-functional layer 103a is about 6 nanometers. Therefore, the presence of the first sub-functional layer 103a can increase the effective drift region thickness of the semiconductor device 100 in the second region Q2, so that the dimension of the depletion region in the third direction z of the second region Q2 is greater than that of the first region Q1.

[0082] For example, referring to Figure 8 , Figure 8a cathode voltage-cathode current graph of a semiconductor device, Figure 9 In the graph, the horizontal axis is the cathode voltage in volts (V), and the vertical axis is the cathode current in amperes (A). The solid line is the voltage-current graph of the semiconductor device 100 shown in Figure 3 The dashed line is the voltage-current graph of the semiconductor device 100 shown in Figure 4 The exemplary first metal layer 201 is the cathode. It can be seen that when the cathode current is greater than 10-23 amperes, the cathode voltage of the semiconductor device 100 shown in Figure 4 The cathode voltage of the semiconductor device 100 shown in Figure 3 The cathode voltage of the semiconductor device 100 shown in Figure 4 The semiconductor device 100 shown in has better voltage resistance.

[0083] Referring to Figure 9 and Figure 10 , Figure 9 is Figure 3 the electric field distribution graph of the semiconductor device B region shown in Figure 10 is Figure 4 the electric field distribution graph of the semiconductor device B region shown in Figure 9 and Figure 10 is the electric field distribution graph of the semiconductor device 100 when the anode voltage is 900 volts, in combination with Figure 3 and Figure 9 It can be seen that Figure 3 The electric field of the semiconductor device 100 shown in is mainly distributed in the drift layer 104, in combination with Figure 4 and Figure 10 It can be seen that Figure 4 The semiconductor device 100 shown in is not only distributed in the drift layer 104, but also in the first sub-functional layer 103a. Moreover, compared with Figure 9 , Figure 10 In the graph, the orange and yellow areas for representing high voltage are smaller, indicating that Figure 4 The semiconductor device 100 shown in can improve the electric field concentration phenomenon of the second region Q2, making the electric field distribution of the second region Q2 more uniform, thereby improving the voltage resistance of the second region Q2 of the semiconductor device 100.

[0084] Referring to Figure 11 and Figure 12 , Figure 11 is a lateral electric field distribution graph of a semiconductor device, Figure 12 is a longitudinal electric field distribution graph of a semiconductor device. Figure 11 In the graph, the horizontal axis is the size of the semiconductor device 100 in the second direction x in micrometers (µm), and the vertical axis is the electric field of the semiconductor device 100 at a depth of 0.5 micrometers in the first direction y in volts per centimeter (V / cm).Figure 12 In the figure, the abscissa is the size of the semiconductor device 100 in the first direction y, in micrometers (pm), and the ordinate is the electric field of the semiconductor device 100 at a depth of 0.5 micrometers in the second direction x, in volts per centimeter (V / cm). In the figure, the solid line is the electric field distribution curve of the semiconductor device 100 shown in Figure 3 In the figure, the abscissa is the size of the semiconductor device 100 in the first direction y, in micrometers (pm), and the ordinate is the electric field of the semiconductor device 100 at a depth of 0.5 micrometers in the second direction x, in volts per centimeter (V / cm). In the figure, the solid line is the electric field distribution curve of the semiconductor device 100 shown in Figure 4 In the figure, the abscissa is the size of the semiconductor device 100 in the first direction y, in micrometers (pm), and the ordinate is the electric field of the semiconductor device 100 at a depth of 0.5 micrometers in the second direction x, in volts per centimeter (V / cm). In the figure, the solid line is the electric field distribution curve of the semiconductor device 100 shown in

[0085] In combination with Figure 3 , Figure 4 and Figure 11 , it can be seen that at the abscissa of about 26 micrometers, Figure 4 the peak electric field of the semiconductor device 100 shown in Figure 3 is about 1.8 x 106V / cm, Figure 4 the peak electric field of the semiconductor device 100 shown in is about 2.3 x 106V / cm,

[0086] and the lateral peak electric field of the semiconductor device 100 shown in Figure 3 is lower, which is conducive to improving the voltage resistance of the semiconductor device 100. Figure 4 Figure 12 In combination with Figure 4 , Figure 3 and Figure 4 , it can be seen that when the abscissa is greater than or equal to 3 micrometers, the electric field of the semiconductor device 100 shown in

[0087] is equal to Figure 13 , Figure 14 , Figure 13 the electric field of the semiconductor device 100 shown in Figure 3 is improved, and the overall electric field distribution is more uniform, which is conducive to reducing the electric field concentration phenomenon of the semiconductor device 100 and improving the voltage resistance of the semiconductor device 100. Figure 14 Figure 4 Referring to Figure 3 and Figure 13 , Figure 3 it can be seen that the highest point of the impact ionization rate of the semiconductor device 100 shown in Figure 4 is located at the edge of the second region Q2, in combination with Figure 14 and Figure 4 , it can be seen that the highest point of the impact ionization rate of the semiconductor device 100 shown in Figure 4 is located at the side of the first doped layer 105 close to the substrate 101 of the first region Q1.The breakdown point of the semiconductor device 100 is located inside the semiconductor device 100, which is beneficial to protect the surface structure of the semiconductor device 100 and improve the reliability of the semiconductor device 100.

[0088] In summary, the semiconductor device 100 includes a first region Q1 and a second region Q2 located around the first region Q1, and the semiconductor device 100 is provided with a functional layer 103, the functional layer 103 includes a second sub-functional layer 103b located in the first region Q1 and a first sub-functional layer 103a located in the second region Q2, the first sub-functional layer 103a can affect the size of the depletion region of the second region Q2 in the third direction z, and the doping concentration of the first sub-functional layer 103a is lower than the doping concentration of the second sub-functional layer 103b, so as to increase the thickness of the effective drift region of the second region Q2, thereby increasing the size of the depletion region of the second region Q2 in the third direction z, which can effectively reduce the surface electric field of the second region Q2 and improve the withstand voltage capability of the second region Q2 of the semiconductor device 100.

[0089] The thickness and / or doping concentration of the second sub-functional layer 103b can affect the size of the depletion region of the first region Q1 in the third direction z, and the existence of the second sub-functional layer 103b increases the sum of the sizes of the second sub-functional layer 103b and the drift layer 104 in the third direction z, which also increases the size of the depletion region of the first region Q1 in the third direction z. In this case, by increasing the doping concentration of the second sub-functional layer 103b, the doping concentration of the second sub-functional layer 103b is greater than the doping concentration of the first sub-functional layer 103a, which can effectively reduce the size of the depletion region of the first region Q1 in the third direction z. And the doping concentration of the second sub-functional layer 103b is greater than the doping concentration of the drift layer 104, which can further reduce the thickness of the effective drift region of the first region Q1, thereby reducing the size of the depletion region of the first region Q1 in the third direction z, which can effectively improve the conduction performance of the first region Q1.

[0090] Continuing to refer to Figure 4 In some possible embodiments, the semiconductor device 100 further includes a buffer layer 102 located between the substrate 101 and the functional layer 103. The buffer layer 102 has the same doping type as the functional layer 103, and the buffer layer 102 is in contact with the functional layer 103. The buffer layer 102 has the same doping type as the drift layer 104. For example, the buffer layer 102 has an N-type doping type.

[0091] The buffer layer 102 can block the expansion of the depletion layer of the semiconductor device 100 in the direction of the substrate 101 in the reverse blocking state, thereby avoiding the influence of the defects of the substrate 101 on the long-term reliability of the semiconductor device 100.

[0092] In some possible embodiments, the semiconductor device 100 further comprises at least one junction termination structure 106 disposed on the side of the drift layer 104 away from the substrate 101. The junction termination structure 106 is disposed in the second region Q2, and the junction termination structure 106 surrounds the first region Q1. Exemplarily, the junction termination structure 106 can be any one of a field limiting ring, a field plate, or a junction termination extension.

[0093] The junction termination structure 106 can reduce the surface electric field of the second region Q2 of the semiconductor device 100, alleviate the surface electric field concentration phenomenon of the second region Q2, and reduce the breakdown risk of the second region Q2, thereby improving the voltage resistance of the semiconductor device 100.

[0094] In some possible embodiments, the semiconductor device 100 further comprises a passivation layer 203 disposed on the side of the drift layer 104 away from the substrate 101 and located in the second region Q2. The passivation layer 203 covers the at least one junction termination structure 106. Exemplarily, the material of the passivation layer 203 comprises silicon oxide (SiO2).

[0095] The passivation layer 203 can electrically isolate the junction termination structure 106 and the second metal layer 202 to avoid short-circuit damage of the semiconductor device 100, and the passivation layer 203 can adjust the electric field and improve the voltage resistance of the second region Q2 of the semiconductor device 100 to a certain extent.

[0096] In some possible embodiments, the semiconductor device 100 further comprises a first doped layer 105, a first metal layer 201, and a second metal layer 202. The first doped layer 105 is disposed on the side of the drift layer 104 away from the substrate 101 and located in the first region Q1, and the doping type of the first doped layer 105 is different from that of the drift layer 104. The first metal layer 201 is disposed on the side of the substrate 101 away from the drift layer 104 and in contact with the substrate 101. The second metal layer 202 is disposed on the side of the first doped layer 105 away from the substrate 101 and in contact with the first doped layer 105. As a possible implementation manner, the semiconductor device 100 can be a diode.

[0097] In some possible embodiments, referring to Figure 15 and Figure 16 , Figure 15 FIG. 2 is a structural diagram of another semiconductor device provided according to some embodiments, Figure 16 is Figure 15 a AA direction view of a functional layer in FIG. 1.

[0098] The semiconductor device 100 comprises a substrate 101, a functional layer 103, and a drift layer 104. The semiconductor device 100 can comprise a first region Q1 and a second region Q2 located around the first region Q1.

[0099] The functional layer 103 is disposed on one side of the substrate 101. The functional layer 103 includes a first sub-functional layer 103a, a second sub-functional layer 103b, and a third sub-functional layer 103c. The first sub-functional layer 103a is disposed in the second region Q2, the second sub-functional layer 103b is disposed in the first region Q1, and the doping concentration of the second sub-functional layer 103b is greater than that of the first sub-functional layer 103a. The third sub-functional layer 103c is disposed in the first region Q1, and the doping concentration of the third sub-functional layer 103c is less than that of the second sub-functional layer 103b. The functional layer 103 includes, for example, a plurality of second sub-functional layers 103b, and the third sub-functional layer 103c is disposed between at least two adjacent second sub-functional layers 103b. The second sub-functional layer 103b can be rectangular, for example.

[0100] The second sub-functional layer 103b and the third sub-functional layer 103c both extend along a first direction y, and the second sub-functional layer 103b and the third sub-functional layer 103c are alternately disposed along a second direction x. The first direction y and the second direction x are both perpendicular to a thickness direction z of the substrate 101, and the first direction y and the second direction x are perpendicular to each other. The doping concentration of the first sub-functional layer 103a can be the same as that of the third sub-functional layer 103c, for example.

[0101] Figure 15 The remaining structure of the semiconductor device 100 is substantially the same as that of the semiconductor device 100 shown in Figure 4 and will not be described again.

[0102] In the process of forming the second sub-functional layer 103b, ion implantation and other processes can be used, which can cause lattice damage to the functional layer 103. By reducing the area of the second sub-functional layer 103b, the lattice damage to the functional layer 103 can be effectively reduced, the growth quality of the drift layer 104 can be improved, and thus the electrical performance of the semiconductor device 100 can be improved.

[0103] In some possible embodiments, referring to Figure 15 and Figure 17 , Figure 15 a structural diagram of another semiconductor device provided according to some embodiments, Figure 17 is Figure 15 another AA direction view of the functional layer.

[0104] The semiconductor device 100 includes a substrate 101, a functional layer 103, and a drift layer 104. The semiconductor device 100 can include a first region Q1 and a second region Q2 surrounding the first region Q1.

[0105] The functional layer 103 is disposed on one side of the substrate 101. The functional layer 103 includes a first sub-functional layer 103a, a second sub-functional layer 103b, and a third sub-functional layer 103c. The first sub-functional layer 103a is disposed in the second region Q2, the second sub-functional layer 103b is disposed in the first region Q1, and the doping concentration of the second sub-functional layer 103b is greater than that of the first sub-functional layer 103a. The third sub-functional layer 103c is disposed in the first region Q1, and the doping concentration of the third sub-functional layer 103c is less than that of the second sub-functional layer 103b. The functional layer 103 includes, for example, a plurality of second sub-functional layers 103b. Among the plurality of second sub-functional layers 103b, a part of the second sub-functional layers 103b extends along the first direction y, and another part of the second sub-functional layers 103b extends along the second direction x. The part of the second sub-functional layers 103b extending along the first direction y and the other part of the second sub-functional layers 103b extending along the second direction x intersect with each other to form a mesh structure. The third sub-functional layer 103c is located in an opening of the mesh structure. The third sub-functional layer 103c can be, for example, rectangular, circular, or the like.

[0106] Figure 15 The remaining structure of the semiconductor device 100 is substantially the same as that of the semiconductor device 100 shown in Figure 4 , and thus will not be described again.

[0107] In some possible embodiments, referring to Figure 15 and Figure 18 , Figure 15 a structure diagram of another semiconductor device provided according to some embodiments, Figure 18 is Figure 15 a schematic view of the functional layer in AA direction.

[0108] The semiconductor device 100 includes a substrate 101, a functional layer 103, and a drift layer 104. The semiconductor device 100 can include a first region Q1 and a second region Q2 located around the first region Q1.

[0109] The functional layer 103 is disposed on one side of the substrate 101. The functional layer 103 includes a first sub-functional layer 103a, a second sub-functional layer 103b, and a third sub-functional layer 103c. The first sub-functional layer 103a is disposed in the second region Q2, the second sub-functional layer 103b is disposed in the first region Q1, and the doping concentration of the second sub-functional layer 103b is greater than that of the first sub-functional layer 103a. The third sub-functional layer 103c is disposed in the first region Q1, and the doping concentration of the third sub-functional layer 103c is less than that of the second sub-functional layer 103b. The functional layer 103 includes, for example, a plurality of second sub-functional layers 103b. The second sub-functional layers 103b are annular structures, and the plurality of second sub-functional layers 103b are sequentially sleeved and spaced apart. The third sub-functional layer 103c is located between two second sub-functional layers 103b adjacent in the radial direction of the second sub-functional layer 103b.

[0110] In some possible embodiments, the first sub-functional layer 103a, the second sub-functional layer 103b, and the third sub-functional layer 103c can also be annular rings as shown in Figure 19 Figure 19 for example. Figure 15 Another AA direction view of the functional layer.

[0111] In some possible embodiments, the semiconductor device 100 can also be a semiconductor device such as a field effect transistor, as shown in Figure 20 Figure 20 for example.

[0112] The semiconductor device 100 includes a substrate 101, a functional layer 103, and a drift layer 104. The semiconductor device 100 can include a first region Q1 and a second region Q2 located around the first region Q1.

[0113] The functional layer 103 is disposed on one side of the substrate 101. The functional layer 103 includes a first sub-functional layer 103a and a second sub-functional layer 103b. The first sub-functional layer 103a is disposed in the second region Q2, and the second sub-functional layer 103b is disposed in the first region Q1. The doping concentration of the second sub-functional layer 103b is greater than that of the first sub-functional layer 103a.

[0114] ​​The semiconductor device 100 further comprises a source region 302, a gate 303, and a drain. The source region 302 is disposed on the side of the drift layer 104 away from the substrate 101 and in the first region Q1, and at least part of the source region 302 has a doping type different from that of the drift layer 104. The gate 303 is disposed in the first region Q1, and the gate 303 is disposed on the side of the drift layer 104 away from the substrate 101 and connected to part of the source region 302. The semiconductor device 100 further comprises a gate dielectric layer 304 disposed at least between the drift layer 104 and the gate 303. The drain can be disposed on the side of the substrate 101 away from the drift layer 104, or can be part of the substrate 101 and disposed on the side away from the drift layer 104.

[0115] In some possible embodiments, the source region 302 comprises a first sub-source region 302a and a second sub-source region 302b, the first sub-source region 302a and the second sub-source region 302b are arranged along the second direction x, and the second sub-source region 302b is closer to the gate 303 than the first sub-source region 302a. The doping type of the exemplary first sub-source region 302a is different from that of the drift layer 104, and the doping type of the second sub-source region 302b is the same as that of the first sub-source region 302a.

[0116] In some possible embodiments, the semiconductor device 100 further comprises a first doped layer 105 disposed between the source region 302 and the drift layer 104, part of the first doped layer 105 extends towards the gate 303 and contacts the gate dielectric layer 304.

[0117] In some possible embodiments, the semiconductor device 100 further comprises a buffer layer 102 disposed between the substrate 101 and the functional layer 103. The doping type of the buffer layer 102 is the same as that of the functional layer 103, and the buffer layer 102 contacts the functional layer 103.

[0118] In some possible embodiments, the semiconductor device 100 further comprises at least one junction termination structure 106 disposed on the side of the drift layer 104 away from the substrate 101. The junction termination structure 106 is disposed in the second region Q2, and the junction termination structure 106 surrounds the first region Q1.

[0119] In some possible embodiments, the semiconductor device 100 further comprises a passivation layer 203 disposed on the side of the drift layer 104 away from the substrate 101 and in the second region Q2. The passivation layer 203 covers the at least one junction termination structure 106.

[0120] In some possible embodiments, the semiconductor device 100 further comprises a first metal layer 201 and a second metal layer 202. The first metal layer 201 is disposed on the side of the substrate 101 away from the drift layer 104 and in contact with the drain. The second metal layer 202 is disposed on the side of the drift layer 104 away from the substrate 101 and in contact with the first doped layer 105. The gate dielectric layer 304 is further disposed between the gate 303 and the second metal layer 202.

[0121] It should be noted that when the semiconductor device 100 is a field effect transistor, the functional layer 103 can also have a functional layer structure as shown in Figure 15 and Figures 16-18 .

[0122] Based on the above embodiments, the present disclosure further provides a preparation method of a semiconductor device, referring to Figure 21 , Figure 21 a flowchart of a preparation method of a semiconductor device according to some embodiments is shown. The preparation method of the semiconductor device 100 comprises steps S10 to S30.

[0123] In step S10, an initial functional layer 1031 is formed on one side of the substrate 101.

[0124] In step S20, ion implantation is performed on a target region of the initial functional layer 1031 to form a second sub-functional layer 103b, and the region of the initial functional layer 1031 other than the target region forms a first sub-functional layer 103a. For example, the first sub-functional layer 103a surrounds the second sub-functional layer 103b, and the first sub-functional layer 103a and the second sub-functional layer 103b form the functional layer 103.

[0125] In step S30, a drift layer 104 is formed on the side of the functional layer 103 away from the substrate 101.

[0126] The present disclosure further provides a preparation method of a semiconductor device, as shown in Figures 22-27 , Figure 22 a flowchart of another preparation method of a semiconductor device according to some embodiments is shown, Figures 23-27 for Figure 22 a semiconductor structure corresponding to different steps in the preparation method.

[0127] The preparation method of the semiconductor device 100 comprises steps S40 to S70.

[0128] In step S40, a buffer layer 102 is formed on one side of the substrate 101, obtaining a semiconductor structure 500 as shown in Figure 23 .

[0129] In step S50, an initial functional layer 1031 is formed on the side of the buffer layer 102 away from the substrate 101, obtaining a semiconductor structure 500 as shown in Figure 24 .

[0130] In step S60, ion implantation is performed on the target region of the initial functional layer 1031 to form a second sub-functional layer 103b, and the region of the initial functional layer 1031 other than the target region forms a first sub-functional layer 103a, obtaining a semiconductor structure 500 as shown in Figure 26 . For example, the first sub-functional layer 103a surrounds the second sub-functional layer 103b, and the first sub-functional layer 103a and the second sub-functional layer 103b form the functional layer 103.

[0131] In step S70, a drift layer 104 is formed on the side of the functional layer 103 away from the substrate 101, obtaining a semiconductor structure 500 as shown in Figure 27 .

[0132] After step S70, other processes are used to form the semiconductor device 100 as in Figure 4 , Figure 15 or Figure 20 using the semiconductor structure 500.

[0133] In some possible embodiments, step S60 includes step S61 and step S62.

[0134] In step S61, the mask layer 401 and the ion implantation process are used to form the second sub-functional layer 103b in the target region of the initial functional layer 1031, and the first sub-functional layer 103a in the region of the initial functional layer 1031 other than the target region.

[0135] For example, the mask layer 401 is formed on the side away from the substrate 101, and the mask layer 401 is patterned so that the mask layer 401 exposes the target region of the initial functional layer 1031 and covers the remaining regions other than the target region, obtaining a semiconductor structure 500 as shown in Figure 25 . The ion implantation process is used to form the second sub-functional layer 103b in the target region of the initial functional layer 1031, and the first sub-functional layer 103a in the other regions of the initial functional layer 1031 other than the target region, which is covered by the mask layer 401.

[0136] By forming different mask layer 401 patterns, the functional layer 103 can have structures as in Figure 5 , Figure 16 , Figure 17 , Figure 18 or Figure 19 .

[0137] In step S62, the mask layer 401 is removed, and a semiconductor structure 500 as shown in FIG. 5C is obtained. Figure 26

[0138] The above merely provides the specific implementation of the present application, but the protection scope of the present application is not limited thereto, any person skilled in the art can easily think of the changes or replacements within the technical range disclosed by the present application, which should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.​

Claims

1. A semiconductor device, characterized by, The semiconductor device comprises a first region and a second region surrounding the first region, and comprises: a substrate; a functional layer disposed on the substrate; a drift layer disposed on a side of the functional layer away from the substrate, the drift layer having the same doping type as the functional layer; wherein the functional layer comprises a first sub-functional layer and a second sub-functional layer, the first sub-functional layer is disposed in the second region, and the second sub-functional layer is disposed in the first region; the doping concentration of the second sub-functional layer is greater than the doping concentration of the first sub-functional layer; the functional layer further comprises at least one third sub-functional layer disposed in the first region, the doping concentration of the third sub-functional layer is less than the doping concentration of the second sub-functional layer; and the functional layer comprises a plurality of second sub-functional layers, and the third sub-functional layer is disposed between at least two adjacent second sub-functional layers; the semiconductor device further comprises a buffer layer between the substrate and the functional layer, the buffer layer having the same doping type as the functional layer and being in contact with the functional layer.

2. The semiconductor device according to claim 1, wherein The second sub-functional layer and the third sub-functional layer extend along a first direction, and the second sub-functional layer and the third sub-functional layer are alternately arranged along a second direction; The first direction and the second direction are perpendicular to the thickness direction of the substrate, and the first direction and the second direction are perpendicular to each other.

3. The semiconductor device of claim 1, wherein In the plurality of second sub-functional layers, a part of the second sub-functional layers extend along the first direction, and another part of the second sub-functional layers extend along the second direction, and the part of the second sub-functional layers and the another part of the second sub-functional layers intersect to form a mesh structure; The third sub-functional layer is located in an opening of the mesh structure.

4. The semiconductor device of claim 1, wherein The second sub-functional layer is in a ring structure, and a plurality of second sub-functional layers are sequentially and spacedly arranged; The third sub-functional layer is located between two second sub-functional layers adjacent in a radial direction of the second sub-functional layer.

5. The semiconductor device according to any one of Claims 1 to 4, wherein The first sub-functional layer is also disposed in the first region, and the first sub-functional layer is located around the second sub-functional layer.

6. The semiconductor device of any one of claims 1-4, wherein: The doping concentration of the second sub-functional layer is greater than or equal to the doping concentration of the drift layer.

7. The semiconductor device according to any one of Claims 1 to 4, wherein Further comprising: at least one junction termination structure disposed on a side of the drift layer away from the substrate; the junction termination structure is disposed in the second region and surrounds the first region; a passivation layer disposed on a side of the drift layer away from the substrate and located in the second region; The passivation layer covers the at least one junction termination structure.

8. The semiconductor device according to any one of Claims 1-4, wherein Further comprising: a first doped region disposed on a side of the drift layer away from the substrate and located in the first region; The doping type of the first doped region is different from the doping type of the drift layer; a first metal layer disposed on a side of the substrate away from the drift layer; a second metal layer disposed on a side of the first doped region away from the substrate and in contact with the first doped region.

9. The semiconductor device according to any one of Claims 1-4, wherein Further comprising: a source region disposed on a side of the drift layer away from the substrate and located in the first region; a doping type of at least part of the source region is different from a doping type of the drift layer; a gate disposed on the first region, the gate located on a side of the drift layer away from the substrate and connected with part of the source region; a drain disposed on a side of the substrate away from the drift layer.

10. A method of manufacturing a semiconductor device, characterized by, The semiconductor device includes a first region and a second region located around the first region; the preparation method includes: forming an initial functional layer on a side of a substrate; performing ion implantation on a target region of the initial functional layer to form a second sub-functional layer, and a region of the initial functional layer other than the target region forms a first sub-functional layer; the first sub-functional layer surrounds the second sub-functional layer, and the first sub-functional layer and the second sub-functional layer form a functional layer; a doping concentration of the second sub-functional layer is greater than a doping concentration of the first sub-functional layer; the first sub-functional layer is disposed in the second region, and the second sub-functional layer is disposed in the first region; forming a drift layer on a side of the functional layer away from the substrate, and a doping type of the drift layer is the same as a doping type of the functional layer; wherein the functional layer further includes at least one third sub-functional layer disposed in the first region, and a doping concentration of the third sub-functional layer is less than a doping concentration of the second sub-functional layer; the functional layer includes a plurality of the second sub-functional layers, and the third sub-functional layer is disposed between at least two adjacent second sub-functional layers; the semiconductor device further includes a buffer layer located between the substrate and the functional layer, a doping type of the buffer layer is the same as a doping type of the functional layer, and the buffer layer is in contact with the functional layer.

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