Process method for separately forming N-type and P-type metal gates

Abstract

The invention discloses a process method for separately forming an N-type metal gate and a P-type metal gate, which comprises the following steps of: 1, providing a semiconductor substrate on which a P-type metal gate is formed, and sequentially forming a metal hard mask layer, a dielectric covering layer, a BARC layer and photoresist on the semiconductor substrate; and 2, photoetching is carried out, and the photoresist is patterned to form a photoresist pattern, so that the NMOS forming region is opened, and the PMOS forming region is covered. And step 3, etching the BARC layer and the dielectric covering layer in sequence. And 4, sequentially removing the photoresist pattern and the BARC layer. And step 5, etching the metal hard mask layer by taking the dielectric covering layer as a mask so as to remove the metal hard mask layer in the NMOS forming region, and exposing the top surface of the dummy gate structure in the NMOS forming region. And step 6, removing the dummy gate structure. According to the invention, polymer defects and adverse effects on the threshold voltage of an NMOS (N-channel Metal Oxide Semiconductor) can be eliminated in the process of removing the dummy gate structure in the forming region of the N-type metal gate after the P-type metal gate is formed.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly to a process for forming an N-type and P-type metal gate (MG) separately (N / P split). Background Art

[0002] In NMOS and PMOS with metal gates (MG), NMOS uses an N-type metal work function layer (NWF) and PMOS uses a P-type metal work function layer (PWF). In order to achieve better independent control of NMOS and PMOS, the N / Psplit process is used, which is a process method in which N-type and P-type metal gates are formed separately. Unlike the metal gates of NMOS and PMOS, which share some film layers, in the N / Psplit process, the metal gate of PMOS, also known as P-type metal gate (PMG), and the metal gate of NMOS, also known as N-type metal gate (NMG), are formed completely independently. Usually, PMG is formed first, followed by NMG.

[0003] However, a problem with the NMG fabrication process is that polymer defects are generated after the etch / wet clean process of the NMOS dummy polysilicon removal (NDPR). This defect not only shifts the NMOS threshold voltage (VT) but also causes large fluctuations.

[0004] In existing improved processes, adjusting parameters such as the thickness (THK) of the well implant (IMP) / lightly doped region (LDD) IMP / NMG cannot effectively solve the problem of large VT shift and varation of NMOS. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a process method for separately forming N-type and P-type metal gates, which can eliminate polymer defects in the process of removing the pseudo gate structure in the formation area of the N-type metal gate after forming the P-type metal gate, and thereby eliminate the adverse effects of polymer defects on the threshold voltage of NMOS.

[0006] To solve the above technical problems, the present invention provides a process for forming N-type and P-type metal gates separately, comprising the following steps:

[0007] Step 1: Provide a semiconductor substrate with a P-type metal gate, form a dummy gate structure in the N-type metal gate formation area, and sequentially form a metal hard mask layer, a dielectric cover layer, a BARC layer and a photoresist on the semiconductor substrate.

[0008] Step 2: Perform photolithography to pattern the photoresist to form a photoresist pattern, wherein the photoresist pattern opens the NMOS formation area and covers the PMOS formation area.

[0009] Step three: using the photoresist pattern as a mask, sequentially etching the BARC layer and the dielectric cover layer.

[0010] Step 4: remove the photoresist pattern and the BARC layer in sequence.

[0011] Step 5: Using the dielectric cover layer as a mask, the metal hard mask layer is etched to remove the metal hard mask layer in the NMOS formation region, exposing the top surface of the dummy gate structure in the NMOS formation region.

[0012] Step six: removing the dummy gate structure.

[0013] A further improvement is that the semiconductor substrate includes a silicon substrate.

[0014] A further improvement is that a zeroth interlayer film is formed on the semiconductor substrate, and the top surface of the zeroth interlayer film is flush with the top surface of the dummy gate structure and the top surface of the P-type metal gate.

[0015] A further improvement is that the material of the metal hard mask layer includes TiN.

[0016] A further improvement is that the material of the dielectric cover layer includes silicon dioxide.

[0017] A further improvement is that the dummy gate structure includes a first gate dielectric layer and a first gate material layer, and the material of the first gate material layer is polysilicon or amorphous silicon.

[0018] Further improvements include:

[0019] Step seven: forming an N-type metal gate in the region where the dummy gate structure is removed.

[0020] A further improvement is that, in step 6, both the first gate material layer and the first gate dielectric layer are removed; or, in step 6, the first gate material layer is removed, and the first gate dielectric layer is retained, and the first gate dielectric layer serves as the gate dielectric layer of the N-type metal gate;

[0021] A further improvement is that, in step six, the etching process for removing the dummy gate structure is dry etching or wet etching.

[0022] After the etching process of the dummy gate structure is completed, wet cleaning is further performed to remove etching byproducts.

[0023] A further improvement is that a contact etch stop layer is also formed on the semiconductor substrate, and the contact etch stop layer is located on the side of the dummy gate structure, the side of the P-type metal gate, and the surface of the semiconductor substrate outside the dummy gate structure and the P-type metal gate.

[0024] A further improvement is that the thickness of the metal hard mask layer is several tens of

[0025] A further improvement is that the thickness of the dielectric covering layer is several tens of

[0026] A further improvement is that the thickness of the BARC layer is several hundred

[0027] Compared with the prior art in which a BARC layer and a photoresist are directly coated on the metal hard mask layer after forming a P-type metal gate, and the metal hard mask layer is finally patterned and etched using the patterned photoresist and BARC layer as a mask, the present invention forms a dielectric cover layer on the metal hard mask layer before coating the BARC layer. The BARC layer and the photoresist are removed after patterning the dielectric cover layer, and then the metal hard mask layer is patterned and etched using the dielectric cover layer as a mask. Since the photoresist and the BARC layer are removed when etching the metal hard mask layer, a large amount of polymers that cannot be eliminated when etching the metal hard mask layer with the photoresist and the BARC layer can be eliminated. Therefore, after removing the dummy gate structure, the polymer defects can be eliminated, thereby eliminating the adverse effects of the polymer defects on the threshold voltage of the NMOS. Therefore, compared with the NMOS formed by the prior art, the threshold voltage of the NMOS of the present invention does not produce a drift region and has better threshold voltage uniformity. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0029] Figure 1A-1E It is a schematic diagram of the device structure in each step of the existing process method for forming N-type and P-type metal gates separately;

[0030] Figure 2 This is a flow chart of a process method for separately forming N-type and P-type metal gates according to an embodiment of the present invention;

[0031] Figures 3A-3F Schematic diagram of the device structure in each step of the process method for separately forming N-type and P-type metal gates according to an embodiment of the present invention;

[0032] Figure 4A This is a photo of the existing process method of forming N-type and P-type metal gates separately after removing the dummy gate structure;

[0033] Figure 4B This is a photo of the process method for forming N-type and P-type metal gates separately according to an embodiment of the present invention after removing the dummy gate structure;

[0034] Figure 5 This is a statistical diagram of the threshold voltage of NMOS formed by the existing process method of forming N-type and P-type metal gates separately and the embodiment of the present invention. DETAILED DESCRIPTION

[0035] The process method for separately forming the N-type and P-type metal gates 205 according to the embodiment of the present invention is formed based on an in-depth analysis of the technical problems existing in the existing process method for separately forming the N-type and P-type metal gates 205. Before describing in detail the process method for separately forming the N-type and P-type metal gates 205 according to the embodiment of the present invention, the existing process method for separately forming the N-type and P-type metal gates 205 is first described as follows:

[0036] like Figures 1A to 1E FIG. 1 is a schematic diagram of a device structure in each step of a conventional process method for forming an N-type and P-type metal gate separately. The conventional process method for forming an N-type and P-type metal gate separately includes the following steps:

[0037] like Figure 1A As shown, a semiconductor substrate 101 is provided with a P-type metal gate 105, a dummy gate structure 102 is formed in the N-type metal gate formation area, and a TiN layer 106, a BARC layer 107 and a photoresist 108 are sequentially formed on the semiconductor substrate 101 as a metal hard mask layer.

[0038] A zeroth interlayer film 104 is formed on the semiconductor substrate 101 . The top surface of the zeroth interlayer film 104 is flush with the top surface of the dummy gate structure 102 and the top surface of the P-type metal gate 105 .

[0039] The dummy gate structure 102 includes a first gate dielectric layer and a first gate material layer. The material of the first gate material layer is polysilicon or amorphous silicon.

[0040] A contact etch stop layer 103 is also formed on the semiconductor substrate 101 . The contact etch stop layer 103 is located on the side of the dummy gate structure 102 , the side of the P-type metal gate 105 , and the surface of the semiconductor substrate 101 outside the dummy gate structure 102 and the P-type metal gate 105 .

[0041] Figure 1A In the figure, the P-type metal gate 105 is directly represented by a dotted frame, and the multi-layer structure inside the dotted frame can be configured as needed. The P-type metal gate 105 includes: a PMOS gate dielectric layer, a P-type metal work function layer, and a gate conductive material layer.

[0042] like Figure 1A As shown, photolithography is performed to pattern the photoresist 108 to form a photoresist 108 pattern, and the photoresist 108 pattern opens the NMOS formation region 101b and covers the PMOS formation region 101a.

[0043] Figure 1A In FIG, the left side of the dotted line AA is the NMOS formation region 101 b , and the right side is the PMOS formation region 101 a .

[0044] like Figure 1A As shown, the BARC layer 107 is etched using the photoresist 108 pattern as a mask.

[0045] like Figure 1B As shown, the TiN layer 106 is etched to remove the TiN layer 106 in the NMOS formation region 101 b , and the top surface of the dummy gate structure 102 in the NMOS formation region 101 b is exposed.

[0046] like Figure 1C As shown, the photoresist 108 pattern and the BARC layer 107 are removed in sequence. Figure 1B As shown, during the etching process of the TiN layer 106 , a heavier polymer 109 is generated. Figure 1A Polymer 109 is also produced. Figure 1C Polymer 109 will also be produced, which will increase the amount of polymer 109.

[0047] like Figure 1D As shown, etching is performed to remove the dummy gate structure 102 , and the removed region of the dummy gate structure 102 forms a gate trench 110 .

[0048] The etching process for removing the dummy gate structure 102 is dry etching or wet etching.

[0049] like Figure 1E As shown, wet cleaning is performed to remove etching byproducts. Figure 1E and Figure 1D As shown, Figure 1E The amount of polymer 109 in the surface is reduced to a certain extent, but it cannot be completely removed by wet cleaning. This is because heavier polymer 109 has accumulated in the past, especially Figure 1B The etching process of the TiN layer 106 is shown to produce a heavier polymer 109 .

[0050] Subsequently, an N-type metal gate is formed in the gate trench 110 .

[0051] The presence of polymer 109 will affect the threshold voltage, so the threshold voltage of NMOS will be offset; this is because: the VT of NMOS, that is, the threshold voltage, is adjusted by diffusing TiAl as the N-type metal work function layer of NMOS and Al in the gate conductive material layer into the TiN of the bottom barrier layer (BBM). Due to the presence of polymer 109, Al cannot diffuse effectively, so the VT of NMOS remains high.

[0052] At the same time, the amount of the polymer 109 remaining in the gate trench 110 in different regions of the same semiconductor substrate 101 is not the same, so the threshold voltage of the NMOS may fluctuate greatly.

[0053] like Figure 2 FIG. 1 is a flow chart of a process for forming N-type and P-type metal gates separately according to an embodiment of the present invention; Figures 3A to 3F FIG. 1 is a schematic diagram of a device structure in each step of a process method for forming an N-type and P-type metal gate separately according to an embodiment of the present invention. The process method for forming an N-type and P-type metal gate separately according to an embodiment of the present invention includes the following steps:

[0054] Step 1: Figure 3A As shown, a semiconductor substrate 201 with a P-type metal gate 205 is provided, a dummy gate structure 202 is formed in the formation area of the N-type metal gate, and a metal hard mask layer 206, a dielectric covering layer 207, a BARC layer 208 and a photoresist 209 are sequentially formed on the semiconductor substrate 201.

[0055] In the embodiment of the present invention, the semiconductor substrate 201 includes a silicon substrate.

[0056] A zeroth interlayer film 204 is formed on the semiconductor substrate 201 . The top surface of the zeroth interlayer film 204 is flush with the top surface of the dummy gate structure 202 and the top surface of the P-type metal gate 205 .

[0057] In this embodiment of the present invention, the material of the metal hard mask layer 206 includes TiN. The material of the dielectric cover layer 207 includes silicon dioxide. In other embodiments, the materials of the metal hard mask layer 206 and the dielectric cover layer 207 can be set as needed. The material of the dielectric cover layer 207 only needs to ensure that it can serve as a mask for the metal hard mask layer 206.

[0058] The dummy gate structure 202 includes a first gate dielectric layer and a first gate material layer. The material of the first gate material layer is polysilicon or amorphous silicon.

[0059] In an embodiment of the present invention, a contact etch stop layer 203 is further formed on the semiconductor substrate 201, and the contact etch stop layer 203 is located on the side of the dummy gate structure 202, the side of the P-type metal gate 205, and the surface of the semiconductor substrate 201 outside the dummy gate structure 202 and the P-type metal gate 205.

[0060] In some embodiments, the thickness of the metal hard mask layer 206 is several tens of like

[0061] The thickness of the dielectric cover layer 207 is several tens of like

[0062] The thickness of the BARC layer 208 is several hundred like

[0063] Figure 3A In the figure, the P-type metal gate 205 is directly represented by a dotted frame, and the multi-layer structure inside the dotted frame can be set as needed. The P-type metal gate 205 includes: a PMOS gate dielectric layer, a P-type metal work function layer, and a gate conductive material layer. In some embodiments, the P-type metal work function layer is TiN, and the material of the gate conductive material layer includes Al. An interface layer is also formed between the PMOS gate dielectric layer and the semiconductor substrate 201; a bottom barrier layer (BBM) is formed between the PMOS gate dielectric layer and the P-type metal work function layer, and the bottom barrier layer is generally a stacked layer of TiN and TaN; a top barrier layer (TBM) is formed between the P-type metal work function layer and the gate conductive material layer, and the material of the top barrier layer is generally a stacked layer of TiN and Ti. The material of the PMOS gate dielectric layer includes a high dielectric constant (HK) material, and the material of the interface layer includes silicon dioxide.

[0064] Step 2: Figure 3A As shown, photolithography is performed to pattern the photoresist 209 to form a photoresist 209 pattern, and the photoresist 209 pattern opens the NMOS formation region 201b and covers the PMOS formation region 201a.

[0065] Figure 3A In FIG, the left side of the dotted line AA is the NMOS formation region 201 b , and the right side is the PMOS formation region 201 a .

[0066] Step 3: Figure 3A As shown, the BARC layer 208 is etched using the photoresist 209 pattern as a mask.

[0067] like Figure 3B As shown, the dielectric cover layer 207 is etched using the pattern of the photoresist 209 as a mask. In this way, the pattern of the photoresist 209 is transferred downward into the dielectric cover layer 207.

[0068] Step 4: Figure 3C As shown, the photoresist 209 pattern and the BARC layer 208 are removed in sequence.

[0069] Step 5: Figure 3D As shown, the metal hard mask layer 206 is etched using the dielectric cover layer 207 as a mask to remove the metal hard mask layer 206 in the NMOS formation region 201b, exposing the top surface of the dummy gate structure 202 in the NMOS formation region 201b.

[0070] Depend on Figure 3D As shown, since the photoresist 209 and the BARC layer 208 are no longer present on top of the metal hard mask layer 206 during etching, the etching process does not result in significant polymer buildup. This means that the present embodiment can significantly reduce polymer buildup during the etching of the metal hard mask layer 206. Even if a small amount of polymer is present, it can be removed during the subsequent wet cleaning step (step 6). Therefore, the present embodiment solves the technical problem of existing methods where a large amount of polymer is generated and cannot be completely removed during the subsequent cleaning process.

[0071] Step 6: Figure 3E As shown, the dummy gate structure 202 is removed. The removed region of the dummy gate structure 202 forms a gate trench 210.

[0072] In the embodiment of the present invention, the etching process for removing the dummy gate structure 202 is dry etching or wet etching.

[0073] like Figure 3F As shown, after the etching process of the dummy gate structure 202 is completed, wet cleaning is further performed to remove etching byproducts.

[0074] In some embodiments, both the first gate material layer and the first gate dielectric layer are removed; in this case, the gate dielectric layer of the N-type metal gate needs to be formed first in the subsequent process of forming the N-type metal gate.

[0075] In some embodiments, the first gate material layer may be removed, and the first gate dielectric layer may be retained, and the first gate dielectric layer may serve as the gate dielectric layer of the N-type metal gate.

[0076] The follow-up also includes:

[0077] Step seven: forming an N-type metal gate in the gate trench 210 where the dummy gate structure 202 is removed.

[0078] The N-type metal gate can be formed by using existing conventional processes and will not be described in detail here. Generally, the N-type metal gate includes an NMOS gate dielectric layer, an N-type metal work function layer, and a gate conductive material layer. In some embodiments, the N-type metal work function layer is TiAl, and the material of the gate conductive material layer includes Al. An interface layer is also formed between the NMOS gate dielectric layer and the semiconductor substrate 201; a bottom barrier layer is formed between the NMOS gate dielectric layer and the N-type metal work function layer, and the bottom barrier layer is usually a stacked layer of TiN and TaN; a top barrier layer is formed between the N-type metal work function layer and the gate conductive material layer, and the material of the top barrier layer is usually a stacked layer of TiN and Ti. In some embodiments, the material of the NMOS gate dielectric layer includes a high dielectric constant (HK) material. In this case, the first gate dielectric layer is usually removed in step six. In some embodiments, the material of the gate dielectric layer of the NMOS can be silicon dioxide. For example, the gate dielectric layer of the NMOS of the output-output (IO) device can directly use silicon dioxide. In this case, the first gate dielectric layer can be retained in step six and used as the gate dielectric layer of the NMOS.

[0079] In some embodiments, the material of the interface layer includes silicon dioxide.

[0080] Compared with the prior art, in which a BARC layer and a photoresist are directly coated on the metal hard mask layer after forming a P-type metal gate, and the metal hard mask layer is finally patterned and etched using the patterned photoresist and BARC layer as a mask, the embodiment of the present invention forms a dielectric cover layer 207 on the metal hard mask layer 206 before coating the BARC layer 208. The BARC layer 208 and the photoresist 209 are removed after patterning the dielectric cover layer 207, and then the metal hard mask layer is patterned and etched using the dielectric cover layer 207 as a mask. Since the photoresist 209 and the BARC layer 208 are removed when the metal hard mask layer is etched, a large amount of polymers that cannot be eliminated when the metal hard mask layer is etched with the photoresist 209 and the BARC layer 208 can be eliminated, so that the polymer defects can be eliminated after the pseudo gate structure 202 is removed, thereby eliminating the adverse effects of the polymer defects on the threshold voltage of the NMOS. Therefore, compared with the NMOS formed by the existing method, the threshold voltage of the NMOS in the embodiment of the present invention does not produce a drift region and the threshold voltage uniformity is better.

[0081] like Figure 4A, is a photograph of the process method of forming the N-type and P-type metal gates separately in the prior art after the dummy gate structure is removed; it can be seen that there is residual polymer 109a.

[0082] like Figure 4B FIG. 1 is a photograph of the process method for forming N-type and P-type metal gates separately according to an embodiment of the present invention after removing the dummy gate structure; it can be seen that no polymer 109a remains.

[0083] like Figure 5 , which is a statistical graph of the threshold voltages of NMOSs formed using the conventional process method of forming N-type and P-type metal gates separately and in accordance with an embodiment of the present invention. The values in dashed circle 301 are within the target value range of the threshold voltage; the values in dashed circle 302 are the test values of the threshold voltages of NMOSs formed using the conventional process method of forming N-type and P-type metal gates separately, collected on two wafers. It can be seen that the threshold voltages in dashed circle 302 are all greater than the target values in dashed circle 301, and the threshold voltage fluctuation range in dashed circle 302 is relatively large. The values in dashed circle 303 are the test values of the threshold voltages of NMOSs formed using the process method of forming N-type and P-type metal gates separately in accordance with an embodiment of the present invention. It can be seen that the threshold voltages in dashed circle 303 are within the target value range of dashed circle 301.

[0084] The present invention has been described in detail above by means of specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principles of the present invention, those skilled in the art may make many variations and improvements, which should also be considered as the scope of protection of the present invention.

Claims

1. A process for forming N-type and P-type metal gates separately, characterized in that: The steps include: Step 1: providing a semiconductor substrate with a P-type metal gate formed thereon, forming a dummy gate structure in the N-type metal gate formation region, and sequentially forming a metal hard mask layer, a dielectric cap layer, a BARC layer, and a photoresist on the semiconductor substrate; Step 2: Performing photolithography to pattern the photoresist to form a photoresist pattern, wherein the photoresist pattern opens the NMOS formation area and covers the PMOS formation area; Step 3: using the photoresist pattern as a mask to sequentially etch the BARC layer and the dielectric cover layer; Step 4: removing the photoresist pattern and the BARC layer in sequence; Step 5: etching the metal hard mask layer using the dielectric cover layer as a mask to remove the metal hard mask layer in the NMOS formation region, exposing the top surface of the dummy gate structure in the NMOS formation region; Step six: removing the dummy gate structure.

2. The process for forming N-type and P-type metal gates separately as claimed in claim 1, wherein: The semiconductor substrate includes a silicon substrate.

3. The process for forming N-type and P-type metal gates separately as claimed in claim 1, wherein: A zeroth interlayer film is formed on the semiconductor substrate, and a top surface of the zeroth interlayer film is flush with a top surface of the dummy gate structure and a top surface of the P-type metal gate.

4. The process for forming N-type and P-type metal gates separately as claimed in claim 1, wherein: The material of the metal hard mask layer includes TiN.

5. The process for forming N-type and P-type metal gates separately as claimed in claim 4, wherein: The material of the dielectric cover layer includes silicon dioxide.

6. The process for forming N-type and P-type metal gates separately as claimed in claim 1, wherein: The dummy gate structure includes a first gate dielectric layer and a first gate material layer, and the material of the first gate material layer is polysilicon or amorphous silicon.

7. The process for forming N-type and P-type metal gates separately as claimed in claim 6, wherein: The follow-up also includes: Step seven: forming an N-type metal gate in the region where the dummy gate structure is removed.

8. The process for forming N-type and P-type metal gates separately as claimed in claim 7, wherein: In step six, both the first gate material layer and the first gate dielectric layer are removed; or, in step six, the first gate material layer is removed, and the first gate dielectric layer is retained, and the first gate dielectric layer serves as the gate dielectric layer of the N-type metal gate.

9. The process for forming N-type and P-type metal gates separately as claimed in claim 1, wherein: In step six, the etching process for removing the dummy gate structure is dry etching or wet etching; After the etching process of the dummy gate structure is completed, wet cleaning is further performed to remove etching byproducts.

10. The process for forming N-type and P-type metal gates separately as claimed in claim 3, wherein: A contact etch stop layer is also formed on the semiconductor substrate. The contact etch stop layer is located on the side of the dummy gate structure, the side of the P-type metal gate, and the surface of the semiconductor substrate outside the dummy gate structure and the P-type metal gate.

11. The process for forming N-type and P-type metal gates separately as claimed in claim 5, wherein: The thickness of the metal hard mask layer is several tens 12. The process for forming N-type and P-type metal gates separately as claimed in claim 11, wherein: The thickness of the dielectric covering layer is several tens 13. The process for forming N-type and P-type metal gates separately as claimed in claim 11, wherein: The thickness of the BARC layer is several hundred

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