Memory device and method of manufacturing the same
By forming shallow trench isolation areas and high dielectric constant dielectric layers during the manufacturing process of the memory device, and forming doped areas after the annealing process, the problem of gate-related leakage current in the memory device is solved, and a more stable threshold voltage and a reduced leakage current are achieved.
Patent Information
- Application Number
- CN202510609170.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2025-02-12
- Filing Date
- 2025-05-13
- Publication Date
- 2025-08-08
AI Technical Summary
As the critical size of semiconductor components decreases, gate-related device leakage current problems in memory devices frequently occur, affecting device performance.
During the manufacturing of the memory device, by forming shallow trench isolation areas on the substrate, an epitaxial layer and a high dielectric constant dielectric layer are formed, and doped regions are formed after the annealing process, and a sacrificial layer is used to block the diffusion of metal elements and reduce leakage current.
It effectively reduces the threshold voltage and leakage current of the memory device, and improves the stability and performance of the device.
Smart Images
Figure CN120456608A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to memory devices and methods of manufacturing the same. Background Art
[0002] The critical dimension (CD) of semiconductor components in memory devices has decreased with advancements in semiconductor technology, thereby increasing the device integration density within memory devices. However, as the CD of components decreases, semiconductor process technology also faces numerous challenges. For example, the reduction in semiconductor components in memory devices may result in more frequent device leakage current associated with the memory device's gate. Summary of the Invention
[0003] According to some embodiments of the present disclosure, a method for manufacturing a memory device includes the following steps. A shallow trench isolation region is formed in a substrate to divide the substrate region into a first substrate region and a second substrate region. An epitaxial layer is formed on the first substrate region, and the second substrate region is exposed. A high-k dielectric layer is formed on the epitaxial layer and the second substrate region. A first sacrificial layer is formed on a first portion of the high-k dielectric layer located above the first substrate region, and a second portion of the high-k dielectric layer located above the second substrate region is exposed. A metal layer is formed on the first sacrificial layer and the high-k dielectric layer. An annealing process is performed to form a doped region in the high-k dielectric layer located above the second substrate region. The metal layer and the first sacrificial layer are removed. A gate electrode layer is formed on the high-k dielectric layer, and a gate cap layer is formed on the gate electrode layer. The gate cap layer, the gate electrode layer, and the high-k dielectric layer are patterned into a first gate structure located above the epitaxial layer and a second gate structure located above the doped region.
[0004] In some embodiments, the method further includes forming a second sacrificial layer covering the metal layer, forming a covering layer covering the second sacrificial layer, performing an annealing process to drive metal elements of the metal layer into the high dielectric constant dielectric layer to form a doped region, and removing the covering layer and the second sacrificial layer after the annealing process.
[0005] In some embodiments, the first sacrificial layer and the second sacrificial layer are formed of the same material.
[0006] In some embodiments, after the annealing process, the metal elements of the metal layer stop at the bottom of the high-k dielectric layer.
[0007] In some embodiments, after forming the first sacrificial layer over the first substrate region, a plurality of sidewalls of the first sacrificial layer are flush with a plurality of sidewalls of the epitaxial layer.
[0008] In some embodiments, a sidewall of the doped region is flush with a sidewall of the first sacrificial layer.
[0009] In some embodiments, forming the epitaxial layer on the first substrate region includes epitaxially growing a silicon-containing layer on the first substrate region using a SiH 4 -based precursor, and doping the silicon-containing layer with germanium to form the epitaxial layer.
[0010] In some embodiments, the high-k dielectric layer covers a top surface of the epitaxial layer, sidewalls of the epitaxial layer, and a top surface of the second substrate region, and the high-k dielectric layer has a flat top surface.
[0011] In some embodiments, after forming the epitaxial layer on the first substrate region, the epitaxial layer extends onto a top surface of the shallow trench isolation region.
[0012] In some embodiments, the metal layer and the first sacrificial layer are removed using an etching process, and the etching process stops at a top surface of the high-k dielectric layer.
[0013] In some embodiments, the method further includes patterning the epitaxial layer such that sidewalls of the epitaxial layer are flush with sidewalls of the first gate structure, and patterning the doped region such that sidewalls of the doped region are flush with sidewalls of the second gate structure.
[0014] In some embodiments, after the annealing process, the doped region is located between a bottom surface of the high-k dielectric layer above the second substrate region and a middle position of the high-k dielectric layer.
[0015] According to some embodiments of the present disclosure, a memory device includes a first transistor having a first conductivity type and a second transistor having a second conductivity type, the second conductivity type being different from the first conductivity type. The first transistor includes a first substrate region, an epitaxial layer located above the first substrate region, and a first high-k metal gate structure located on the epitaxial layer. The second transistor includes a second substrate region, a doped region located above the second substrate region, and a second high-k metal gate structure located on the doped region. The doped region includes a high-k dielectric material doped with a metal element. The first high-k metal gate structure includes a high-k dielectric layer having a high-k dielectric material, a gate electrode layer located on the high-k dielectric layer, and a gate cap layer located on the gate electrode layer.
[0016] In some embodiments, the concentration of the metal element increases from the bottom surface of the doped region toward the top surface of the doped region.
[0017] In some embodiments, the highest concentration of the metal element in the doped region is located at the top surface of the doped region.
[0018] In some embodiments, the thickness of the doped region is the same as the thickness of the epitaxial layer.
[0019] In some embodiments, the first transistor is a p-type transistor and the second transistor is an n-type transistor.
[0020] In some embodiments, the epitaxial layer is a SiGe layer, and the doped region is a high-k dielectric material doped with lanthanum.
[0021] In some embodiments, the first high-k metal gate structure is separated from the second high-k metal gate structure, the epitaxial layer is separated from the doped region, and a shallow trench isolation region is interposed between the first substrate region and the second substrate region.
[0022] In some embodiments, the epitaxial layer serves as a channel region between the first high-k metal gate structure and the first substrate region.
[0023] According to the above-described embodiments, a method for manufacturing a memory device includes forming a first sacrificial layer for a first transistor before forming a high-k metal gate structure to block diffusion of metal elements in a second transistor into the channel region of the first transistor. Consequently, the epitaxial layer in the first transistor and the doped region in the second transistor can reduce the threshold voltage of the memory device, and the high-k metal gate structure reduces leakage current in the memory device. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] Various aspects of the present disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.
[0025] Figure 1 A flowchart is shown of an example method for manufacturing a memory device according to some embodiments of the present disclosure.
[0026] Figures 2 to 9 Schematic cross-sectional views of a memory device at various fabrication stages are shown according to some embodiments of the present disclosure. DETAILED DESCRIPTION
[0027] In order to realize the different features of the mentioned subject matter, the following disclosure provides many different embodiments or examples. Specific examples of components, configurations, etc. are described below to simplify the present disclosure. Of course, these are merely examples and are not restrictive. For example, in the following description, forming a first feature on or above a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature is formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not itself represent the relationship between the various embodiments and / or configurations discussed.
[0028] Furthermore, spatially relative terms, such as "below," "beneath," "lower," "above," "upper," and the like, may be used herein to describe one element or feature in relation to another element or feature as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
[0029] According to some embodiments of the present disclosure, Figure 1 A flow chart of an exemplary method 100 for manufacturing a memory device is shown. Figure 1 and Figures 2 to 9 To explain, Figures 2 to 9 Schematic cross-sectional views of a memory device 200 at various stages of fabrication are shown according to some embodiments of the present disclosure. Method 100 is merely an example, and in other embodiments, additional steps may be added before, during, or after method 100, and some of the steps described may be moved, replaced, or deleted. In other embodiments, additional features may be added to the illustrated memory device 200, and some of the features described may be replaced, modified, or deleted.
[0030] At block 110 , the method 100 includes forming a shallow trench isolation (STI) region in a substrate to separate the substrate region into a first substrate region and a second substrate region. Figure 2In one embodiment of block 110, a substrate 210 is provided for forming the memory device 200. In some embodiments, the substrate 210 may be a semiconductor substrate, such as a silicon (Si) substrate. The substrate 210 may include a single crystalline semiconductor material, such as, but not limited to, Si, Ge, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP. Alternatively, the substrate 210 may include a compound semiconductor and / or an alloy semiconductor.
[0031] A shallow trench isolation region 220 is formed in the substrate 210, wherein the shallow trench isolation region 220 extends from the top surface of the substrate 210 toward the bottom surface of the substrate 210. The bottom surface of the shallow trench isolation region 220 may be as shown in FIG. Figure 2 The shallow trench isolation region 220 is shown as stopping in the substrate 210, or in some other embodiments, may pass through the substrate 210. The shallow trench isolation region 220 divides the substrate 210 into a first substrate region 212 and a second substrate region 214. In other words, the shallow trench isolation region 220 is interposed between the first substrate region 212 and the second substrate region 214. The first substrate region 212 and the second substrate region 214 will serve as substrates for two transistors of different conductivity types. For example, the first substrate region 212 may be the substrate for an n-type metal-oxide-semiconductor (NMOS) transistor of the memory device 200, while the second substrate region 214 may be the substrate for a p-type metal-oxide-semiconductor (PMOS) transistor of the memory device 200.
[0032] In some embodiments, the shallow trench isolation region 220 may be formed of an oxide, such as SiO x The shallow trench isolation region 220 may be formed by etching trenches in the substrate 210 and filling the trenches with an oxide material. Figure 2 The shallow trench isolation region 220 in the figure is depicted as a trapezoid having a larger top width at the top surface of the substrate 210 and a smaller bottom width below the top surface of the substrate 210. In other embodiments, the shallow trench isolation region 220 may have other shapes. After forming the shallow trench isolation region 220, a planarization process, such as chemical mechanical polishing (CMP), may be performed on the substrate 210 and the shallow trench isolation region 220 before forming other components on the substrate 210.
[0033] At block 120, the method 100 includes forming an epitaxial layer on the first substrate region and exposing the second substrate region. Figure 2In one embodiment of block 120, an epitaxial layer 230 is formed on the first substrate region 212, but the epitaxial layer 230 is not formed on the second substrate region 214. Therefore, the epitaxial layer 230 covers the top surface of the first substrate region 212, while the epitaxial layer 230 exposes the second substrate region 214. The epitaxial layer 230 may extend to the top surface of the shallow trench isolation region 220, or the sidewalls of the epitaxial layer 230 may be located on the top surface of the first substrate region 212. The epitaxial layer 230 may serve as a channel region between a subsequently formed high-k dielectric metal gate and the first substrate region 212, wherein the epitaxial layer 230 reduces the threshold voltage (V t ).
[0034] In some embodiments where the first substrate region 212 is used for a p-type transistor, the epitaxial layer 230 can be formed of a crystalline semiconductor material, such as, but not limited to, SiGe. For example, a silicon-containing layer can be grown on the first substrate region 212 using an epitaxial or deposition process using a SiH4-based gas as a precursor, such as chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), atomic layer deposition (ALD), other suitable deposition processes, or combinations thereof. Subsequently, the silicon-containing region is doped with germanium (Ge) to form the epitaxial layer 230. During the deposition and / or doping of the epitaxial layer 230, a mask layer (not shown) can be used to cover the second substrate region 214. Because the epitaxial layer 230 is formed using a SiH4-based deposition process, the formed epitaxial layer 230 can have a low surface roughness, thereby reducing defects in the memory device 200.
[0035] At block 130, the method 100 includes forming a high-k dielectric layer on the epitaxial layer and the second substrate region. Figure 3 In one embodiment of block 130, a high-k dielectric layer 240 is formed on the epitaxial layer 230 and the second substrate region 214. The thickness of the high-k dielectric layer 240 along the z-axis is sufficient to cover the top surface of the epitaxial layer 230, the sidewalls of the epitaxial layer 230 proximate to the second substrate region 214, and the top surface of the second substrate region 214. After forming the high-k dielectric layer 240, a planarization process (e.g., chemical mechanical polishing) may be performed on the high-k dielectric layer 240 to provide a planar top surface of the high-k dielectric layer 240.
[0036] In some embodiments, the high-k dielectric layer 240 may be formed of a dielectric material having a higher k-value than SiO 2 , such as HfO 2 , HfSiO 2 , or the like. x , TiO2, ZrO2, other dielectric materials with a dielectric constant greater than 3.9, or combinations thereof. The high-k dielectric layer 240 may be formed by chemical vapor deposition, atomic layer deposition, physical vapor deposition (PVD), or other suitable deposition processes.
[0037] At block 140 , the method 100 includes forming a first sacrificial layer on the high-k dielectric layer located above the first substrate region and exposing the high-k dielectric layer located above the second substrate region. Figure 4 In one embodiment of block 140, a first sacrificial layer 250 is formed over the first substrate region 212, but is not formed over the second substrate region 214. Thus, the first sacrificial layer 250 covers a first portion of the top surface of the high-k dielectric layer 240 over the first substrate region 212, while exposing a second portion of the top surface of the high-k dielectric layer 240 over the second substrate region 214. The first sacrificial layer 250 may extend to the top surface of the high-k dielectric layer 240 over the shallow trench isolation region 220. Sidewalls of the first sacrificial layer 250 may be flush with sidewalls of the epitaxial layer 230.
[0038] In some embodiments, the first sacrificial layer 250 may be formed of a hard mask material, wherein the hard mask material can prevent metal elements from penetrating into the first sacrificial layer 250 during subsequent processes. For example, the first sacrificial layer 250 may be formed of a nitride, such as titanium nitride (TiN) or silicon nitride (SiN). The first sacrificial layer 250 may be formed by performing a deposition process using the hard mask material on the entire top surface of the high-k dielectric layer 240, and removing a portion of the hard mask material located above the second substrate region 214 through a wet etching process.
[0039] At block 150, the method 100 includes forming a metal layer on the first sacrificial layer and the high-k dielectric layer, forming a second sacrificial layer on the metal layer, and forming a capping layer on the second sacrificial layer. Figure 5In one embodiment of block 150 , a metal layer 260 is formed over the first substrate region 212 and the second substrate region 214 . The thickness of the metal layer 260 along the z-axis is sufficient to cover the top surface of the first sacrificial layer 250 , the sidewalls of the first sacrificial layer 250 , and the top surface of the high-k dielectric layer 240 located over the second substrate region 214 . In some embodiments, the metal layer 260 can be formed of a metal element that will serve as the second channel region over the second substrate region 214 . For example, when the second substrate region 214 will function as an n-type transistor, the metal layer 260 can be formed of lanthanum (La). The metal layer 260 can be conformally formed by atomic layer deposition, sputtering, electroplating, or a combination thereof.
[0040] A second sacrificial layer 270 is formed on the metal layer 260, wherein the second sacrificial layer 270 conformally covers the metal layer 260. Next, a capping layer 280 is formed on the second sacrificial layer 270, wherein the capping layer 280 conformally covers the second sacrificial layer 270. In some embodiments, the second sacrificial layer 270 can be formed of the same material as the first sacrificial layer 250, so that the first sacrificial layer 250 and the second sacrificial layer 270 can prevent metal elements in the metal layer 260 from penetrating into the first sacrificial layer 250 and the second sacrificial layer 270 during subsequent processing. For example, both the first sacrificial layer 250 and the second sacrificial layer 270 can be formed of a TiN layer having a thickness in the range of 1 nm to 5 nm, such as 1 nm, 2 nm, 3 nm, 4 nm, or 5 nm. The capping layer 280 can be formed of amorphous silicon. The second sacrificial layer 270 and the capping layer 280 can be formed using a highly conformal deposition process, such as atomic layer deposition.
[0041] At block 160 , the method 100 includes performing an annealing process to form a doped region in the high-k dielectric layer overlying the second substrate region. Figure 6 In one embodiment of block 160, Figure 5 An annealing process is performed on the structure in the substrate. During the annealing process, the metal elements in the metal layer 260 are driven into the high-k dielectric layer 240 above the second substrate region 214. Therefore, the metal elements in the metal layer 260 dope a portion of the high-k dielectric layer 240 located above the second substrate region 214, thereby forming a doped region 290 in the high-k dielectric layer 240. The doped region 290, located between the subsequently formed high-k dielectric metal gate and the second substrate region 214, can reduce the threshold voltage of the second transistor of the memory device 200.
[0042] Because the first sacrificial layer 250 covers the high-k dielectric layer 240 located above the first substrate region 212, the metal elements in the metal layer 260 do not diffuse into the high-k dielectric layer 240 located above the first substrate region 212. In other words, during the formation of the doped region 290, the first sacrificial layer 250 protects the high-k dielectric layer 240 and the epitaxial layer 230 located above the first substrate region 212. This ensures that the transistor including the epitaxial layer 230 has a highly stable epitaxial layer 230 and a high threshold voltage. In addition, the second sacrificial layer 270 located on the metal layer 260 prevents the metal elements from diffusing into the capping layer 280.
[0043] In some embodiments, an annealing process can be controlled to form a doped region 290 at the bottom of the high-k dielectric layer 240. For example, an annealing process can be performed at a temperature of approximately 950°C to approximately 1020°C for approximately 1 to 5 seconds, so that metal elements diffused from the metal layer 260 stop at the bottom surface of the high-k dielectric layer 240. After the annealing process, the doped region 290 can be formed between the bottom surface of the high-k dielectric layer 240 and a plane below the middle of the high-k dielectric layer 240, or between the bottom surface of the high-k dielectric layer 240 and a plane flush with the middle of the high-k dielectric layer 240. The thickness of the doped region 290 along the z-axis can be similar to or the same as the thickness of the epitaxial layer 230. For example, the thickness of the doped region 290 can be in a range of 0.5 nm to 1.5 nm, such as 0.5 nm, 1 nm, or 1.5 nm. The sidewalls of the doped region 290 relatively close to the first substrate region 212 may be flush with the sidewalls of the first sacrificial layer 250, or the sidewalls of the doped region 290 may directly contact the sidewalls of the epitaxial layer 230. The concentration of the metal element from the metal layer 260 may increase from the bottom surface of the doped region 290 toward the top surface of the doped region 290. For example, the highest lanthanum concentration in the doped region 290 may be located at the top surface of the doped region 290, while the lowest lanthanum concentration at the bottom surface of the doped region 290 may be close to zero.
[0044] At block 170, the method 100 includes removing the material layer located above the high-k dielectric layer. Figure 7 In one embodiment of block 170, Figure 6 An etching process is performed on the structure in block 170 to remove the capping layer 280, the second sacrificial layer 270, the metal layer 260, and the first sacrificial layer 250. The etching process can be a multi-step wet etching process or a dry etching process, wherein the etching process stops at the top surface of the high-k dielectric layer 240, so that during the etching process of block 170, the high-k dielectric layer 240, the doped regions 290 in the high-k dielectric layer 240, and the epitaxial layer 230 remain substantially unetched.
[0045] At block 180 , the method 100 includes forming a gate electrode layer on the high-k dielectric layer, and forming a gate cap layer on the gate electrode layer. Figure 8 In one embodiment of block 180, a gate electrode layer 300 is formed on the high-k dielectric layer 240 to cover the top surface of the high-k dielectric layer 240. Next, a gate cap layer 310 is formed on the gate electrode layer 300. In some embodiments, the gate electrode layer 300 may be formed of a metal, a metal nitride, other conductive materials, or a combination thereof, and the gate electrode layer 300 may be formed by chemical vapor deposition, atomic layer deposition, electroplating, or other suitable deposition processes. The gate cap layer 310 may be formed of a conductive material or a non-conductive material different from the gate electrode layer 300, and the gate cap layer 310 may be formed by chemical vapor deposition, atomic layer deposition, physical vapor deposition, or other suitable deposition processes. For example, the gate electrode layer 300 may be formed of TiN, and the gate cap layer may be formed of polysilicon. After forming the gate cap layer 310, a planarization process (e.g., chemical mechanical polishing) may be performed on the gate cap layer 310 to provide a flat top surface of the gate stack.
[0046] At block 190 , the method 100 includes patterning the gate cap layer, the gate electrode layer, and the high-k dielectric layer into a first gate structure located above the first substrate region and a second gate structure located above the second substrate region. Figure 9 In one embodiment of block 190, the gate cap layer 310, the gate electrode layer 300, and the high-k dielectric layer 240 located above the first substrate region 212 are patterned into a first gate structure 322. The epitaxial layer 230 below the first gate structure 322 may also be patterned such that the sidewalls of the epitaxial layer 230 are flush with the sidewalls of the first gate structure 322. Similarly, the gate cap layer 310, the gate electrode layer 300, and the high-k dielectric layer 240 located above the second substrate region 214 are patterned into a second gate structure 324. The doped region 290 in the high-k dielectric layer 240 may also be patterned such that the sidewalls of the doped region 290 are flush with the sidewalls of the second gate structure 324.
[0047] After forming the first gate structure 322 and the second gate structure 324, the memory device 200 includes a first transistor 202 and a second transistor 204 separated by a shallow trench isolation region 220. The first transistor 202 has a first conductivity type, and the second transistor 204 has a second conductivity type different from the first conductivity type. The first transistor 202 includes a first substrate region 212, an epitaxial layer 230 located above the first substrate region 212, and a first gate structure 322 located on the epitaxial layer 230. The second transistor 204 includes a second substrate region 214, a doped region 290 located above the second substrate region 214, and a second gate structure 324 located on the doped region 290. The first gate structure 322 and the second gate structure 324 are high-k metal gate structures including a high-k dielectric layer 240, a gate electrode layer 300, and a gate cap layer 310.
[0048] In some embodiments where the first transistor 202 is a p-type transistor and the second transistor 204 is an n-type transistor, a high-k metal gate structure within either the first transistor 202 or the second transistor 204 can reduce leakage current associated with the high-k metal gate structure, such as leakage current between the high-k metal gate structure and the source / drain regions. The epitaxial layer 230 located between the first gate structure 322 and the first substrate region 212 can reduce the threshold voltage at which the first transistor 202 operates relative to a transistor having a high-k metal gate structure located directly on the substrate. Similarly, the lanthanum-doped doped region 290 located between the second gate structure 324 and the second substrate region 214 can reduce the threshold voltage at which the second transistor 204 operates. Furthermore, forming the epitaxial layer 230 using a SiH precursor can reduce surface roughness of the epitaxial layer 230 and corresponding defects in the memory device 200.
[0049] According to the above-described embodiments, the disclosed method for manufacturing a memory device includes forming a first sacrificial layer above the channel region of a first transistor to block the diffusion of metal elements of a second transistor into the channel region of the first transistor. Consequently, the epitaxial layer in the first transistor and the metal-doped region in the second transistor can be stable and reduce the threshold voltage of the transistor in the operating memory device. The manufacturing method also includes forming a high-k metal gate structure above the epitaxial layer and the doped region, thereby reducing leakage current in the transistor while preventing the threshold voltage of the operating transistor from deviating from 0 volts.
[0050] The features of some embodiments are summarized above so that those skilled in the art can better understand the viewpoints of the present disclosure. Those skilled in the art will understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also understand that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and modifications may be made without departing from the spirit and scope of the present disclosure.
[0051]
Explanation of symbols
[0052] 100: Method
[0053] 110,120,130,140,150,160,170,180,190: Square
[0054] 200: memory device
[0055] 202: first transistor
[0056] 204: second transistor
[0057] 210:Substrate
[0058] 212: first substrate area
[0059] 214: Second substrate area
[0060] 220: shallow trench isolation area
[0061] 230: epitaxial layer
[0062] 240: High dielectric constant dielectric layer
[0063] 250: First sacrificial layer
[0064] 260:Metal layer
[0065] 270: Second sacrificial layer
[0066] 280: Covering layer
[0067] 290: doped region
[0068] 300: Gate electrode layer
[0069] 310: Gate covering layer
[0070] 322: first gate structure
[0071] 324: Second gate structure
[0072] x,y,z: axes.
Claims
1. A method for manufacturing a memory device, characterized in that: include: forming a shallow trench isolation region in a substrate to divide the substrate into a first substrate region and a second substrate region; forming an epitaxial layer on the first substrate region and exposing the second substrate region; forming a high-k dielectric layer on the epitaxial layer and the second substrate region; forming a first sacrificial layer on a first portion of the high-k dielectric layer located above the first substrate region and exposing a second portion of the high-k dielectric layer located above the second substrate region; forming a metal layer on the first sacrificial layer and the high-k dielectric layer; performing an annealing process to form a doped region in the high-k dielectric layer above the second substrate region; removing the metal layer and the first sacrificial layer; forming a gate electrode layer on the high-k dielectric layer, and forming a gate cap layer on the gate electrode layer; and The gate capping layer, the gate electrode layer and the high-k dielectric layer are patterned into a first gate structure located above the epitaxial layer and a second gate structure located above the doped region.
2. The method according to claim 1, wherein Further including: forming a second sacrificial layer covering the metal layer; forming a covering layer covering the second sacrificial layer; performing the annealing process to drive the metal elements of the metal layer into the high-k dielectric layer to form the doped region; and After the annealing process, the capping layer and the second sacrificial layer are removed. The method according to claim 2 , wherein the first sacrificial layer and the second sacrificial layer are formed of the same material. 4 . The method according to claim 2 , wherein after the annealing process, the metal element of the metal layer stops at a bottom of the high-k dielectric layer. 5 . The method according to claim 1 , wherein after forming the first sacrificial layer above the first substrate region, a plurality of sidewalls of the first sacrificial layer are flush with a plurality of sidewalls of the epitaxial layer. The method according to claim 1 , wherein a sidewall of the doped region is flush with a sidewall of the first sacrificial layer.
7. The method according to claim 1 , wherein forming the epitaxial layer on the first substrate region comprises: epitaxially growing a silicon-containing layer on the first substrate region using a SiH4-based precursor; and The epitaxial layer is formed by doping the silicon-containing layer with germanium. 8 . The method according to claim 1 , wherein the high-k dielectric layer covers a top surface of the epitaxial layer, sidewalls of the epitaxial layer, and a top surface of the second substrate region, and the high-k dielectric layer has a flat top surface. 9 . The method of claim 1 , wherein after forming the epitaxial layer on the first substrate region, the epitaxial layer extends onto a top surface of the shallow trench isolation region. 10 . The method of claim 1 , wherein the metal layer and the first sacrificial layer are removed using an etching process, the etching process stopping at a top surface of the high-k dielectric layer.
11. The method according to claim 1, wherein Further including: patterning the epitaxial layer so that the sidewalls of the epitaxial layer are flush with the sidewalls of the first gate structure; and The doped region is patterned so that the sidewalls of the doped region are flush with the sidewalls of the second gate structure. 12 . The method of claim 1 , wherein after the annealing process, the doped region is located between a bottom surface of the high-k dielectric layer above the second substrate region and a middle position of the high-k dielectric layer.
13. A memory device, characterized in that: include: A first transistor having a first conductivity type includes: a first substrate region; an epitaxial layer located above the first substrate region; and A first high-k metal gate structure is located on the epitaxial layer; and a second transistor having a second conductivity type, wherein the second conductivity type is different from the first conductivity type, the second transistor comprising: a second substrate region; a doped region located above the second substrate region, wherein the doped region comprises a high-k dielectric material doped with a metal element; and A second high-k metal gate structure is located on the doped region. The first high-k metal gate structure includes a high-k dielectric layer having the high-k dielectric material, a gate electrode layer located on the high-k dielectric layer, and a gate capping layer located on the gate electrode layer. 14 . The memory device of claim 13 , wherein a concentration of the metal element increases from a bottom surface of the doped region toward a top surface of the doped region. 15 . The memory device of claim 13 , wherein a highest concentration of the metal element in the doped region is located at a top surface of the doped region. The memory device of claim 13 , wherein a thickness of the doped region is the same as a thickness of the epitaxial layer.
17. The memory device of claim 13, wherein the first transistor is a p-type transistor, and the second transistor is an n-type transistor.
18. The memory device of claim 13, wherein the epitaxial layer is a SiGe layer, and the doped region is the high-k dielectric material doped with lanthanum.
19. The memory device of claim 13, wherein the first high-k metal gate structure is separated from the second high-k metal gate structure, the epitaxial layer is separated from the doped region, and a shallow trench isolation region is interposed between the first substrate region and the second substrate region. 20 . The memory device of claim 13 , wherein the epitaxial layer serves as a channel region between the first high-k metal gate structure and the first substrate region.