Semiconductor device, preparation method thereof and storage system

Abstract

The invention provides a semiconductor device, a preparation method thereof and a storage system. The semiconductor device comprises a semiconductor layer, a gate structure, a contact structure and a connection structure. The gate structure is located at one side of the semiconductor layer, the contact structure is located at one side of the semiconductor layer close to the gate structure and at one side of the gate structure along a first direction, and the first direction is parallel to the semiconductor layer. The connection structure extends along a second direction and is connected with the contact structure, and the second direction is perpendicular to the semiconductor layer. Wherein the connecting structure comprises a first surface close to the contact structure, the contact structure comprises a second surface close to the connecting structure, and the size of the second surface is the same as that of the first surface. Since the size of the first surface is the same as that of the second surface, the contact structure and the connection structure can be formed together by using a self-alignment process, a required process window is small, and the overall size of the semiconductor device can be further reduced.

Description

Technical Field

[0001] The present application generally relates to the field of electronic devices, and more particularly, to a semiconductor device, a method for manufacturing the same, and a storage system. Background Art

[0002] In the semiconductor field, a memory may include a peripheral circuit, which may be composed of multiple transistors. However, existing peripheral circuit devices have the problem of being large in overall size. Summary of the Invention

[0003] The purpose of this application is to provide a semiconductor device, a manufacturing method thereof, and a storage system, aiming to reduce the size of the semiconductor device.

[0004] In a first aspect, the present application provides a semiconductor device, comprising:

[0005] semiconductor layer;

[0006] a gate structure, located on one side of the semiconductor layer;

[0007] a contact structure, located on a side of the semiconductor layer close to the gate structure and on a side of the gate structure along a first direction parallel to the semiconductor layer;

[0008] a connecting structure extending along a second direction and connected to the contact structure, wherein the second direction is perpendicular to the semiconductor layer;

[0009] The connection structure includes a first surface close to the contact structure, and the contact structure includes a second surface close to the connection structure, and the size of the second surface is the same as the size of the first surface.

[0010] In some embodiments, the semiconductor device further comprises:

[0011] The doped region is located in the semiconductor layer, and the contact structure is connected between the doped region and the connection structure.

[0012] In some embodiments, the connection structure further includes a third surface away from the contact structure, and the contact structure further includes a fourth surface away from the connection structure; a size of the third surface is greater than or equal to a size of the first surface.

[0013] In some embodiments, a size of the second surface is greater than or equal to a size of the fourth surface.

[0014] In some embodiments, a size of the second surface is larger than a size of the fourth surface, and a size of the contact structure in a direction parallel to the plane of the semiconductor layer gradually decreases from the second surface to the fourth surface.

[0015] In some embodiments, the semiconductor device further comprises:

[0016] a gate insulating layer, located between the semiconductor layer and the gate structure, wherein the contact structure is connected to the gate insulating layer in the first direction;

[0017] The second surface of the contact structure is located on a side of the gate insulation layer away from the semiconductor layer, and the fourth surface of the contact structure is located on a side of the gate insulation layer close to the semiconductor layer.

[0018] In some embodiments, the gate insulation layer includes a fifth surface connected to the semiconductor layer, and the contact structure includes a first contact portion and a second contact portion, the first contact portion is located on a side of the fifth surface close to the semiconductor layer, and the second contact portion is located on a side of the fifth surface away from the semiconductor layer.

[0019] In some embodiments, the gate insulation layer includes a fifth surface connected to the semiconductor layer, and the contact structure is located on a side of the fifth surface away from the semiconductor layer.

[0020] In some embodiments, the gate structure includes a dielectric layer and a conductive layer, the dielectric layer is located between the conductive layer and the semiconductor layer, and the conductive layer includes:

[0021] a first conductive layer, located on a side of the dielectric layer away from the semiconductor layer;

[0022] The second conductive layer is located on a side of the first conductive layer away from the dielectric layer.

[0023] In some embodiments, the gate structure includes a first gate structure and a second gate structure, and a threshold voltage of a transistor corresponding to the first gate structure is smaller than a threshold voltage of a transistor corresponding to the second gate structure;

[0024] The second conductive layer in the first gate structure includes a first metal layer, a second metal layer surrounding the first metal layer, and a first metal nitride layer surrounding the second metal layer;

[0025] The second conductive layer in the second gate structure includes the first metal layer, the second metal layer, the first metal nitride layer, and a second metal nitride layer, and the second metal nitride layer is located between the first metal nitride layer and the second metal layer.

[0026] In some embodiments, the semiconductor layer includes a first semiconductor portion and a second semiconductor portion, and the semiconductor device further includes:

[0027] The isolation structure extends along the second direction in the semiconductor layer and is located between the first semiconductor portion and the second semiconductor portion, wherein one of the first semiconductor portion and the second semiconductor portion includes an N-type semiconductor and the other includes a P-type semiconductor.

[0028] In a second aspect, the present application provides a method for preparing a semiconductor device, the method comprising:

[0029] forming a semiconductor layer;

[0030] forming a gate structure on one side of the semiconductor layer;

[0031] forming a contact structure on a side of the semiconductor layer close to the gate structure, wherein the contact structure is located on a side of the gate structure along a first direction, wherein the first direction is parallel to the semiconductor layer;

[0032] A connection structure is formed extending along a second direction and connected to the contact structure, wherein the second direction is perpendicular to the semiconductor layer, the connection structure includes a first surface close to the contact structure, and the size of the second surface along the first direction is the same as the size of the first surface along the first direction.

[0033] In some embodiments, the method for preparing the semiconductor device further includes:

[0034] forming a doped region in the semiconductor layer before forming the contact structure;

[0035] Wherein, the contact structure is connected between the doping region and the connection structure.

[0036] In some embodiments, the steps of forming the contact structure and the connection structure include:

[0037] forming a contact hole extending along the second direction and connected to the doped region;

[0038] forming a contact structure connected to the doped region at the bottom of the contact hole;

[0039] A connection structure connected to the contact structure is formed in the contact hole, and the connection structure is located on a side of the contact structure away from the doping region.

[0040] In some embodiments, the step of forming a contact structure connected to the doped region at the bottom of the contact hole includes:

[0041] forming a metal layer on the bottom and sidewalls of the contact hole;

[0042] performing an annealing process to combine the metal layer at the bottom of the contact hole with the elements in the doped region to form the contact structure;

[0043] A cleaning process is performed to remove the metal layer on the sidewall of the contact hole.

[0044] In some embodiments, the step of forming the gate structure and the doped region includes:

[0045] forming a dielectric layer, a first conductive layer and a sacrificial layer in sequence on the semiconductor layer, with a first opening between two adjacent sacrificial layers;

[0046] Performing ion doping in the semiconductor layer to form a doped region, wherein the doped region is adjacent to the sacrificial layer along the first direction;

[0047] filling the first opening with an insulating layer;

[0048] removing the sacrificial layer to form a second opening between adjacent insulating layers;

[0049] forming a second conductive layer in the second opening;

[0050] The gate structure includes the dielectric layer, the first conductive layer and the second conductive layer.

[0051] In a third aspect, the present application provides a storage system, comprising:

[0052] The semiconductor device according to any of the above embodiments;

[0053] A controller is connected to the semiconductor device and is used to control the semiconductor device to store data.

[0054] The present application provides a semiconductor device, a preparation method thereof, and a storage system, wherein the semiconductor device includes a semiconductor layer, a gate structure, a contact structure, and a connection structure. The gate structure is located on one side of the semiconductor layer, the contact structure is located on the side of the semiconductor layer close to the gate structure, and is located on one side of the gate structure along a first direction, wherein the first direction is parallel to the semiconductor layer. The connection structure extends along a second direction and is connected to the contact structure, wherein the second direction is perpendicular to the semiconductor layer. The connection structure includes a first surface close to the contact structure, the contact structure includes a second surface close to the connection structure, and the size of the second surface is the same as the size of the first surface. Since the size of the first surface is the same as the size of the second surface, the contact structure and the connection structure can be formed together using a self-alignment process, and the required process window is smaller, thereby reducing the overall size of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] The following detailed description of the specific embodiments of the present application in conjunction with the accompanying drawings will make the technical solutions and other beneficial effects of the present application apparent.

[0056] Figure 1 is a schematic structural diagram of a semiconductor device provided by some embodiments of the present application;

[0057] Figure 2 is a schematic flow chart of a method for manufacturing a semiconductor device provided in some embodiments of the present application;

[0058] Figures 3a-3f is a schematic structural diagram of a semiconductor device during the manufacturing process provided by some embodiments of the present application;

[0059] Figure 4 This is a structural diagram of the storage system provided in some embodiments of the present application. DETAILED DESCRIPTION

[0060] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0061] It should be understood that although the terms first, second, etc. may be used herein to describe various components, these components should not be limited by these terms. These terms are used to distinguish one component from another. For example, a first component can be referred to as a second component, and similarly, a second component can be referred to as a first component without departing from the scope of this application.

[0062] It should be understood that when a component is said to be "on" or "connected" to another component, it can be directly on or connected to the other component, or there may be intervening components. Other words used to describe the relationship between components should be interpreted in a similar manner.

[0063] As used herein, the term "layer" refers to a portion of a material that includes an area having a thickness. A layer may extend over the entire underlying or superstructure, or may have an extent that is less than the extent of the underlying or superstructure. In addition, a layer may be an area of a uniform or non-uniform continuous structure having a thickness that is less than the thickness of a continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any set of horizontal planes at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer that may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductive layers and contact layers and one or more dielectric layers.

[0064] It should be noted that the illustrations provided in the embodiments of the present application are only schematic illustrations of the basic concept of the present application. Although the illustrations only show components related to the present application and are not drawn according to the number, shape and size of components in actual implementation, the type, quantity and proportion of each component in actual implementation may be changed at will, and the component layout may also be more complicated.

[0065] See also Figure 1 , Figure 1 1 is a schematic diagram of the structure of a semiconductor device provided by some embodiments of the present application. The semiconductor device 100 can be a wafer or a three-dimensional memory, or a portion of a three-dimensional memory. The three-dimensional memory can be applied to communications products, consumer electronics, automotive products, aerospace products, artificial intelligence products, or big data. Consumer electronics products include, but are not limited to, mobile phones, computers, tablets, cameras, smart glasses, or gaming products.

[0066] Specifically, the semiconductor device 100 may be a peripheral circuit or a part of a peripheral circuit, and the peripheral circuit may include a complementary metal oxide semiconductor (CMOS).

[0067] The semiconductor device 100 includes a semiconductor layer 10, a gate structure 11, a contact structure 12, and a connection structure 13. The gate structure 11 is located on one side of the semiconductor layer 10. The contact structure 12 is located on a side of the semiconductor layer 10 near the gate structure 11 and on one side of the gate structure 11 along a first direction (X), wherein the first direction (X) is parallel to the semiconductor layer 10. The connection structure 13 extends along a second direction (Y) and is connected to the contact structure 12. The second direction (Y) is perpendicular to the semiconductor layer 10. The connection structure 13 includes a first surface 131 near the contact structure 12. The contact structure 12 includes a second surface 121 near the connection structure 13. The second surface 121 has the same size as the first surface 131.

[0068] In some embodiments, the semiconductor layer 10 may be silicon (Si), germanium (Ge), a SiGe substrate, a silicon-on-insulator (SOI), or a germanium-on-insulator (GOI). In some embodiments, the semiconductor layer 10 may also be other elemental semiconductors or compound semiconductors, and may also be a stacked structure, such as Si / SiGe.

[0069] The gate structure 11 and the contact structure 12 are located on the same side of the semiconductor layer 10. In some embodiments, the gate structure 11 and the contact structure 12 are adjacent to each other in the first direction (X). Specifically, the contact structure 12 is located on both sides of the gate structure 11 along the first direction (X).

[0070] In some embodiments, the gate structure 11 may include a dielectric layer 111 and a conductive layer 112, wherein the dielectric layer 111 is located between the conductive layer 112 and the semiconductor layer 10. The conductive layer 112 includes a first conductive layer 1121 and a second conductive layer 1122, wherein the first conductive layer 1121 is located on a side of the dielectric layer 111 away from the semiconductor layer 10, and the second conductive layer 1122 is located on a side of the first conductive layer 1121 away from the dielectric layer 111. The dielectric layer 111 may include a high-K (dielectric constant) dielectric layer, such as hafnium oxide (HfO), and the first conductive layer 1121 may include a metal nitride, such as titanium nitride (TiN).

[0071] In some embodiments, the gate structure 11 includes a first gate structure 11a and a second gate structure 11b, wherein the threshold voltage of the transistor corresponding to the first gate structure 11a is lower than the threshold voltage of the transistor corresponding to the second gate structure 11b. The second conductive layer 1122 in the first gate structure 11a includes a first metal layer 1122a, a second metal layer 1122b surrounding the first metal layer 1122a, and a first metal nitride layer 1122c surrounding the second metal layer 1122b. The second metal layer 1122b may surround the sidewalls and bottom of the first metal layer 1122a, and the first metal nitride layer 1122c may surround the sidewalls and bottom of the second metal layer 1122b. Specifically, the first metal layer 1122a may include aluminum, the second metal layer 1122b may include a TiAl alloy, and the first metal nitride layer 1122c may include tantalum nitride (TaN).

[0072] The second conductive layer 1122 in the second gate structure 11b may include the first metal layer 1122a, the second metal layer 1122b, the first metal nitride layer 1122c, and the second metal nitride layer 1122d, wherein the second metal nitride layer 1122d is located between the first metal nitride layer 1122c and the second metal layer 1122b. The difference between the second gate structure 11b and the first gate structure 11a is that the second gate structure 11b also includes a second metal nitride layer 1122d for adjusting the work function of the high threshold voltage transistor. Specifically, the second metal nitride layer 1122d surrounds the sidewalls and bottom of the second metal layer 1122b, and the first metal nitride layer 1122c surrounds the sidewalls and bottom of the second metal nitride layer 1122d. The second metal nitride layer 1122d may be titanium nitride (TiN).

[0073] It should be noted that the "surface size" in this article may refer to the area of the surface, that is, the area of the first surface 131 is equal to the area of the second surface 121; the "surface size" in this article may also refer to the length of the surface along the first direction (X), that is, the length of the first surface 131 along the first direction (X) is equal to the length of the second surface 121 along the first direction (X).

[0074] In some embodiments, the orthographic projection of the second surface 121 on the semiconductor layer 10 is located within the range of the orthographic projection of the first surface 131 on the semiconductor layer 10 .

[0075] In some embodiments, the first surface 131 of the connection structure 13 and the second surface 121 of the contact structure 12 may completely overlap.

[0076] In some embodiments, the connection structure 13 also includes a third surface 132 away from the contact structure 12, and the contact structure 12 also includes a fourth surface 122 away from the connection structure 13; the size of the third surface 132 is greater than or equal to the size of the first surface 131, and the size of the second surface 121 is greater than or equal to the size of the fourth surface 122.

[0077] In some embodiments, the size of the third surface 132 is larger than that of the first surface 131 , and the size of the second surface 121 is larger than that of the fourth surface 122 .

[0078] Specifically, from the second surface 121 to the fourth surface 122 , the size of the contact structure 12 in the direction parallel to the plane of the semiconductor layer 10 gradually decreases, for example Figure 1 The cross-sectional area of the contact structure 12 along the XY plane gradually decreases from top to bottom. From the third surface 132 to the first surface 131, the size of the connection structure 13 in the direction parallel to the plane of the semiconductor layer 10 gradually decreases, for example Figure 1 The cross-sectional area of the connection structure 13 along the XY plane direction gradually decreases from top to bottom.

[0079] The semiconductor device 100 may further include a gate insulating layer 14, which is located between the semiconductor layer 10 and the gate structure 11. The contact structure 12 is connected to the gate insulating layer 14 in the first direction (X). Alternatively, the contact structure 12 extends through the gate insulating layer 14 along the second direction (Y). The gate insulating layer 14 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric.

[0080] In some embodiments, the second surface 121 of the contact structure 12 is located on a side of the gate insulating layer 14 away from the semiconductor layer 10, and the fourth surface 122 of the contact structure 12 is located on a side of the gate insulating layer 14 close to the semiconductor layer 10. Figure 1 In the embodiment, the upper surface of the contact structure 12 is located above the gate insulating layer 14 , and the lower surface of the contact structure 12 is located below the contact structure 12 .

[0081] The contact structure 12 may include any suitable metal silicide material, such as WSix, CoSix, NiSix, AlSix, etc., or any combination thereof.

[0082] In some embodiments, the contact structure 12 includes a first contact portion 12a and a second contact portion 12b, and the gate insulating layer 14 includes a fifth surface 141 connected to the semiconductor layer 10. With the fifth surface 141 as a reference, the first contact portion 12a is located on a side of the fifth surface 141 close to the semiconductor layer 10, and the second contact portion 12b is located on a side of the fifth surface 141 away from the semiconductor layer 10. Figure 1 As shown, the fifth surface 141 is the bottom surface of the gate insulation layer 14. The first contact portion 12a and the second contact portion 12b are separated by a dotted line in the figure. The first contact portion 12a is located below the fifth surface 141, and the second contact portion 12b is located above the fifth surface 141. Therefore, the semiconductor layer 10 has a groove at the position corresponding to the first contact portion 12a.

[0083] In other embodiments, the contact structure 12 is located on a side of the fifth surface 141 away from the semiconductor layer 10 , that is, the contact structure 12 is completely above the fifth surface 141 , so the semiconductor layer 10 has no groove at a position corresponding to the first contact portion 12 a .

[0084] The semiconductor device 100 may further include a doped region 15 located within the semiconductor layer 10, with the contact structure 12 connected between the doped region 15 and the connection structure 13. Specifically, the doped region 15 is exposed on the surface of the semiconductor layer 10 near the gate insulating layer 14, and the connection structure 13 leads the doped region 15 out to connect to the interconnect layer through the contact structure 12. The contact structure 12 can reduce the contact resistance between the doped region 15 and the connection structure 13.

[0085] In some embodiments, the interconnect layer connected by the connection structure 13 can be bonded to the interconnect layer of the memory array, wherein the connection structure 13 may include a conductive layer, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicide, or any combination thereof. In one embodiment, the connection structure 13 may also include a dielectric layer surrounding the sidewalls of the conductive layer, wherein the dielectric layer includes but not limited to any one or more combinations of silicon oxide, silicon nitride, and silicon oxynitride.

[0086] In some embodiments, the doped regions 15 are located on both sides of the gate structure 11 along the first direction (X). The doped regions 15 located on both sides of the gate structure 11 can serve as source regions and drain regions. In one embodiment, two adjacent gate structures 11 can share a source region or a drain region.

[0087] The semiconductor device 100 may further include an isolation structure 16 extending along the second direction (Y) in the semiconductor layer 10. The semiconductor layer 10 includes a first semiconductor portion 10a and a second semiconductor portion 10b. The isolation structure 16 is located between the first semiconductor portion 10a and the second semiconductor portion 10b. One of the first semiconductor portion 10a and the second semiconductor portion 10b includes an N-type semiconductor, and the other includes a P-type semiconductor.

[0088] Specifically, the first semiconductor portion 10a may include an N-type semiconductor, the second semiconductor portion 10b may include a P-type semiconductor, the doping region 15 corresponding to the first semiconductor portion 10a may include P-type dopant ions, and the doping region 15 corresponding to the second semiconductor portion 10b may be N-type dopant, so a PMOS may be formed in the N-type semiconductor, and an NMOS may be formed in the P-type semiconductor.

[0089] The semiconductor device 100 provided in an embodiment of the present application includes a semiconductor layer 10, a gate structure 11, a contact structure 12, and a connection structure 13. The gate structure 11 is located on one side of the semiconductor layer 10. The contact structure 12 is located on a side of the semiconductor layer 10 proximate to the gate structure 11 and on one side of the gate structure 11 along a first direction (X), wherein the first direction (X) is parallel to the semiconductor layer 10. The connection structure 13 extends along a second direction (Y) and is connected to the contact structure 12. The second direction (Y) is perpendicular to the semiconductor layer 10. The connection structure 13 includes a first surface 131 proximate to the contact structure 12. The contact structure 12 includes a second surface 121 proximate to the connection structure 13. The size of the second surface 121 is the same as the size of the first surface 131. Because the size of the first surface 131 and the size of the second surface 121 are the same, the contact structure 12 and the connection structure 13 can be formed together using a self-aligned process, requiring a smaller process window, thereby reducing the overall size of the semiconductor device 100. For the specific process, please refer to the preparation method of the semiconductor device 100 below.

[0090] See also Figure 2 , Figure 2 This is a flow chart of a method for preparing a semiconductor device according to some embodiments of the present application. Figures 3a-3f , Figures 3a-3f This is a schematic diagram of the structure of the semiconductor device provided in some embodiments of the present application during the preparation process. This embodiment takes the preparation of the above-mentioned semiconductor device 100 as an example to illustrate the preparation method of the semiconductor device 100, so please refer to the following examples. Figure 1 The method for preparing the semiconductor device 100 includes the following steps S1-S4.

[0091] Step S1: forming a semiconductor layer 10 .

[0092] In some embodiments, as Figure 3a As shown, the semiconductor layer 10 may include a silicon substrate, which may be doped with different types of ions to form a first semiconductor portion 10a and a second semiconductor portion 10b distributed along a first direction (X). For example, the first semiconductor portion 10a may include an N-type semiconductor, and the second semiconductor portion 10b may include a P-type semiconductor. An isolation structure 16 may also be formed in the semiconductor layer 10. The isolation structure 16 is located between the first semiconductor portion 10a and the second semiconductor portion 10b and may include an insulating material such as silicon oxide or silicon nitride.

[0093] Step S2 : forming a gate structure 11 on one side of the semiconductor layer 10 .

[0094] Before forming the gate structure 11, the method for preparing the semiconductor device 100 further includes: Figure 3a As shown, a gate insulating layer 14 is formed between the semiconductor layer 10 and the gate structure 11. The gate insulating layer 14 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. In some embodiments, the method for forming the gate insulating layer 14 may include, but is not limited to, chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD) such as thermal oxidation, evaporation, sputtering, and other methods.

[0095] like Figure 3a As shown, a dielectric layer 111 , a first conductive layer 1121 and a sacrificial layer 1122 a may be sequentially formed on the semiconductor layer 10 , with a first opening A1 being defined between two adjacent sacrificial layers 1122 a .

[0096] Specifically, an initial dielectric layer, a first initial conductive layer, and an initial sacrificial layer can be sequentially deposited on the semiconductor layer 10 using a suitable deposition process. The initial sacrificial layer can include polysilicon. A patterned etching process is then performed to form the dielectric layer 111, a first conductive layer 1121 located on the dielectric layer 111, a sacrificial layer 1122a located on the first conductive layer 1121, and a first opening A1. The first opening A1 is located between two adjacent sacrificial layers 1122a, between two adjacent dielectric layers 111, and between two adjacent first conductive layers 1121.

[0097] like Figures 3b-3cAs shown, the first openings A1 are filled with an insulating layer 17, and then the sacrificial layer 1122a is removed to form a second opening A2 located between adjacent insulating layers 17. Then, a second conductive layer 1122 is formed in the second openings A2. The insulating layer 17 may include, but is not limited to, any one or more combinations of silicon oxide, silicon nitride, and silicon oxynitride.

[0098] Specifically, such as Figure 3b As shown, a first metal nitride layer 1122c and a second metal nitride layer 1122d are sequentially formed in the second opening A2; Figure 3c As shown, a second metal layer 1122b and a first metal layer 1122a are sequentially formed on the surface of the second metal nitride layer 1122d; Figure 3d As shown, a chemical mechanical polishing process may be further performed on the second conductive layer 1122 to form a plurality of independent gate structures 11, and then an insulating layer 17 is formed to cover the gate structures 11. The gate structure 11 includes the dielectric layer 111, the first conductive layer 1121, and the second conductive layer 1122. The second conductive layer 1122 includes a first metal layer 1122a, a second metal layer 1122b, a first metal nitride layer 1122c, and a second metal nitride layer 1122d.

[0099] In some embodiments, the gate structure can be formed directly on the gate insulating layer (a "gate-first" process) by referring to step 3d. The gate structure 11 formed by the "gate-last" process, in which the sacrificial layer 1122a is first formed in step S2 and then replaced with the second conductive layer 1122, has better performance and more adjustable threshold voltage than the gate structure formed by the "gate-first" process.

[0100] In some embodiments, the gate structure 11 may be used for transistors with different threshold voltages, and the gate structures 11 required for transistors with different threshold voltages may be different. Figure 3c and 3d As shown, an etching process can be used to remove part of the second metal nitride layer 1122d at the second opening A2, so that the gate structure 11 (the first gate structure 11a) finally formed does not have the second metal nitride layer 1122d, while the other gate structures 11 (the second gate structure 11b) include the first metal layer 1122a, the second metal layer 1122b, the first metal nitride layer 1122c and the second metal nitride layer 1122d.

[0101] Step S3 : forming a contact structure 12 on a side of the semiconductor layer 10 close to the gate structure 11 , wherein the contact structure 12 is located on a side of the gate structure 11 along a first direction (X) parallel to the semiconductor layer 10 .

[0102] The method for manufacturing the semiconductor device 100 may further include: forming a doped region 15 in the semiconductor layer 10 before forming the contact structure 12 .

[0103] Specifically, such as Figure 3a As shown, after forming the first opening A1 , the semiconductor layer 10 may be subjected to a plasma implantation process to form a doping region 15 so that the subsequently formed contact structure 12 may be connected to the doping region 15 , that is, the contact structure 12 is connected between the doping region 15 and the connection structure 13 .

[0104] Step S4: Form a connection structure 13 extending along a second direction (Y) and connected to the contact structure 12, wherein the second direction (Y) is perpendicular to the semiconductor layer 10, and the connection structure 13 includes a first surface 131 close to the contact structure 12, and the size of the second surface 121 along the first direction (X) is the same as the size of the first surface 131 along the first direction (X).

[0105] In some embodiments, the connection structure 13 and the contact structure 12 may be formed together, such as Figures 3e-3f As shown, step S3 and step S4 include the following steps.

[0106] 1) forming a contact hole A3 extending along the second direction (Y) and connected to the doping region 15 .

[0107] like Figure 3e As shown, the insulating layer 17 and the gate insulating layer 14 can be etched along the second direction (Y) to form a contact hole A3 to expose the doped region 15. In some embodiments, the bottom of the contact hole A3 can be located on the doped region 15 or extend into the doped region 15.

[0108] 2) A contact structure 12 connected to the doped region 15 is formed at the bottom of the contact hole A3.

[0109] like Figure 3f As shown, a metal layer can be first formed on the bottom and sidewalls of the contact hole A3, and then an annealing process can be performed to combine the metal layer at the bottom of the contact hole A3 with the elements in the doped region 15 to form the contact structure 12. Finally, a cleaning process can be performed to remove the metal layer on the sidewalls of the contact hole A3. The metal layer can include nickel, and the contact structure 12 can include nickel silicide (SiNi).

[0110] 3) forming a connection structure 13 connected to the contact structure 12 in the contact hole A3 , wherein the connection structure 13 is located on a side of the contact structure 12 away from the doping region 15 .

[0111] like Figure 1As shown, after forming the contact structure 12, a conductive layer is directly filled into the contact hole A3 to form a connection structure 13 connected to the contact structure 12. Since both the contact structure 12 and the connection structure 13 are formed in the contact hole A3, the contact surface size of the two is the same.

[0112] In some embodiments, the gate insulating layer 14 can be etched first to form a first opening, and the contact structure 12 can be formed in the first opening; then the insulating layer 17 can be etched to form a second opening, and a connection structure 13 (not shown) connected to the contact structure 12 can be formed in the second opening. In order to ensure that the connection structure 13 can be aligned and connected to the contact structure 12, the size of the contact structure 12 along the first direction (X) needs to be large enough to facilitate the connection structure 13 to fall on the contact structure 12, so this will increase the etching process window required for the contact structure 12. And when forming the etching process of the connection structure 13, there is a certain offset in the alignment of the second opening and the contact structure 12, so the process window required for etching the second opening is increased. In general, this formation process will lead to an increase in the etching process window required for the contact structure 12 and the connection structure 13, thereby increasing the overall size of the device.

[0113] The preparation method of the semiconductor device 100 provided in the embodiment of the present application directly forms a contact hole A3 that penetrates the insulating layer 17 and the gate insulating layer 14, so that the contact structure 12 and the connection structure 13 can be formed in a self-aligned manner, which not only reduces the size of the contact structure 12 along the first direction (X), but also reduces the required process window. Therefore, the spacing between the gate structures 11 can also be reduced, thereby reducing the size of the overall semiconductor device 100.

[0114] See also Figure 4 , Figure 4 2 is a schematic diagram of the structure of a storage system provided in some embodiments of the present application. The storage system 200 includes a semiconductor device 201 and a controller 202. The semiconductor device 201 may include any of the semiconductor devices in the above embodiments. The controller 202 is connected to the semiconductor device 201 and is used to control the semiconductor device 201 to store data. The semiconductor device 201 can perform data storage operations based on the control of the controller 202.

[0115] In some embodiments, the storage system may be implemented as a storage device such as a Universal Flash Storage (UFS) device, a solid-state drive (SSD), a multimedia card in the form of MMC, eMMC, RS-MMC and micro MMC, a secure digital card in the form of SD, mini SD and micro SD, a Personal Computer Memory Card International Association (PCMCIA) card type storage device, a Peripheral Component Interconnect (PCI) type storage device, a PCI-Express (PCI-E) type storage device, a Compact Flash (CF) card, a smart media card or a memory stick, etc.

[0116] The semiconductor device 201 includes: a semiconductor layer; a gate structure located on one side of the semiconductor layer; a contact structure located on a side of the semiconductor layer close to the gate structure and on one side of the gate structure along a first direction, wherein the first direction is parallel to the semiconductor layer; a connecting structure extending along a second direction and connected to the contact structure, wherein the second direction is perpendicular to the semiconductor layer; wherein the connecting structure includes a first surface close to the contact structure, the contact structure includes a second surface close to the connecting structure, and the size of the second surface is the same as the size of the first surface.

[0117] The description of the above embodiments is only used to help understand the technical solutions and core ideas of this application; ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A semiconductor device, characterized in that: The semiconductor device comprises: semiconductor layer; a gate structure, located on one side of the semiconductor layer; a contact structure, located on a side of the semiconductor layer close to the gate structure and on a side of the gate structure along a first direction parallel to the semiconductor layer; a connecting structure extending along a second direction and connected to the contact structure, wherein the second direction is perpendicular to the semiconductor layer; The connection structure includes a first surface close to the contact structure, and the contact structure includes a second surface close to the connection structure, and the size of the second surface is the same as the size of the first surface.

2. The semiconductor device according to claim 1, wherein The semiconductor device further includes: The doped region is located in the semiconductor layer, and the contact structure is connected between the doped region and the connection structure.

3. The semiconductor device according to claim 1, wherein The connection structure further includes a third surface away from the contact structure, and the contact structure further includes a fourth surface away from the connection structure; a size of the third surface is greater than or equal to a size of the first surface.

4. The semiconductor device according to claim 3, wherein The size of the second surface is greater than or equal to the size of the fourth surface.

5. The semiconductor device according to claim 4, wherein The size of the second surface is larger than that of the fourth surface, and the size of the contact structure in a direction parallel to the plane of the semiconductor layer gradually decreases from the second surface to the fourth surface.

6. The semiconductor device according to claim 3, wherein The semiconductor device further includes: a gate insulating layer, located between the semiconductor layer and the gate structure, wherein the contact structure is connected to the gate insulating layer in the first direction; The second surface of the contact structure is located on a side of the gate insulation layer away from the semiconductor layer, and the fourth surface of the contact structure is located on a side of the gate insulation layer close to the semiconductor layer.

7. The semiconductor device according to claim 6, wherein: The gate insulation layer includes a fifth surface connected to the semiconductor layer, and the contact structure includes a first contact portion and a second contact portion. The first contact portion is located on a side of the fifth surface close to the semiconductor layer, and the second contact portion is located on a side of the fifth surface away from the semiconductor layer.

8. The semiconductor device according to claim 6, wherein: The gate insulating layer includes a fifth surface connected to the semiconductor layer, and the contact structure is located on a side of the fifth surface away from the semiconductor layer.

9. The semiconductor device according to claim 1, wherein The gate structure includes a dielectric layer and a conductive layer, wherein the dielectric layer is located between the conductive layer and the semiconductor layer, and the conductive layer includes: a first conductive layer, located on a side of the dielectric layer away from the semiconductor layer; The second conductive layer is located on a side of the first conductive layer away from the dielectric layer.

10. The semiconductor device according to claim 9, wherein The gate structure includes a first gate structure and a second gate structure, wherein a threshold voltage of a transistor corresponding to the first gate structure is lower than a threshold voltage of a transistor corresponding to the second gate structure; The second conductive layer in the first gate structure includes a first metal layer, a second metal layer surrounding the first metal layer, and a first metal nitride layer surrounding the second metal layer; The second conductive layer in the second gate structure includes the first metal layer, the second metal layer, the first metal nitride layer, and a second metal nitride layer, and the second metal nitride layer is located between the first metal nitride layer and the second metal layer.

11. The semiconductor device according to claim 1, wherein The semiconductor layer includes a first semiconductor portion and a second semiconductor portion, and the semiconductor device further includes: The isolation structure extends along the second direction in the semiconductor layer and is located between the first semiconductor portion and the second semiconductor portion, wherein one of the first semiconductor portion and the second semiconductor portion includes an N-type semiconductor and the other includes a P-type semiconductor.

12. A method for preparing a semiconductor device, characterized in that: The method for preparing the semiconductor device comprises: forming a semiconductor layer; forming a gate structure on one side of the semiconductor layer; forming a contact structure on a side of the semiconductor layer close to the gate structure, wherein the contact structure is located on a side of the gate structure along a first direction, wherein the first direction is parallel to the semiconductor layer; A connection structure is formed extending along a second direction and connected to the contact structure, wherein the second direction is perpendicular to the semiconductor layer, the connection structure includes a first surface close to the contact structure, and the size of the second surface along the first direction is the same as the size of the first surface along the first direction.

13. The method for preparing a semiconductor device according to claim 12, wherein: The method for preparing the semiconductor device further includes: forming a doped region in the semiconductor layer before forming the contact structure; Wherein, the contact structure is connected between the doping region and the connection structure.

14. The method for manufacturing a semiconductor device according to claim 13, wherein: The steps of forming the contact structure and the connection structure include: forming a contact hole extending along the second direction and connected to the doped region; forming a contact structure connected to the doped region at the bottom of the contact hole; A connection structure connected to the contact structure is formed in the contact hole, and the connection structure is located on a side of the contact structure away from the doping region.

15. The method for manufacturing a semiconductor device according to claim 14, wherein: The step of forming a contact structure connected to the doped region at the bottom of the contact hole comprises: forming a metal layer on the bottom and sidewalls of the contact hole; performing an annealing process to combine the metal layer at the bottom of the contact hole with the elements in the doped region to form the contact structure; A cleaning process is performed to remove the metal layer on the sidewall of the contact hole.

16. The method for manufacturing a semiconductor device according to claim 13, wherein: The step of forming the gate structure and the doped region includes: forming a dielectric layer, a first conductive layer and a sacrificial layer in sequence on the semiconductor layer, with a first opening between two adjacent sacrificial layers; Performing ion doping in the semiconductor layer to form a doped region, wherein the doped region is adjacent to the sacrificial layer along the first direction; filling the first opening with an insulating layer; removing the sacrificial layer to form a second opening between adjacent insulating layers; forming a second conductive layer in the second opening; The gate structure includes the dielectric layer, the first conductive layer and the second conductive layer.

17. A storage system, characterized in that: include: The semiconductor device according to claims 1 to 11; A controller is connected to the semiconductor device and is used to control the semiconductor device to store data.

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