Display panel and method of manufacturing the same

Abstract

Disclosed are a display panel and a method of manufacturing the same, the display panel including: a first light emitting element including a first anode, a first cathode, and a first intermediate layer disposed between the first anode and the first cathode; a second light emitting element including a second cathode, a second anode, and a second intermediate layer disposed between the second cathode and the second anode; a first transistor; a second transistor; connecting wires; and a pixel defining film, and the second anode includes an end portion connected to the light emitting connection member and another end portion spaced apart from the end portion in cross section.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2024-0018268 filed in the Korean Intellectual Property Office on February 6, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The embodiments described herein relate to apparatuses and methods, and more particularly, to a display panel with improved display quality and a method of manufacturing the display panel. Background Art

[0004] Multimedia electronic devices such as televisions (TVs), mobile phones, tablet personal computers (PCs), computers, navigation systems, game consoles, etc. include display panels for displaying images.

[0005] Display panels include light-emitting elements and circuits for driving the light-emitting elements. The light-emitting elements included in the display panel emit light based on a voltage applied from the circuits, generating an image. Research has been underway to improve the connection between the light-emitting elements and the circuits to improve the reliability of display panels. Summary of the Invention

[0006] The embodiment provides a display panel capable of preventing damage to a light emitting layer and a method of manufacturing the display panel.

[0007] The embodiment provides a display panel capable of preventing reliability degradation of display quality and a method of manufacturing the display panel.

[0008] However, the embodiments are not limited to the embodiments set forth herein. The above and other embodiments will become more apparent to those skilled in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given below.

[0009] According to an embodiment, a display panel includes: a first light-emitting element including a first anode, a first cathode arranged on the first anode, and a first intermediate layer arranged between the first anode and the first cathode; a second light-emitting element including a second cathode, a second anode arranged on the second cathode, and a second intermediate layer arranged between the second cathode and the second anode; a first transistor electrically connected to the first light-emitting element; a second transistor electrically connected to the second light-emitting element; a connection wiring arranged between the second light-emitting element and the second transistor in a cross section, and the connection wiring includes a driving connection part connected to the second transistor and a light-emitting connection part connected to the second anode; and a pixel defining film including: a first light-emitting opening overlapping with the first light-emitting element and in which a portion of the first cathode is arranged; a second light-emitting opening overlapping with the second light-emitting element and spaced apart from the first light-emitting opening, in which a portion of the second anode is arranged; and a first connection opening spaced apart from the first light-emitting opening and the second light-emitting opening, wherein the second anode includes an end portion connected to the light-emitting connection part and another end portion spaced apart from the end portion in a cross section.

[0010] The display panel may further include a hydrogen supply film disposed under the second cathode and overlapping the second light emitting opening.

[0011] The display panel may further include a spacer disposed on the pixel defining film and disconnecting the second anode.

[0012] The first intermediate layer may include a luminescent material generating light having a blue color, and the second intermediate layer may include a luminescent material generating light having a color different from the blue color.

[0013] The first intermediate layer may include: a first hole control layer, which is arranged on the pixel defining film; a first light-emitting layer, which is arranged on the first hole control layer and generates light having a first color; and a first electron control layer, which is arranged on the first light-emitting layer, and the second intermediate layer may include: a second electron control layer, which is arranged on the pixel defining film; a second light-emitting layer, which is arranged on the second electron control layer and includes a light-emitting material that generates light having a color different from the first color; and a second hole control layer, which is arranged on the second light-emitting layer.

[0014] The hydrogen supply film may contain silicon nitride (SiN x ) or polyacrylic acid.

[0015] The thickness of the second electron control layer may be approximately or larger and approximately or smaller.

[0016] The connection wiring may include: a first layer containing titanium (Ti); a second layer provided on the first layer and containing aluminum (Al); and a third layer provided on the second layer and containing titanium (Ti).

[0017] The first cathode and the second cathode may be spaced apart from each other in a plan view.

[0018] The first light emitting element may be disposed in the first region, the second light emitting element may be disposed in the second region, the first region and the second region may be partitioned by a partition, and the first connection opening may be spaced apart from the first region in a plan view.

[0019] According to an embodiment, a display panel includes: a first light-emitting element including: a first anode; a first cathode disposed on the first anode; and a first intermediate layer disposed between the first anode and the first cathode; a second light-emitting element including: a second cathode; a second anode disposed on the second cathode; and a second intermediate layer disposed between the second cathode and the second anode; a third light-emitting element including: a third cathode; a third anode disposed on the third cathode; and a third intermediate layer disposed between the third cathode and the third anode; a first transistor electrically connected to the first light-emitting element; a second transistor electrically connected to the second light-emitting element; a third transistor electrically connected to the third light-emitting element; a first connection a wiring that is arranged between the second light-emitting element and the second transistor in cross section and includes: a first drive connection part connected to the second transistor; and a first light-emitting connection part connected to the second anode; and a second connection wiring that is arranged between the third light-emitting element and the third transistor in cross section and includes: a second drive connection part connected to the third transistor; and a second light-emitting connection part connected to the third anode, wherein the second anode includes an end portion connected to the first light-emitting connection part and another end portion spaced apart from the end portion in cross section, and the third anode includes an end portion connected to the second light-emitting connection part and another end portion spaced apart from the end portion in cross section.

[0020] The first intermediate layer may include a luminescent material generating light having a blue color, the second intermediate layer may include a luminescent material generating light having a red color, and the third intermediate layer may include a luminescent material generating light having a green color.

[0021] The display panel may further include: a first hydrogen supply film disposed under the second cathode; and a second hydrogen supply film disposed under the third cathode.

[0022] The display panel may further include a separator that disconnects the second anode and the third anode.

[0023] The second cathode and the third cathode may be electrically connected to each other.

[0024] Each of the first connection wiring and the second connection wiring may include a first layer containing titanium (Ti); a second layer provided on the first layer and containing aluminum (Al); and a third layer provided on the second layer and containing titanium (Ti).

[0025] The first light-emitting element may be disposed in the first region, the second light-emitting element may be disposed in the second region, the third light-emitting element may be disposed in the third region, the first region, the second region, and the third region may be divided by a partition, and the first light-emitting connecting part and the second light-emitting connecting part may be spaced apart from the first region in a plan view.

[0026] According to an embodiment, a method for manufacturing a display panel includes: forming a first lower electrode and a second lower electrode on a base layer; forming a first light-emitting opening and a second light-emitting opening, at least a portion of the first lower electrode is exposed through the first light-emitting opening, and at least a portion of the second lower electrode is exposed through the second light-emitting opening, the first light-emitting opening and the second light-emitting opening are arranged on the base layer and cover the first lower electrode and the second lower electrode; forming a first hole control layer, a first light-emitting layer and a first electron control layer inside the first light-emitting opening; and forming a second electron control layer, a second light-emitting layer and a second hole control layer inside the second light-emitting opening, wherein the first hole control layer and the second hole control layer are formed simultaneously.

[0027] The first and second hole control layers, the first and second light emitting layers, and the first and second electron control layers may be formed by an inkjet method.

[0028] The method may further include patterning the base layer and forming a hydrogen supply film on the patterned base layer before forming the first lower electrode and the second lower electrode on the base layer, wherein the second lower electrode may be formed on the hydrogen supply film. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The above and other objects and features of the present disclosure will become apparent by describing in detail embodiments of the present disclosure with reference to the accompanying drawings.

[0030] Figure 1 is a schematic block diagram of a display panel according to an embodiment.

[0031] Figure 2 is a schematic diagram of an equivalent circuit of a pixel according to an embodiment.

[0032] Figure 3A and Figure 3B is a schematic plan view of a display panel according to an embodiment.

[0033] Figure 4A 、 Figure 4B and Figure 4Cis an enlarged schematic plan view showing a portion of a display panel according to an embodiment.

[0034] Figure 5 is a schematic cross-sectional view of a display panel according to an embodiment.

[0035] Figure 6A 、 Figure 6B and Figure 6C is an enlarged schematic cross-sectional view of a portion of a display panel according to an embodiment.

[0036] Figure 7 is an enlarged schematic cross-sectional view of a portion of a display panel according to an embodiment.

[0037] Figure 8A and Figure 8B is an enlarged schematic cross-sectional view of a light emitting element according to an embodiment.

[0038] Figure 9 is an enlarged schematic cross-sectional view of a portion of a display panel according to an embodiment.

[0039] Figure 10A 、 Figure 10B 、 Figure 10C 、 Figure 10D 、 Figure 10E and Figure 10F is a schematic cross-sectional view illustrating a method of manufacturing a display panel according to an embodiment. DETAILED DESCRIPTION

[0040] In the following description, for the purpose of explanation, many specific details are set forth in order to provide a thorough understanding of various embodiments or implementations of the present invention. As used herein, "embodiment" and "implementation" are interchangeable terms that serve as non-limiting examples of the apparatus or method disclosed herein. However, it is apparent that various embodiments may be practiced without these specific details or with one or more equivalent arrangements. Here, various embodiments are not necessarily exclusive and do not limit the present disclosure. For example, the specific shape, configuration, and characteristics of an embodiment may be used or implemented in another embodiment.

[0041] Unless otherwise indicated, the embodiments shown will be understood to provide features of the present invention. Therefore, unless otherwise indicated, the features, components, modules, layers, films, panels, regions and / or aspects of the various embodiments (hereinafter individually or collectively referred to as "elements") may be combined, separated, interchanged and / or rearranged in other ways without departing from the scope of the present invention.

[0042] The use of cross hatching and / or shading in the drawings is generally provided to clarify the boundaries between adjacent elements. Therefore, unless otherwise specified, the presence and absence of cross hatching or shading neither conveys nor indicates any preference or requirement for the specific materials, material properties, size, proportions, commonality between the elements shown and / or any other characteristics, attributes, properties, etc. of the elements. In addition, in the drawings, the size and relative sizes of the elements may be exaggerated for clarity and / or descriptive purposes. When embodiments can be implemented differently, the specific process sequence can be performed differently from the order described. For example, two processes described in succession can be performed substantially simultaneously or in an order opposite to the order described. In addition, the same figure numbers refer to the same elements.

[0043] When an element or layer is referred to as being "on" another element or layer, "connected to" or "coupled to" another element or layer, the element or layer may be directly on, directly connected to or directly coupled to the other element or layer, or there may be intervening elements or layers. However, when an element or layer is referred to as being "directly on" another element or layer, "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. For this purpose, the term "connected" may refer to a physical connection, an electrical connection and / or a fluid connection with or without intervening elements. In addition, the axis of the first direction DR1, the axis of the second direction DR2 and the axis of the third direction DR3 are not limited to three axes such as the X-axis, the Y-axis and the Z-axis of a rectangular coordinate system, and may be interpreted in a broader sense. For example, the axis of the first direction DR1, the axis of the second direction DR2 and the axis of the third direction DR3 may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purposes of this disclosure, "at least one of A and B" may be understood to mean only A, only B or any combination of A and B. In addition, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0044] Although the terms "first," "second," etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, without departing from the teachings of the present disclosure, the first element discussed below may be referred to as the second element.

[0045] For descriptive purposes, spatially relative terms such as "under," "beneath," "beneath," "down," "over," "upper," "across," "higher," and "side" (e.g., as in "sidewall") may be used herein and thereby describe the relationship of one element to another element(s) as shown in the accompanying drawings. Spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture in addition to the orientations depicted in the accompanying drawings. For example, if the device in the drawings is turned over, elements described as "under" or "beneath" other elements or features would then be oriented "over" the other elements or features. Thus, the term "under" can encompass both above and below orientations. Furthermore, the device may be oriented in other ways (e.g., rotated 90 degrees or at other orientations), and therefore, the spatially relative descriptors used herein should be interpreted accordingly.

[0046] The terms used herein are for the purpose of describing specific embodiments and are not intended to be limiting. Unless the context clearly indicates otherwise, as used herein, the singular forms "a", "an", and "the" are also intended to include the plural forms. In addition, when used in this specification, the terms "comprises, comprising" and / or "includes, including" illustrate the presence of the stated features, wholes, steps, operations, elements, components and / or groups thereof, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof. It is also noted that, as used herein, the terms "substantially", "approximately" and other similar terms are used as terms of approximation rather than terms of degree, and therefore, are used to explain the inherent deviations in measurements, calculations and / or provided values that will be recognized by those of ordinary skill in the art.

[0047] Various embodiments are described herein with reference to cross-sectional and / or exploded views that are schematic representations of embodiments and / or intermediate structures. Thus, variations from the shapes of the illustrations due to, for example, manufacturing techniques and / or tolerances are to be expected. Thus, the embodiments disclosed herein should not necessarily be construed as limited to the shapes of the particular illustrated regions, but are to include deviations in shape due to, for example, manufacturing. In this manner, the regions illustrated in the figures may be schematic in nature, and the shapes of these regions may not reflect the actual shapes of regions of a device, and, therefore, are not necessarily intended to be limiting.

[0048] Unless otherwise defined, all terms (including technical and scientific terms) used in the description have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. In addition, unless explicitly defined herein, terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with the meaning in the context of the relevant technology and should not be interpreted in an overly idealized or overly formalized sense.

[0049] Hereinafter, embodiments will be described with reference to the accompanying drawings.

[0050] Figure 1 is a schematic block diagram of a display panel DP according to an embodiment.

[0051] Reference Figure 1 The display panel DP may include a timing controller TC, a scan driver SDC, a data driver DDC, and pixels PX overlapping the active area AA. In the embodiment, the display panel DP is described as a light-emitting display panel. Light-emitting display panels may include organic light-emitting display panels, inorganic light-emitting display panels, and quantum dot light-emitting display panels. In the embodiment, the organic light-emitting display panel will be described in detail as an example.

[0052] The timing controller TC receives an input image signal, converts the data format of the input image signal to meet the interface specification with the data driver unit DDC, and generates image data D-RGB. The timing controller TC outputs the image data D-RGB and various control signals DCS and SCS.

[0053] The scan driver unit SDC may receive a scan control signal SCS from the timing controller TC. The scan control signal SCS may include, for example, a vertical start signal for initiating operation of the scan driver unit SDC and a clock signal for determining signal output timing. The scan driver unit SDC may generate scan signals and sequentially output the scan signals to the corresponding signal lines SL1 to SLn and GL1 to GLn. Furthermore, the scan driver unit SDC may generate a light emission control signal in response to the scan control signal SCS and output the light emission control signal to the corresponding signal lines LEL1 to LELn.

[0054] Figure 1 The scanning signal and the light-emission control signal are output from a single scanning driving unit SDC, but the embodiment is not limited thereto. In an embodiment, the scanning driving unit may divide, generate, and then output the scanning signal, and may divide, generate, and then output the light-emission control signal. In addition, in an embodiment, the driving circuit that generates and outputs the scanning signal and the driving circuit that generates and outputs the light-emission control signal may be distinguished from each other.

[0055] The data driver unit DDC may receive a data control signal DCS and image data D-RGB from the timing controller TC. The data driver unit DDC may convert the image data D-RGB into data signals and output the data signals to data lines DL1, DL2, ..., and DLm, as described later, where m is a positive integer. The data signals may be analog voltages corresponding to the grayscale values of the image data D-RGB.

[0056] The display panel DP may include a first group of scan lines SL1, SL2, SL3, ..., and SLn, a second group of scan lines GL1, GL2, GL3, ..., and GLn, a third group of scan lines HL1, HL2, HL3, ..., and HLn, emission lines LEL1, LEL2, LEL3, ..., and LELn, data lines DL1 to DLm, a first voltage line PL, a second voltage line RL, and pixels PX, where n is a positive integer. The first group of scan lines SL1 to SLn, the second group of scan lines GL1 to GLn, the third group of scan lines HL1 to HLn, and the emission lines LEL1 to LELn extend in a first direction DR1 and may be arranged in a second direction DR2 intersecting the first direction DR1.

[0057] The data lines DL1 to DLm may be insulated from and intersect the scan lines SL1 to SLn of the first group, the scan lines GL1 to GLn of the second group, the scan lines HL1 to HLn of the third group, and the emission lines LEL1 to LELn of the third group. Each of the plurality of pixels PX may be connected to a corresponding signal line among the plurality of signal lines. The connection relationship between the pixel PX and the signal line may vary depending on the configuration of the driving circuit of the pixel PX.

[0058] The first voltage line PL may receive a first power voltage ELVDD. The second voltage line RL may receive an initialization voltage Vint. The initialization voltage Vint may have a lower level than the first power voltage ELVDD. The second power voltage ELVSS may be applied to the light emitting element OLED (see FIG. 1 ). Figure 2 ). The second power voltage ELVSS may have a lower level than the first power voltage ELVDD.

[0059] According to the present disclosure, a 'conductive pattern' described hereinafter may correspond to at least one of a scan line, a data line, and a power line.

[0060] Pixels PX may include groups that generate light of different colors. For example, a pixel PX may include a red pixel that generates red light, a green pixel that generates green light, and a blue pixel that generates blue light. The light-emitting elements of the red pixel, the green pixel, and the blue pixel may each include light-emitting layers made of different materials.

[0061] The pixel driving unit PDC (see FIG. Figure 2 ) may include a transistor, a capacitor connected (eg, electrically connected) to the transistor, and the above-mentioned conductive pattern. At least one of the scan driving unit SDC and the data driving unit DDC may include a pixel driving unit PDC (see Figure 2 ) transistors formed by the same process.

[0062] The signal lines, pixels PX, scan driver SDC, and data driver DDC described above may be formed on the base layer through a photolithography process. The insulating layer may be formed on the base layer through multiple deposition or coating processes. The insulating layer may be a thin film arranged to correspond to the pixels PX, and some of the multiple insulating layers may include insulating patterns that overlap only with specific conductive patterns. The insulating layer may include an organic layer and / or an inorganic layer.

[0063] Figure 2 is a schematic diagram of an equivalent circuit of a pixel PXij according to an embodiment.

[0064] Figure 2 The scanning lines SL1 to SLn connected to the first group are illustratively shown. Figure 1 ) and is connected to the data lines DL1 to DLm (see Figure 1 ) among the pixels PXij of the j-th data line DLj (for supplying the j-th data signal Dj), where i is an integer greater than or equal to 1 and less than or equal to n, and j is an integer greater than or equal to 1 and less than or equal to m.

[0065] In an embodiment, the pixel driving unit PDC may include first to seventh transistors T1 to T7, a capacitor Cst, and the above-mentioned conductive pattern. In the embodiment, it is described that the first transistor T1, the second transistor T2, and the fifth to seventh transistors T5 to T7 are P-type transistors and the third transistor T3 and the fourth transistor T4 are N-type transistors. However, the embodiment is not limited thereto, and the first to seventh transistors T1 to T7 may be implemented as P-type transistors or N-type transistors. In addition, in another example, at least one of the first to seventh transistors T1 to T7 may be omitted.

[0066] In an embodiment, the first transistor T1 may be a driving transistor, and the second transistor T2 may be a switching transistor. The capacitor Cst may be connected between the first voltage line PL receiving the first power voltage ELVDD and the reference node RD. The capacitor Cst may include a first electrode Cst1 connected to the reference node RD and a second electrode Cst2 connected to the first voltage line PL.

[0067] The first transistor T1 may be connected between the first voltage line PL and one electrode of the light-emitting element OLED. The source S1 of the first transistor T1 may be connected (e.g., electrically connected) to the first voltage line PL. Another transistor may be provided between the source S1 of the first transistor T1 and the first voltage line PL or may be omitted.

[0068] The drain electrode D1 of the first transistor T1 may be connected (e.g., electrically connected) to the first electrode AE of the light-emitting element OLED. Another transistor may be provided between the drain electrode D1 of the first transistor T1 and the first electrode AE of the light-emitting element OLED or may be omitted. The gate electrode G1 of the first transistor T1 may be connected (e.g., electrically connected) to the reference node RD.

[0069] The second transistor T2 may be connected between the j-th data line DLj and the source S1 of the first transistor T1. The source S2 of the second transistor T2 may be connected (e.g., electrically connected) to the j-th data line DLj, and the drain D2 of the second transistor T2 may be connected (e.g., electrically connected) to the source S1 of the first transistor T1. In an embodiment, the gate G2 of the second transistor T2 may be connected (e.g., electrically connected) to the i-th scan line SLi among the scan lines SL1 to SLn of the first group.

[0070] The third transistor T3 may be connected between the reference node RD and the drain D1 of the first transistor T1. The drain D3 of the third transistor T3 may be connected (e.g., electrically connected) to the drain D1 of the first transistor T1, and the source S3 of the third transistor T3 may be connected (e.g., electrically connected) to the reference node RD. In an embodiment, the gate G3 of the third transistor T3 may be connected (e.g., electrically connected) to the scan lines GL1 to GLn of the second group (see Figure 1 ) among the i-th scanning line GLi (for supplying the i-th scanning signal GWNi).

[0071] The fourth transistor T4 may be connected between the reference node RD and the second voltage line RL. The drain D4 of the fourth transistor T4 may be connected (e.g., electrically connected) to the reference node RD, and the source S4 of the fourth transistor T4 may be connected (e.g., electrically connected) to the second voltage line RL. In an embodiment, the gate G4 of the fourth transistor T4 may be connected (e.g., electrically connected) to the scan lines HL1 to HLn of the third group (see Figure 1 ) for supplying the i-th scan signal GIi.

[0072] The fifth transistor T5 may be connected between the first voltage line PL and the source S1 of the first transistor T1. The source S5 of the fifth transistor T5 may be connected (e.g., electrically connected) to the first voltage line PL, and the drain D5 of the fifth transistor T5 may be connected (e.g., electrically connected) to the source S1 of the first transistor T1. The gate G5 of the fifth transistor T5 may be connected (e.g., electrically connected) to the i-th emission line LELi for supplying the i-th emission signal Ei.

[0073] The sixth transistor T6 may be connected between the drain D1 of the first transistor T1 and the light-emitting element OLED. A source S6 of the sixth transistor T6 may be connected (e.g., electrically connected) to the drain D1 of the first transistor T1, and a drain D6 of the sixth transistor T6 may be connected (e.g., electrically connected) to the first electrode AE of the light-emitting element OLED. A gate G6 of the sixth transistor T6 may be connected (e.g., electrically connected) to the i-th light-emitting line LELi.

[0074] The seventh transistor T7 may be connected between the drain D6 of the sixth transistor T6 and the second voltage line RL. The source S7 of the seventh transistor T7 may be connected (e.g., electrically connected) to the drain D6 of the sixth transistor T6, and the drain D7 of the seventh transistor T7 may be connected (e.g., electrically connected) to the second voltage line RL. The gate G7 of the seventh transistor T7 may be connected (e.g., electrically connected) to the (i+1)th scan line SLi+1 for supplying the (i+1)th scan signal GWPi+1 among the scan lines SL1 to SLn of the first group.

[0075] Figure 3A and Figure 3B is a schematic plan view of a display panel DP according to an embodiment.

[0076] Figure 3A and Figure 3B : is a schematic plan view showing a display panel DP according to an embodiment. Figure 3A and Figure 3B In the following, some components are omitted. Figure 3A and Figure 3B The present disclosure is described.

[0077] Reference Figure 3A The display panel DP according to the embodiment may be divided into a display area DA and a peripheral area NDA (or a non-display area). The display area DA may include a light emitting portion EP.

[0078] The light emitting portion EP may be a pixel PXij (see Figure 2) area where light is emitted. For example, each of the plurality of light emitting portions EP may correspond to a light emitting opening OP-PDL (see Figure 5 ), which will be described later. The light emitting opening OP-PDL may be referred to as an opening or an opening portion.

[0079] The peripheral area NDA may be disposed adjacent to the display area DA. In the embodiment, the peripheral area NDA is shown to have a shape surrounding the edge of the display area DA. However, this is shown for illustrative purposes, and the peripheral area NDA may be disposed on one side of the display area DA or may be omitted, and the embodiment is not limited thereto.

[0080] In an embodiment, the scan driver unit SDC may be disposed in the display area DA, and the data driver unit DDC may be disposed in the peripheral area NDA. The scan driver unit SDC may overlap at least some of the plurality of light-emitting portions EP arranged in the display area DA in a plan view. Since the scan driver unit SDC is disposed in the display area DA, the area of the peripheral area NDA can be reduced compared to a display panel according to the related art in which the scan driver unit is disposed in the peripheral area, and a display device with a narrow frame can be easily realized.

[0081] For example, with Figure 3A Unlike the illustration shown in FIG. 1 , the scan driving unit SDC may be provided as two distinct components. The two scan driving units SDC may be spaced apart from each other in the left-right direction (e.g., the first direction DR1), with the center of the display area DA located between the two scan driving units SDC. In another example, the scan driving unit SDC may be provided as three or more scan driving units SDC, but the embodiment is not limited thereto.

[0082] Figure 3A An example of a display panel DP is shown, and the data driving unit DDC may be provided in the display area DA. For example, some of the plurality of light emitting parts EP arranged in the display area DA may overlap with the data driving unit DDC in a plan view.

[0083] In an embodiment, the data driving unit DDC may be provided (or formed) in the form of a separate driving chip independent of the display panel DP and connected to the display panel DP. However, this is described illustratively, and the data driving unit DDC and the scan driving unit SDC may be formed in the same process for forming the display panel DP, but the embodiment is not limited thereto.

[0084] like Figure 3BAs shown in FIG, the length of the display panel DP in the first direction DR1 may be greater than the length of the display panel DP in the second direction DR2. It is illustratively shown that pixels PX11 to PXnm are arranged in n rows and m columns in the display area DA. In an embodiment, the display panel DP may include scan driving units SDC1 and SDC2. It is illustratively shown that the scan driving units SDC1 and SDC2 include a first scan driving unit SDC1 and a second scan driving unit SDC2 spaced apart from each other in the first direction DR1.

[0085] The first scan driving unit SDC1 may be connected to some of the scan lines GL1 to GLn, and the second scan driving unit SDC2 may be connected to the other scan lines GL1 to GLn. For example, the first scan driving unit SDC1 may be connected to odd-numbered scan lines among the scan lines GL1 to GLn, and the second scan driving unit SDC2 may be connected to even-numbered scan lines among the scan lines GL1 to GLn.

[0086] For the convenience of description, Figure 3B The pads PD connected to the data lines DL1 to DLm are shown. The pads PD may be defined at the end portions of the data lines DL1 to DLm. The data lines DL1 to DLm may be connected to the data driving unit DDC (see FIG. Figure 3A ).

[0087] According to an embodiment, the pads PD may be dividedly arranged at positions spaced apart from each other in the peripheral area NDA, with the display area DA interposed therebetween. For example, some of the plurality of pads PD may be arranged on the upper side (for example, on the side adjacent to the first scan line GL1 among the scan lines GL1 to GLn), and other pads PD of the plurality of pads PD may be arranged on the lower side (for example, on the side adjacent to the last scan line GLn among the scan lines GL1 to GLn). In an embodiment, the pads PD connected to the odd-numbered data lines among the data lines DL1 to DLm may be arranged on the upper side, and the pads PD connected to the even-numbered data lines among the data lines DL1 to DLm may be arranged on the lower side.

[0088] For example, the display panel DP may include a plurality of upper data driving units connected to the pads PD arranged on the upper side and / or a plurality of lower data driving units connected to the pads PD arranged on the lower side. However, this is described illustratively, and the display panel DP may also include one upper data driving unit connected to the pads PD arranged on the upper side and / or one lower data driving unit connected to the pads PD arranged on the lower side. The pads PD according to an embodiment may be provided on only one side of the display panel DP and connected to a single data driving unit, but the embodiment is not limited thereto.

[0089] also, Figure 3B The scan driving units SDC1 and SDC2 and / or the data driving unit DDC in the display panel DP may also be as follows: Figure 3A Therefore, some of the plurality of light emitting parts EP arranged in the display area DA may overlap with the scan driving units SDC1 and SDC2 and / or the data driving unit DDC in a plan view.

[0090] Figures 4A to 4C is an enlarged schematic plan view showing a portion of the display panel DP according to the embodiment.

[0091] Figure 4A shows an area in which four light emitting units are arranged in two rows and two columns, and Figure 4B It shows Figure 4A An enlarged schematic diagram of a portion of the area shown in . Figure 4C Omit or emphasize Figure 4A In the following, reference will be made to some of the components shown in Figures 4A to 4C The present disclosure is described.

[0092] Figure 4A The light emitting cells UT11, UT12, UT21, and UT22 in two rows and two columns are shown. The light emitting cells in the first row Rk may include light emitting cells forming the first row and first column light emitting cells UT11 and the first row and second column light emitting cells UT12, and the light emitting cells in the second row Rk+1 may include light emitting cells forming the second row and first column light emitting cells UT21 and the second row and second column light emitting cells UT22. Figure 4B The light emitting cells in the first row Rk are shown. Figures 4A to 4C Shown among components of the display panel DP are a spacer SPR, light emitting parts EP1 , EP2 , and EP3 arranged in regions partitioned by the spacer SPR, connection wirings CN1 , CN2 , and CN3 , a first electrode EL1 , and second electrodes EL2_1 , EL2_2 , and EL2_3 .

[0093] As described above, each of the light emitting portions EP1, EP2, and EP3 may correspond to a light emitting opening OP-PDL to be described later. For example, the light emitting portions EP1, EP2, and EP3 may be regions in which light is emitted by the above-mentioned light emitting elements and may correspond to regions forming a portion displayed on the display panel DP (see FIG. Figure 1 ) in the image. In more detail, the light emitting portions EP1, EP2, and EP3 may correspond to the light emitting openings OP-PDL (see FIG. Figure 5 ) defined by the light emitting opening OP-PDL (for example, an area defined by the lower side of the light emitting opening OP-PDL).

[0094] The light-emitting parts EP1, EP2, and EP3 may include a first light-emitting part EP1, a second light-emitting part EP2, and a third light-emitting part EP3. The first light-emitting part EP1, the second light-emitting part EP2, and the third light-emitting part EP3 may emit light having different colors from each other. For example, the first light-emitting part EP1 may emit red light, the second light-emitting part EP2 may emit green light, and the third light-emitting part EP3 may emit blue light. However, the combination of colors is not limited to this. In addition, at least two of the light-emitting parts EP1, EP2, and EP3 may emit light having the same color. For example, all of the first light-emitting part EP1, the second light-emitting part EP2, and the third light-emitting part EP3 may emit blue light or may emit white light.

[0095] For example, among the light-emitting sections EP1, EP2, and EP3, the third light-emitting section EP3 that emits light emitted by the third light-emitting element may include two sub-light-emitting sections EP31 and EP32 spaced apart from each other in the second direction DR2. However, this is shown for illustrative purposes only, and the third light-emitting section EP3 may be provided as a single pattern having an integral shape like the other light-emitting sections EP1 and EP2, and at least one of the other light-emitting sections EP1 and EP2 may include sub-light-emitting sections spaced apart from each other. However, embodiments are not limited thereto.

[0096] The light-emitting cells in the first row Rk may include light-emitting portions EP1, EP2, and EP3 forming the first-row, first-column light-emitting cell UT11 and the first-row, second-column light-emitting cell UT12, and the light-emitting cells in the second row Rk+1 may include light-emitting portions EP1, EP2, and EP3 forming the second-row, first-column light-emitting cell UT21 and the second-row, second-column light-emitting cell UT22. Some of the plurality of light-emitting cells in the first row Rk and some of the plurality of light-emitting cells in the second row Rk+1 may have symmetrical shapes. The third light-emitting portion EP3 of the second-row, first-column light-emitting cell UT21 and the third light-emitting portion EP3 of the first-row, first-column light-emitting cell UT11 may have shapes and arrangements that are line-symmetrical with respect to an axis parallel to the first direction DR1. However, this is illustrative, and embodiments are not limited thereto.

[0097] Hereinafter, the first row and first column light emitting unit UT11 will be described. Figure 4BThe second electrodes EL2_1, EL2_2, and EL2_3, the pixel drive units PDC1, PDC2, and PDC3, and the connection wirings CN1a, CN1b, CN2a, CN2b, CN3a, and CN3b are shown. The second electrodes EL2_1, EL2_2, and EL2_3 can be separated from each other by a separator SPR and electrically disconnected from each other. In an embodiment, one light-emitting unit UT may include three light-emitting portions EP1, EP2, and EP3. Therefore, the light-emitting unit UT may include three second electrodes EL2_1, EL2_2, and EL2_3, three pixel drive units PDC1, PDC2, and PDC3, and three connection wirings CN1a, CN2a, and CN3a or CN1b, CN2b, and CN3b. However, this is shown illustratively, and the number and arrangement of the light-emitting units UT may be designed differently, and the embodiment is not limited thereto.

[0098] The first pixel driving unit PDC1, the second pixel driving unit PDC2, and the third pixel driving unit PDC3 can be connected (e.g., electrically connected) to the light-emitting element forming the first light-emitting portion EP1, the light-emitting element forming the second light-emitting portion EP2, and the light-emitting element forming the third light-emitting portion EP3, respectively. In the description, the wording "connected" includes not only the case of being connected by direct contact (e.g., physically connected), but also the case of being connected (e.g., electrically connected).

[0099] In addition, if Figure 4B As shown in FIG, the region where the pixel driving units PDC1, PDC2, and PDC3 are defined in a plan view may correspond to the pixel driving unit PDC included in the light emitting element for driving the pixel (see FIG. Figure 2 ) is a unit in which transistor and capacitor elements are repeatedly arranged.

[0100] The first pixel driving unit PDC1, the second pixel driving unit PDC2, and the third pixel driving unit PDC3 may be sequentially arranged in the first direction DR1. For example, the arrangement positions of the first pixel driving unit PDC1, the second pixel driving unit PDC2, and the third pixel driving unit PDC3 may be independently designed, regardless of the positions or shapes of the first light-emitting portion EP1, the second light-emitting portion EP2, and the third light-emitting portion EP3.

[0101] For example, the first pixel driving unit PDC1, the second pixel driving unit PDC2, and the third pixel driving unit PDC3 may be regions separated and defined by a separator SPR (for example, they may be arranged at a position different from the position where the second electrodes EL2_1, EL2_2, and EL2_3 are arranged), or may be designed to have a shape and area different from the shape and area of the second electrodes EL2_1, EL2_2, and EL2_3. In another example, the first pixel driving unit PDC1, the second pixel driving unit PDC2, and the third pixel driving unit PDC3 may be regions that are arranged to overlap with the position where the first light-emitting portion EP1, the second light-emitting portion EP2, and the third light-emitting portion EP3 are provided and separated and defined by a separator SPR, and, for example, may be designed to have a shape and area similar to the shape and area of the second electrodes EL2_1, EL2_2, and EL2_3.

[0102] In an embodiment, the first pixel driving unit PDC1, the second pixel driving unit PDC2 and the third pixel driving unit PDC3 are shown in a rectangular shape, the first light-emitting portion EP1, the second light-emitting portion EP2 and the third light-emitting portion EP3 can be arranged with an area smaller than the area of the first pixel driving unit PDC1, the second pixel driving unit PDC2 and the third pixel driving unit PDC3 and in a shape different from the shape of the first pixel driving unit PDC1, the second pixel driving unit PDC2 and the third pixel driving unit PDC3, and the second electrodes EL2_1, EL2_2 and EL2_3 can be arranged at a position overlapping with the first light-emitting portion EP1, the second light-emitting portion EP2 and the third light-emitting portion EP3 and are shown in an irregular shape.

[0103] Therefore, if Figure 4B As shown in , the first pixel driving unit PDC1 can be set at a position partially overlapping with the first light-emitting portion EP1, the second light-emitting portion EP2 and another adjacent light-emitting portion (plurality of light-emitting portions). The second pixel driving unit PDC2 can be set at a position overlapping with the first light-emitting portion EP1, the second light-emitting portion EP2 and the third light-emitting portion EP3. The third pixel driving unit PDC3 can be set at a position overlapping with the third light-emitting portion EP3. For example, it is illustratively shown that the positions of the first pixel driving unit PDC1, the second pixel driving unit PDC2 and the third pixel driving unit PDC3 can be designed in various shapes and arrangements independently of the light-emitting portions EP1, EP2 and EP3, but the embodiment is not limited thereto.

[0104] The connection wiring CN may be provided as a plurality of connection wirings CN spaced apart from each other. A single connection wiring CN may connect (e.g., electrically connect) any single pixel driving unit PDC among the pixel driving units PDC1, PDC2, and PDC3 and a light emitting element corresponding to the pixel driving unit PDC. For example, the connection wiring CN may correspond to the light emitting element OLED (see FIG. Figure 2 ) is connected to the pixel driving unit PDC (see Figure 2 ) node.

[0105] The connection wiring CN may include a first connection part (or a light emitting connection part CE) and a second connection part (or a driving connection part CD). The light emitting connection part CE may be provided on one side of the connection wiring CN, and the driving connection part CD may be provided on the other side of the connection wiring CN.

[0106] The drive connection component CD may be a portion of the connection wiring CN connected to the pixel driving unit PDC. In an embodiment, the drive connection component CD may be connected to an electrode of a transistor included in the pixel driving unit PDC. Therefore, the position of the drive connection component CD may correspond to the transistor TR (see FIG. 1 ) in the pixel driving unit PDC that is connected (e.g., physically connected) to the connection wiring CN. Figure 6A ) position. The light emitting connection component CE may be a portion of the connection wiring CN connected to the light emitting element. In an embodiment, the light emitting connection component CE may be connected to the second electrode EL2a of the light emitting element (see Figure 6A ).

[0107] The light emitting unit UT may include a first connection wiring CN1, a second connection wiring CN2, and a third connection wiring CN3. The first connection wiring CN1 may connect the light emitting elements forming the first light emitting portion EP1 to the first pixel driving unit PDC1, the second connection wiring CN2 may connect the light emitting elements forming the second light emitting portion EP2 to the second pixel driving unit PDC2, and the third connection wiring CN3 may connect the light emitting elements forming the third light emitting portion EP3 to the third pixel driving unit PDC3.

[0108] For example, the first connection wiring CN1 and the second connection wiring CN2 can connect the second electrodes EL2_1 and EL2_2 and the first pixel driving unit PDC1 and the second pixel driving unit PDC2, respectively. The third connection wiring CN3 can connect the first electrode EL1_3 and the third pixel driving unit PDC3. The first connection wiring CN1 may include a first drive connection component CD1 connected to the first pixel driving unit PDC1 and a first light-emitting connection component CE1 connected to the (2-1)th electrode EL2_1. The second connection wiring CN2 may include a second drive connection component CD2 connected to the second pixel driving unit PDC2 and a second light-emitting connection component CE2 connected to the (2-2)th electrode EL2_2. The third connection wiring CN3 may include a third drive connection component CD3 connected to the third pixel driving unit PDC3 and a third light-emitting connection component CE3 connected to the (1-3)th electrode EL1_3.

[0109] The first drive connection component CD1, the second drive connection component CD2, and the third drive connection component CD3 can be aligned in the first direction DR1. As described above, the first drive connection component CD1, the second drive connection component CD2, and the third drive connection component CD3 can correspond to the positions of the connection transistors included in the first pixel drive unit PDC1, the second pixel drive unit PDC2, and the third pixel drive unit PDC3. The connection transistor can be a transistor including an electrode as a connection node, at which the pixel drive unit PDC and the light-emitting element are connected to each other in a single pixel. According to an embodiment, regardless of the shape or size of the light-emitting portion and the color of the light, the shape, position, and arrangement of the pixel drive units PDC of all pixels can be simply configured and designed.

[0110] In the embodiment, the first light-emitting connection part CE1, the second light-emitting connection part CE2, and the third light-emitting connection part CE3 may be arranged at a position that does not overlap with the light-emitting portions EP1, EP2, and EP3 in a plan view. As described above, each of some of the light-emitting connection parts CE1 and CE2 among the light-emitting connection parts CE1, CE2, and CE3 of the connection wiring CN may be a light-emitting element LDa (see FIG. Figure 6A ) is connected to the portion where the tip portion TP is defined (see Figure 6A ) portion, and may be provided without contact with the light emitting opening OP-PDLa (see Figure 6A ) overlap.

[0111] The light emitting connection components CE1, CE2, and CE3 may be arranged at positions of the second electrodes EL2_1, EL2_2, and EL2_3 that are spaced apart from the light emitting portions EP1, EP2, and EP3. Furthermore, some of the second electrodes EL2_1, EL2_2, and EL2_3 may include partial regions that protrude from the light emitting portions EP1 and EP2 in a plan view, for connection to the connection wirings CN1 and CN2 at positions where the light emitting connection components CE1 and CE2 are provided.

[0112] For example, the (2-1)th electrode EL2_1 may include a protruding portion having a shape protruding from the first light-emitting portion EP1 at a position not overlapping with the first light-emitting portion EP1, for connecting to the first connection wiring CN1 at a position where the first light-emitting connection component CE1 is provided, and the first light-emitting connection component CE1 may be provided (or formed) in the protruding portion of the (2-1)th electrode EL2_1.

[0113] In addition, the first connection wiring CN1 is connected to the transistor TR (see Figure 6A ) is located at a position where the first pixel driving unit PDC1 (for example, the first driving connection part CD1) may be limited to a position that does not overlap with the first light emitting portion EP1 in a plan view. According to an embodiment, the first connection wiring CN1 may be provided in the first light emitting portion EP1, and thus the (2-1)th electrode EL2_1 and the first pixel driving unit PDC1, which are spaced apart from each other, may be easily connected to each other.

[0114] The second power voltage ELVSS (see Figure 2 ) can be applied to the (1-1)th electrode EL1_1 and the (1-2)th electrode EL1_2. The first power voltage ELVDD (see Figure 2 ) can be applied to the (1-3)th electrode EL1_3.

[0115] Return to reference Figure 4A, the light-emitting cells in the second row Rk+1 may be light-emitting cells having shapes and arrangements that are line-symmetrical with respect to an axis parallel to the first direction DR1 or the second direction DR2, with respect to the first-row, first-column light-emitting cells UT11 and the first-row, second-column light-emitting cells UT12. For example, due to the characteristics of the shapes and arrangements of the first-row, first-column light-emitting cells UT11 and the first-row, second-column light-emitting cells UT12, the second-row, first-column light-emitting cells UT21 and the second-row, second-column light-emitting cells UT22 may be light-emitting cells that are substantially shifted in the first direction DR1 or the second direction DR2, with respect to the first-row, first-column light-emitting cells UT11 and the first-row, second-column light-emitting cells UT12. For example, the second-row, first-column light-emitting cells UT21 may be light-emitting cells having the same shape as the first-row, second-column light-emitting cells UT12, and the second-row, second-column light-emitting cells UT22 may be light-emitting cells having the same shape as the first-row, first-column light-emitting cells UT11.

[0116] Therefore, the shape and arrangement of the connection wiring CN-c arranged in the second row and first column light emitting cell UT21 can be different from the shape and arrangement of the connection wiring CN1b, CN2b and CN3b arranged in the first row and second column light emitting cell UT12 (see FIG. Figure 4B For example, the shape and arrangement of the connection wiring CN-d arranged in the second row and second column light emitting unit UT22 may be the same as the shape and arrangement of the connection wiring CN1a, CN2a and CN3a arranged in the first row and first column light emitting unit UT11 (see FIG. Figure 4B ) are of the same shape and arrangement.

[0117] However, the embodiment is not limited to the illustration of the drawings, the third connection wiring CN3 may be arranged differently, and the embodiment is not limited thereto.

[0118] Reference Figure 4C The first electrodes EL1 of the light emitting elements according to the embodiment may be commonly provided (or formed) on the first light emitting portion EP1 (see Figure 4B ) and the second light emitting portion EP2 (see Figure 4B ) and can be independently provided (or formed) in the third light emitting portion EP3 (see Figure 4B For example, the layer of the first electrode EL1 provided (or formed) in the first and second light emitting parts EP1 and EP2 may be disposed to overlap with the partition SPR, and the layer of the first electrode EL1 provided (or formed) in the third light emitting part EP3 may not overlap with the partition SPR.

[0119] In another example, the first electrode EL1 of the light emitting element may be formed as independent conductive patterns spaced apart from each other and may be connected to each other (eg, electrically connected) through another conductive layer, and thus, all patterns of the first electrode EL1 may be arranged not to overlap with the partition SPR.

[0120] The second power voltage ELVSS (see Figure 2 ) can be applied to the (1-1)th electrode EL1_1 and the (1-2)th electrode EL1_2. The second power voltage ELVSS (see Figure 2 ) can be applied to the (2-3)th electrode EL2_3 (see Figure 4B ).

[0121] For example, according to an embodiment, an opening may be defined in the (1-1)th electrode EL1_1 and the (1-2)th electrode EL1_2, and the opening may pass through the layer of the (1-1)th electrode EL1_1 and the (1-2)th electrode EL1_2. The opening formed in the layer of the (1-1)th electrode EL1_1 and the (1-2)th electrode EL1_2 may be arranged at a position that does not overlap with the light emitting portion EP and may be substantially defined at a position that overlaps with the partition SPR. The opening may facilitate (or utilize) the organic layer (e.g., the sixth insulating layer 60 (see FIG. 1 )) disposed below the (1-1)th electrode EL1_1 and the (1-2)th electrode EL1_2. Figure 5 )) The gas generated by the display panel DP is discharged. Therefore, in the process of manufacturing the display panel DP, the gas in the organic layer provided below the light emitting element can be sufficiently discharged, and after manufacturing, the gas discharged from the organic layer can be reduced, and thus the degradation rate of the light emitting element can be reduced.

[0122] According to the embodiment, since the connection wiring CN (see Figure 4A ) is included in the light emitting element and the pixel driving unit PDC (see Figure 2 ), so the light emitting element can be easily connected to the pixel driving unit PDC without changing the arrangement or shape of the light emitting portion by changing only the shape of the anode or cathode. Therefore, the degree of freedom for the arrangement of the pixel driving unit PDC can be improved, and the display panel DP (see FIG. Figure 1 )'s light-emitting portion.

[0123] Figure 5 is a schematic cross-sectional view of a display panel DP according to an embodiment.

[0124] Reference Figure 5 The display panel DP may include a base layer BL, a driving element layer DDL, a light emitting element layer LDL (see Figure 6A), encapsulation layer ECL, and sensing layer ISL. The driving element layer DDL may include insulating layers 10, 20, 30, 40, and 50 arranged on the base layer BL, and conductive patterns and semiconductor patterns arranged between the insulating layers 10, 20, 30, 40, and 50. The conductive patterns and semiconductor patterns may be arranged between the insulating layers 10, 20, 30, 40, and 50 to form a pixel driving unit PDC. Each layer will be described in detail below.

[0125] The display panel DP may include a first area AA1, a second area AA2, and a third area AA3. The first to third areas AA1 to AA3 may be divided by spacers SPR.

[0126] The first area AA1 may overlap with the first light emitting element LD1. The first area AA1 may overlap with the first light emitting opening OP1-PDL, and at least a portion of the first light emitting element LD1 may be exposed through the first light emitting opening OP1-PDL. The first light emitting element LD1 may include a light emitting material that generates red light or green light.

[0127] The second area AA2 may overlap with the second light emitting element LD2. The second area AA2 may overlap with the second light emitting opening OP2-PDL, and at least a portion of the second light emitting element LD2 may be exposed through the second light emitting opening OP2-PDL. The second light emitting element LD2 may include a light emitting material that generates green light or red light.

[0128] The third area AA3 may overlap with the third light emitting element LD3. The third area AA3 may overlap with the third light emitting opening OP3-PDL, and at least a portion of the third light emitting element LD3 may be exposed through the third light emitting opening OP3-PDL. The third light emitting element LD3 may include a light emitting material that generates blue light.

[0129] The arrangement relationship between the components of the first light-emitting element LD1 provided in the first area AA1 may be substantially the same as the arrangement relationship between the components of the second light-emitting element LD2 provided in the second area AA2. The arrangement relationship between the components of the first light-emitting element LD1 provided in the first area AA1 may be different from the arrangement relationship between the components of the third light-emitting element LD3 provided in the third area AA3.

[0130] For example, referring to the region LD1-A of the first light emitting element LD1 overlapping with the first light emitting opening OP1-PDL and the region LD2-A of the second light emitting element LD2 overlapping with the second light emitting opening OP2-PDL shown in the drawings, as will be described later. Figure 6A As described in the (1-1) electrode EL1_1 (see Figure 4C) (or the first electrode EL1a) and the (1-2)th electrode EL1_2 (see Figure 4C ) (or the first electrode EL1a) may be a cathode and the (2-1)th electrode EL2_1 (or the second electrode EL2a) and the (2-2)th electrode EL2_2 (see Figure 4B ) (or the second electrode EL2a) may be an anode. Referring to the region LD3-A of the third light emitting element LD3 that overlaps with the third light emitting opening OP3-PDL, as will be described later. Figure 7 As described in, the (1-3) electrode EL1_3 (see Figure 4C ) (or the first electrode EL1b) may be an anode, and the (2nd-3rd) electrode EL2_3 (see Figure 4B ) (or the second electrode EL2b) can be a cathode.

[0131] Refer to it together Figure 4C , the (1-1) electrode EL1_1 (or first cathode) of the first light emitting element LD1 and the second electrode EL2a (or second cathode) of the second light emitting element LD2 can be connected to each other, and the second electrode EL2b (or third cathode) of the third light emitting element LD3 can be separated from the first cathode of the first light emitting element LD1 and the second cathode of the second light emitting element LD2 in a plan view.

[0132] In addition, the embodiment is not limited thereto, and on a cross section parallel to the third direction DR3, the first connection opening OP1-CE in the first area AA1 and the second connection opening OP2-CE in the second area AA2 have similar cross-sectional shapes, but the connection opening may not be provided in the third area AA3.

[0133] For example, the arrangement relationship and shapes between the components of the first area AA1 and the components of the third area AA3 may be different from each other, and this will be described later.

[0134] Figures 6A to 6C is an enlarged schematic cross-sectional view of a portion of the display panel DP according to the embodiment. Figure 6A yes Figure 5 , which is an enlarged schematic cross-sectional view of a portion of the first area AA1 or a portion of the second area AA2 shown in FIG. Figure 6B yes Figure 6A An enlarged schematic cross-sectional view of a portion F6b shown in FIG. Figure 6C yes Figure 6A An enlarged schematic cross-sectional view of a portion F6c shown in FIG.

[0135] Reference Figure 6AThe base layer BL may be a member that provides a base surface on which the pixel driving unit PDCa is disposed. The base layer BL may be a rigid substrate or a flexible substrate that is bendable, foldable, and rollable. The base layer BL may be a glass substrate, a metal substrate, a polymer substrate, or the like. However, the embodiment is not limited thereto, and the base layer BL may also be an inorganic layer, an organic layer, or a composite material layer.

[0136] The base layer BL may have a multi-layer structure. The base layer BL may include a first polymer resin layer, a silicon oxide (SiO x ) layer, an amorphous silicon (a-Si) layer disposed on the silicon oxide layer, and a second polymer resin layer disposed on the amorphous silicon layer. The silicon oxide layer and the amorphous silicon layer may be referred to as a substrate barrier layer.

[0137] The polymer resin layer may include a polyimide resin. In addition, the polymer resin layer may include at least one of an acrylate resin, a methacrylate resin, a polyisoprene resin, a vinyl resin, an epoxy resin, a urethane resin, a cellulose resin, a siloxane resin, a polyamide resin, and a perylene resin. In the description, the "~~" resin means a resin containing a functional group of "~~".

[0138] The insulating layer, the conductive layer, and the semiconductor layer disposed on the base layer BL may be formed by a coating process and / or a deposition process. Thereafter, the insulating layer, the semiconductor layer, and the conductive layer may be selectively patterned by a photolithography process, so that a hole may be formed in the insulating layer or a semiconductor pattern, a conductive pattern, a signal line, etc. may be formed.

[0139] The driving element layer DDL may include a first insulating layer 10 , a second insulating layer 20 , a third insulating layer 30 , a fourth insulating layer 40 , and a fifth insulating layer 50 sequentially stacked on the base layer BL, and a pixel driving unit PDCa. Figure 6A The transistor TR and two capacitors C1 and C2 of the pixel driving unit PDCa are shown. The pixel driving unit PDCa can be Figure 5 ) is connected (eg, electrically connected) to the first light emitting element LD1 (see FIG. Figure 5 ) of the first pixel driving unit PDC1 (see Figure 5 ) or connected (eg, electrically connected) to the second light emitting element LD2 (see Figure 5 ) of the second pixel driving unit PDC2 (see Figure 5 ).

[0140] The transistor TR may correspond to a transistor connected to the light emitting element LDa through the connection wiring CNa (for example, a connection transistor connected to a node corresponding to the anode of the light emitting element LDa). For example, other transistors included in the pixel driving unit PDCa may have the same Figure 6A However, this is described illustratively, and other transistors included in the pixel driving unit PDCa may have the same structure as the transistor TR shown in FIG. Figure 6A The structure of the transistor TR shown in FIG. 1 is different from that of FIG. 1 , and the embodiment is not limited thereto.

[0141] The first insulating layer 10 may be provided on the base layer BL. The first insulating layer 10 may be an inorganic layer and / or an organic layer and may have a single-layer structure or a multi-layer structure. The first insulating layer 10 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. In the embodiment, the first insulating layer 10 is shown as a single silicon oxide layer. For example, the insulating layer to be described later may be an inorganic layer and / or an organic layer and may have a single-layer structure or a multi-layer structure. The inorganic layer may include at least one of the above materials, but the embodiment is not limited thereto.

[0142] For example, the first insulating layer 10 may cover the lower conductive layer BCL. For example, the display panel DP may further include a lower conductive layer BCL disposed so as to overlap the transistor TR. The lower conductive layer BCL may prevent the potential caused by the polarization of the base layer BL from affecting the transistor TR. Furthermore, the lower conductive layer BCL may block light incident on the transistor TR from the bottom. At least one of an inorganic barrier layer and a buffer layer may also be disposed between the lower conductive layer BCL and the base layer BL.

[0143] The lower conductive layer BCL may include a reflective metal. For example, the lower conductive layer BCL may include titanium (Ti), molybdenum (Mo), a molybdenum-containing alloy, aluminum (Al), an aluminum-containing alloy, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), or copper (Cu).

[0144] In an embodiment, the lower conductive layer BCL can be connected to the drain of the transistor TR through the drain electrode pattern W1. For example, the lower conductive layer BCL can be synchronized with the drain of the transistor TR. However, this is shown illustratively, and the lower conductive layer BCL can be connected to the gate of the transistor TR and synchronized with the gate. In another example, the lower conductive layer BCL can be connected to another electrode to independently receive a constant voltage or pulse signal. In another example, the lower conductive layer BCL can be provided (or formed) in a form isolated from other conductive patterns. The lower conductive layer BCL according to the embodiment can be provided (or formed) in various forms and is not limited to the embodiment.

[0145] The transistor TR may be disposed on the first insulating layer 10. The transistor TR may include a semiconductor pattern SP and a gate electrode GE. The semiconductor pattern SP may be disposed on the first insulating layer 10. The semiconductor pattern SP may include an oxide semiconductor. For example, the oxide semiconductor may include a transparent conductive oxide (TCO) such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), or indium oxide (In2O3). However, the embodiment is not limited thereto, and the semiconductor pattern SP may include amorphous silicon, low-temperature polysilicon, or polycrystalline silicon.

[0146] The semiconductor pattern SP may include a source region SR, a drain region DR, and a channel region CR, each differentiated by its degree of conductivity. The channel region CR may be a portion overlapping the gate electrode GE in a plan view. The source region SR and the drain region DR may be portions spaced apart from each other, with the channel region CR interposed therebetween. If the semiconductor pattern SP is an oxide semiconductor, the source region SR and the drain region DR may be reduced regions. Therefore, the source region SR and the drain region DR may have a relatively high reduced metal content compared to the channel region CR. In another example, if the semiconductor pattern SP is polycrystalline silicon, the source region SR and the drain region DR may be regions doped at a high concentration.

[0147] The source region SR and the drain region DR may have relatively higher conductivity than that of the channel region CR. The source region SR may correspond to a source electrode of the transistor TR, and the drain region DR may correspond to a drain electrode of the transistor TR. Figure 6A As shown in FIG, a separate drain electrode pattern W1 and a separate source electrode pattern W2 connected to the drain region DR and the source region SR, respectively, may also be provided. For example, the separate drain electrode pattern W1 and the separate source electrode pattern W2 may be formed with the pixel driving unit PDC (see FIG. Figure 2 ) is integral (or integrally formed), and the embodiment is not limited thereto.

[0148] The second insulating layer 20 may overlap with the pixels and cover the semiconductor pattern SP. The second insulating layer 20 may be an inorganic layer and / or an organic layer and may have a single-layer structure or a multi-layer structure. The second insulating layer 20 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. In an embodiment, the second insulating layer 20 may be a single-layer silicon oxide layer.

[0149] The gate electrode GE may be disposed on the second insulating layer 20. The gate electrode GE may correspond to the gate of the transistor TR. In addition, the gate electrode GE may be disposed above the semiconductor pattern SP. However, this is illustratively shown, and the gate electrode GE may be disposed below the semiconductor pattern SP, and the embodiment is not limited thereto.

[0150] The gate electrode GE may include titanium (Ti), silver (Ag), molybdenum (Mo), aluminum (Al), aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), or an alloy thereof, but the embodiment is not limited thereto.

[0151] The third insulating layer 30 may be provided on the gate electrode GE. The third insulating layer 30 may be an inorganic layer and / or an organic layer and may have a single-layer structure or a multi-layer structure. The fourth insulating layer 40 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide.

[0152] The first capacitor electrode CPE1 and the second capacitor electrode CPE2 among the drain electrode pattern W1, the source electrode pattern W2, the first capacitor electrode CPE1, the second capacitor electrode CPE2, and the third capacitor electrode CPE3 may form a first capacitor C1. The first capacitor electrode CPE1 and the second capacitor electrode CPE2 may be spaced apart from each other with the first insulating layer 10 and the second insulating layer 20 interposed therebetween.

[0153] In an embodiment, the first capacitor electrode CPE1 and the lower conductive layer BCL may have an integral shape. In addition, the second capacitor electrode CPE2 and the gate electrode GE may have an integral shape.

[0154] The third capacitor electrode CPE3 may be disposed on the third insulating layer 30. The third capacitor electrode CPE3 may be spaced apart from the second capacitor electrode CPE2 with the third insulating layer 30 interposed therebetween. The third capacitor electrode CPE3 and the second capacitor electrode CPE2 may overlap in plan view. The third capacitor electrode CPE3 and the second capacitor electrode CPE2 may form a second capacitor C2.

[0155] The fourth insulating layer 40 may be disposed on the third insulating layer 30 and / or the third capacitor electrode CPE3. The fourth insulating layer 40 may be an inorganic layer and / or an organic layer and may have a single-layer structure or a multi-layer structure. The fourth insulating layer 40 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide.

[0156] A drain electrode pattern W1 and a source electrode pattern W2 may be disposed on the fourth insulating layer 40. The drain electrode pattern W1 may be connected to the drain region DR of the transistor TR through a first contact hole CNT1, and the drain electrode pattern W1 and the drain region DR of the semiconductor pattern SP may function as the drain of the transistor TR. The source electrode pattern W2 may be connected to the source region SR of the transistor TR through a second contact hole CNT2, and the source electrode pattern W2 and the source region SR of the semiconductor pattern SP may function as the source of the transistor TR. A fifth insulating layer 50 may be disposed on the drain electrode pattern W1 and the source electrode pattern W2.

[0157] The connection wiring CNa may be provided on the fifth insulating layer 50. The connection wiring CNa may connect (e.g., electrically connect) the pixel driving unit PDCa and the light-emitting element LDa. For example, the connection wiring CNa may connect (e.g., electrically connect) the transistor TR and the light-emitting element LDa. The connection wiring CNa may be a connection node connecting the pixel driving unit PDCa and the light-emitting element LDa. Depending on the design of the pixel driving unit PDCa, the connection wiring CNa may be defined as a node connected to various elements among the elements included in the pixel driving unit PDCa, as long as the connection wiring CNa can be connected to the light-emitting element LDa, and the embodiment is not limited thereto.

[0158] The sixth insulating layer 60 may be provided on the connection wiring CNa. The sixth insulating layer 60 may be provided on the fifth insulating layer 50 to cover the connection wiring CNa. The fifth insulating layer 50 and the sixth insulating layer 60 may be organic layers. For example, each of the fifth insulating layer 50 and the sixth insulating layer 60 may include a polymer such as benzocyclobutene (BCB), hexamethyldisiloxane (HMDSO), polymethyl methacrylate (PMMA), and polystyrene (PS), a polymer derivative having a phenolic group, an acrylic polymer, an imide polymer such as polyimide, an aryl ether polymer, an amide polymer, a fluorine-containing polymer, a paraxylene polymer, a vinyl alcohol polymer, and a blend thereof.

[0159] An opening through which at least a portion of the connection wiring CNa is exposed may be provided (or formed) in the sixth insulating layer 60. The connection wiring CNa may be connected (e.g., electrically connected) to the light-emitting element LDa via the at least a portion of the connection wiring CNa exposed from the sixth insulating layer 60. For example, the connection wiring CNa may connect (e.g., electrically connect) the transistor TR and the light-emitting element LDa. This will be described in detail later. For example, in the display panel DP according to the embodiment, the sixth insulating layer 60 may be omitted or may be provided as a plurality of sixth insulating layers 60, but the embodiment is not limited thereto.

[0160] The light-emitting element layer LDL may be disposed on the sixth insulating layer 60. The light-emitting element layer LDL may include a pixel-defining layer PDL, a light-emitting element LDa, and a spacer SPR. The pixel-defining layer PDL may be an organic film. For example, the pixel-defining layer PDL may include polymers such as BCB, HMDSO, PMMA, and PS, polymer derivatives having phenolic groups, acrylic polymers, imide polymers such as polyimide, aryl ether polymers, amide polymers, fluorine-containing polymers, paraxylene polymers, vinyl alcohol polymers, and blends thereof.

[0161] In an embodiment, the pixel defining layer (PDL) may have a light-absorbing property and may have a color such as black. For example, the pixel defining layer (PDL) may include a black colorant. The black colorant may include a black dye and a black pigment. The black colorant may include carbon black, a metal such as chromium, or an oxide of the metal. The pixel defining layer (PDL) may include a light-shielding pattern having light-shielding properties.

[0162] An opening OP-PDLa (hereinafter, referred to as a light emitting opening OP-PDLa) may be defined in the pixel defining film PDL, through which at least a portion of the first electrode EL1a to be described later is exposed. The light emitting opening OP-PDLa may be provided as a plurality of light emitting openings OP-PDLa arranged to correspond to a plurality of light emitting elements, respectively. All components of the light emitting element LDa may be arranged to overlap with the light emitting opening OP-PDLa, and the light emitting opening OP-PDLa may be a region in which light emitted by the light emitting element LDa is substantially emitted. Therefore, the light emitting portion EP (see Figure 3A ) can basically correspond to the shape of the light-emitting opening OP-PDLa in a plan view.

[0163] The light-emitting element LDa may include a first electrode EL1a, an intermediate layer IMLa, and a second electrode EL2a. The first electrode EL1a may be a semi-transmissive electrode, a transmissive electrode, or a reflective electrode. According to an embodiment, the first electrode EL1a may include a reflective layer formed of silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a compound thereof, and a transparent electrode layer or a semi-transparent electrode layer formed on the reflective layer. The transparent electrode layer or the semi-transparent electrode layer may include at least one selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), gallium zinc oxide (IGZO), zinc oxide (ZnO), indium oxide (In2O3), and aluminum-doped zinc oxide (AZO). For example, the first electrode EL1a may have a stacked structure of ITO / Ag / ITO.

[0164] The light emitting element LDa can be Figure 5 The first light emitting element LD1 or the second light emitting element LD2 described in .

[0165] In an embodiment, the first electrode EL1a may be a cathode of the light emitting element LDa. For example, the second power voltage ELVSS (see Figure 2 ) may be applied to the first electrode EL1a. The second electrode EL2a may be an anode of the light emitting element LDa.

[0166] exist Figure 6A In the cross-sectional view of FIG, it is shown that the first electrode EL1a overlaps with the light emitting opening OP-PDL and does not overlap with the partition SPR. However, as described above in Figure 4C As shown in Figure 6A The (1-1)th electrode EL1_1 corresponding to the first electrode EL1a of the light emitting element LDa may have an integral shape and may have a mesh shape or a lattice shape in which an opening is defined in a partial area of the first electrode EL1a. For example, when the same second power voltage ELVSS (see Figure 2 ), the shape of the first electrode EL1a may be variously provided, and the embodiment is not limited thereto.

[0167] The first electrode EL1a may be connected to the power connection wiring CN-1. The second power voltage ELVSS (see Figure 2 ) can be applied to the first electrode EL1a through the power connection wiring CN-1. The first layer L1-1, the second layer L2-1 and the third layer L3-1 of the power connection wiring CN-1 can have the same connection with the connection wiring CNa (the first connection wiring CN1 (see Figure 4A ))The physical properties of the first layer L1, the second layer L2 and the third layer L3 are the same physical properties.

[0168] The intermediate layer IMLa may be disposed between the first electrode EL1a and the second electrode EL2a. The intermediate layer IMLa may include a light-emitting layer EMLa and a functional layer FNLa. The light-emitting element LDa may include the intermediate layer IMLa having various structures, and the embodiment is not limited thereto. For example, the functional layer FNLa may be provided as two or more layers spaced apart from each other with the light-emitting layer EMLa interposed therebetween. In another example, the functional layer FNLa may be omitted.

[0169] The light-emitting layer EMLa may include an organic light-emitting material. Alternatively, the light-emitting layer EMLa may include an inorganic light-emitting material or may be provided as a mixed layer of an organic light-emitting material and an inorganic light-emitting material. In an embodiment, the light-emitting layer EMLa included in each of adjacent light-emitting portions EP may include a light-emitting material that displays a different color. Figure 6AThe light emitting layer EMLa shown in FIG can provide red light or green light. However, the embodiment is not limited thereto, and all the light emitting layers EMLa arranged in the light emitting portion EP can include light emitting materials that display the same color. For example, the light emitting layer EMLa can provide blue light or white light. In addition, Figure 5 , wherein the light emitting layer EMLa and the functional layer FNLa have different shapes. However, the embodiment is not limited thereto, and the light emitting layer EMLa and the functional layer FNLa may be arranged in the same shape in a plan view.

[0170] The functional layer FNLa can be provided between the first electrode EL1a and the second electrode EL2a. For example, the functional layer FNLa can be provided between the first electrode EL1a and the light-emitting layer EMLa, or between the second electrode EL2a and the light-emitting layer EMLa. In another example, the functional layer FNLa can be provided both between the first electrode EL1a and the light-emitting layer EMLa and between the second electrode EL2a and the light-emitting layer EMLa. In the embodiment, the light-emitting layer EMLa is shown embedded in the functional layer FNLa. However, this is shown for illustrative purposes only, and the functional layer FNLa may include a layer provided between the light-emitting layer EMLa and the first electrode EL1a and / or a layer provided between the light-emitting layer EMLa and the second electrode EL2a, and may be provided as a plurality of functional layers FNLa, and the embodiment is not limited thereto.

[0171] The functional layer FNLa can control the movement of charges between the first electrode EL1a and the second electrode EL2a. The functional layer FNLa may include a hole injection / transport material and / or an electron injection / transport material. The functional layer FNLa may include at least one of an electron blocking layer, a hole transport layer, a hole injection layer, a hole blocking layer, an electron transport layer, an electron injection layer, and a charge generation layer. This will be discussed later. Figure 8A and Figure 8B Described in detail in.

[0172] The second electrode EL2a may be provided on the intermediate layer IMLa. As described above, the second electrode EL2a may be connected to the connection wiring CNa and connected (e.g., electrically connected) to the pixel driving unit PDCa. For example, the second electrode EL2a may be connected (e.g., electrically connected) to the transistor TR via the connection wiring CNa.

[0173] As described above, the connection wiring CNa may include a driving connection component CDa and a light-emitting connection component CEa. The driving connection component CDa may be a portion of the connection wiring CNa connected to the pixel driving unit PDCa (specifically, a portion of the connection wiring CNa substantially connected to the transistor TR). In an embodiment, the driving connection component CDa may be connected (e.g., electrically connected) to the source region SR of the semiconductor pattern SP through the source electrode pattern W2 and through the fifth insulating layer 50. The light-emitting connection component CEa may be a portion of the connection wiring CNa connected to the light-emitting element LDa. The light-emitting connection component CEa may be a portion defined in an area exposed from the sixth insulating layer 60 and to which the second electrode EL2a is connected. For example, a tip portion TP may be defined in the light-emitting connection component CEa.

[0174] Reference Figure 6A and Figure 6B , the light emitting connection component CEa of the connection wiring CNa will be described in more detail. Figure 6A and Figure 6B As shown in , the connection wiring CNa may have a three-layer structure. For example, the connection wiring CNa may include a first layer L1, a second layer L2, and a third layer L3 sequentially stacked in the third direction DR3. The second layer L2 may include a material different from that of the first layer L1. In addition, the second layer L2 may include a material different from that of the third layer L3. The second layer L2 may have a thickness relatively greater than that of the first layer L1. In addition, the second layer L2 may have a thickness relatively greater than that of the third layer L3. The second layer L2 may include a material having high electrical conductivity. In an embodiment, the second layer L2 may include aluminum (Al).

[0175] For example, the first layer L1 may include a material having an etching rate lower than that of the second layer L2. For example, the second layer L2 may be made of a material having a high etching selectivity relative to the first layer L1. In an embodiment, the first layer L1 may include titanium (Ti), and the second layer L2 may include aluminum (Al). For example, the side surface L1_W of the first layer L1 may be defined outside the side surface L2_W of the second layer L2. For example, the light-emitting connection part CEa of the connection wiring CNa may have a shape in which the side surface L1_W of the first layer L1 protrudes outward from the side surface L2_W of the second layer L2. For example, the light-emitting connection part CEa of the connection wiring CNa may have a shape in which the side surface L2_W of the second layer L2 is recessed inward from the side surface L1_W of the first layer L1.

[0176] In addition, the third layer L3 may include a material having an etching rate lower than that of the second layer L2. In an embodiment, the third layer L3 may include titanium (Ti), and the second layer L2 may include aluminum (Al). For example, the side surface L3_W of the third layer L3 may be defined outside the side surface L2_W of the second layer L2. For example, the light-emitting connection part CEa of the connection wiring CNa may have a shape in which the side surface L3_W of the third layer L3 protrudes outward from the side surface L2_W of the second layer L2. For example, the light-emitting connection part CEa of the connection wiring CNa may have an undercut shape or an overhang structure, and the tip portion TP of the light-emitting connection part CEa may be defined by a portion of the third layer L3 protruding from the second layer L2.

[0177] The sixth insulating layer 60 and the pixel defining film PDL may expose at least a portion of the tip portion TP and at least a portion of the side surface L2_W. A portion of the connection wiring CNa may overlap with the connection opening OP-CE. For example, a first opening OP1 may be defined in the sixth insulating layer 60, through which one side of the connection wiring CNa is exposed, and a second opening OP2 may be defined in the pixel defining film PDL that overlaps with the first opening OP1. The planar area of the second opening OP2 may be greater than the planar area of the first opening OP1. However, the embodiment is not limited thereto, and the planar area of the second opening OP2 may be less than or equal to the planar area of the first opening OP1, as long as at least a portion of the tip portion TP and at least a portion of the side surface L2_W of the second layer L2 can be exposed.

[0178] The intermediate layer IMLa may be provided on the pixel definition film PDL. The intermediate layer IMLa may also be provided on a portion of the sixth insulating layer 60 exposed by the second opening OP2 of the pixel definition film PDL. In addition, the intermediate layer IMLa may also be provided on a portion of the connection wiring CNa exposed by the first opening OP1 of the sixth insulating layer 60. Figure 6B As shown in FIG, the intermediate layer IMLa may include an end portion IN1 provided along the upper surface of the fifth insulating layer 50 and another end portion IN2 provided along the upper surface of the connection wiring CNa and the upper surface of the tip portion TP. For example, when viewed in cross section, the intermediate layer IMLa may have a shape that is partially disconnected relative to the tip portion TP in the region where the light emitting connection part CEa is defined. However, in a plan view, the intermediate layer IMLa may be partially disconnected in the region defined as a closed line by the partition SPR (see FIG. Figure 4A ) has an integral shape connected as a whole.

[0179] The second electrode EL2a may be provided on the intermediate layer IMLa. The second electrode EL2a may also be provided on a portion of the sixth insulating layer 60 exposed by the second opening OP2 of the pixel definition film PDL. In addition, the second electrode EL2a may also be provided on a portion of the connection wiring CNa exposed by the first opening OP1 of the sixth insulating layer 60. Figure 6B As shown in FIG, the second electrode EL2a may include an end portion EN1 provided along the upper surface of the fifth insulating layer 50 and another end portion EN2 provided along the upper surface of the connection wiring CNa and the upper surface of the tip portion TP. For example, when viewed in cross section, the second electrode EL2a may have a shape that is partially disconnected relative to the tip portion TP in the region where the light emitting connection part CEa is defined. However, in a plan view, the second electrode EL2a may be partially disconnected in the region defined as a closed line by the partition SPR (see FIG. Figure 4A ) has an integral shape connected as a whole.

[0180] For example, the end portion EN1 of the second electrode EL2a may be disposed along the side surface L2_W of the second layer L2 and may be in contact with the side surface L2_W of the second layer L2. For example, the second electrode EL2a may be formed so as to contact the side surface L2_W of the second layer L2 exposed from the intermediate layer IMLa via the tip portion TP due to the difference between the deposition angle of the second electrode EL2a and the deposition angle of the intermediate layer IMLa. For example, the second electrode EL2a may be connected to the connection wiring CNa without requiring a separate patterning process for the intermediate layer IMLa, and thus, the light-emitting element LDa may be connected (e.g., electrically connected) to the pixel driving unit PDCa via the connection wiring CNa.

[0181] In addition, in the embodiment, the other end portion IN2 of the intermediate layer IMLa and the other end portion EN2 of the second electrode EL2a are shown to cover the side surface L3_W of the third layer L3. This is shown for illustrative purposes only, and at least a portion of the side surface L3_W of the third layer L3 may be exposed from the other end portion IN2 of the intermediate layer IMLa and / or the other end portion EN2 of the second electrode EL2a.

[0182] For example, as described above, the display panel DP may include a spacer SPR. The spacer SPR may be provided on the pixel defining film PDL. In an embodiment, the second electrode EL2a and the intermediate layer IMLa may be formed on the pixel by a common deposition process via an open mask. For example, the second electrode EL2a and the intermediate layer IMLa may be divided by the spacer SPR. As described above, the spacer SPR may have a closed line shape for each light-emitting portion, and therefore, the second electrode EL2a and the intermediate layer IMLa may have a divided shape in each light-emitting portion. For example, the second electrode EL2a and the intermediate layer IMLa may be electrically independent for each adjacent pixel.

[0183] Will refer to Figure 6A and Figure 6C The separator SPR is described in more detail. Figure 6C As shown in , the spacer SPR may have a reverse tapered shape. For example, the angle θ (hereinafter referred to as the tapered angle θ) between the upper surface of the pixel defining film PDL and the side surface SPR_W of the spacer SPR may be an obtuse angle. However, this is shown illustratively, and the tapered angle θ may be set differently as long as the spacer SPR can electrically disconnect the second electrode EL2a in each pixel. In addition, the spacer SPR may have the same structure as that of the tip portion TP, but the embodiment is not limited thereto.

[0184] In an embodiment, the spacer SPR may include an insulating material, and for example, may include an organic insulating material. According to an embodiment, the spacer SPR may include an inorganic insulating material, may include a multilayer structure of an organic insulating material and an inorganic insulating material, and may include a conductive material. For example, as long as the second electrode EL2a can be electrically disconnected for each pixel, the type of material of the spacer SPR is not limited. In the drawings, only the first light emitting element LD1 (see FIG. 1 ) is shown. Figure 5 ) and the second light emitting element LD2 (see Figure 5 ) may be electrically disconnected in each pixel. However, the embodiment is not limited thereto, and the first light emitting element LD1 (see Figure 5 ) of the second electrode EL2a and the third light emitting element LD3 (see Figure 5 ) of the second electrode EL2b (see Figure 7 ) or the second light emitting element LD2 (see Figure 5 ) of the second electrode EL2a and the third light emitting element LD3 (see Figure 5 ) of the second electrode EL2b (see Figure 7 ) can be electrically disconnected from each other.

[0185] A dummy layer UP may be provided on the separator SPR. The dummy layer UP may include a first dummy layer UP1 provided on the separator SPR and a second dummy layer UP2 provided on the first dummy layer UP1. The first dummy layer UP1 may be formed by the same process as that of the intermediate layer IMLa and include the same material as that of the intermediate layer IMLa. The second dummy layer UP2 may be formed by the same process as that of the second electrode EL2a and include the same material as that of the second electrode EL2a. For example, the first dummy layer UP1 and the second dummy layer UP2 may be formed simultaneously with the formation of the intermediate layer IMLa and the second electrode EL2a. In an embodiment, the display panel DP may not include the dummy layer UP.

[0186] like Figure 6C As shown in , in an embodiment, the second electrode EL2a may include a first end portion EN1a, and the second dummy layer UP2 may include a second end portion EN2a. The first end portion EN1a may be spaced apart from the spacer SPR and positioned on the pixel definition film PDL, and the second end portion EN2a may be spaced apart from the first end portion EN1a and positioned on the side surface SPR_W of the spacer SPR. However, Figure 6C The first end portion EN1a is shown as being spaced apart from the side surface SPR_W of the spacer SPR by a predetermined distance, but the embodiment is not limited thereto, and the first end portion EN1a may be in contact with the side surface SPR_W of the spacer SPR, as long as the first end portion EN1a can be electrically disconnected from the second end portion EN2a. In addition, when the first end portion EN1a and the second end portion EN2a are connected and not distinguished from each other, when the resistance is high due to the small thickness of the portion of the spacer SPR formed along the side surface SPR_W, and when the second electrode EL2a is electrically disconnected between adjacent pixels, it can be considered that the second electrode EL2a is divided by the spacer SPR.

[0187] According to the embodiment, in the absence of a separate patterning process for the second electrode EL2a or the intermediate layer IMLa, the second electrode EL2a or the intermediate layer IMLa is not formed on the side surface SPR_W of the separator SPR or is formed thin, and thus the second electrode EL2a or the intermediate layer IMLa can be divided in each pixel. In addition, in the case where the second electrode EL2a or the intermediate layer IMLa can be electrically disconnected between adjacent pixels, the shape of the separator SPR can be deformed differently, but the embodiment is not limited thereto.

[0188] Return to reference Figure 6A, the encapsulation layer ECL may be disposed on the light-emitting element layer LDL. The encapsulation layer ECL may cover the light-emitting element LDa and the spacer SPR. The encapsulation layer ECL may include a first inorganic layer IL1, an organic layer OL, and a second inorganic layer IL2 stacked sequentially. However, the embodiment is not limited thereto, and the encapsulation layer ECL may further include an inorganic layer and an organic layer. In addition, the encapsulation layer ECL may be a glass substrate.

[0189] The first inorganic layer IL1 and the second inorganic layer IL2 can protect the light-emitting element LDa from moisture and oxygen outside the display panel DP, and the organic layer OL can protect the light-emitting element LDa from foreign matter such as particles remaining in the process of forming the first inorganic layer IL1. The first inorganic layer IL1 and the second inorganic layer IL2 may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The organic layer OL may include an acrylic organic layer, and the type of material is not limited thereto.

[0190] The sensing layer ISL can sense external input. In an embodiment, the sensing layer ISL can be formed on the encapsulation layer ECL through a subsequent process. For example, it can be stated that the sensing layer ISL is directly provided on the encapsulation layer ECL. Directly provided can mean that there are no components between the sensing layer ISL and the encapsulation layer ECL. For example, a separate adhesive member may not be provided between the sensing layer ISL and the encapsulation layer ECL. However, this is shown illustratively, and in the display panel DP according to the embodiment, the sensing layer ISL can be formed separately and then coupled to the display panel DP through the adhesive member, but the embodiment is not limited thereto.

[0191] The sensing layer ISL may include a conductive layer and an insulating layer. The conductive layer may include a first sensing conductive layer MTL1 and a second sensing conductive layer MTL2, and the insulating layer may include a first sensing insulating layer 71, a second sensing insulating layer 72, and a third sensing insulating layer 73. However, this is shown for illustrative purposes only, and the number of conductive layers and the number of insulating layers are not limited to the embodiment.

[0192] The first sensing insulating layer 71, the second sensing insulating layer 72, and the third sensing insulating layer 73 may have a single-layer structure or a multi-layer structure in which multiple layers are stacked in the third direction DR3. The first sensing insulating layer 71, the second sensing insulating layer 72, and the third sensing insulating layer 73 may include an inorganic film. The inorganic film may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. The first sensing insulating layer 71, the second sensing insulating layer 72, and the third sensing insulating layer 73 may include an organic film. The organic film may include at least one of an acrylic resin, a methacrylate resin, a polyisoprene resin, a vinyl resin, an epoxy resin, a urethane resin, a cellulose resin, a siloxane resin, a polyimide resin, a polyamide resin, and a perylene resin.

[0193] The first sensing conductive layer MTL1 may be disposed between the first sensing insulating layer 71 and the second sensing insulating layer 72, and the second sensing conductive layer MTL2 may be disposed between the second sensing insulating layer 72 and the third sensing insulating layer 73. A portion of the second sensing conductive layer MTL2 may be connected to the first sensing conductive layer MTL1 through a contact hole CNT formed in the second sensing insulating layer 72. The first sensing conductive layer MTL1 and the second sensing conductive layer MTL2 may have a single-layer structure or a multi-layer structure in which multiple layers are stacked in the third direction DR3.

[0194] The sensing conductive layer having a single-layer structure may include a metal layer or a transparent conductive layer. The metal layer may include molybdenum, silver, titanium, copper, aluminum, or alloys thereof. The transparent conductive layer may include a transparent conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium zinc tin oxide (IZTO). In another example, the transparent conductive layer may include a conductive polymer such as PEDOT, metal nanowires, or graphene.

[0195] The sensing conductive layer having a multi-layer structure may include a metal layer. For example, the metal layer may have a three-layer structure of titanium (Ti) / aluminum (Al) / titanium (Ti). In another example, the sensing conductive layer having a multi-layer structure may include at least one metal layer and at least one transparent conductive layer.

[0196] The first sensing conductive layer MTL1 and the second sensing conductive layer MTL2 may form a sensor for sensing an external input in the sensing layer ISL. The sensor may be driven using a capacitive method and may be driven using either a mutual capacitance method or a self-capacitive method. However, this is described illustratively, and in addition to the capacitive method, the sensor may also be driven using a resistive film method, an ultrasonic method, or an infrared method, but the embodiment is not limited thereto.

[0197] The first sensing conductive layer MTL1 and the second sensing conductive layer MTL2 may include a transparent conductive oxide or may have a mesh shape formed of an opaque conductive material (e.g., metal). The first sensing conductive layer MTL1 and the second sensing conductive layer MTL2 may have various materials and various shapes as long as the visibility of the image displayed by the display panel DP is not degraded, and the embodiment is not limited thereto.

[0198] Figure 7 is an enlarged schematic cross-sectional view of a portion of the display panel DP according to the embodiment. Figure 7 yes Figure 5 An enlarged schematic cross-sectional view of the third area AA3 is shown in FIG.

[0199] Reference Figure 7 The light emitting element LDb may include a first electrode EL1b, an intermediate layer IMLb, and a second electrode EL2b. In an embodiment, the first electrode EL1b may be an anode of the light emitting element LDb. That is, the first power voltage ELVDD (see Figure 2 ) can be applied to the first electrode EL1b. The second electrode EL2b can be the cathode of the light emitting element LDb. The second power voltage ELVSS (see Figure 2 ) can be applied to the second electrode EL2b. The light emitting element LDb can be the above Figure 5 The pixel driving unit PDCb may be connected (eg, electrically connected) to the third light emitting element LD3 described above. Figure 5 The third pixel driving unit PDC3 of the third light emitting element LD3 described in

[0045] The light emitting element LDb may be provided in the light emitting opening OP-PDLb.

[0200] The connection wiring CNb may include a driving connection component CDb and a light emitting connection component CEb. The driving connection component CDb may be a portion of the connection wiring CNb connected to the pixel driving unit PDCb and a portion substantially connected to the transistor TR. In an embodiment, the driving connection component CDb may be connected (e.g., electrically connected) to the source region SR of the semiconductor pattern SP through the source electrode pattern W2 and through the fifth insulating layer 50.

[0201] In addition, unlike the first and second areas AA1 and AA2, in the third area AA3, the light emitting connection component CEb may not be exposed to the outside. For example, the connection opening OP-CE (see FIG. Figure 6A ) may not be limited to the third area AA3. In addition, the connection opening OP-CE (see Figure 6A ) may be spaced apart from the third area AA3 in a plan view.

[0202] Figure 8A and Figure 8Bis an enlarged schematic cross-sectional view of the light emitting elements LD1 , LD2 , and LD3 according to the embodiment. Figure 8A yes Figure 6A An enlarged schematic cross-sectional view of the light emitting element LDa shown in FIG. Figure 8B yes Figure 7 An enlarged schematic cross-sectional view of the light-emitting element LDb shown in FIG.

[0203] As mentioned above, Figure 6A The light emitting element LDa shown in FIG may be a first light emitting element LD1 and a second light emitting element LD2 .

[0204] The first light emitting element LD1 may include a first cathode CAT1, a first electron control layer ECL1, a first light emitting layer EML1, a first hole control layer HCL1, and a first anode ANO1.

[0205] The first electron control layer ECL1, the first light emitting layer EML1, and the first hole control layer HCL1 of the first light emitting element LD1 may correspond to the intermediate layer IMLa (see Figure 6A ), and the first electron control layer ECL1 and the first hole control layer HCL1 of the first light emitting element LD1 may correspond to the functional layer FNLa (see Figure 6A ).

[0206] The first anode electrode ANO1 may be provided on the first cathode electrode CAT1 of the first light emitting element LD1. The first cathode electrode CAT1 of the first light emitting element LD1 may correspond to the first electrode EL1a (see FIG. Figure 6A ), and the first anode ANO1 of the first light emitting element LD1 may correspond to the second electrode EL2a (see Figure 6A The first electron control layer ECL1, the first light emitting layer EML1, and the first hole control layer HCL1 may be disposed between the first cathode CAT1 and the first anode ANO1 of the first light emitting element LD1.

[0207] The first light emitting layer EML1 may include an organic light emitting material. In addition, the first light emitting layer EML1 may include an inorganic light emitting material or may be provided as a mixed layer of an organic light emitting material and an inorganic light emitting material.

[0208] In an embodiment, the first light emitting layer EML1 of the first light emitting element LD1 may provide red light, but the embodiment is not limited thereto, and the first light emitting layer EML1 may provide green light.

[0209] The first electron control layer ECL1 and the first hole control layer HCL1 may control movement of charges between the first cathode CAT1 and the first anode ANO1. The first electron control layer ECL1 may include an electron injection / transport material, and the first hole control layer HCL1 may include a hole injection / transport material.

[0210] The first hole control layer HCL1 may include a first hole transport layer HCL1-1 and a first hole injection layer HCL1-2. The first hole injection layer HCL1-2 may be disposed on the first hole transport layer HCL1-1. The first hole transport layer HCL1-1 may include ZnO, ZnMgO, or an inorganic material, etc., but the embodiment is not limited thereto, and the first hole transport layer HCL1-1 may include various materials.

[0211] The second light emitting element LD2 may include a second cathode CAT2, a second electron control layer ECL2, a second light emitting layer EML2, a second hole control layer HCL2, and a second anode ANO2.

[0212] The second electron control layer ECL2, the second light emitting layer EML2 and the second hole control layer HCL2 may correspond to the intermediate layer IMLa (see Figure 6A ), and the second electron control layer ECL2 and the second hole control layer HCL2 may correspond to the functional layer FNLa (see Figure 6A ).

[0213] The second cathode CAT2 may correspond to the first electrode EL1a (see Figure 6A ), and the second anode ANO2 may correspond to the second electrode EL2a (see Figure 6A The second electron control layer ECL2, the second light emitting layer EML2, and the second hole control layer HCL2 may be disposed between the second cathode CAT2 and the second anode ANO2.

[0214] The second light emitting layer EML2 of the second light emitting element LD2 may provide green light, but the embodiment is not limited thereto, and the second light emitting layer EML2 may provide red light.

[0215] The second electron control layer ECL2 may include an electron injection / transport material, and the second hole control layer HCL2 may include a hole injection / transport material.

[0216] The first hole control layer HCL1 and the second hole control layer HCL2 may be disposed on the first light emitting layer EML1 and the second light emitting layer EML2, respectively. Figure 8B ) operation, the first light emitting layer EML1 and the second light emitting layer EML2 can be prevented from being used to form the third light emitting layer EML3 (see Figure 8B ) solvents and be damaged.

[0217] The thickness of each of the first electron control layer ECL1 and the second electron control layer ECL2 may be smaller than the thickness of each of the first hole control layer HCL1 and the second hole control layer HCL2. As an example, the thickness of each of the first electron control layer ECL1 and the second electron control layer ECL2 may be approximately or larger and approximately or smaller.

[0218] Reference Figure 8B The third light emitting element LD3 may include a third anode ANO3, a third hole control layer HCL3, a third light emitting layer EML3, a third electron control layer ECL3 and a third cathode CAT3.

[0219] The third hole control layer HCL3, the third light emitting layer EML3, and the third electron control layer ECL3 of the third light emitting element LD3 may correspond to the intermediate layer IMLb (see Figure 7 ), and the third hole control layer HCL3 and the third electron control layer ECL3 of the third light emitting element LD3 may correspond to the functional layer FNLb (see Figure 7 ). Light-emitting layer EMLb (see Figure 7 ) may be disposed between the first electrode EL1b and the functional layer FNLb.

[0220] The third anode ANO3 of the third light emitting element LD3 may correspond to the first electrode EL1b (see Figure 7 ), and the third cathode CAT3 may correspond to the second electrode EL2b (see Figure 7 The third hole control layer HCL3, the third light emitting layer EML3, and the third electron control layer ECL3 may be disposed between the third anode ANO3 and the third cathode CAT3.

[0221] The third light emitting layer EML3 may include an organic light emitting material. In addition, the third light emitting layer EML3 may include an inorganic light emitting material or may be provided as a mixed layer of an organic light emitting material and an inorganic light emitting material.

[0222] In an embodiment, the third light emitting layer EML3 of the third light emitting element LD3 may provide blue light.

[0223] The third hole control layer HCL3 and the third electron control layer ECL3 may control the movement of charges between the third anode ANO3 and the third cathode CAT3. The third hole control layer HCL3 may include a hole injection / transport material, and the third electron control layer ECL3 may include an electron injection / transport material.

[0224] The third hole control layer HCL3 may include a third hole transport layer HCL3-1 and a third hole injection layer HCL3-2. The third hole injection layer HCL3-2 may be disposed on the third hole transport layer HCL3-1.

[0225] Figure 9 is an enlarged schematic cross-sectional view of a portion of the display panel DP according to the embodiment. Figure 9 Show Figure 6A An embodiment of the first area AA1 shown in FIG. 1 and another embodiment.

[0226] In the description Figure 9 When the same / similar reference numerals are assigned to Figure 6A The same / similar components shown in FIG are also shown, and detailed descriptions of the same / similar components will be omitted for convenience of description.

[0227] Reference Figure 9 The display panel DP may include a hydrogen supply film OSL. The hydrogen supply film OSL may be disposed between the light-emitting element LDa and the sixth insulating layer 60. The hydrogen supply film OSL may increase the electrical conductivity of the first electrode EL1a of the light-emitting element LDa. For example, the hydrogen supply film OSL may inject or transfer charges into or transfer charges to the first electrode EL1a, which functions as a cathode, to increase the electrical conductivity of the first electrode EL1a. Consequently, the efficiency and lifetime of the light-emitting element LDa may be improved.

[0228] According to an embodiment, the hydrogen supply film OSL may include silicon nitride (SiN x However, the embodiment is not limited thereto, and the hydrogen supply film OSL may include other materials.

[0229] As shown in the drawings, a recessed pattern PT-60 may be formed in the sixth insulating layer 60, and a hydrogen supply film OSL may be disposed on the recessed pattern PT-60. However, the embodiment is not limited thereto, and the hydrogen supply film OSL may be disposed on the sixth insulating layer 60 without a separate recessed pattern PT-60, and the embodiment is not limited thereto.

[0230] Figure 10A 、 Figure 10B 、 Figure 10C 、 Figure 10D 、 Figure 10E and Figure 10F is a schematic cross-sectional view illustrating a method of manufacturing the display panel DP according to an embodiment.

[0231] The method of manufacturing the display panel DP according to the embodiment may include: Figure 5) is formed on the first lower electrode CAT1 (first cathode CAT1), the second lower electrode CAT2 (second cathode CAT2) and the third lower electrode ANO3 (third anode ANO3); the pixel definition film PDL is formed, and the pixel definition film PDL is provided on the base layer BL (see Figure 5 ) and covers the first lower electrode CAT1, the second lower electrode CAT2 and the third lower electrode ANO3, and in the pixel definition film PDL, at least a portion of the first lower electrode CAT1 passes through the first light emitting opening OP1-PDL (see Figure 5 ) is exposed, at least a portion of the second lower electrode CAT2 is exposed through the second light emitting opening OP2-PDL (see Figure 5 ) is exposed, and at least a portion of the third lower electrode ANO3 is exposed through the third light emitting opening OP3-PDL (see Figure 5 ) exposed; in the first light emitting opening OP1-PDL (see Figure 5 ) is formed inside the first electron control layer ECL1, the first light emitting layer EML1 and the first hole control layer HCL1; in the second light emitting opening OP2-PDL (see Figure 5 ) inside the second electron control layer ECL2, the second light-emitting layer EML2 and the second hole control layer HCL2; and in the third light-emitting opening OP3-PDL (see Figure 5 ) The operation of forming a third hole control layer HCL3, a third light-emitting layer EML3 and a third electron control layer ECL3 inside.

[0232] In addition, the first hole control layer HCL1 , the second hole control layer HCL2 , and the third hole control layer HCL3 may be formed simultaneously.

[0233] Reference Figure 10A The pixel definition film PDL may be disposed on the sixth insulating layer 60. The lower electrodes CAT1, CAT2, and ANO3 may be formed in the first light emitting opening OP1-PDL (see FIG. 1 ) formed in the pixel definition film PDL. Figure 5 ), the second light emitting opening OP2-PDL (see Figure 5 ) and the third light emitting opening OP3-PDL (see Figure 5 )middle.

[0234] The first lower electrode CAT1 may be formed in the first light emitting opening OP1-PDL (see Figure 5 ), the second lower electrode CAT2 may be formed in the second light emitting opening OP2-PDL (see Figure 5 ), and the third lower electrode ANO3 may be formed in the third light emitting opening OP3-PDL (see Figure 5 )middle.

[0235] The first light emitting opening OP1-PDL (see Figure 5 ) in the first preliminary light emitting element P-LD1 may correspond to the first light emitting element LD1 (see Figure 8A ) of the first cathode CAT1 (see Figure 8A ). Formed in the second light emitting opening OP2-PDL (see Figure 5 ) in the second preliminary light emitting element P-LD2 may correspond to the second light emitting element LD2 (see Figure 8A ) of the second cathode CAT2 (see Figure 8A ). Formed in the third light emitting opening OP3-PDL (see Figure 5 ) in the third preliminary light emitting element P-LD3 may correspond to the third light emitting element LD3 (see Figure 8A ) of the third anode ANO3.

[0236] The first electron control layer ECL1 may be provided in the first light emitting opening OP1-PDL (see Figure 5 ) is disposed on a first lower electrode CAT1 of a first preliminary light emitting element P-LD1. A first light emitting layer EML1 may be disposed on the first electron control layer ECL1.

[0237] The second electron control layer ECL2 may be provided in the second light emitting opening OP2-PDL (see Figure 5 ) is disposed on a second lower electrode CAT2 of the second preliminary light emitting element P-LD2. The second light emitting layer EML2 may be disposed on the second electron control layer ECL2.

[0238] Reference Figure 10B , a first hole control layer HCL1 may be formed on the first light emitting layer EML1 , a second hole control layer HCL2 may be formed on the second light emitting layer EML2 , and a third electron control layer ECL3 may be formed on the third lower electrode ANO3 .

[0239] For example, the first hole control layer HCL1 , the second hole control layer HCL2 , and the third hole control layer HCL3 may be formed simultaneously.

[0240] In the case of forming the first hole control layer HCL1, the second hole control layer HCL2 and the third hole control layer HCL3, and then, in the case of forming the third light emitting layer EML3 (see Figure 10C), the first hole-controlling layer HCL1 may cover the first light-emitting layer EML1 and the second hole-controlling layer HCL2 may cover the second light-emitting layer EML2, so that the first light-emitting layer EML1 and the second light-emitting layer EML2 can be prevented from being damaged. Therefore, the efficiency of the first light-emitting layer EML1 and the second light-emitting layer EML2 can be prevented from being reduced, and the lifespan of the first light-emitting layer EML1 and the second light-emitting layer EML2 can be increased.

[0241] Reference Figure 10C , the third light emitting layer EML3 may be formed on the third hole control layer HCL3.

[0242] As described above, in the case of forming the third light emitting layer EML3 , the first and second light emitting layers EML1 and EML2 may be prevented from being damaged by the first and second hole control layers HCL1 and HCL2 .

[0243] Reference Figure 10D and Figure 10E , a third electron control layer ECL3 can be formed on the third light-emitting layer EML3, a first upper electrode ANO1 (first anode ANO1) can be formed on the first hole control layer HCL1, a second upper electrode ANO2 (second anode ANO2) can be formed on the second hole control layer HCL2, and a third upper electrode CAT3 (third cathode CAT3) can be formed on the third electron control layer ECL3.

[0244] Reference Figure 10F Before forming the first and second lower electrodes CAT1 and CAT2, a hydrogen supply film OSL may be formed on the sixth insulating layer 60. The first and second lower electrodes CAT1 and CAT2 may be formed on the first and second hydrogen supply films OSL1 and OSL2, respectively.

[0245] The drawings illustrate that the recess pattern PT-60 is formed in the sixth insulating layer 60 and the hydrogen supply film OSL is disposed in the recess pattern PT-60, but the embodiment is not limited thereto, and the hydrogen supply film OSL may be disposed on the sixth insulating layer 60 without a separate recess pattern PT-60.

[0246] According to the display panel DP (see Figure 6A ) and the method for manufacturing the display panel DP can prevent the light emitting layer EMLa (see Figure 6A ) damage.

[0247] The display panel DP and the method of manufacturing the display panel DP according to the embodiment can prevent reliability of display quality from being deteriorated.

[0248] In summarizing the detailed description, it will be appreciated by those skilled in the art that many changes and modifications may be made to the embodiments without departing substantially from the principles, spirit and scope of the present disclosure. Therefore, the disclosed embodiments are used in a general and descriptive sense only and not for the purpose of limitation.

Claims

1. A display panel, wherein: The display panel includes: A first light-emitting element includes a first anode, a first cathode disposed on the first anode, and a first intermediate layer disposed between the first anode and the first cathode; a second light-emitting element comprising a second cathode, a second anode disposed on the second cathode, and a second intermediate layer disposed between the second cathode and the second anode; a first transistor electrically connected to the first light emitting element; a second transistor electrically connected to the second light emitting element; a connection wiring provided between the second light emitting element and the second transistor in cross section, the connection wiring including a drive connection part connected to the second transistor and a light emitting connection part connected to the second anode; and Pixel defining film, including: a first light emitting opening overlapping with the first light emitting element and in which a portion of the first cathode is disposed; a second light emitting opening overlapping the second light emitting element and spaced apart from the first light emitting opening, a portion of the second anode being disposed in the second light emitting opening; and A first connection opening is spaced apart from the first light emitting opening and the second light emitting opening, wherein the second anode includes an end portion connected to the light emitting connection member and another end portion spaced apart from the end portion in cross section.

2. The display panel according to claim 1, wherein: The display panel further includes: A hydrogen supply film is provided below the second cathode and overlaps with the second light emitting opening.

3. The display panel according to claim 1, wherein: The display panel further includes: A spacer is provided on the pixel definition film and disconnects the second anode.

4. The display panel according to claim 1, wherein: The first intermediate layer includes a luminescent material that generates light having a blue color, and The second intermediate layer includes a luminescent material that generates light having a color different from the blue color.

5. The display panel according to claim 1, wherein: The first intermediate layer comprises: a first hole control layer, disposed on the pixel defining film; a first light-emitting layer disposed on the first hole-controlling layer, the first light-emitting layer generating light having a first color; and a first electron control layer, disposed on the first light-emitting layer, and The second intermediate layer comprises: a second electron control layer, disposed on the pixel defining film; a second light emitting layer disposed on the second electron control layer and including a light emitting material that generates light having a color different from the first color; and The second hole control layer is arranged on the second light-emitting layer. The display panel according to claim 2 , wherein: The hydrogen supply film contains silicon nitride or polyacrylic acid.

7. The display panel according to claim 5, wherein: The thickness of the second electron control layer is or larger and or smaller.

8. The display panel according to claim 1, wherein: The connecting wiring comprises: The first layer contains titanium; a second layer disposed on the first layer and containing aluminum; and The third layer is disposed on the second layer and contains titanium.

9. The display panel according to claim 1, wherein: The first cathode and the second cathode are spaced apart from each other in a plan view.

10. The display panel according to claim 3, wherein: The first light emitting element is disposed in the first region, The second light emitting element is disposed in the second region, The first region and the second region are divided by the partition, and The first connection opening is spaced apart from the first region in a plan view.

11. A display panel, wherein: The display panel includes: The first light-emitting element comprises: a first anode; a first cathode disposed on the first anode; and a first intermediate layer disposed between the first anode and the first cathode; The second light-emitting element comprises: a second cathode; a second anode disposed on the second cathode; and a second intermediate layer disposed between the second cathode and the second anode; The third light-emitting element comprises: a third cathode; a third anode disposed on the third cathode; and a third intermediate layer, disposed between the third cathode and the third anode; a first transistor electrically connected to the first light emitting element; a second transistor electrically connected to the second light emitting element; a third transistor electrically connected to the third light-emitting element; A first connection wiring is provided between the second light-emitting element and the second transistor in a cross section, the first connection wiring including: a first drive connection component connected to the second transistor; and a first light-emitting connection member connected to the second anode; and A second connecting wiring is provided between the third light-emitting element and the third transistor in a cross section, the second connecting wiring including: a second drive connection component connected to the third transistor; and A second light-emitting connection component is connected to the third anode, wherein: The second anode includes an end portion connected to the first light emitting connection member and another end portion spaced apart from the end portion in cross section, and The third anode includes an end portion connected to the second light emitting connection member and another end portion spaced apart from the end portion in cross section.

12. The display panel according to claim 11, wherein: The first intermediate layer includes a luminescent material that generates light having a blue color, The second intermediate layer includes a luminescent material that generates light having a red color, and The third intermediate layer includes a luminescent material that generates light having a green color.

13. The display panel according to claim 11, wherein: The display panel further includes: a first hydrogen supply membrane disposed below the second cathode; and The second hydrogen supply membrane is disposed below the third cathode.

14. The display panel according to claim 11, wherein: The display panel further includes: A separator is provided to disconnect the second anode and the third anode.

15. The display panel according to claim 11, wherein The second cathode and the third cathode are electrically connected to each other.

16. The display panel according to claim 11, wherein Each of the first connecting wiring and the second connecting wiring includes: The first layer contains titanium; a second layer disposed on the first layer and containing aluminum; and The third layer is disposed on the second layer and contains titanium.

17. The display panel according to claim 14, wherein: The first light emitting element is disposed in the first region, The second light emitting element is arranged in the second region, and the third light emitting element is arranged in the third region. The first region, the second region, and the third region are divided by the partition, and The first light emitting connecting part and the second light emitting connecting part are spaced apart from the first region in a plan view.

18. A method for manufacturing a display panel, wherein: The method comprises: forming a first lower electrode and a second lower electrode on the base layer; forming a first light-emitting opening and a second light-emitting opening, wherein at least a portion of the first lower electrode is exposed through the first light-emitting opening, and at least a portion of the second lower electrode is exposed through the second light-emitting opening, and the first light-emitting opening and the second light-emitting opening are arranged on the base layer and cover the first lower electrode and the second lower electrode; forming a first hole control layer, a first light emitting layer and a first electron control layer inside the first light emitting opening; and forming a second electron control layer, a second light emitting layer, and a second hole control layer inside the second light emitting opening; The first hole control layer and the second hole control layer are formed simultaneously.

19. The method according to claim 18, wherein The first hole control layer, the second hole control layer, the first light emitting layer, the second light emitting layer, and the first electron control layer and the second electron control layer are formed by inkjet method.

20. The method according to claim 18, wherein The method further comprises: Before forming the first lower electrode and the second lower electrode on the base layer, patterning the base layer and forming a hydrogen supply film on the patterned base layer, Wherein, the second lower electrode is formed on the hydrogen supply film.

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