3D cell and array architecture

Abstract

Various 3D memory cells, array architectures, and processes are disclosed. In one embodiment, a memory cell structure including a vertical bit line, a first semiconductor layer surrounding a first portion of the vertical bit line, and a first gate surrounding the first semiconductor layer is provided. The memory cell structure also includes a second semiconductor layer surrounding a second portion of the vertical bit line and a gate dielectric layer surrounding a third portion of the vertical bit line. The gate dielectric layer separates the first semiconductor layer and the first gate from the second semiconductor layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of priority under 35 U.S.C. §119(e) to U.S. Provisional Patent Application No. 63 / 421,522, filed on November 1, 2022, entitled “3D Cell and Array Structures”; U.S. Provisional Patent Application No. 63 / 458,634, filed on April 11, 2023, entitled “3D Cell and Array Structures”; U.S. Provisional Patent Application No. 63 / 459,406, filed on April 14, 2023, entitled “3D Cell and Array Structures and Processes”; U.S. Provisional Patent Application No. 63 / 460,406, filed on April 19, 2023, entitled “3D Memory Cell and Array Structures”; U.S. Provisional Patent Application No. 63 / 461,406, filed on April 30, 2023, entitled “3D Memory Cell and Array Structures”; and U.S. Provisional Patent Application No. 63 / 467,406, filed on April 18, 2023, entitled “3D Memory Cell and Array Structures.” U.S. Provisional Patent Application No. 3,040, entitled “3D Memory Cell and Array Structures”; U.S. Provisional Patent Application No. 63 / 465,526, filed on May 10, 2023, entitled “3D Cell and Array Structures”; U.S. Provisional Patent Application No. 63 / 466,155, filed on May 12, 2023, entitled “3D Cell and Array Structures”; U.S. Provisional Patent Application No. 63 / 467,004, filed on May 16, 2023, entitled “3D Cell and Array Structures”; and U.S. Provisional Patent Application No. 63 / 542,526, filed on October 5, 2023, entitled “3D Array Structures and Processes,” the entire contents of all of the above applications are incorporated herein by reference. Technical Field

[0003] Exemplary embodiments of the present invention relate generally to the field of memories, and more particularly to 3D memory cell and array structures and related processes. Background Art

[0004] As electronic circuits continue to increase in complexity and density, memory size, complexity, and cost have become significant considerations. One approach to increasing memory capacity is to use three-dimensional (3D) array structures. However, cost-effective 3D array structures have yet to be fully realized. Summary of the Invention

[0005] In various exemplary embodiments, memory cells, array structures, and processes are disclosed. For example, three-dimensional (3D) NOR-type cells and array structures and processes are disclosed. The disclosed embodiments are applicable to many technologies. For example, in one embodiment, dynamic random access memory (DRAM) can be formed. In other embodiments, the present invention can be used to form ferroelectric random access memory (FRAM), resistive random access memory (RRAM), phase change memory (PCM), and magnetoresistive random access memory (MRAM). In another embodiment, the present invention can be used to form memory elements called "synapses" in artificial neural networks. In addition, the present invention can be applied to any other application not listed but still within the scope of the present invention.

[0006] In an exemplary embodiment, a memory cell structure is provided that includes a vertical bit line, a first semiconductor layer surrounding a first portion of the vertical bit line, and a first gate surrounding the first semiconductor layer. The memory cell structure also includes a second semiconductor layer surrounding a second portion of the vertical bit line and a gate dielectric layer surrounding a third portion of the vertical bit line. The gate dielectric layer separates the first semiconductor layer and the first gate from the second semiconductor layer.

[0007] In an exemplary embodiment, a memory cell structure is provided that includes a vertical bit line, a first semiconductor layer surrounding a first portion of the vertical bit line, and a first gate surrounding the first semiconductor layer. The memory cell structure also includes a gate dielectric layer surrounding the first semiconductor layer and the first gate, and a second semiconductor layer surrounding a second portion of the vertical bit line and located below a bottom portion of the gate dielectric layer.

[0008] Additional features and benefits of exemplary embodiments of the present invention will become apparent from the detailed description, drawings, and claims set forth below. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Exemplary embodiments of the present invention will be more fully understood from the following detailed description and accompanying drawings, which illustrate various embodiments of the present invention but should not be construed as limiting the present invention to these specific embodiments. The drawings are for explanation and understanding purposes only.

[0010] Figures 1A to 1C An embodiment of a 3D DRAM cell formed from a one-transistor one-capacitor (1T1C) structure according to the present invention is shown.

[0011] Figures 2A to 2B An embodiment of a 3D DRAM cell structure according to the present invention is shown.

[0012] Figures 3A to 3B An embodiment of a 3D DRAM cell structure according to the present invention is shown.

[0013] Figures 4A to 4C An embodiment of a 3D DRAM cell structure according to the present invention is shown.

[0014] Figures 5A to 5C An embodiment of a 3D DRAM cell structure according to the present invention is shown.

[0015] Figures 6A to 6B An embodiment of a 3D DRAM cell structure according to the present invention is shown.

[0016] 7A to 7C An embodiment of a 3D DRAM cell structure according to the present invention is shown.

[0017] Figures 8A to 8B An embodiment of a 3D DRAM cell structure according to the present invention is shown.

[0018] Figures 9A to 9B An embodiment of a 3D DRAM cell structure according to the present invention is shown.

[0019] FIG. 10A to FIG. 10B An embodiment of a 3D DRAM cell structure according to the present invention is shown.

[0020] Figure 11 The present invention is shown based on Figure 1A An embodiment of a 3D DRAM array structure with a cell structure is shown.

[0021] Figure 12A An embodiment of a 3D DRAM array according to the present invention is shown.

[0022] Figure 12B Another embodiment of a 3D DRAM array according to the present invention is shown.

[0023] 13A to 13C An embodiment of a 3D DRAM cell structure according to the present invention is shown.

[0024] Figure 13D Shows something like Figure 13A The illustrated embodiment is however for an embodiment of a cell structure having a different shape of the gate dielectric layer.

[0025] 14A to 14C An embodiment of a 3D DRAM cell structure according to the present invention is shown.

[0026] Figures 15A to 15C An embodiment of a 3D DRAM cell structure according to the present invention is shown.

[0027] 16A to 16B An embodiment of a 3D DRAM cell structure according to the present invention is shown.

[0028] 17A to 17B An embodiment of a 3D DRAM cell structure according to the present invention is shown.

[0029] 18A to 18C An embodiment of a 3D DRAM cell structure according to the present invention is shown.

[0030] 19A to 19C An embodiment of a 3D DRAM cell structure according to the present invention is shown.

[0031] 20A to 20C An embodiment of a 3D DRAM cell structure according to the present invention is shown.

[0032] Figure 21A Shows the use Figure 20A An example of a structure formed by the unit structure is shown.

[0033] Figure 21B Shows the use Figure 13A An example of a structure formed by the unit structure is shown.

[0034] Figures 22A to 22E An embodiment of a cell structure according to the present invention is shown.

[0035] Figure 23A The use of the present invention is shown Figure 13A The unit structure shown is an embodiment of a 3D array structure formed as an example.

[0036] Figure 23B The use of the present invention is shown Figure 16A The unit structure shown is an embodiment of a 3D array structure formed as an example. DETAILED DESCRIPTION

[0037] Those skilled in the art will recognize that the following detailed description is illustrative only and not restrictive. Other embodiments of the present invention will be apparent to those skilled in the art having the benefit of this disclosure. Implementation of exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. Throughout the drawings and the following detailed description, the same reference numerals or numbers are used to refer to the same or similar components.

[0038] Three-dimensional (3D) cell and array structures are disclosed. Embodiments of the present invention are applicable to many memory technologies. For example, in one embodiment, the present invention can be used to form a 3D dynamic random access memory (DRAM). In another embodiment, the present invention can be applied to any other technology suitable for forming a 3D cell and array structure, such as a ferroelectric random access memory (FRAM). Such applications are within the scope of the present invention.

[0039] For purposes of illustration, an embodiment of the present invention forming a DRAM cell is described as an example. However, the materials of the components of the cell structure may vary depending on the cell technology used within the scope of the present invention.

[0040] Figure 1A An embodiment of a 3D DRAM cell formed from a one-transistor one-capacitor (1T1C) structure according to the present invention is shown.

[0041] Figure 1B Shown is a view taken along line A-A' Figure 1A It should be noted that for the sake of clarity, the cross-sectional top view shows the entire area around the bit line 101.

[0042] Figure 1C Shown Figure 1A 13. The equivalent circuit of the unit structure shown in FIG. In one embodiment, the unit structure includes a dual-gate select transistor consisting of two transistors 130a and 130b and a capacitor 131. Select transistors 130a and 130b are formed as thin-film transistors. Compared to conventional PN junction transistors, such thin-film transistors provide better controllability of the channel. Consequently, compared to PN transistors, the leakage current of the channel is significantly reduced. This allows the size of capacitor 131 to be reduced.

[0043] The cell structure includes a bit line (BL) 101 formed of a conductive material (e.g., metal or polysilicon). The cell structure also includes a semiconductor layer (SL) 102, which includes a material such as silicon, polysilicon, silicon germanium, or an oxide-based semiconductor such as indium gallium zinc oxide (IGZO). IGZO is known to have extremely low leakage current in the off state, which can reduce the size requirements of the capacitor.

[0044] It should be noted that the semiconductor materials used in all embodiments of the cell structures constructed according to the present invention include any suitable semiconductor materials, such as silicon (Si), polycrystalline silicon (Poly-Si), germanium (Ge), silicon germanium (SiGe), gallium (Ga), arsenic (As), indium (In), gallium nitride (GaN), gallium arsenide (GaAs), indium silicon (InSi), indium germanium (GeIn), indium gallium arsenide (InGaAs), silicon carbide (SiC), oxide-based semiconductors such as indium gallium zinc oxide (IGZO), and other suitable materials. For simplicity, for illustrative purposes, the embodiments shown herein use silicon and polycrystalline silicon materials as examples. However, the use of any other semiconductor materials is still within the scope of the present invention.

[0045] The semiconductor layer 102 forms the channels of the select transistors 130a and 130b. The semiconductor layer 102 can be heavily N-type doped or P-type doped to form N-channel or P-channel devices, respectively. The insulator material 107 includes materials such as oxides or nitrides.

[0046] The gates 104a and 104b of the select transistors are formed of a conductive material such as a metal or polysilicon material. Gate dielectric layers 105a and 105b are also provided, which may include a material such as a thin oxide or a high-K material (eg, HfO2). Figure 1C As shown, gate electrodes 104a and 104b, gate dielectric layers (GDLs) 105a and 105b, and semiconductor layer 102 form dual-gate thin-film transistors 130a and 130b. Drain regions 115a and 115b of the transistors are connected to bit line 101. Channel regions 116a and 116b are also shown. Source region 117 is part of a capacitor 131 formed by source region 117, capacitor dielectric layer 106, and conductor layer 103, as described below.

[0047] The capacitor dielectric layer (CDL) 106 includes a material such as a thin oxide or a high-K material (e.g., HfO2). The conductor layer (CL) 103 includes a material such as a metal or polysilicon that forms an electrode of the capacitor 131. The conductor layer 103, the capacitor dielectric layer 106, and the source region 117 of the semiconductor layer 102 form the capacitor 131. Figure 1C shown.

[0048] In one embodiment, the gates 104a and 104b of the transistors are connected to a word line (WL).The conductive layer 103 is connected to a capacitor plate (CP), which is connected to a constant voltage, such as VDD or VSS (eg, 0V).

[0049] Figure 2A An embodiment of a 3D DRAM cell structure according to the present invention is shown. This embodiment is similar to Figure 1A The embodiment shown differs in that a conductor layer (CL) 108 including a material such as metal or polysilicon is formed between the capacitor dielectric layer 106 and the source region 117 of the semiconductor layer 102 to serve as a capacitor electrode to enhance the characteristics of the capacitor 131 .

[0050] Figure 2B Shown is a view taken along line A-A' Figure 2A A top view of a cross section of the unit is shown.

[0051] Figure 3A An embodiment of a 3D DRAM cell structure according to the present invention is shown. This embodiment is similar to Figure 1A The embodiment shown is different in that the semiconductor layer 102 is formed into a different pattern or shape. Figure 1A In the embodiment shown, the channel regions 116a and 116b of the transistor are formed in a horizontal direction. Figure 3A In the illustrated embodiment, the channel regions 116a and 116b of the transistor are formed in a vertical direction. Figure 3A Also shown are insulating layers 121 a and 121 b including a material such as an oxide or nitride material.

[0052] Figure 3B Shown is a view taken along line A-A' Figure 3A A top view of a cross section of the cell structure is shown.

[0053] The vertical channel structure shown in this embodiment is applicable to the cell structures of all other embodiments. For simplicity, the vertical channel structure of other embodiments is not shown, however, these changes are within the scope of the present invention.

[0054] Figure 4A An embodiment of a 3D DRAM cell structure according to the present invention is shown. This embodiment is similar to Figure 1A The embodiment shown differs in that the second gate 104b is excluded. Also shown is an insulating layer 121 comprising a material such as an oxide or nitride material. This forms a single gate select transistor 130a, such as Figure 4C Before forming the insulating layer 121 , bottom portions of the semiconductor layer 102 and the gate dielectric layer 106 are etched through the space occupied by the insulating layer 121 using an isotropic etching process (eg, wet etching).

[0055] Figure 4B Shown is a view taken along line A-A' Figure 4A A top view of a cross section of the cell structure is shown.

[0056] Figure 4C Shown Figure 4A The equivalent circuit of the unit structure is shown.

[0057] Figure 5A FIG. 1 shows an embodiment of a 3D DRAM cell structure according to the present invention. This embodiment forms a two-transistor 2T DRAM gain cell, such as Figure 5A Transistors 130 and 132 are shown. This cell is called a gain cell because the read operation uses current sensing rather than charge sharing as is typically used in conventional DRAM cells.

[0058] Figure 5B Shown is a view taken along line A-A' Figure 5A A top view of a cross section of the cell structure is shown.

[0059] Figure 5C Shown Figure 5AThe equivalent circuit of the unit structure shown in FIG. Figure 4C The circuit embodiment shown is different in that Figure 4C The capacitor 131 shown is replaced by a transistor 132, as shown Figure 5C shown.

[0060] The cell structure includes a write transistor 130 and a storage transistor 132. The gate 133 of the storage transistor 132 acts as a capacitor to store charge to represent data. During a write operation, a voltage is supplied to the selected write word line WWL 135 to turn on the channel of the write transistor 130, thereby writing data from the bit line 101 to the gate 133 of the storage transistor 132.

[0061] In one embodiment, the source of the storage transistor 132 is connected to a source line (SL) 138 (also referred to as a read word line (RWL)). The drain of the storage transistor 132 is connected to the bit line 101. During a read operation, the selected source line 138 is provided with a selected voltage, such as VDD or VSS (0V). If the data stored in the gate 133 of the storage transistor 132 is 1 (VDD), the channel of the storage transistor 132 will turn on to pass the voltage from the source line 138 to the bit line 101. If the data stored in the gate 133 of the storage transistor 132 is 0 (VSS), the channel of the storage transistor 132 will turn off, so no current can flow from the source line 138 to the bit line 101. A sensing circuit (not shown) connected to the bit line 101 detects the current or voltage of the bit line 101 to determine the data being read. Because the read operation is performed without using a charge sharing mechanism, the capacitor size of the cell is reduced. Additionally, the read operations are non-destructive, thus eliminating the need for a restore store operation after each read operation.

[0062] Reference again Figure 5A Bit line 101 is formed of a conductive material such as metal or polysilicon. Semiconductor layer 102 includes a material such as silicon, polysilicon, silicon germanium, or an oxide-based semiconductor material such as indium gallium zinc oxide (IGZO). IGZO is known to have extremely low leakage current in the off state, so its use reduces the size requirements of the capacitor.

[0063] The semiconductor layer 102 forms a channel 116 of the write transistor 130, such as Figure 5C As shown, the semiconductor layer 102 can be heavily N-type doped or P-type doped to form an N-channel or P-channel device, respectively. The insulator 107 includes a material such as an oxide or a nitride.

[0064] Layer 104 forms the gate of write transistor 130, as Figure 5CAs shown. Gate 104 is formed of a conductive material such as a metal or polysilicon material. Gate dielectric layers 105a and 105b include a material such as a thin oxide material or a high-K material such as HfO2. Also shown are a drain region 115, a channel region 116, and a source region 117 of a write transistor 130. The source region 117 is connected to a conductor 133 such as a metal or polysilicon material, which forms a gate 133 of a storage transistor 132, as shown. Figure 5C shown.

[0065] The semiconductor layer 109 forms a channel of the memory transistor 132, such as Figure 5C As shown. Semiconductor layer 109 includes a material such as silicon, polysilicon, silicon germanium, or an oxide-based semiconductor material such as indium gallium zinc oxide (IGZO). IGZO is known to have extremely low leakage current in the off state, so it can reduce the size requirements of the capacitor. Semiconductor layer 109 is heavily N-doped or P-doped to form an N-channel or P-channel device, respectively.

[0066] Figure 5A 1 and 2. The channel region 112, source region 113, and drain region 114 of the memory transistor 132 are shown. The channel region 112 is coupled to the gate 133. The drain region 114 is connected to the bit line 101. The source region 113 is connected to the source line 138, as shown in FIG. Figure 5C The insulator 111 includes a material such as an oxide or a nitride material.

[0067] Figure 6A An embodiment of a 3D DRAM cell structure according to the present invention is shown. This embodiment is similar to Figure 5A The embodiment shown differs in that a conductor layer 110 comprising a material such as metal or polysilicon is formed in contact with the source region 113 of the memory transistor 132 to reduce the resistance of the source line.

[0068] Figure 6B Shown is a view taken along line A-A' Figure 6A A top view of a cross section of the cell structure is shown.

[0069] Figure 7A An embodiment of a 3D DRAM cell structure according to the present invention is shown.

[0070] Figure 7B Shown is a view taken along line A-A' Figure 7A A top view of a cross section of the cell structure is shown.

[0071] Figure 7C Shown 7A to 7B The equivalent circuit of the unit structure shown in FIG. Figure 5CThe embodiment shown differs in that a read transistor 136 is added between the storage transistor 132 and the bit line 101. This structure forms a three-transistor (3T) gain cell. The gate of the read transistor 136 is connected to a read word line (RWL) 137. The source of the storage transistor 132 is connected to a source line (SL) 138. In one embodiment, the source line 138 is connected to a common voltage source, such as VDD or VSS.

[0072] During a read operation, a voltage is supplied to the selected read word line 137 to turn on the channel of the read transistor 136. If the data stored in the gate 133 of the storage transistor 132 is 1 (VDD), the channel of the storage transistor 132 is turned on to pass the voltage from the source line 138 through the read transistor 136 to the bit line 101. If the data stored in the gate 133 of the storage transistor 132 is 0 (VSS), the channel of the storage transistor 132 is turned off, so no current can flow from the source line 138 to the bit line 101. A sensing circuit (not shown) connected to the bit line 101 detects the current or voltage of the bit line 101 to determine the data being read.

[0073] refer to Figure 7A , this embodiment is similar to Figure 5A The embodiment shown is different in that a gate 118 and a gate dielectric layer 105c are formed as shown. The gate 118 is formed of a conductive material such as a metal or polysilicon material. The gate dielectric layer 105c is formed of an insulating material such as a thin oxide or a high-K material such as HfO2. The gate 118 is coupled to the channel region 119 of the semiconductor layer 109 to form a read transistor 136. The drain region 114 of the read transistor 136 is connected to the bit line 101. The source region of the read transistor is connected to the channel 112 of the storage transistor 132. The source region 113 of the storage transistor 132 is connected to the source line SL. Thus, a gate 118 is formed as shown in FIG. Figure 7C The unit circuit is shown in Figure 2. For an additional detailed description of the unit structure, the reader can refer to Figure 5A Description.

[0074] Figure 8A An embodiment of a 3D DRAM cell structure according to the present invention is shown. Figure 8B Shown is a view taken along line A-A' Figure 8A The cross-sectional top view of the unit structure is shown. Figure 7A The embodiment shown is different in that the semiconductor layer 109 is formed using a different pattern or shape. Figure 7A In FIG, the channel region 112 of the memory transistor 132 is formed in a vertical direction. Figure 8AIn FIG. 1 , the channel region 112 of the storage transistor 132 is formed in a horizontal direction. For a detailed description of the unit structure, the reader can refer to Figure 7A Description.

[0075] Figure 9A An embodiment of a 3D DRAM cell structure according to the present invention is shown. Figure 9B Shown is a view taken along line A-A' Figure 9A The cross-sectional top view of the unit structure is shown. Figure 8A The embodiment shown is different in that a conductor layer 110 such as metal or polysilicon is formed and contacts the source region (SR) 113 of the storage transistor 132 to reduce the resistance of the source line. A write transistor 130, a storage transistor 132, and a read transistor 136 are also shown. For a detailed description of the cell structure, the reader can refer to Figure 8A Description.

[0076] Figure 10A An embodiment of a 3D DRAM cell structure according to the present invention is shown. Figure 10B Shown is a view taken along line A-A' Figure 10A The cross-sectional top view of the unit structure is shown. Figure 6A The embodiment shown is different in that the semiconductor layer 109 and the conductor layer 110 are formed using different patterns or shapes. Figure 6A In FIG, the channel region 112 of the memory transistor 132 is formed outside the gate 133. Figure 10A In FIG. 1 , the channel region 112 of the storage transistor 132 is formed inside the gate 133. For a detailed description of the cell structure, the reader may refer to Figure 6A Description.

[0077] although Figures 1A to 10B The embodiment of the 3D cell structure shown uses a DRAM cell as an example, but the disclosed cell structure can also be applied to any other 3D cell technology, such as ferroelectric random access memory (FRAM). The materials used for the components in the disclosed cell structure can vary depending on the technology. Such variations and modifications are within the scope of the present invention.

[0078] Figure 11 The present invention is shown based on Figure 1A The embodiment of the 3D DRAM array structure of the cell structure shown. Figure 1A The cell structure shown is an example, but it is also possible to use Figures 1A to 10B Any of the unit structures shown can be used to form an embodiment of an array structure. For simplicity, embodiments using other unit structures are not shown. However, these embodiments are within the scope of the present invention.

[0079] like Figure 11 As shown, the 3D array structure includes multiple layers of cells to form a stack. As an example, three cell layers including cell layers 120a to 120c are shown. The array also includes insulating layers 122a to 122d, which include materials for separating the cell layers, such as oxide materials. Vertical bit lines 101a to 101c and gates 104a to 104f of the cell selection transistors are also provided. Gates 104a to 104f are connected to word line WL signals. The array also includes conductor layers 103a to 103c that form capacitor plates. Conductor layers 103a to 103c are connected to a common voltage source, such as VDD or VSS.

[0080] Figure 12A An embodiment of a 3D DRAM array according to the present invention is shown. The array includes a plurality of cell stacks 124a to 124c, such as Figure 11 The cell stacks 124a to 124c are separated by vertical slits (e.g., slits 123a and 123b). In one embodiment, the vertical slits 123a and 123b are filled with an insulating material ( Figure 12A ), such as an oxide or nitride material.

[0081] Figure 12B Another embodiment of a 3D DRAM array according to the present invention is shown. This embodiment is similar to Figure 12A The embodiment shown differs in that Figure 12A Vertical slots 123a and 123b are shown filled with a conductive material, such as a metal or polysilicon material, to form vertical capacitor plates 125a and 125b. Vertical capacitor plates 125a and 125b are connected to conductive layers, such as layers 103a to 103c. An insulating layer, such as layer 126, is formed on the sidewalls of word lines, such as word lines 104a to 104f, to prevent word lines 104a to 104f from shorting to vertical capacitor plates 125a and 125b.

[0082] Figure 13A An embodiment of a 3D DRAM cell structure according to the present invention is shown. Figures 13B to 13C Shows the images taken along line AA' and line BB', respectively. Figure 1A The equivalent circuit of this embodiment is shown in FIG. Figure 7C As shown. Gates 135 and 137 are respectively part of the write transistor 130 and the read transistor 136, as shown Figure 7C As shown, gates 135 and 137 are formed of a conductive material, such as metal or heavily doped polysilicon. Gates 135 and 137 are connected to a write word line WWL and a read word line RWL, respectively.

[0083] Figure 13A It also shows that Figure 7C The gate 133 of the memory transistor 132 is shown. The gate 133 is formed of a conductive material such as a metal or a heavily doped polysilicon material. The gate 133 serves as a storage node to store data (VDD or VSS) to turn the memory transistor 132 on or off. Gate dielectric layers 105a to 105c are also shown, including a material such as an oxide or a high-K material such as hafnium oxide (HfO2). Semiconductor layers 140a and 140b form the channel of the transistor. The semiconductor layers 140a and 140b are formed of any suitable semiconductor material, such as silicon, polysilicon, silicon germanium (SiGe), or indium gallium zinc oxide (IGZO). In one embodiment, the semiconductor layers 140a and 140b are thin layers having an N+ or P+ doping type to form a junctionless thin film transistor.

[0084] Figure 13A Also shown is a bit line 101 formed of a conductive material such as a metal or a semiconductor material such as heavily doped polysilicon. A source line (source) 138 is formed of a conductive material such as a metal or a semiconductor material such as heavily doped polysilicon. An insulating layer 141 comprising a material such as an oxide or nitride is also provided.

[0085] To write to the cell, a voltage above the threshold voltage (Vt) is applied to gate 135 to turn on channel 140a. This allows charge (e.g., electrons) to flow from bit line 101 to gate 133. When gate 135 is supplied with a voltage below the threshold voltage, channel 140a is turned off and charge is trapped within gate 133.

[0086] If the voltage stored in the gate 133 is higher than the threshold voltage, the gate 133 turns on the channel 140b under the gate 133. If the voltage stored in the gate 133 is lower than the threshold voltage, the storage node 133 turns off the channel 140b under the gate 133.

[0087] To read data, a voltage higher than the threshold voltage is applied to gate 137 to turn on the portion of channel 140b not covered by gate 133. Bit line 101 and source line 138 are supplied with different voltages, for example, 1V and 0V, respectively. If channel 140b below gate 133 is on, current flows from bit line 101 to source line 138. If channel 140b below gate 133 is off, current does not flow from bit line 101 to source line 138. Sensing circuitry, such as a sense amplifier, can be coupled to bit line 101 or source line 138 to detect the current and determine the data.

[0088] It should be noted that for all embodiments of the unit structure shown herein, the shapes and sizes of the components shown for the unit structure are exemplary. Obviously, the components can have various other shapes and sizes. These variations are within the scope of the present invention.

[0089] In another embodiment, 13A to Figure 13C The illustrated bit line 101, channels 140a and 140b, and gate 133 are formed in various shapes, such as square, rectangular, triangular, or elliptical.

[0090] Figure 13D Shows something like Figure 13A An embodiment of the cell structure of the embodiment shown, but with a different shape for the gate dielectric layer 105b. Figure 13A and Figure 13D In other embodiments, all gate dielectric layers (e.g. Figure 1A to Figure 1B The gate dielectric layers 105a to 105c shown may be formed in different shapes. Such variations are within the scope of the present invention.

[0091] Figure 14A An embodiment of a 3D DRAM cell structure according to the present invention is shown. This embodiment is similar to Figure 13A The embodiment shown differs in that the bit line 101 is formed of a conductive material such as a metal and a semiconductor layer 142 including a material such as heavily doped silicon or polysilicon is formed as a drain region or buffer layer between the bit line 101 and the channels 140a and 140b.

[0092] Figure 14B An embodiment of a 3D DRAM cell structure according to the present invention is shown. This embodiment is similar to Figure 13A The embodiment shown differs in that the channel 140a is formed in a vertical direction rather than a horizontal direction. The drain region (DR) 146 is formed of a conductive material (e.g., metal) or a semiconductor (e.g., heavily doped silicon or polysilicon). Insulating layers 147a, 147b, and 148, including materials such as oxides or nitrides, are also provided.

[0093] Figure 14C An embodiment of a 3D DRAM cell structure according to the present invention is shown. This embodiment is similar to Figure 14B The embodiment shown is different in that the gate 133 is formed at a different position.

[0094] Figure 15A An embodiment of a 3D DRAM cell structure according to the present invention is shown. Figures 15B to 15C Shows the images taken along line AA' and line BB', respectively. Figure 15A The cross-sectional top view of the unit structure is shown. Figure 14A The embodiment shown is different in that the channels 140a and 140b are formed in different shapes. In this embodiment, the channels 140a and 140b are formed as semiconductor layers surrounding the insulating layers 143a and 143b, respectively.

[0095] In one embodiment, Figure 15A The structure shown is formed using the following steps. First, recesses are formed in layers 133 and 138 using an isotropic etching process (e.g., wet etching). Second, semiconductor layers 140a and 140b are formed on the sidewall surfaces of the recesses using a thin film deposition process (e.g., atomic layer deposition (ALD) or epitaxial growth). Next, insulators 143a and 143b are deposited to fill the recesses. Channels 140a and 140b are formed separately.

[0096] Figure 16A An embodiment of a 3D DRAM cell structure according to the present invention is shown. This embodiment is similar to Figure 14A The embodiment shown differs in that the gate 137 and the gate dielectric layer 105c are excluded. Figure 5C The unit structure of the equivalent circuit shown.

[0097] Figure 16B An embodiment of a 3D DRAM cell structure according to the present invention is shown. This embodiment is similar to Figure 15A The embodiment shown differs in that the gate 137 and the gate dielectric layer 105c are excluded. Figure 5C The unit structure of the equivalent circuit shown.

[0098] Similar to 16A to 16B In the embodiment shown, Figures 13A to 21B In all other embodiments of the cell structure shown, the gate 137 and the gate dielectric layer 105c may be excluded to form a Figure 5C The unit structure of the equivalent circuit shown.

[0099] Figure 17A An embodiment of a 3D DRAM cell structure according to the present invention is shown. This embodiment is similar to Figure 13A The embodiment shown differs in that additional insulating layers 145a and 145b including materials such as oxide or nitride materials are formed between the bit line 101 and the gates 135 and 137. This reduces parasitic capacitance and noise coupling between the bit line 101 and the gates 135 and 137. Figure 17A In the embodiment shown, additional insulating layers 145a and 145b may be added to Figures 13A to 21B All other embodiments of the cell structure shown.

[0100] Figure 17BAn embodiment of a 3D DRAM cell structure according to the present invention is shown. This embodiment is similar to Figure 17A The embodiment shown is different in that an additional insulating layer 149 including a material such as an oxide or nitride material is formed between the gate 137 and the source line 138. This reduces parasitic capacitance and noise coupling between the gate 137 and the source line 138. Figure 17B In the embodiment shown, an additional insulating layer 149 may be added to Figures 13A to 21B All other embodiments of the cell structure shown.

[0101] Figure 18A An embodiment of a 3D DRAM cell structure according to the present invention is shown. Figures 18B to 18C Shows the images taken along line AA' and line BB', respectively. Figure 18A The cross-sectional top view of the unit structure is shown. Figure 13A The embodiment shown is different in that the source line 138 is formed in a different shape.

[0102] Figure 19A An embodiment of a 3D DRAM cell structure according to the present invention is shown. Figures 19B to 19C Shows the images taken along line AA' and line BB', respectively. Figure 19A The cross-sectional top view of the unit structure is shown. Figure 13A The embodiment shown is different in that the source line 138 is formed in a different shape.

[0103] Figure 20A An embodiment of a 3D DRAM cell structure according to the present invention is shown. FIG. 20B to FIG. 20C Shows the images taken along line AA' and line BB', respectively. Figure 20A The cross-sectional top view of the unit structure is shown. Figure 16A In the embodiment shown, the difference is that the source line 138 is formed into a different shape. In this embodiment, the semiconductor layer of the channel 140b is formed into a shape as shown in the figure. This shape allows the semiconductor layer of the channel 140b to be shared with the adjacent cell located below the cell, such as Figure 21A shown. Figure 20A Also shown is an insulating layer 144 comprising a material such as an oxide or nitride material.

[0104] Figure 21A Shows the use Figure 20A The cell structure shown forms an embodiment of a structure. Two cells 151a and 151b are shown as an example. Cells 151a and 151b share the semiconductor layer for channels 140c and 140d.

[0105] Figure 21B Shows the use Figure 13A The embodiment of the structure formed by the unit structure shown. Two units 151a and 151b are shown as an example. Figure 21A In the illustrated embodiment, cells 151a and 151b share the semiconductor layer for channels 140c and 140d as shown.

[0106] Figure 22A An embodiment of the cell structure according to the present invention is shown. This embodiment is similar to Figure 21A The embodiment shown differs in that the channel 140c is formed in a different shape. In this embodiment, the channel 140c is formed as a layer. Since the channel 140c is shared by two cells 151a and 151b, the two cells 151a and 151b can be used to store one data value.

[0107] Figure 22B An embodiment of the cell structure according to the present invention is shown. This embodiment is similar to Figure 22A The embodiment shown is different in that the source line 138 is formed into a different shape. In this embodiment, the channel 140c is formed into a disk, which is similar to Figure 18C Disc 140b is shown.

[0108] Figure 22C An embodiment of the cell structure according to the present invention is shown. This embodiment is similar to Figure 22B The illustrated embodiment differs in that insulating layers 141 a and 141 b are formed including a material such as an oxide or nitride material, as shown.

[0109] Figure 22D An embodiment of the cell structure according to the present invention is shown. This embodiment is similar to Figure 22C The embodiment shown differs in that insulating layers 141a and 141b are replaced by read word lines 137a and 137b. Gate dielectric layers 105c and 105d are provided and include a material such as an oxide or a high-k material such as hafnium oxide (HfO2). During a read operation, a voltage is applied to selected read word lines 137a and 137b to turn on channel 140c beneath the read word lines. Unselected read word lines 137a and 137b are applied with a voltage to turn off channel 140c beneath the read word lines. This allows current to flow only from the selected cell to source line 138.

[0110] Figure 22E Another embodiment of the cell structure according to the present invention is shown. This embodiment is similar to Figure 22DThe embodiment shown differs in that channel 140c is formed in a different shape or pattern. Insulating layer 143 includes a material, such as an oxide or nitride material, that isolates channels 140c and 140d. This allows cells 151a and 151b to be read independently by selecting read word line 135a or 135b, thereby activating channel 140c or 140d, respectively, beneath the selected read word line.

[0111] Figure 23A The use of the present invention is shown Figure 13A The unit structure shown is used as an example to form an embodiment of a 3D array structure. The 3D array structure can be used Figures 13A to 21B The 3D array structure includes a plurality of vertical bit lines, such as bit lines 101a to 101c. Each bit line is connected to a plurality of cells, such as cells 150a to 150d. The array structure also includes write word lines 135a to 135d, read word lines 137a to 137d, source lines 138a to 138d, and insulating layers 148a to 148d, such as oxide or nitride materials, between the cells.

[0112] Figure 23B The use of the present invention is shown Figure 16A The unit structure shown is used as an example to form an embodiment of a 3D array structure. The 3D array structure can be used Figures 13A to 21B This embodiment is similar to Figure 23A The embodiment shown differs in that read word lines 137a to 137d are excluded.

[0113] While there has been shown and described exemplary embodiments of the present invention, it will be apparent to those skilled in the art that, based on the teachings herein, changes and modifications may be made without departing from the exemplary embodiments and their broader aspects. It is therefore intended that the appended claims include within their scope all changes and modifications that come within the true spirit and scope of the exemplary embodiments of the present invention.

Claims

1. A memory cell structure comprising: vertical bit lines; a first semiconductor layer surrounding a first portion of the vertical bit line; a first gate surrounding the first semiconductor layer; a second semiconductor layer surrounding a second portion of the vertical bit line; A gate dielectric layer surrounds a third portion of the vertical bit line, wherein the gate dielectric layer separates the first semiconductor layer and the first gate from the second semiconductor layer.

2. The memory cell structure according to claim 1, wherein: The first gate is coupled to the second semiconductor layer to form a first channel region. 3 . The memory cell structure according to claim 1 , further comprising a second gate coupled to the first semiconductor layer to form a second channel region. 4 . The memory cell structure according to claim 1 , further comprising a third gate coupled to the second semiconductor layer to form a third channel region. 5 . The memory cell structure according to claim 1 , further comprising a conductor surrounding the second semiconductor layer.

6. A memory cell structure comprising: vertical bit lines; a first semiconductor layer surrounding a first portion of the vertical bit line; a first gate surrounding the first semiconductor layer; a gate dielectric layer surrounding the first semiconductor layer and the first gate; and A second semiconductor layer surrounds the second portion of the vertical bit line and is located below a bottom portion of the gate dielectric layer.

7. The memory cell structure according to claim 5, wherein: The first gate is coupled to the second semiconductor layer to form a first channel region. 8 . The memory cell structure according to claim 5 , further comprising a second gate coupled to the first semiconductor layer to form a second channel region. 9 . The memory cell structure according to claim 5 , further comprising a conductor surrounding the second semiconductor layer.

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