Programmable hybrid memory and capacitive device in DRAM process

Abstract

A DRAM fabrication process for producing a semiconductor die adapted to have capabilities as both a hybrid memory and a power supply capacitance. The DRAM array on the semiconductor die may be individually selected to function as a memory or as a supplemental capacitance on a power distribution network serving as circuitry on one or more semiconductor dies in a three-dimensional active-to-active (AoA) stacked semiconductor die package configuration. Defective DRAM array trench capacitors may be reused for use as supplemental capacitance on a power distribution network. When the power monitor senses that additional power capacitance is required, the DRAM array trench capacitor may be dynamically reassigned as a supplemental capacitance.

Description

Technical Field

[0001] Embodiments of the present invention generally relate to integrated circuit devices having active-on-active (AoA) stacked semiconductor dies, and particularly to AoA stacks having dynamic random access memory (DRAM) cells to provide a combination of both memory and power network capacitance. Background Art

[0002] Electronic products such as tablets, computers, copiers, digital cameras, smartphones, control systems, and ATMs often utilize electronic components that utilize chip packaging to increase functionality and component density. Conventional chip packaging solutions typically utilize multiple integrated circuit (IC) dies mounted on a single package substrate. The IC dies may include memory, logic, processors, or other IC devices.

[0003] The power density of planar programmable device architectures has been steadily increasing as fabrication nodes shrink the feature sizes of computing logic. This has driven innovation in power delivery network (PDN) technology, including advances in packaging, interposers, and silicon used to regulate power and reduce electrical noise. To manage the electrical noise and voltage drops caused by transient power consumption, capacitance is added at every power distribution level in systems and devices—discrete capacitors between the board voltage regulator module (VRM) and the package (which surrounds or encapsulates the IC device); additional capacitors on the package next to the IC device or embedded in the IC's shadow; trench capacitors embedded in the interposer of the chip-on-wafer-on-substrate (CoWoS); metal-insulator-metal capacitors (MIMCAPs) embedded in the upper metal layer of the silicon die; and metal-oxide-semiconductor capacitors (MOSCAPs) constructed from transistors on the silicon itself. The various capacitance solutions present performance, cost, and form factor tradeoffs, and power integrity can be a high priority for achieving efficient computing architectures.

[0004] With the implementation of three-dimensional (3D) IC devices, compute and power densities have jumped dramatically, unmatched by the ability to distribute power or access off-chip memory, both of which are limited by the planar surface area of the package pins for power and input-output (I / O) at the base of the semiconductor die stack. High-speed memory access (e.g., high-bandwidth memory (HBM) DRAM) is further limited by the linear edge of the device. Neither the edge nor the surface of a planar IC device scales when the device is stacked, creating a discrepancy between the ratio of complementary metal-oxide-semiconductor (CMOS) logic to I / O relative to planar devices. Furthermore, due to the higher logic density, the compute logic is almost certainly thermally constrained and / or has power integrity issues. This presents an opportunity to restructure the device to balance the tradeoffs of memory hierarchy and power distribution in a way that was previously impossible due to the opportunity cost of the required silicon.

[0005] In architectures that maximize computational density within the thermal envelope, power efficiency can be improved by minimizing the cost of data movement through an extended memory hierarchy, thereby increasing the locality of data being computed, without fully utilizing the 3D silicon area. For example, the relative cost of accessing 3D-connected level 2 cache memory (L2 SRAM) is an order of magnitude lower than that of off-chip HBM, shifting power consumption from data movement and I / O to further increasing maximum computational capacity. Furthermore, the bandwidth between tiers (to 3D-connected SRAM) is more than an order of magnitude greater than the bandwidth to off-chip HBM. While an improvement over planar devices, this technology has drawbacks. SRAM consumes more static power than DRAM, has approximately 10 times lower density, and is manufactured using standard CMOS processes, leaving little opportunity to improve power integrity by adding capacitance.

[0006] To improve power integrity, an alternative process can be used to fabricate a trench capacitor layer with a density approximately 50-100 times higher than that of MOSCAPs fabricated in standard CMOS processes. While this process may be inexpensive compared to the logic layer, it is unlikely to be compatible with any other useful resources, meaning that an entire layer must be dedicated solely to capacitance. The returns on increasing capacitance gradually diminish, and capacitors significantly smaller than the full layer area are required to mitigate supply voltage drops.

[0007] Therefore, there is a need to improve power distribution in an AoA stack and to more efficiently utilize IC die area of devices in an AoA stack. Summary of the Invention

[0008] Dedicating an entire semiconducting die layer to capacitors comes at the opportunity cost of lost logic area, and the ideal solution would be to dedicate a small portion of a die to dense capacitors and the remainder to logic or memory. Active-to-active / 3D integration is an emerging technology in the semiconductor industry that allows for dense interconnects across a flat surface between multi-layer silicon devices. Adding a third dimension to device design fundamentally changes the impact of architectural tradeoffs and allows for a reevaluation of memory hierarchy and power delivery methods. Embodiments disclosed herein describe the construction of 3D devices in which one or more layers, fabricated using DRAM processes, consist of multiple trench capacitors, both for memory cells and to enhance their power delivery network (PDN). In one embodiment, trench capacitors in one silicon layer can be used as capacitors in the PDN for CMOS logic in an adjacent layer. In one embodiment, a method is provided for programmable assignment of trench capacitors as power capacitors or for memory cells in at least one semiconductor die. In one embodiment, a silicon reclamation method is provided in which defective memory elements are identified and dynamically reassigned as capacitors. Utilizing one or more silicon layers fabricated in a DRAM process, hybrid memory and power capacitor planes can be used to improve both the memory hierarchy and power integrity characteristics of the CMOS logic layer in an AoA 3D device.

[0009] The advantage of using DRAM processes to produce semiconductor dies suitable for use as both hybrid memory and capacitors in power distribution is that an optimal balance of area can be dedicated to the extended memory hierarchy, and transient power effects can be exploited and compensated for to maximize the computational and power efficiency of the device. DRAM cells use small trench capacitors to store data rather than power, but a small portion of these memory storage capacitors can be reused as distributed power capacitors throughout the device, while still providing much higher memory density and equivalent bandwidth than SRAM in CMOS logic dies.

[0010] Defect tolerance is another consideration for device architecture, which becomes more pronounced for AoA products because wafer-to-wafer (WoW) hybrid bonding increases the physical size of the silicon by a factor equal to the number of layers and reduces the probability of defect-free devices. Typical strategies for defect tolerance include fine-grained or coarse-grained redundancy. For example, a fine-grained redundancy mechanism for DRAM can include additional columns in each memory bank and a mechanism to disable columns with defective cells by shifting the output to select only from cells known to be working. Similarly, a coarse-grained redundancy mechanism can include an entire redundant memory bank, which can be configured to transparently replace another entire memory bank that is not working. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order that the manner in which the above-described features of the present invention may be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the drawings illustrate only typical embodiments of the invention and are therefore not to be considered limiting of the scope of the invention, as the invention may admit to other equally effective embodiments.

[0012] FIG1 illustrates a schematic isometric representation of an Adaptive Compute Acceleration Platform (ACAP) device configuration according to one or more specific example embodiments of the present disclosure.

[0013] 2 illustrates a schematic diagram representation of 16-bit DRAM banks in a 4×4 configuration according to one or more specific example embodiments of the present disclosure.

[0014] 3 illustrates a schematic representation of a trench capacitor bank directly connected to the power rails of adjacent logic, according to one or more specific example embodiments of the present disclosure.

[0015] 4 illustrates a schematic diagram representation of a 16-bit DRAM bank in a 4×4 configuration with capacitor enable circuitry according to one or more specific example embodiments of the present disclosure.

[0016] FIG5 illustrates a schematic block diagram of an ACAP device with dynamic assignment of DRAM and capacitor arrays according to one or more specific example embodiments of the present disclosure.

[0017] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements of one embodiment may be beneficially incorporated in other embodiments. DETAILED DESCRIPTION

[0018] Embodiments of the present disclosure generally involve dedicating at least one silicon layer in an AoA stack to a plurality of trench capacitors that can be adapted for use as both DRAM memory storage and power network capacitance. The result is a computing device with improved power efficiency, both in terms of reduced off-chip data movement and lower dropout voltage. In addition to the core concept of hybrid memory and capacitance layers, it is contemplated and within the scope of the present disclosure to add programmability to dynamically select which trench capacitors or groups of trench capacitors are connected to power and which can be used as memory. Programmability can be used to tune (adapt) power and memory characteristics to specific applications, or as a mechanism for defect tolerance and silicon recycling (reuse).

[0019] Referring to FIG1 , a schematic isometric representation of an adaptive compute acceleration platform (ACAP) device configuration according to one or more specific example embodiments of the present disclosure is depicted. As shown in FIG1 , a 3D stacked device 100 may include, for example, but not limited to, a four-deep stack comprising a layer of CMOS logic 102, a semiconductor structure 106 (i.e., a DRAM capacitor structure 120) replaced with a silicon layer fabricated in a DRAM process, an input / output (I / O) layer 108, an interposer substrate 110, and a high-bandwidth memory (HBM) 112. The DRAM capacitor structure 120 may include a portion of trench capacitors 232 for memory and the remainder for power network capacitance. It is contemplated and within the scope of the present disclosure that the DRAM capacitor structure 120, including the silicon layer of trench capacitors 232, may be used for both DRAM cells and PSN capacitors, not limited to CMOS logic, and may also benefit (enhance) the memory and power characteristics of other semiconductor devices formed in the 3D stack.

[0020] Hybrid memory and capacitor implementation In the simplest implementation, the 3D stacked ACAP device 100 can be designed with one or more layers fabricated in a DRAM process, and a portion of the trench capacitors used as voltage storage capacitors can be statically allocated to a power distribution network (PDN) by hardwiring the trench capacitors to the power rail without using interposer transistors.

[0021] Referring to FIG2 , a schematic diagram illustrating a 16-bit DRAM bank in a 4×4 configuration is shown, according to one or more specific example embodiments of the present disclosure. Typical banks in modern DRAM products are much larger, for example, 64k×8k. Word lines 222 run horizontally from a selector circuit (row address demultiplexer 224) on one edge of a DRAM array 226 to select a word, and bit lines 228 are routed vertically to sense amplifiers 230 on the adjacent edge to read the memory contents (data) stored in trench capacitors 232.

[0022] Referring to FIG3 , a schematic diagram of a trench capacitor bank directly connected to the power rail of adjacent logic is depicted, according to one or more specific example embodiments of the present disclosure. In one embodiment, trench capacitors 332 (trench capacitors 232 ) in the entire trench capacitor array 326 can be directly connected to the power rail 334 of the adjacent logic circuit without any transistors coupled to the trench capacitor array 326 . This type of coarse-grained capacitor design is the simplest, with perfect regularity across the trench capacitor array 326 . The power rail 334 can be coupled to a power distribution network (PDN) 336 .

[0023] In another embodiment, DRAM array 226 can use a portion of its trench capacitors 232 for memory in a typical configuration, where some columns omit transistors 238 and instead route trench capacitors 232 directly to bit lines 228, which are connected to power through-silicon vias (TSVs). Finer granularity may be more attractive for reducing wire resistance in the power delivery network (PDN) by distributing power directly through the Z plane with fewer X / Y dimensions.

[0024] In another embodiment, an array of trench capacitors 232, independent of the bank configuration, can be added to or adjacent to one or more DRAM arrays 226. For example, trench capacitors 232 located near precharge circuits and / or sense amplifiers 230 typically need to drive larger transient currents and can significantly benefit from the additional decoupling capacitance of nearby trench capacitors 332. This can improve timing margins and / or improve reliability of the overall power distribution network (PDN).

[0025] Programmable allocation of capacitors / memory Referring to FIG4 , a schematic diagram depicting a 16-bit DRAM bank in a 4×4 configuration with capacitor-enable circuitry is depicted, according to one or more specific example embodiments of the present disclosure. By adding a capacitor-enable transistor 440 in series with the DRAM cell transistor 238, programmability can be increased, at the expense of increasing the resistance to the trench capacitor 232, allowing the DRAM memory bank (DRAM array 426) to be dynamically reconfigured to provide capacitance to a power delivery network (PDN). As shown in FIG4 , each bitline 228 of the DRAM array 426 has a gated connection to a power rail 434, where a global signal (capacitor-enable signal 442) enables coupling between the bitline 228 and the power rail 434 and pulls all wordlines 222 of the DRAM array 226 high, coupling individual trench capacitors 232 to the bitline 228. Thus, using the circuit shown in FIG4 , defective trench capacitors 232 of the DRAM array 426 can be connected to the power rail 434 by turning on the capacitor-enable transistor 440, thereby coupling those trench capacitors 232 to the PDN. By turning off the capacitor enable transistor 440, the other trench capacitors 232 of the functional DRAM array 426a can be used as DRAM memory.

[0026] Defect tolerance As an extension of the circuit configuration depicted in FIG4 , the recovery of useful silicon can be maximized by adding a defect tolerance mechanism that reassigns the memory banks of the DRAM array 426 to a capacitive network coupled to the PDN due to the design failure of a single cell, sense amplifier, and / or row controller. In conventional DRAM products, defects result in "wasted" silicon, which can outweigh the cost of reconfiguring the programmability of cells that are unsuitable for use as a PDN. If the associated supporting electronics of the trench capacitors 232 of FIG4 prove partially defective or inoperable for their intended purpose as a functional DRAM array 426, they can be "repurposed."

[0027] In embodiments utilizing a 3D stack with multiple DRAM arrays 426 on a semiconductor die, i.e., a DRAM capacitor structure 120, multiple identical dies can be stacked together, but a single die can then be configured / assigned to function as either traditional DRAM or as a decoupling capacitor layer. This avoids having to deserialize two different dies and can also provide a means of collecting dies that are not functional enough to perform as operational DRAM. As an example, a nine-high stack of DRAM dies (DRAM capacitor structure 120) can be fabricated, with one layer serving as the decoupling capacitor layer for the entire DRAM stack. After fabrication, particularly in the case of wafer-to-wafer (WoW) bonding, where known good die testing is not practical for matching good die to good die, the individual stacks can be tested to determine which (if any) layers or sub-regions of layers are defective from a DRAM functionality perspective. If at most one layer or sub-region of a layer is defective for DRAM operation but can function as a decoupling capacitor, that layer or sub-region can be configured as such, leaving the remaining eight fully functional DRAM layers to provide the desired DRAM functionality. (If no layer or sub-region of a layer is defective, then a layer can be arbitrarily selected to provide the required decoupling capacitance.) Dynamic Assignment of DRAM and Capacitor Arrays Referring to FIG5 , a schematic block diagram of an ACAP device with dynamic assignment of DRAM and capacitor arrays is depicted, according to one or more specific example embodiments of the present disclosure. The ACAP device 100a may include multiple stacked integrated circuit dies in a WoW configuration. The WoW configuration may include an input-output die 108, a processing and control logic die 104, multiple DRAM / capacitor dies 120, a configuration selection circuit 550, a power distribution network (PDN) 552, and power quality monitoring and control 554 associated with each DRAM / capacitor die 120. The power quality monitoring and control 554 is adapted to detect when certain DRAM arrays should be dynamically reassigned to the capacitor arrays when more capacitance needs to be coupled to the PDN 552. The power quality monitoring and control 554 detects when there is a power supply voltage drop or when large data transfers are occurring, thereby improving data transmission immunity and data integrity during current surges that may cause power supply voltage drops. Power quality monitoring and control 554 may communicate with configuration selection circuitry 550 via communication line 560 to relay detection of power problems and their locations.

[0028] The configuration of which DRAM arrays 226 will be used for DRAM operation and which will be used as supplemental PDN capacitors can also be programmed to occur before a power-intensive event occurs and / or when a defective DRAM array is known to be usable only as supplemental PDN capacitors. Configuration selection circuitry 550 can select which of the DRAM arrays 226 will be used for DRAM operation and which other DRAM arrays 226 will be used as supplemental PDN capacitors on control line 442. Configuration selection circuitry 550 can also communicate with processing and control logic die 104 via communication bus 556 to receive instructions regarding which DRAM arrays 226 will be used as supplemental PDN capacitors (dynamic selection programming). Configuration selection circuitry 550 can also communicate with processing and control logic die 104 to notify which DRAM arrays 226 can be used only as supplemental PDN capacitors.

[0029] The allocation of DRAM elements for use as PDN capacitors can be dynamically assigned based on overall system power performance requirements. Power monitors (e.g., power quality monitoring and control 554) can be included at various locations within the CMOS layers and device packaging to determine the quality of the power supply at those locations. These power quality monitoring and control 554 can be adapted to detect when the quality of the power supply approaches a threshold triggering an invalid condition, indicating the need for additional capacitance coupled to the PDN. Once triggered, several methods can be used to dynamically transition the memory elements. In hardware-managed cache-like scenarios, the memory elements can be invalidated and remain in that state. Alternatively, in software-managed scenarios where a memory manager (instructing configuration selection circuitry 550) allocates memory, the contents of those memory elements can be migrated and then marked as unused. In any of these control scenarios, or in other scenarios, the memory storage elements (trench capacitors 232) used as capacitors can be reclaimed when the power quality monitoring and control 554 indicates when the threshold for valid operating conditions has been met.

[0030] While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope of the invention is determined by the claims that follow.

Claims

1. An integrated circuit (IC) stack, comprising: a plurality of semiconductor IC dies stacked together and having circuit interconnections between the plurality of semiconductor IC dies; and at least one semiconductor IC die of the plurality of semiconductor IC dies includes a plurality of dynamic random access memory (DRAM) arrays, wherein each DRAM array of the plurality of DRAM arrays includes a plurality of trench capacitors and support circuitry for the plurality of trench capacitors, The plurality of trench capacitors of at least one DRAM array of the plurality of DRAM arrays is adapted to be coupled to a power bus. 2 . The IC stack of claim 1 , wherein the power bus is adapted to be coupled to a power distribution network (PDN) of at least one semiconductor IC die of the plurality of semiconductor IC dies. 3 . The IC stack of claim 1 , wherein the plurality of trench capacitors are adapted to be directly coupled to the power bus. 4 . The IC stack of claim 1 , wherein the plurality of trench capacitors are adapted to be coupled to the power bus through the support circuitry. 5 . The IC stack of claim 1 , wherein the plurality of trench capacitors are adapted to be coupled to a plurality of power busses.

6. The IC stack of claim 1, wherein the plurality of DRAM arrays without trench capacitors coupled to the power bus are capable of functioning as memory.

7. The IC stack of claim 6, wherein configuration selection circuitry selects which of the plurality of DRAM arrays are used for memory and which other of the plurality of DRAM arrays have trench capacitors coupled to the power bus.

8. The IC stack of claim 7, wherein the configuration selection circuit selects which of the plurality of DRAM arrays have trench capacitors coupled to the power bus when logic activity or current consumption increases.

9. The IC stack of claim 7, wherein the configuration selection circuit dynamically assigns which of the plurality of DRAM arrays are used for memory and which other of the plurality of DRAM arrays have trench capacitors coupled to the power bus.

10. The IC stack of claim 9, wherein the trench capacitor is selected for coupling to the power bus when a power quality monitoring circuit detects a low power voltage or a fault at the trench capacitor's associated DRAM array.

11. A system of integrated circuit (IC) dies arranged in a three-dimensional stacked configuration, the system comprising: an interposer substrate adapted to connect to an external circuit; a logic circuit IC die, the logic circuit IC die being electrically coupled to the interposer substrate; at least one memory IC die, the at least one memory IC die comprising a plurality of dynamic random access memory (DRAM) arrays, each DRAM array of the plurality of DRAM arrays comprising a plurality of trench capacitors and support circuitry for the plurality of trench capacitors; and At least one digital logic and processing IC die, Wherein some of the plurality of DRAM arrays are used for memory and some other of the plurality of DRAM arrays have associated trench capacitors coupled to a power bus adapted to be coupled to a power distribution network (PDN) for supplying power to the IC die.

12. The system of claim 11, wherein selection of which of the plurality of DRAM arrays are used for memory and which other of the plurality of DRAM arrays not used for memory have trench capacitors coupled to the power bus is dynamically assigned.

13. The system of claim 11 , wherein the configuration selection circuit is programmed to select which of the plurality of DRAM arrays are used for memory and which other of the plurality of DRAM arrays not used for memory have trench capacitors coupled to the power bus.

14. The system of claim 11, wherein signals and power are coupled between the stacked ICs through through silicon vias (TSVs).

15. A method for capacitively coupling to a power distribution network (PDN) in an integrated circuit (IC) stack, the method comprising: selecting at least one dynamic random access memory (DRAM) array of a plurality of dynamic random access memory (DRAM) arrays for use as a memory, wherein each of the plurality of DRAM arrays includes a plurality of trench capacitors and support circuitry for the plurality of trench capacitors, and wherein the plurality of DRAM arrays are within at least one semiconductor IC die of a plurality of semiconductor IC dies stacked together with circuit interconnections between the plurality of semiconductor IC dies; as well as Trench capacitors not associated with the at least one of the plurality of DRAM arrays selected for use as memory are selected for coupling to a power bus adapted to couple to the PDN.

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