Thin film capacitor, method for manufacturing same, and electronic circuit board provided with thin film capacitor

Abstract

The invention provides a thin film capacitor which can be accessed from two sides. A thin film capacitor (1) is provided with: a metal foil (10), the main surfaces (11, 12) of which are roughened; a dielectric film (13) that covers the main surfaces (11, 12); an electrode layer (E1) which is in contact with the metal foil (10) via an opening provided in the dielectric film (13), and which has a surface comprising a metal terminal (41); an electrode layer (E2) which is in contact with the dielectric film (13) without being in contact with the metal foil (10), and which has a surface comprising a metal terminal (42); and an electrode layer (E3) which is in contact with the dielectric film (13) without being in contact with the metal foil (10), and which has a surface comprising a metal terminal (52).

Description

Technical Field

[0001] The present invention relates to a thin film capacitor and a method for manufacturing the same, and more particularly to a thin film capacitor using a metal foil and a method for manufacturing the same. Furthermore, the present invention relates to an electronic circuit board including such a thin film capacitor. Background Art

[0002] Circuit boards that carry ICs typically feature decoupling capacitors to stabilize the potential of the power supply to the IC. Multilayer ceramic chip capacitors are commonly used as decoupling capacitors, and the required decoupling capacitance is ensured by mounting multiple multilayer ceramic chip capacitors on the surface of the circuit board.

[0003] In recent years, as circuit boards have become smaller, there has been a shortage of space for mounting multiple multilayer ceramic chip capacitors. Consequently, film capacitors that can be embedded in circuit boards have sometimes been used instead of multilayer ceramic chip capacitors (see Patent Documents 1 to 4).

[0004] The thin-film capacitor described in Patent Document 1 has a structure in which a porous metal substrate is used, and an upper electrode is formed on the surface of the substrate via a dielectric film. The thin-film capacitor described in Patent Document 2 has a structure in which a metal substrate with one main surface roughened is used, and an upper electrode is formed on the roughened surface via a dielectric film. The thin-film capacitors described in Patent Documents 3 and 4 have a structure in which a conductive porous substrate is formed on the support portion, and an upper electrode is formed on the roughened surface via a dielectric film.

[0005] Prior art literature

[0006] Patent Literature

[0007] Patent Document 1: International Publication No. WO2015-118901

[0008] Patent Document 2: International Publication No. WO2018-092722

[0009] Patent Document 3: International Publication No. WO2017-026247

[0010] Patent Document 4: International Publication No. WO2017-014020 Summary of the Invention

[0011] Problems to be solved by the invention

[0012] However, the thin film capacitor described in Patent Document 1 has a side electrode structure, so the electrode line length is long, so there is a structural problem that ESR (equivalent series resistance) and ESL (equivalent series inductance) become larger. In addition, since the thin film capacitor described in Patent Document 1 uses a metal substrate that is made porous as a whole, it is not easy to separate the lower electrode composed of the metal substrate and the upper electrode covered with the metal substrate through a dielectric film, which easily causes a short circuit problem. In addition, since the thin film capacitor described in Patent Document 2 has one main surface of the metal substrate functioning as the upper electrode and the other main surface functioning as the lower electrode, in order to arrange a pair of terminal electrodes on the same surface, it is necessary to lead the electrodes through the side of the [0] element, which has a problem of complex structure. Furthermore, since the pair of terminal electrodes of the thin film capacitors described in Patent Documents 3 and 4 are arranged on both sides of the metal substrate, it is impossible to access the pair of terminal electrodes from one side. In addition, since a support body is used, there is a problem of overall thickness becoming thicker.

[0013] Therefore, an object of the present invention is to provide an improved thin film capacitor and a method for manufacturing the same. In addition, an object of the present invention is to provide an electronic circuit board having such a thin film capacitor.

[0014] Technical solutions to problems

[0015] A thin film capacitor according to one aspect of the present invention comprises: a metal foil having a roughened first principal surface and a roughened second principal surface located opposite the first principal surface; a first dielectric film covering the first principal surface of the metal foil; a second dielectric film covering the second principal surface of the metal foil; a first electrode layer in contact with the metal foil via an opening provided in the first dielectric film, the surface of which comprises a first metal terminal; a second electrode layer in contact with the first dielectric film rather than the metal foil, the surface of which comprises a second metal terminal; and a third electrode layer in contact with the second dielectric film rather than the metal foil, the surface of which comprises a third metal terminal.

[0016] In a method for manufacturing a thin-film capacitor according to one aspect of the present invention, a first principal surface and a second principal surface opposite to the first principal surface of a metal foil are roughened, a first dielectric film and a second dielectric film are formed on the first principal surface and the second principal surface of the metal foil, respectively. A portion of the first dielectric film is removed to expose a portion of the metal foil, thereby forming a first electrode layer that contacts a portion of the metal foil and has a first metal terminal on its surface; a second electrode layer that contacts the first dielectric film but does not contact the metal foil and has a second metal terminal on its surface; and a third electrode layer that contacts the second dielectric film but does not contact the metal foil and has a third metal terminal on its surface.

[0017] Effects of the Invention

[0018] According to the present invention, since the opening is provided in a portion of the first dielectric film, a pair of terminal electrodes can be arranged on the same surface without using side electrodes, etc. Furthermore, since the third metal terminal is provided on the back side, access is possible from both sides. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1A It is a schematic cross-sectional view for explaining the structure of a thin film capacitor 1 according to the first embodiment of the present technology. Figure 1B It is a schematic top view of the film capacitor 1 .

[0020] Figures 2A to 38A is a schematic cross-sectional view for explaining the manufacturing process of the film capacitor 1, showing the Figures 2B to 38B The cross section along line AA is shown.

[0021] Figure 39 It is a schematic cross-sectional view for explaining the structure of a thin film capacitor 2 according to a second embodiment of the present technology.

[0022] Figure 40 It is a schematic cross-sectional view for explaining the structure of a thin film capacitor 3 according to a third embodiment of the present technology.

[0023] Figure 41 1 is a schematic cross-sectional view for explaining the structure of a thin film capacitor 4 according to a fourth embodiment of the present technology.

[0024] Figure 42 1 is a schematic cross-sectional view showing an electronic circuit substrate having a structure in which a thin film capacitor 1 is embedded in a multilayer substrate 100 .

[0025] Figure 43 1 is a schematic cross-sectional view showing an electronic circuit board having a structure in which a thin film capacitor 1 is mounted on the surface of a multilayer substrate 300 . DETAILED DESCRIPTION

[0026] Hereinafter, embodiments according to the technology of the present invention will be described in detail with reference to the accompanying drawings.

[0027] Figure 1A It is a schematic cross-sectional view for explaining the structure of a thin film capacitor 1 according to the first embodiment of the present technology. Figure 1B It is a schematic plan view of the film capacitor 1 . Figure 1A Indicates along Figure 1B The cross section along line AA is shown.

[0028] like Figure 1A and Figure 1BAs shown, the thin film capacitor 1 of the first embodiment includes a metal foil 10, electrode layers E1 and E2 formed on the upper surface, or principal surface 11, of the metal foil 10, and electrode layers E3 and E4 formed on the lower surface, or principal surface 12, of the metal foil 10. The metal foil 10 is made of a metal material such as aluminum, copper, chromium, nickel, or tantalum, and its two principal surfaces 11 and 12 are roughened. Aluminum is the most preferred material for the metal foil 10. The center portion of the metal foil 10 in the thickness direction is not roughened. A dielectric film 13 is formed on the roughened principal surfaces 11 and 12 of the metal foil 10. When the metal foil 10 is made of aluminum, the dielectric film 13 may also be made of, for example, aluminum oxide.

[0029] On the upper surface, principal surface 11, of metal foil 10, a plurality of ring-shaped or polygonal insulating resins 21 and insulating resin 23 extending along the periphery of principal surface 11 are provided. Furthermore, on the lower surface, principal surface 12, of metal foil 10, a ring-shaped or polygonal insulating resin 22 and insulating resin 24 extending along the periphery of principal surface 12 are provided. Dielectric film 13 is removed from the region surrounded by insulating resins 21 and 22.

[0030] Furthermore, the electrode layer E1 is formed in a region surrounded by the insulating resin 21, and the electrode layer E2 is formed outside the region surrounded by the insulating resin 21 and in a region surrounded by the insulating resin 23. Thus, the electrode layer E1 is connected to the unroughened central portion of the metal foil 10, while the electrode layer E2 is insulated from the metal foil 10 by the dielectric film 13. Furthermore, the electrode layers E1 and E2 are insulated by the insulating resin 21. Thus, the electrode layers E1 and E2 function as a pair of capacitor electrodes facing each other via the dielectric film 13.

[0031] Similarly, electrode layer E4 is formed in an area surrounded by insulating resin 22, and electrode layer E3 is formed outside the area surrounded by insulating resin 22 and in an area surrounded by insulating resin 24. Thus, electrode layer E4 is connected to the unroughened center portion of metal foil 10, while electrode layer E3 is insulated from metal foil 10 by dielectric film 13. Furthermore, electrode layer E3 and electrode layer E4 are insulated by insulating resin 22. Thus, electrode layer E3 and electrode layer E4 function as a pair of capacitor electrodes facing each other via dielectric film 13.

[0032] The electrode layers E1 and E4 respectively have metal terminals 41 and 51 constituting the surfaces of the electrode layers E1 and E4. The electrode layers E1 and E4 may also include seed layers 31 and 32 respectively provided between the metal terminals 41 and 51 and the metal foil 10. Grooves 14 and 15 are respectively formed in the metal foil 10 in the portions connecting the electrode layers E1 and E4. The depth of the grooves 14 and 15 is greater than the thickness of the roughened surface portion of the metal foil 10. As a result, the unroughened central portion of the metal foil 10 is exposed at the bottom of the grooves 14 and 15. The central portion of the metal foil 10 exposed at the bottom of the grooves 14 and 15 may also be flat. The bottom of the groove 14 is in contact with the seed layer 31 and the insulating resin 21, and the bottom of the groove 15 is in contact with the seed layer 32 and the insulating resin 22.

[0033] Electrode layers E2 and E3 include a conductive polymer layer 30 that is not in contact with metal foil 10 but in contact with dielectric film 13; and metal terminals 42 and 52 disposed on conductive polymer layer 30 and forming the surfaces of electrode layers E2 and E3, respectively. Electrode layers E2 and E3 may also include seed layers 31 and 32 disposed between metal terminals 42 and 52 and conductive polymer layer 30, respectively.

[0034] Metal terminals 41, 42, 51, 52 can be made of metal materials such as copper, nickel, gold, and alloys thereof. Metal terminals 41, 42, 51, 52 may also have a structure formed by stacking these metal materials. Seed layers 31, 32 are preferably made of a material that provides a barrier function to prevent the diffusion of copper and other materials contained in metal terminals 41, 42, 51, 52, has high adhesion to metal foil 10 and conductive polymer layer 30, and does not damage conductive polymer layer 30.

[0035] like Figure 1A As shown, a plurality of through-holes 16 are provided in the metal foil 10. The inner walls of the through-holes 16 are covered with a dielectric film 13, thereby preventing the metal foil 10 from being exposed in the portions where the through-holes 16 are provided. The through-holes 16 are provided at positions overlapping both the electrode layers E2 and E3, and a conductive polymer layer 30 is provided in the area surrounded by the inner walls of the through-holes 16. Thus, the conductive polymer layer 30 provided on the main surface 11 side of the metal foil 10 and the conductive polymer layer 30 provided on the main surface 12 side of the metal foil 10 are connected via the conductive polymer layer 30 provided within the through-holes 16.

[0036] Through such a structure, the electrode layers E1 and E4 are electrically connected to the metal foil 10, and the electrode layers E2 and E3 are not electrically connected to the metal foil 10, but are insulated from the metal foil 10 by the dielectric film 13. Thus, a capacitor is formed in which the electrode layers E1 and E4 are used as one electrode and the electrode layers E2 and E3 are used as another electrode. Moreover, not only is the main surface 11 of the metal foil 10 roughened, but the main surface 12 side is also roughened, and a conductive polymer layer 30 is provided on its surface across the dielectric film 13, so that a large capacitance can be obtained. In addition, the inner wall of the through hole 16 is also roughened, and its surface is covered with the dielectric film 13, so that an even larger capacitance can be obtained.

[0037] The thin-film capacitor 1 of this embodiment can be used as a decoupling capacitor by being embedded in a multilayer substrate. In this embodiment, the electrode layers E1 and E2 are exposed on the main surface 11 of the metal foil 10, while the electrode layers E3 and E4 are exposed on the main surface 12 of the metal foil 10. This allows for access to the decoupling capacitor from both sides. Furthermore, since the electrode layer E1 is divided into multiple layers, ESR and ESL can be reduced compared to a single electrode layer.

[0038] Next, an example of a method for manufacturing the thin film capacitor 1 will be described. Figures 2A to 38A Along the Figures 2B to 38B A rough cross-sectional view along line AA is shown.

[0039] First, prepare a metal foil 10 ( Figure 2A 、 Figure 2B ), a plurality of recesses 17 ( Figure 3A 、 Figure 3B ), and a plurality of recesses 18 ( Figure 4A 、 Figure 4B The planar position of recess 17 is substantially the same as the planar position of recess 18. At this point, recesses 17 and 18 do not necessarily need to penetrate through metal foil 10. Recesses 17 and 18 can be formed by stamping or the like. Even on surfaces where recesses 17 and 18 are not formed, some concavities and convexities can be formed by stamping.

[0040] Next, the surface of the metal foil 10 is roughened by etching ( Figure 5A 、 Figure 5B). Thus, porous layer 11a and porous layer 12a are formed on metal foil 10, located on main surface 11 and main surface 12, and through-holes 16 are formed at positions corresponding to recesses 17 and 18. The central portion between porous layer 11a and porous layer 12a is non-porous layer 10a, which has not been roughened. Etching of metal foil 10 is preferably performed under conditions that maximize the surface area of main surfaces 11 and 12.

[0041] Next, a dielectric film 13 ( Figure 6A 、 Figure 6B ). Thus, dielectric film 13 is formed on main surfaces 11 and 12 of metal foil 10 and the inner wall of through-hole 16. Dielectric film 13 can be formed by oxidizing the surface of metal foil 10 made of aluminum or the like, or by using a film-forming method with excellent coverage, such as ALD, CVD, or atomized CVD. As a material for dielectric film 13, TiO2, Ta2O5, or the like can be used instead of Al2O3.

[0042] Next, after the metal foil 10 is placed on the support substrate 60 via the adhesive layer 61 ( Figure 7A 、 Figure 7B ), a photosensitive liquid resist 70 ( Figure 8A 、 Figure 8B ), exposure and development are performed, thereby forming an opening 71 ( Figure 9A 、 Figure 9B Next, the dielectric film 13 and the metal foil 10 are etched using the resist 70 as a mask, thereby forming a groove 14 in the metal foil 10 ( Figure 10A 、 Figure 10B ). The depth of the groove 14 is set to Figure 6A As a result, the non-porous layer 10a, which is the center portion of the metal foil 10, is exposed at the bottom of the groove 14.

[0043] Next, after removing the resist 70 ( Figure 11A 、 Figure 11B ), a photosensitive insulating resin 72 is formed on the main surface 11 of the metal foil 10 ( Figure 12A 、 Figure 12B ), exposure and development are performed, thereby patterning the insulating resin 72 ( Figure 13A 、 Figure 13B). Thus, annular insulating resins 21 and 23 are formed on the main surface 11 of the metal foil 10. The inner peripheral wall of the annular insulating resin 21 is preferably located inside the groove 14 formed in the metal foil 10. The outer peripheral wall of the annular insulating resin 21 needs to be located outside the groove 14 formed in the metal foil 10. Next, a conductive polymer layer 30 ( Figure 14A 、 Figure 14B ). Thus, conductive polymer layer 30 also penetrates into through-hole 16. On the other hand, conductive polymer layer 30 is not formed outside the region surrounded by insulating resin 21 or the region surrounded by insulating resin 23.

[0044] Next, a seed layer 31 ( Figure 15A 、 Figure 15B Before forming the seed layer 31, the residue remaining on the surface may be removed by reverse sputtering or the like. Then, a photosensitive liquid resist 73 ( Figure 16A 、 Figure 16B ), exposure and development are performed, thereby patterning the resist 73 ( Figure 17A 、 Figure 17B ). Thus, the seed layer 31 in the region where the metal terminals 41 and 42 are to be formed is exposed. Next, electroplating is performed to form the metal terminals 41 and 42 ( Figure 18A 、 Figure 18B ). As a result, the metal terminal 41 is connected to the metal foil 10 , and the metal terminal 42 is connected to the conductive polymer layer 30 covering the dielectric film 13 .

[0045] Next, after the resist 73 is removed by ashing or the like ( Figure 19A 、 Figure 19B ), remove the unnecessary seed layer ( Figure 20A 、 Figure 20B Next, a photosensitive liquid resist 74 ( Figure 21A 、 Figure 22B ), exposure and development are performed, thereby forming an opening 75 ( Figure 22A 、 Figure 22B Next, the dielectric film 13 and the metal foil 10 are etched using the resist 74 as a mask, thereby separating the metal foil 10 into individual pieces ( Figure 23A 、 Figure 23B ).

[0046] Next, after removing the resist 74 ( Figure 24A 、 Figure 24B), after attaching another support substrate 80 to the metal terminals 41 and 42 via another adhesive layer 81, the adhesive layer 61 on the main surface 12 side and the support substrate 60 are peeled off ( Figure 25A 、 Figure 25B Next, a photosensitive liquid resist 76 is formed on the main surface 12 side of the metal foil 10 ( Figure 26A 、 Figure 26B ), exposure and development are performed, thereby forming an opening 77 ( Figure 27A 、 Figure 27B Next, the dielectric film 13 and the metal foil 10 are etched using the resist 76 as a mask, thereby forming a groove 15 in the metal foil 10 ( Figure 28A 、 Figure 28B ). The depth of groove 15 is Figure 6A As a result, the non-porous layer 10 a , which is the center portion of the metal foil 10 , is exposed at the bottom of the groove 15 .

[0047] Next, after removing the resist 76 ( Figure 29A 、 Figure 29B ), a photosensitive insulating resin 78 is formed on the main surface 12 of the metal foil 10 ( Figure 30A 、 Figure 30B ), exposure and development are performed, thereby patterning the insulating resin 78 ( Figure 31A 、 Figure 31B ). Thus, annular insulating resins 22 and 24 are formed on the main surface 12 of the metal foil 10. The inner peripheral wall of the annular insulating resin 22 is preferably located inside the groove 15 formed in the metal foil 10. The outer peripheral wall of the annular insulating resin 22 needs to be located outside the groove 15 formed in the metal foil 10. Next, a conductive polymer layer 30 ( Figure 32A 、 Figure 32B ). Thus, conductive polymer layer 30 formed on the main surface 12 side is integrated with conductive polymer layer 30 provided inside through-hole 16. On the other hand, conductive polymer layer 30 is not formed outside the area surrounded by insulating resin 22 or the area surrounded by insulating resin 24.

[0048] Next, a seed layer 32 ( Figure 33A 、 Figure 33B Before forming the seed layer 32, the residue remaining on the surface may be removed by reverse sputtering or the like. Then, a photosensitive liquid resist 79 ( Figure 34A 、 Figure 34B ), exposure and development are performed, thereby patterning the resist 79 ( Figure 35A 、 Figure 35B). Thus, the seed layer 32 in the region where the metal terminals 51 and 52 are to be formed is exposed. Next, electroplating is performed to form the metal terminals 51 and 52 ( Figure 36A 、 Figure 36B ). As a result, the metal terminal 51 is connected to the metal foil 10 , and the metal terminal 52 is connected to the conductive polymer layer 30 covering the dielectric film 13 .

[0049] Next, after the resist 79 is removed by ashing or the like ( Figure 37A 、 Figure 37B ), remove the unnecessary seed layer ( Figure 38A 、 Figure 38B ). Then, if the support substrate 80 and the adhesive layer 81 are removed, Figure 1A 、 Figure 1B The film capacitor 1 shown is completed.

[0050] Figure 39 1 is a schematic cross-sectional view showing the structure of a thin film capacitor 2 according to a second embodiment of the present technology.

[0051] like Figure 39 As shown, the film capacitor 2 of the second embodiment differs from the film capacitor 1 of the first embodiment in that the metal terminal 51 constituting the electrode layer E4 is not in contact with the non-porous layer 10a of the metal foil 10, but is in contact with the porous layer 12a of the metal foil 10. In the portion in contact with the metal terminal 51, the dielectric film 13 covering the surface of the porous layer 12a is removed, thereby ensuring electrical connection between the metal terminal 51 and the metal foil 10. The rest of the basic structure is the same as that of the film capacitor 1 of the first embodiment. Therefore, the same reference numerals are used for the same elements, and repeated descriptions are omitted. As illustrated in the film capacitor 2 of the second embodiment, it is not necessary to provide the groove 15 in the metal foil 10; a structure in which the metal terminal 51 is in contact with the porous layer 12a is also possible.

[0052] Figure 40 It is a schematic cross-sectional view for explaining the structure of a thin film capacitor 3 according to a third embodiment of the present technology.

[0053] like Figure 40 As shown, the film capacitor 3 of the third embodiment differs from the film capacitor 2 of the second embodiment in that the metal foil 10 does not have through-holes 16. The rest of the basic structure is the same as that of the film capacitor 2 of the second embodiment. Therefore, identical elements are denoted by identical reference numerals, and duplicate descriptions are omitted. As illustrated in the film capacitor 3 of the third embodiment, it is not essential to have through-holes 16 in the metal foil 10.

[0054] Figure 41 1 is a schematic cross-sectional view showing the structure of a thin film capacitor 4 according to a fourth embodiment of the present technology.

[0055] like Figure 41 As shown, the film capacitor 4 of the fourth embodiment is different from the film capacitor 3 of the third embodiment in that a metal terminal 51 is provided on the entire surface of the main surface 12 side of the metal foil 10. Therefore, there is no electrode layer E3, and the entire surface of the main surface 12 of the metal foil 10 is covered by the metal terminal 51. The other basic structures are the same as those of the film capacitor 3 of the third embodiment, so the same symbols are marked on the same elements and repeated descriptions are omitted. As illustrated in the film capacitor 4 of the fourth embodiment, it is not necessary to provide the electrode layer E3 on the main surface 12 side of the metal foil 10, and the metal terminal 51 may be provided on the entire surface of the main surface 12 side. Alternatively, instead of providing the electrode layer E4 on the main surface 12 side of the metal foil 10, the electrode layer E3 including the conductive polymer layer 30 and the metal terminal 52 may be provided on the entire surface of the main surface 12 side.

[0056] The thin film capacitors 1 to 4 described above may be embedded in the multi-layer substrate or mounted on the surface of the multi-layer substrate.

[0057] Figure 42 The electronic circuit board shown has a structure in which a semiconductor IC 200 is mounted on a multilayer substrate 100. The multilayer substrate 100 is a multilayer substrate including a plurality of insulating layers including insulating layers 101 to 104 and a plurality of wiring patterns including wiring patterns 111 and 112. The number of insulating layers is not particularly limited. Figure 42 In the example shown, a thin film capacitor 1 is embedded between insulating layer 102 and insulating layer 103. Multiple land patterns including land patterns 141 and 142 are provided on the surface of multilayer substrate 100. Semiconductor IC 200 has multiple land electrodes including pad electrodes 201 and 202. For example, one of pad electrodes 201 and 202 is a power supply terminal, and the other is a ground terminal. Pad electrode 201 and pad pattern 141 are connected via solder 211, and pad electrode 202 and pad pattern 142 are connected via solder 212. Furthermore, pad pattern 141 is connected to metal terminal 42 of thin film capacitor 1 via via conductor 121, wiring pattern 111, and via conductor 131. On the other hand, land pattern 142 is connected to metal terminal 41 of thin film capacitor 1 via via conductor 122, wiring pattern 112, and via conductor 132. Thus, thin film capacitor 1 functions as a decoupling capacitor for semiconductor IC 200. Furthermore, the metal terminals 51 and 52 located on the principal surface 12 side of the film capacitor 1 can also be connected to a wiring pattern (not shown).

[0058] Figure 43The electronic circuit board shown has a structure in which a semiconductor IC 400 is mounted on a multilayer substrate 300. The multilayer substrate 300 is a multilayer substrate including a plurality of insulating layers including insulating layers 301 and 302 and a plurality of wiring patterns including wiring patterns 311 and 312. The number of insulating layers is not particularly limited. Figure 43 In the example shown, a thin-film capacitor 1 is surface-mounted on the surface 300a of a multilayer substrate 300. Multiple land patterns, including land patterns 341 to 344, are provided on the surface 300a of the multilayer substrate 300. A semiconductor IC 400 includes multiple land electrodes, including land electrodes 401 and 402. For example, one of the land electrodes 401 and 402 is a power supply terminal, and the other is a ground terminal. The land electrode 401 and the land pattern 341 are connected via solder 411, and the land electrode 402 and the land pattern 342 are connected via solder 412. Furthermore, the land pattern 341 is connected to the metal terminal 42 of the thin-film capacitor 1 via the via conductor 321, the wiring pattern 311, the via conductor 331, the land pattern 343, and the solder 413. Meanwhile, the land pattern 342 is connected to the metal terminal 41 of the thin-film capacitor 1 via the via conductor 322, the wiring pattern 312, the via conductor 332, the land pattern 344, and the solder 414. Thus, the thin film capacitor 1 functions as a decoupling capacitor for the semiconductor IC 400. The metal terminals 51 and 52 located on the principal surface 12 side of the thin film capacitor 1 can also be connected to pad electrodes or pad patterns (not shown) via solder or bonding wires.

[0059] While the embodiments of the technology involved in the present invention have been described above, the technology involved in the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the gist thereof, and these modifications are also included in the technical scope of the present invention.

[0060] Explanation of symbols:

[0061] 1-4…Film capacitor, 10a…Non-porous layer, 11, 12…Main surface, 11a, 12a…Porous layer, 13…Dielectric film, 14, 15…Groove, 16…Through hole, 17, 18…Recess, 21-26…Insulating resin, 30…Conductive polymer layer, 31, 32…Seed layer, 41, 42, 51, 52…Metal terminal, 60…Supporting substrate, 61…Adhesive layer, 70, 73, 74, 76, 79…Resist, 71, 75, 77…Opening, 72, 78…Insulating resin, 80…Supporting substrate, 81…Adhesive layer, 100…Multilayer substrate, 101- 104…insulating layer, 111, 112…wiring pattern, 121, 122, 131, 132…via conductors, 141, 142…pad pattern, 200…semiconductor IC, 201, 202…pad electrodes, 211, 212…solder, 300…multilayer substrate, 300a…surface, 301, 302…insulating layer, 311, 312…wiring pattern, 321, 322, 331, 332…via conductors, 341-344…pad pattern, 400…semiconductor IC, 401, 402…pad electrodes, 411-414…solder, E1-E4…electrode layer.

Claims

1. A film capacitor, characterized in that: have: a metal foil having a roughened first main surface and a roughened second main surface located opposite to the first main surface; a first dielectric film covering the first main surface of the metal foil; a second dielectric film covering the second main surface of the metal foil; a first electrode layer, which contacts the metal foil via an opening provided in the first dielectric film and has a surface formed of a first metal terminal; a second electrode layer, which is not in contact with the metal foil but in contact with the first dielectric film, and whose surface is composed of a second metal terminal; and The third electrode layer is not in contact with the metal foil but in contact with the second dielectric film, and has a surface formed of a third metal terminal.

2. The film capacitor according to claim 1, wherein The fourth electrode layer is further provided. The fourth electrode layer is in contact with the metal foil via an opening provided in the second dielectric film, and the surface of the fourth electrode layer is constituted by a fourth metal terminal.

3. The film capacitor according to claim 1, wherein The metal foil has through holes, The inner wall of the through hole is covered by a third dielectric film, The second electrode layer and the third electrode layer are connected via the through hole.

4. The film capacitor according to claim 3, wherein: The inner wall of the through hole is roughened.

5. The film capacitor according to any one of claims 1 to 4, characterized in that The second electrode layer includes a first conductive polymer layer in contact with the first dielectric film.

6. The film capacitor according to claim 5, wherein: The third electrode layer includes a second conductive polymer layer in contact with the second dielectric film.

7. A method for manufacturing a thin film capacitor, characterized in that: The first main surface of the metal foil and the second main surface opposite to the first main surface are roughened. forming a first dielectric film and a second dielectric film on the first main surface and the second main surface of the metal foil, respectively; by removing a portion of the first dielectric film to expose a portion of the metal foil, A first electrode layer is formed which is in contact with the portion of the metal foil and has a first metal terminal on its surface; a second electrode layer is formed which is not in contact with the metal foil but is in contact with the first dielectric film and has a second metal terminal on its surface; and a third electrode layer is formed which is not in contact with the metal foil but is in contact with the second dielectric film and has a third metal terminal on its surface.

8. The method for manufacturing a thin film capacitor according to claim 7, wherein: further, by removing a portion of the second dielectric film to expose another portion of the metal foil, A fourth electrode layer is formed which contacts the other portion of the metal foil and has a surface composed of a fourth metal terminal.

9. The method for manufacturing a thin film capacitor according to claim 7 or 8, wherein: further, Before forming the second electrode layer and the third electrode layer, a through hole having an inner wall covered by a third dielectric film is formed in the metal foil. The second electrode layer and the third electrode layer are connected via the through hole.

10. The method for manufacturing a thin film capacitor according to claim 9, wherein: The second electrode layer includes a first conductive polymer layer in contact with the first dielectric film. The third electrode layer includes a second conductive polymer layer in contact with the second dielectric film. A third conductive polymer layer connecting the first conductive polymer layer and the second conductive polymer layer is formed in a region surrounded by the inner wall of the through hole.

11. An electronic circuit substrate, characterized in that: have: a substrate having a wiring pattern; and a semiconductor IC provided on the substrate and a thin film capacitor according to any one of claims 1 to 6, The first electrode layer and the second electrode layer of the thin film capacitor are connected to the semiconductor IC via the wiring pattern.

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