Semiconductor device and method for manufacturing semiconductor device

Abstract

The semiconductor device (100) comprises a semiconductor body (10) having a top side (11) and a bottom side (19). The first main electrode (2) is arranged on the top side and the second main electrode (3) is arranged on the bottom side. The semiconductor device includes a gate electrode (4) and at least two trenches, a first type trench (51) and a second type trench (52). The semiconductor body comprises a drift region (14) of a first conductivity type and at least three base regions (13a, 13b, 13c), each of which is of a second conductivity type. The semiconductor body further comprises an implant region (12) of the first conductivity type. The first main electrode is in electrical contact with the implant region. The gate electrode extends into the first type trench. The second type trench has no gate electrode. The third base region comprises at least one contact region (6c) in which the third base region is in electrical contact with an electrode of the semiconductor device different from the gate electrode.

Description

Technical Field

[0001] The present disclosure relates to semiconductor devices and methods for manufacturing semiconductor devices. Background Art

[0002] There is a need for an improved semiconductor device, for example a semiconductor device with improved static and / or dynamic behavior. Furthermore, there is a need for a method for manufacturing such a semiconductor device. Summary of the Invention

[0003] Embodiments of the present disclosure relate to semiconductor devices and methods for manufacturing semiconductor devices.

[0004] First, specify the semiconductor device.

[0005] According to one embodiment, a semiconductor device includes a semiconductor body extending vertically between a top side and a bottom side. A first main electrode is arranged on the top side, and a second main electrode is arranged on the bottom side. Furthermore, the semiconductor device includes a gate electrode and at least two trenches, namely, a first-type trench and a second-type trench, each extending from the top side into the semiconductor body. The semiconductor body includes a drift region of a first conductivity type arranged vertically between the top side and the bottom side, and at least three base regions, namely, a first, second, and third base region, each of the second conductivity type and each arranged vertically between the drift region and the top side. The semiconductor body also includes an implant region of the first conductivity type, vertically spaced from the drift region by the first base region and adjacent to the first base region. The first base region, the first-type trench, the second base region, the second-type trench, and the third base region are arranged sequentially in this order in a first lateral direction. The first main electrode is in electrical contact with the implant region. The gate electrode extends into the first-type trench, where it is isolated from the semiconductor body by a gate insulating layer. The second-type trench is devoid of a gate electrode.

[0006] The arrangement having the second type trench, the second base region, and the third base region is particularly helpful in protecting the first type trench, and in particular the gate insulation layer therein, from avalanches, for example during switching events.

[0007] The semiconductor device described herein may be a power semiconductor device. For example, it is configured to carry a current of at least 10 A and / or handle a voltage of at least 1000 V or at least 3000 V. The semiconductor device may be a transistor device, in particular a gate-insulated transistor device, in particular an IGFET.

[0008] The semiconductor body can be based on silicon or silicon carbide. The thickness of the semiconductor body, measured in the vertical direction, is, for example, at least 100 µm, at least 200 µm, and / or at most 500 µm. The top side and the bottom side are side surfaces of the semiconductor body and delimit the semiconductor body in the vertical direction.

[0009] The first and / or second main electrodes may include or consist of metal. Depending on the type of semiconductor device, the first electrode may also be referred to herein as an "emitter electrode" or "source electrode," and the second main electrode may be referred to herein as a "collector electrode" or "drain electrode," respectively.

[0010] The gate electrode may comprise metal and / or highly doped polysilicon. The gate electrode is in particular an insulated gate electrode, ie, it is electrically insulated from the semiconductor body. This may be achieved, for example, with the aid of a gate insulating layer.

[0011] The trenches extend from the top side of the semiconductor body into the semiconductor body and terminate in the semiconductor body, for example, in the drift region. The trenches have the same depth when measured in the vertical direction. The depth of the trenches can be at least 1µm or at least 5µm and / or at most 20µm or at most 10µm. The trenches can be elongated and can each extend in a lateral direction, wherein the lateral direction is defined herein as a direction perpendicular to the vertical direction. The lateral direction is in particular a direction parallel to the main extension plane of the semiconductor body. For example, the trenches extend parallel to each other.

[0012] The first-type grooves and the second-type grooves may be spaced apart from each other in a first lateral direction. Each groove may extend in a second lateral direction perpendicular to the first lateral direction. The average distance between the first-type grooves and the second-type grooves is, for example, at least 100 nm, at least 500 nm, and / or at most 2 µm. The distance between two grooves is defined herein as, for example, the pitch between the grooves, i.e., the distance between the centers of the grooves. For example, no additional grooves may be arranged laterally between the first-type grooves and the second-type grooves.

[0013] The first-type trench is filled with a conductive material, which is isolated from the semiconductor body by a gate insulating layer. The conductive material is spatially and electrically isolated from the semiconductor body by the gate insulating layer. The gate insulating layer can be an oxide, such as SiO2. The gate insulating layer can have a thickness of at least 10 nm and / or at most 200 nm. For example, the gate insulating layer has a thickness between 50 nm and 150 nm, inclusive.

[0014] "Electrically isolated" here specifically refers to the absence of electrical contact between two components. For example, two electrically isolated components are configured to be independently electrically biased or controlled. This means that during operation of the semiconductor device, they are configured to be at different electrical potentials. In particular, two electrically isolated components can be electrically insulated from each other, meaning that no current can flow between them.

[0015] The conductive material in the first type trench can be metal and / or highly doped polysilicon. The conductive material in the first type trench is part of the gate electrode, i.e., electrically connected to the gate electrode. When two elements are electrically connected or in contact, this means that the two elements cannot be electrically biased or controlled independently. Therefore, they are always at the same electrical potential. The first type trench is also referred to as an "active trench" in this article.

[0016] For example, the conductive material in the first type trench reaches the semiconductor body at least as deep as the first base region and / or the second base region.

[0017] The second type trench has no gate electrode. That is, the second type trench is a gate-less trench. In other words, the second type trench is electrically isolated from the gate electrode.

[0018] The second type trench may also be filled with a conductive material, which may be isolated from the semiconductor body by an insulating layer. However, this conductive material is electrically isolated from the gate electrode, i.e., not electrically connected to it. The insulating layer may be the same as the gate insulating layer. Within the second type trench, the conductive material may extend into the semiconductor body to the same depth as the first and / or second base regions. The conductive material in the second type trench may be metal and / or highly doped polysilicon.

[0019] For example, the conductive material in the second type trench is electrically connected to the first main electrode. In other words, the first main electrode may extend into the second type trench.

[0020] The second type trenches may contain no conductive material, for example, may be filled with only an electrically insulating material instead of a conductive material.

[0021] The second type of trenches are also referred to herein as "passive trenches."

[0022] The drift region of the semiconductor body has a first conductivity type. The first conductivity type is, for example, n-type, i.e., the drift region is n-doped. The second conductivity type is opposite to the first conductivity type and can therefore be p-type. However, the opposite scenario is also possible, where the first conductivity type is p-type and the second conductivity type is n-type.

[0023] For example, the drift region extends continuously over all base regions, that is, in a top view from the top side, the drift region overlaps with all three base regions.

[0024] The first type trench is arranged between the first base region and the second base region in a first lateral direction.For example, the first type trench adjoins the first base region on one side and / or adjoins the second base region on the other side.

[0025] The second base region is arranged between the first type trench and the second type trench in the first lateral direction. The second base region may be adjacent to the second type trench. The second base region may extend continuously (eg, without interruption) from the first type trench to the second type trench.

[0026] The second type trench is arranged between the second base region and the third base region in the first lateral direction.The second type trench may be adjacent to the third base region.

[0027] The third base region may extend continuously (e.g., without interruption) from the second type trench to another trench spaced apart from the second type trench in the first lateral direction. The other trench may be another second type trench, that is, the second type trench is electrically isolated from the gate electrode or is not filled with the gate electrode.

[0028] The structure including the first base region and the adjacent implant structure, the first type trench, the second base region, the second type trench, and the third base region can be repeated several times along the top side. The structure including at least a portion (half) of the first base region and the adjacent implant region, the first type trench, the second base region, the second type trench, and a portion (half) of the third base region is also referred to as a "half cell" or "transistor half cell". The semiconductor device can include multiple such half cells, which can be arranged sequentially in the first lateral direction. Every two adjacent half cells can be mirror-symmetrical with respect to a mirror plane. The mirror plane extends, for example, perpendicular to the first longitudinal direction. The mirror plane can pass through the first and / or third base region at half of the first and / or third base region's respective extension in the first lateral direction.

[0029] The semiconductor body includes an implant region of a first conductivity type. The implant region is vertically spaced apart from the drift region by the first base region and is adjacent to the first base region. The implant region reaches, for example, the top side. The implant region can be embedded in the first base region. For example, the implant region can be adjacent to the first type trench on the same side as the first base region is adjacent to the first type trench. Each half cell can include exactly one such implant region. The implant region is also referred to as a source region.

[0030] The injection region is in electrical contact with the first main electrode, for example, it is adjacent to the first main electrode. During operation of the semiconductor device in a (static) transistor mode, first-type charge carriers (e.g., electrons) are injected from the first main electrode into the injection region. The semiconductor device is configured such that, by applying a potential to the gate electrode, the first base region adjacent to the first-type trench is depleted, thereby forming a path for the first-type charge carriers from the injection region to the drift region, the path extending vertically along the first-type trench.

[0031] The second base region may form a portion of the top side, for example the entire portion of the top side laterally between the first type trench and the second type trench. For example, the semiconductor body is free of any (implanted) regions of the first conductivity type arranged vertically between the second base region and the top side and adjoining the second base region.

[0032] The third base region may also form a portion of the top side, for example the entire portion of the top side laterally located between two trenches that laterally delimit the third base region. The semiconductor body is free of any (implanted) regions of the first conductivity type arranged vertically between the third base region and the top side and adjoining the third base region.

[0033] According to another embodiment, the third base region includes at least one contact region in which the third base region is electrically contacted with an electrode of the semiconductor device different from the gate electrode, eg, the third base region can be controlled / biased independently of the gate electrode.

[0034] During operation, charge carriers can be extracted from the semiconductor body via the contact region. Therefore, the contact region can also be referred to as an "extraction region." This extraction region is advantageous during switching events (e.g., during transistor-mode turn-off) because it helps to quickly reduce the plasma concentration in the semiconductor body. In other words, the contact region constitutes a plasma-control feature. On the other hand, if the semiconductor device is operated in diode mode, the electrical contact between the electrode and the semiconductor body in the contact region provides (additional) charge carrier paths, which reduces on-state losses in diode mode. Because the contact region is in electrical contact with an electrode different from the gate electrode, the charge carrier paths are independent of the gate electrode potential. The location of the contact region in the third base region, separated from the first type trench by the second type trench, helps to protect the gate insulation layer in the first type trench during switching events by reducing the generation of avalanches in the region of the first type trench.

[0035] For example, an electrode electrically connected to the third base region in the contact region is arranged on the top side. This electrode can be the first main electrode or another electrode that can be controlled independently of the first main electrode.

[0036] Because the contact region belongs to the third base region, it is also referred to herein as the third contact region. The contact region may form part of the top side. The third base region may adjoin the electrode over the entire area of the contact region. When viewed from above in a top view, the area of the contact region is particularly smaller than the area of the third base region. For example, in this top view, the area of the contact region is at most 50%, at most 10%, at most 5%, or at most 1% of the area of the third base region. In the case of multiple contact regions, all features disclosed for one contact region are also disclosed for the other contact regions.

[0037] According to another embodiment, the third base region is electrically connected to the first main electrode in at least one contact region.For example, the first main electrode adjoins the third base region in the contact region.

[0038] According to another embodiment, the third base region is electrically connected to an electrode in the at least one contact region, which electrode is configured to operate independently of the first main electrode. This electrode, also referred to herein as the further electrode, is therefore configured to be at a potential different from and independent of the potentials of the gate electrode and the first main electrode.

[0039] According to another embodiment, the semiconductor device is an RC-IGBT, ie a reverse conducting IGBT, or a MISFET, in particular a MOSFET.

[0040] RC-IGBT and MOSFET are semiconductor devices that can operate in reverse mode, ie, diode mode. As mentioned above, for such devices, the contact region where the third base region is in electrical contact with the electrode is particularly advantageous.

[0041] According to another embodiment, the second base region includes at least one contact region in which the second base region electrically contacts an electrode of the semiconductor device that is different from the gate electrode. This electrode may be the same electrode that electrically contacts the third base region in the corresponding (third) contact region. The contact region of the second base region, also referred to herein as the second contact region, may form part of the top side. When viewed in a top view of the top side, the second contact region may have an area smaller than that of the second base region. The same relative dimensions disclosed with respect to the (third) contact region of the third base region also apply here.

[0042] By means of the contact region of the second base region, a further degree of freedom for optimizing the charge carrier extraction is achieved, for example during the transistor mode off and / or during the diode mode.

[0043] According to another embodiment, the first base region includes at least one contact region in which the first base region is electrically contacted with an electrode of the semiconductor device that is different from the gate electrode. This electrode may be the same electrode that is electrically contacted with the third base region in a corresponding (third) contact region. The contact region of the first base region, also referred to herein as the first contact region, may adjoin the top side and / or the implant region.

[0044] By means of the contact region of the first base region, a further degree of freedom for optimizing the charge carrier extraction is achieved, for example during the transistor mode off and / or during the diode mode.

[0045] According to another embodiment, the third base region includes a plurality of (third) contact regions. The third base region electrically contacts the electrode in each of these contact regions. For example, the contact regions of the third base region are spaced apart from each other in at least one lateral direction, such as a first lateral direction. All features disclosed with respect to one contact region of the third base region are also disclosed with respect to all other contact regions of the third base region.

[0046] The contact regions of the third base region can be formed as strips, for example, extending in the second lateral direction. Every two contact regions of the third base region can be spaced apart from each other. In the area outside the contact regions, there is no direct electrical contact between the electrode and the (multiple) third base regions. In particular, outside the contact regions, the electrode does not abut the third base region. For example, when viewed in a top view from the top side, the multiple contact regions of the third base region are arranged in a rectangular pattern. For example, when viewed in this top view, at most 50% and / or at least 10% of the area of the third base region is formed by the contact regions.

[0047] Since the contact regions are in each case part of the respective base region, they are all of the second conductivity type.In each base region, at least one contact region may be spaced apart from a trench laterally delimiting the respective base region.

[0048] According to another embodiment, the third base region extends from the top side into the semiconductor body at least as deep as the second type trench and / or the first type trench. For example, the third base region extends deeper into the semiconductor body than the second type trench and / or the first type trench. It has been found that with this design, the avalanche strength in the vicinity of the first type trench can be significantly reduced.

[0049] According to another embodiment, the first type trench and the second type trench have the same depth. Alternatively, the second type trench can extend deeper into the semiconductor than the first type trench. It has been shown that deeper second type trenches further help keep avalanches away from the first type trenches.

[0050] According to another embodiment, the third base region extends below the second type trench toward the first type trench. Thus, in a top view from the top side, the second type trench and the third base region may overlap each other.

[0051] According to another embodiment, the doping concentration in the third base region is greater in the at least one contact region than in regions laterally adjacent to the contact region. For example, the doping concentration in the contact region is greater by at least one order of magnitude, at least two orders of magnitude, or at least three orders of magnitude than in regions laterally surrounding the at least one contact region.

[0052] According to another embodiment, the semiconductor body includes a conductive layer disposed on a top side of the semiconductor body above the third base region. The conductive layer is electrically connected to an electrode of the semiconductor device that is different from the gate electrode. This means that the conductive layer is configured to be electrically biased / controlled independently of the gate electrode, i.e., it can be set to a different potential than the gate electrode.

[0053] The conductive layer on the top side above the third base region may include or consist of metal and / or highly doped polysilicon.For example, the conductive layer is electrically connected to the first main electrode, or to an electrode that can be controlled / biased independently of the first main electrode.

[0054] In a top plan view from the top side, the conductive layer and the third base region at least partially overlap. That is, in a top plan view from the top side, the conductive layer covers at least a portion of the third base region. The conductive layer can be a continuous layer or can be formed from a plurality of segments spaced apart from one another in at least one lateral direction. In particular, the conductive layer extends parallel to the top side of the semiconductor body and / or parallel to the main extension plane of the semiconductor body.

[0055] According to another embodiment, the conductive layer is positioned near the third base region such that, by electrically biasing the conductive layer, strong capacitive coupling between the third base region and the conductive layer can be achieved, thereby influencing free charge carriers in the third base region. "Influencing" means, for example, that the free charge carriers are attracted or repelled by the conductive layer. In particular, depending on the conductivity type of the third base region, the free charge carriers are second-type charge carriers. Thus, in the case where the third base region is p-doped, the free charge carriers can be holes.

[0056] This conductive layer can improve the operation of the semiconductor device. For example, during static operation, free charge carriers in the third base region can be repelled by the conductive layer, maintaining a high electron-hole plasma in the semiconductor body or diverting them toward the gate electrode in the first-type trench. When switching the semiconductor device, second-type charge carriers can be attracted by the conductive layer, directing the electron-hole plasma out of the first-type trench. This reduces the risk of damage to the gate insulation layer in the first-type trench, for example, due to avalanches.

[0057] The maximum distance between the third base region and the conductive layer for achieving such strong capacitive coupling depends on several factors, such as the potential applied to the conductive layer and the material arranged vertically between the conductive layer and the semiconductor body in the lateral extension of the conductive layer. For example, the maximum vertical distance between the conductive layer and the third base region is of the same order of magnitude as the thickness of the gate insulating layer.

[0058] According to another embodiment, the conductive layer is separated from the top side of the semiconductor body by an electrically insulating layer arranged vertically between the top side and the conductive layer. The electrically insulating layer can be an oxide. For example, it can be the same material as the gate insulating layer. For example, the electrically insulating layer is made of SiO2.

[0059] For example, the conductive layer is separated from the top side only by the electrically insulating layer. That is, the vertical distance between the top side and the conductive layer is defined by the thickness of the electrically insulating layer. The electrically insulating layer may fill a substantial portion of the space between the conductive layer and the top side of the semiconductor body. For example, at least 70%, at least 80%, or at least 90% of the volume between the conductive layer and the top side is filled by the electrically insulating layer.

[0060] According to another embodiment, the thickness of the electrically insulating layer is at most 5 times, at most 3 times, or at most 1.5 times greater than the thickness of the gate insulating layer.

[0061] According to another embodiment, the vertical distance between the conductive layer and the third base region is at most 500 nm, or at most 300 nm, or at most 150 nm. Additionally or alternatively, the vertical distance between the conductive layer and the third base region may be at least 10 nm, or at least 50 nm. This minimum distance exists at least in certain regions of the conductive layer.

[0062] According to another embodiment, the conductive layer and the third base region are electrically isolated from one another. That is, the semiconductor device has no (direct) electrical connection between the conductive layer and the third base region. For example, the electrically insulating layer can extend continuously and without interruption between the conductive layer and the top side of the semiconductor body and over the entire lateral extent of the conductive layer.

[0063] According to another embodiment, an electrical connection is formed between the conductive layer and the third base region. For example, the conductive layer is in electrical contact with the third base region in one or more contact regions of the third base region. In the contact region, the conductive layer may abut the third base region.

[0064] According to another embodiment, in a top view from the top side, the conductive layer covers a substantial portion of the third base region. For example, in this plan view, the conductive layer covers at least 60%, or at least 80%, or at least 90% of the third base region. Additionally or alternatively, in this top view, the conductive layer does not overlap with the second type trenches and / or any trenches that laterally define the third base region. In this top view, the conductive layer may also overlap with the second type trenches or any trench that laterally defines the third base region, but does not extend laterally beyond the trench(es).

[0065] According to another embodiment, the conductive layer is arranged vertically between the top side of the semiconductor body and a portion of the emitter electrode. For example, in a top view from the top side, the portion of the emitter electrode and the conductive layer overlap each other. For example, in this top view, the portion of the emitter electrode completely covers the conductive layer.

[0066] According to another embodiment, a vertical distance between the conductive layer and the third base region is at most half, at most 1 / 5, or at most 1 / 10 of a vertical distance between a portion of the emitter electrode and the top side of the semiconductor body. In particular, the portion of the emitter electrode is distant from the third base region so that it is not capacitively coupled to the third base region.

[0067] For example, the vertical distance between a portion of the emitter electrode and the top side is at least 800 nm or at least 1 µm or at least 1.5 µm.

[0068] A further electrically insulating layer may be arranged vertically between the top side of the semiconductor body and a portion of the emitter electrode. The thickness of this further electrically insulating layer may define the distance between the portion of the emitter electrode and the top side. This further electrically insulating layer may be an oxide, such as SiO2. It is also referred to herein as a "field insulating layer."

[0069] According to another embodiment, in a top view, at least one contact region of the third base region and the conductive layer overlap. For example, the third base region is electrically conductively connected to the conductive layer in the contact region. Alternatively, a cavity can be formed through the conductive layer, through which an electrode in contact with the third base region in the contact region is guided. Within the cavity, the electrode can be spaced apart from the conductive layer, for example, by an electrically insulating layer.

[0070] Next, a method for manufacturing a semiconductor device is described in detail. For example, the semiconductor device described herein can be manufactured using this method. Therefore, all features disclosed in conjunction with the semiconductor device are also disclosed with respect to the method, and vice versa.

[0071] According to one embodiment, a method for generating a semiconductor device includes the steps of providing a semiconductor body having a top side and a bottom side. Then, at least two trenches, namely a first type trench and a second type trench, are formed in the semiconductor body, wherein each trench extends from the top side into the semiconductor body. In addition, a first main electrode is formed on the top side of the semiconductor body and a second main electrode is formed on the bottom side of the semiconductor body. A gate electrode is formed so that the gate electrode extends into the first type trench, where the gate electrode is isolated from the semiconductor body by a gate insulation layer. The second type trench remains free of a gate electrode. A semiconductor device is formed so that the semiconductor body includes a drift region of a first conductivity type vertically arranged between the top side and the bottom side, and at least three base regions, namely a first, second, and third base region, each of which is of the second conductivity type and each of which is vertically arranged between the drift region and the top side. The semiconductor body also includes an implantation region of the first conductivity type, which is vertically spaced apart from the drift region by the first base region and is adjacent to the first base region. The first base region, the first type trench, the second base region, the second type trench, and the third base region are sequentially arranged in this order in the first lateral direction. The first main electrode is in electrical contact with the implantation region.

[0072] The trench may be formed in the semiconductor body before forming the base region and the implantation region. Alternatively, the base region may be at least partially formed before forming the trench.

[0073] According to another embodiment, the semiconductor device is formed such that the third base region includes at least one contact region, wherein in the contact region the third base region is in electrical contact with an electrode of the semiconductor device that is different from the gate electrode.

[0074] According to another embodiment, the semiconductor device is formed such that the first base region includes at least one contact region, wherein in the contact region the first base region is in electrical contact with an electrode of the semiconductor device that is different from the gate electrode.

[0075] According to another embodiment, the semiconductor device is formed such that the doping concentration of the corresponding base region in the contact region is greater than the doping concentration in a region of the corresponding base region laterally adjacent to the contact region. For example, the contact region can be formed by ion implantation. Such a contact region can also be formed in the second base region.

[0076] According to another embodiment, the contact regions are produced simultaneously using one common mask with the aid of ion implantation.For example, the mask comprises holes in the regions where the contact regions are to be formed.

[0077] Hereinafter, semiconductor devices and methods for manufacturing semiconductor devices will be explained in more detail with reference to the accompanying drawings based on exemplary embodiments. The accompanying drawings are included to provide further understanding. In the accompanying drawings, elements with the same structure and / or function may be represented by the same reference symbols. It should be understood that the embodiments shown in the accompanying drawings are illustrative representations and are not necessarily drawn to scale. As long as the functions of elements or components in different figures correspond to each other, their description will not be repeated for each of the following figures. For the sake of clarity, elements may not appear with corresponding reference symbols in all figures. BRIEF DESCRIPTION OF THE DRAWINGS

[0078] Figures 1 to 9 and Figure 13 Different exemplary embodiments of semiconductor devices are shown in different views, Figures 10 to 12 Different locations in an exemplary embodiment of a method for manufacturing a semiconductor device are shown. DETAILED DESCRIPTION

[0079] Figure 1 A first exemplary embodiment of a semiconductor device 100 is shown in cross section. In this case, the semiconductor device 100 is an RC-IGBT. It comprises a semiconductor body 10 having a top side 11 and a bottom side 19 that are vertically opposite to each other. The semiconductor body 10 is based on Si or SiC, for example.

[0080] At the bottom side 19, the semiconductor body 10 comprises alternatingly arranged first type regions 15 and second type regions 16. The regions 15 and 16 are in electrical contact with a second main electrode 3, ie collector 3, on the bottom side 19. The collector 3 is formed of, for example, metal.

[0081] First-type regions 15 are of a first conductivity type, hereinafter referred to as n-type, and second-type regions 16 are of a second conductivity type, hereinafter referred to as p-type. Drift region 14 is arranged between top side 11 and bottom side 19. Drift region 14 is of the first conductivity type, i.e., n-type. Drift region 14 adjoins first-type regions 15 and second-type regions 16.

[0082] A plurality of trenches 51, 52 extend from the top side into the semiconductor body 10 and into the drift region 14. The trenches 51 are first type trenches, also referred to herein as "active trenches", and the trenches 52 are second type trenches, also referred to herein as "inactive trenches" or "dummy trenches".

[0083] The first-type trenches 51 are filled with a conductive material, which is electrically isolated from the semiconductor body 10 by an electrically insulating layer 40 (referred to herein as a "gate insulating layer"). Therefore, there is no direct electrical contact between the semiconductor body 10 and the conductive material in the first-type trenches 51. The gate insulating layer 40 is formed of an oxide such as SiO2. The conductive material in the first-type trenches 51 may be highly doped polysilicon. The conductive material in the first-type trenches 51 is part of the gate electrode 4 of the semiconductor device 100.

[0084] The second type trenches 52 are also filled with an electrically conductive material (e.g., highly doped polysilicon) and are also electrically isolated from the semiconductor body 10 by the same electrically insulating layer as the gate insulating layer 40. The electrically conductive material in the second type trenches 52 is part of the first main electrode 2 (i.e., emitter electrode 2) arranged on the top side 12.

[0085] The semiconductor body 10 includes a plurality of base regions 13 a, 13 b, 13 c, which are arranged vertically between the drift region 14 and the top side 11. The base regions 13 a, 13 b, 13 c are all of the second conductivity type, i.e., p-type, and they all adjoin the drift region 14 and the top side 11. The first and second base regions 13 a, 13 b are shallower (have a smaller vertical extension) than the trenches 51, 52. The third base region 13 c is deeper than the trenches 51, 52, i.e., extends further into the semiconductor body 10.

[0086] The first base region 13a is adjacent to and electrically contacts the emitter electrode 2 in a first contact region 6a (also referred to as "Rb base region"). The third base region 13c is adjacent to and electrically contacts the emitter electrode 2 in a third contact region 6c. The functions of these contact regions 6a, 6c will be explained further below.

[0087] like Figure 1 As shown, the semiconductor device 100 is subdivided into a plurality of so-called half cells. Figure 2 One such half unit is shown in more detail in FIG. Figure 2 The structure between the vertical dashed lines in Figure 1 In the embodiment, a plurality of such half cells are arranged in sequence in the first lateral direction, extending from left to right. Two adjacent half cells are mirror images of each other at a plane perpendicular to the first lateral direction and passing through the third base region 13c (see FIG. Figure 2 ).

[0088] like Figure 2As shown, the half-cell includes a portion (half) of the first base region 13c, a first-type trench 51, a second base region 13b, a second-type trench 52, and a portion (half) of the third base region 13c, arranged in this order along the first lateral direction. The half-cell also includes an implant region 12 (source region 12) of the first conductivity type (i.e., n-type) arranged vertically between the first base region 13c and the top side 11. The implant region 12 is adjacent to the first base region 13c and the first-type trench 51. The implant region 12 is also adjacent to and electrically contacts the emitter electrode 2.

[0089] The operation of a semiconductor device can be as follows: In so-called transistor mode, the emitter electrode 2 is grounded, and the collector electrode 3 is set to a positive potential. The gate electrode 4 is set to a positive potential, causing the first base region 13a to be depleted at the boundary of the first-type trench 51. A conduction path is created in the first base region 13c along the first-type trench 51. Electrons can then be injected from the emitter electrode 2 into the injection region 12, travel along the conduction path, and reach the drift region 14. On the bottom side 19, holes are injected from the collector electrode 3 via the second-type region 16 and also travel into the drift region 14, thereby generating an electron-hole plasma.

[0090] When the transistor mode is off, electron-hole plasma can generate an avalanche in the region of the first type trench 51. This avalanche can in turn damage the gate insulating layer 40, thereby negatively affecting the long-term performance stability of the semiconductor device 10. It has been found that the second type of inactive trench 52 and the third base region extending deeper into the semiconductor body than the trenches 51 and 52 help to divert the avalanche away from the active trenches.

[0091] This effect is further enhanced by the third base region 13c being in electrical contact with the emitter electrode 2 in the third contact region 6c. Charge carriers, such as holes, can be dissipated during switch-off via the third contact region 6c.

[0092] Because semiconductor device 100 is an RC-IGBT, it can also operate in reverse mode (so-called diode mode). In diode mode, emitter electrode 2 is, for example, grounded, and collector electrode 3 is at a negative potential. Electrons are injected from collector electrode 3 into first type region 15 and, after further into the semiconductor body, must recombine with holes from emitter electrode 2.

[0093] Without third contact region 6c of the third base region, the only path would be through first base region 13c via first contact region 6a. At a positive gate-emitter potential, the diode's on-state losses (Vf) increase. This is because, at a positive gate-emitter potential, a channel is established between n-type implant region 12 and n-type drift region 14, creating an electron path. Consequently, since the electron path short-circuits the diode path, hole injection into first base region 13a is reduced, resulting in a lower plasma concentration.

[0094] To keep the diode's on-state losses low, the device 100 can be operated with a negative or shorted (Vg = 0V) gate electrode. In this case, the electron path will not exist. However, this limits the device's usability, as the gate control driver and system need to be tuned (non-standard) or specially designed for the application to achieve the lowest possible losses.

[0095] In combination Figure 1 and Figure 2 In the exemplary embodiment shown, a charge carrier path for diode operation is formed through the third base region 13c via its contact region 6c. Holes can be injected via the third contact region 6c. This charge carrier path is independent of the gate electrode's potential, particularly because the second-type trench 52 adjacent to the third base region 13c is at emitter potential, not gate potential. Consequently, operation can be performed using conventional gate drive schemes while maintaining low reverse recovery charge and Erec.

[0096] Figure 3 Another exemplary embodiment of a semiconductor device 100 is shown. Figure 1 It is essentially the same, but now comprises a plurality of third contact regions 6 c in the third base region 13 c , each of which is in electrical contact with the emitter electrode 2 .

[0097] exist Figure 4 In the Figure 3 FIG1 is a top view of the top side 11 of the semiconductor device 100. As can be seen from the figure, the contact regions 6c are laterally isolated from each other and arranged in a rectangular pattern. In the region between two contact regions 6c, there is no electrical contact with the emitter electrode 2. This means that in these regions, the emitter electrode 2 does not abut the third base region 13c.

[0098] In fact, the size and density of the contact regions 6c can be adjusted to obtain the best performance in transistor mode and diode mode.

[0099] Figure 5 and Figure 6 Again, the cross-sectional view ( Figure 5 ) and a top view of the top side 11 ( Figure 6 ) shows a third exemplary embodiment of a semiconductor device 100. In this exemplary embodiment, additional second contact regions 6b are present in the second base region 13b, in which the second base region 13b is in electrical contact with the emitter electrode 2. Each second base region 13b includes a plurality of such second contact regions 6b (see Figure 6 ). The second contact region 6b may have a similar function to the third contact region 6c, namely providing a charge carrier path for the diode mode and dissipating the charge carriers when the transistor mode is turned off.

[0100] By means of the contact region 6 b in the second base region(s) 13 b and the contact region 6 c in the third base region 13 c , more degrees of freedom are available for optimizing the operation in the transistor mode and in the diode mode.

[0101] exist Figure 7 In the exemplary embodiment of FIG5 , the third contact region 6 c in the third base region 13 c is not electrically contacted with the emitter electrode 2 as in the previously described exemplary embodiment, but is electrically contacted with the further electrode 5. The further electrode 5 can be controlled / biased independently of the gate electrode 4 and the emitter electrode 2. This can further help optimize the static transistor mode and / or the turn-off behavior and / or the diode mode, as another degree of freedom is available.

[0102] exist Figure 8 In the exemplary embodiment of , the conductive layer 8 is arranged on the top side 11 above the third base region 13c. The conductive layer 8 is spaced apart from the semiconductor body 10 by an electrically insulating layer 80, which in this case is identical to the gate insulating layer 40.

[0103] Conductive layer 8 is electrically connected to emitter electrode 2 and is in close proximity to third base region 13 c, thereby capacitively coupling to third base region 13 c. With the aid of conductive layer 8, holes in third base region 13 c can be influenced, for example, attracted or repelled by conductive layer 8. For example, during the transistor off mode, holes are attracted by conductive layer 8. During the diode mode, holes can be repelled by conductive layer 8.

[0104] The conductive layer 8 may be formed of highly doped polysilicon or metal. The distance between the conductive layer 8 and the third base region 13c, determined by the thickness of the electrical insulating layer 80, is, for example, at most 150 nm.

[0105] exist Figure 9In the exemplary embodiment of FIG. 1 , gate electrode 4 and its connections to various regions of semiconductor device 100 are not shown to improve drawing clarity. Instead, a portion of emitter electrode 2 is shown extending above third base region 13 c. A portion of emitter electrode 2 is separated from top side 11 of semiconductor body 10 by another electrically insulating layer 20 (also referred to herein as "field insulating layer 20"). Field insulating layer 20 may be formed of an oxide. The vertical distance between emitter electrode 2 and top side 11 is defined by the thickness of field insulating layer 20 and is significantly greater than the thickness of insulating layer 80 separating conductive layer 8 from top side 11.

[0106] Figure 10 A first position in an exemplary embodiment of a method for manufacturing a semiconductor device 100 is shown. In this position, a semiconductor body 10 having a top side 11 and a bottom side 19 is provided. The bottom side 19 is formed by alternatingly arranged regions of the first type 15 and regions of the second type 16. The top side 11 is formed by base regions 13 of the second conductivity type. A drift region 14 is arranged between the bottom side 19 and the base regions 13, wherein the drift region 14 is of the first conductivity type.

[0107] Figure 11 The position is shown after trenches 51 , 52 have been formed in the semiconductor body 10 . The trenches 51 , 52 are filled with a conductive material. The conductive material in the trenches 51 , 54 is electrically isolated from the semiconductor body 10 by an electrically insulating material 40 (gate insulating layer 40 ) arranged in the trenches 51 , 52 .

[0108] Furthermore, a first base region 13a, a second base region 13b, and a third base region 13c are formed, for example, by ion implantation. Furthermore, an implantation region 12 is formed in the semiconductor body 10, for example, by ion implantation.

[0109] Figure 12 The location of ion implantation into the top side 11 using a mask 200 is shown. The mask 200 includes holes located above the first base region 13a, above the second base region 13b, and above the third base region 13c. By this implantation, contact regions 6a, 6b, 6c are formed in the base regions 13a, 13b, 13c, which have a higher doping concentration than the surrounding base regions.

[0110] Figure 13 The semiconductor component 100 is shown after the electrodes 2, 3, 4 have been applied to the semiconductor body 10. The highly doped contact regions 6a, 6b, 6c are again electrically connected to the emitter electrode 2.

[0111] like Figures 1 to 13The illustrated embodiments represent exemplary embodiments of the improved semiconductor device and the improved method for manufacturing the semiconductor device; therefore, they do not constitute a complete list of all embodiments of the improved semiconductor device according to the improved method. For example, the actual semiconductor device and method may differ from the illustrated embodiments in terms of arrangement, elements, and order of method steps.

[0112] Reference Mark 2First main electrode / emitter electrode 3 Second main electrode / collector 4 gate electrodes 5 Another electrode 6a First contact area 6b Second contact area 6c Third contact area 8 Conductive layer 10Semiconductor body 11 Top side 12 injection area 13 base regions 13a first base region 13b second base region 13c third base region 14 Drift Zone 15 Type 1 area 16 Second type area 19 bottom side 20 Electrical insulation layer / field insulation layer 40 electrical insulation layer / gate insulation layer 51 first type groove 52 Second type groove 80 Electrical insulation layer 100 Semiconductor Devices / RC-IGBT 200 masks

Claims

1. A semiconductor device (100), comprising: - a semiconductor body (10), said semiconductor body (10) extending in a vertical direction between a top side (11) and a bottom side (19), - a first main electrode (2) on the top side (11) and a second main electrode (3) on the bottom side (19), - gate electrode (4), - at least two trenches, namely a first type trench (51) and a second type trench (52), each trench extending from the top side (11) into the semiconductor body (10), wherein - The semiconductor body (10) comprises: - a drift region (14) of a first conductivity type, the drift region (14) of the first conductivity type being arranged vertically between the top side (11) and the bottom side (19), - at least three base regions, namely a first base region (13a), a second base region (13b), and a third base region (13c), each of which is of the second conductivity type and each of which is arranged vertically between the drift region (14) and the top side (11), - an injection region (12) of a first conductivity type, the injection region (12) of the first conductivity type being vertically spaced apart from the drift region (14) by the first base region (13a) and being adjacent to the first base region (13a), wherein - the first base region (13a), the first type trench (51), the second base region (13b), the second type trench (52), and the third base region (13c) are arranged in this order in a first lateral direction, - the first main electrode (2) is in electrical contact with the injection region (12), - the gate electrode (4) extends into the first type trench (51), where the gate electrode (4) is isolated from the semiconductor body (10) by a gate insulating layer (40), - the second type trench (52) is devoid of the gate electrode (4), - the third base region (13c) comprises at least one contact region (6c), in which the third base region (13c) is in electrical contact with an electrode (2, 5) of the semiconductor device (100) different from the gate electrode (4), The third base region (13c) extends deeper from the top side (11) into the semiconductor body (10) than the second-type trench (52).

2. The semiconductor device (100) according to claim 1, wherein - the third base region (13c) is electrically connected to the first main electrode (2) in the at least one contact region (6c).

3. The semiconductor device (100) according to claim 1, wherein - the third base region (13c) is electrically connected in the at least one contact area (6c) to an electrode (5) configured to operate independently of the first main electrode (2).

4. The semiconductor device (100) according to any one of the preceding claims, wherein - The semiconductor device (100) is an RC-IGBT or a MISFET.

5. The semiconductor device (100) according to any one of the preceding claims, wherein The second base region (13b) comprises at least one contact region (6b), in which the second base region (13b) is in electrical contact with an electrode (2, 5) of the semiconductor device (100) that is different from the gate electrode (4).

6. The semiconductor device (100) according to any one of the preceding claims, wherein The first base region (13a) comprises at least one contact region (6a), in which the first base region (13a) is in electrical contact with an electrode (2, 5) of the semiconductor device (100) that is different from the gate electrode (4).

7. The semiconductor device (100) according to any one of the preceding claims, wherein - the third base region (13c) comprises a plurality of contact regions (6c), wherein: The third base region (13c) is in electrical contact with the electrode (2, 5) in each of the plurality of contact regions (6c), - The contact regions (6c) of the third base region (13c) are spaced apart from each other in at least one lateral direction.

8. The semiconductor device (100) according to any one of the preceding claims, wherein - The doping concentration of the third base region (13c) is greater in the at least one contact region (6c) than in a region laterally adjacent to the contact region (6c).

9. The semiconductor device (100) according to any one of the preceding claims, wherein - a conductive layer (8) arranged on the top side (11) above the third base region (13c) and electrically connected to an electrode (2, 5) of the semiconductor device (100) other than the gate electrode (4), - the conductive layer (8) is located close to the third base region (13c) so that by electrically biasing the conductive layer (7), a strong capacitive coupling between the third base region (13c) and the conductive layer (9) can be achieved, thereby affecting the free charge carriers in the third base region (13c).

10. The semiconductor device (100) according to claim 9, wherein - the conductive layer (8) is spaced apart from the top side (11) by an electrically insulating layer (80) arranged vertically between the top side (11) and the conductive layer (8), - the thickness of the electrically insulating layer (80) is at most 5 times greater than the thickness of the gate insulating layer (40), and / or the vertical distance between the conductive layer (8) and the third base region (13c) is at most 500 nm.

11. The semiconductor device (100) according to claim 9 or 10, wherein - In a top view of the top side (11), the conductive layer (8) covers a major portion of the third base region (13c).

12. The semiconductor device (100) according to any one of claims 9 to 11, wherein - the conductive layer (8) is arranged vertically between the top side (11) of the semiconductor body (10) and a portion of the emitter electrode (2), - The vertical distance between the conductive layer (8) and the third base region (13c) is at most half the vertical distance between a portion of the emitter electrode (2) and the top side (11) of the semiconductor body (10).

13. A method for manufacturing a semiconductor device (100), comprising: - providing a semiconductor body (10) having a top side (11) and a bottom side (19), - forming at least two trenches, namely a first type trench (51) and a second type trench (52), each trench extending from the top side (11) into the semiconductor body (10), - forming a first main electrode (2) on the top side (11) and a second main electrode (3) on the bottom side (19), - forming a gate electrode (4) such that the gate electrode (4) extends into the first type trench (51), the gate electrode (4) being isolated from the semiconductor body at the first type trench (51) by a gate insulating layer (40), wherein - the second type trench (52) remains free of the gate electrode (4), The semiconductor device (100) is formed such that the semiconductor body (10) comprises: - a drift region (14) of a first conductivity type, the drift region (14) of the first conductivity type being arranged vertically between the top side (11) and the bottom side (19), - at least three base regions, namely a first base region (13a), a second base region (13b), and a third base region (13c), each of which is of the second conductivity type and each of which is arranged vertically between the drift region (14) and the top side (11), - an injection region (12) of a first conductivity type, the injection region (12) of the first conductivity type being vertically spaced apart from the drift region (14) by the first base region (13a) and being adjacent to the first base region (13a), - the first base region (13a), the first type trench (51), the second base region (13b), the second type trench (52), and the third base region (13c) are arranged in this order in a first lateral direction, - the first main electrode (2) is in electrical contact with the injection region (12), - the third base region (13c) comprises at least one contact region (6c), wherein, in the contact region (6c), the third base region (13c) is in electrical contact with an electrode (2, 5) of the semiconductor device (100) different from the gate electrode (4), The third base region (13c) extends deeper from the top side (11) into the semiconductor body (10) than the second-type trench (52).

14. The method according to claim 13, wherein - the semiconductor device (100) is formed such that the first base region (13a) comprises at least one contact region (6a), in which the first base region (13a) is in electrical contact with an electrode (2, 5) of the semiconductor device (100) different from the gate electrode (4), - in the contact region (6a, 6c), the doping concentration of the corresponding base region (13a, 13c) is greater than the doping concentration in a region of the corresponding base region (13a, 13c) laterally adjacent to the contact region (6b, 6c), - The contact regions (6a, 6c) are produced simultaneously using a common mask (200) with the aid of ion implantation.

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