Hybrid material power device and driving circuit

Abstract

A power integrated circuit includes: a heterojunction structured gallium nitride (GaN) chip including at least one GaN layer and at least one aluminum gallium nitride (AlGaN) layer, where the GaN chip includes at least one main power device including a source terminal, a drain terminal, a gate terminal, and a two-dimensional electron gas (2DEG), a 2DEG formed at an interface between the AlGaN layer and the GaN layer and located between the source terminal and the drain terminal, and a gate terminal for modulating at least a portion of the 2DEG when a charge is applied to the gate terminal; and a driver comprising at least one low-side component and at least one high-side component wherein the low-side component comprises a terminal connected to a low DC voltage rail and at least one other terminal connected to the gate terminal of the main power device, and wherein the low-side component comprises a terminal connected to the low DC voltage rail and at least one other terminal connected to the gate terminal of the main power device. The high-side component comprises at least one terminal connected with a high DC voltage rail and at least one other terminal connected with the grid electrode of the main power device, and the at least one low-side component of the driver is used for discharging an input capacitance of the main power device in the turn-off process of the main power device. And at least one high-side component of the driver, which is used for charging the input capacitor of the main power device and is formed in a semiconductor region containing materials other than GaN, and is integrated with the GaN chip in a monolithic manner, and the at least one high-side component of the driver is used for charging the input capacitor of the main power device and is formed in a semiconductor region containing materials other than GaN.

Description

Technical Field

[0001] The present disclosure relates to power semiconductor devices and drive circuits, and particularly, but not exclusively, to uses of heterojunction AlGaN / GaN high electron mobility transistors and associated silicon chips. Background Art

[0002] Gallium nitride (GaN) is a wide bandgap material suitable for power and radio frequency (RF) semiconductor devices. GaN technology enables transistors to be designed with high electron mobility and high saturation velocity, two properties that are generally useful in the field of power and radio frequency electronic devices. The use of GaN materials in power devices also has other advantages. For example, the wide bandgap of the material (Eg = 3.39 eV) can produce a large critical electric field (Ec = 3.3 MV / cm), thereby achieving a device design with a shorter drift region (and therefore lower on-resistance) than silicon-based devices at the same breakdown voltage.

[0003] The use of aluminum gallium nitride (AlGaN) / GaN heterojunction structure can also form carriers at the heterojunction interface to achieve extremely high carrier mobility values (such as μ = 2000cm 2 In addition, the piezoelectric charge at the AlGaN / GaN heterojunction structure can make the 2DEG layer have a high electron density (such as 1e13 cm -2 Exploiting these characteristics enables the development of high electron mobility transistors (HEMTs) and Schottky barrier diodes with highly competitive performance parameters. Currently, significant research is focused on the development of power devices using AlGaN / GaN heterojunction structures, resulting in the development of various technologies that enable normally-on HEMT devices (Schottky-gate-based technologies) and normally-off HEMT devices (insulated-gate and p-GaN gate technologies). It should be noted that normally-off devices are also referred to as enhancement-mode devices, while normally-on devices are also referred to as depletion-mode devices.

[0004] A gate driver is the interface circuit between a power device and a controller. This circuit receives a low-power input (e.g., pulse-width modulated (PWM)) from a controller integrated circuit (IC) and outputs a suitable signal to charge or discharge the gate of the power device, thereby turning the device on or off. Typically, the gate of a power device cannot be driven directly by a PWM signal from the controller due to its low current capacity. Accordingly, a gate driver should be able to turn the device on by providing a suitable charging current to the device's input capacitor and turn it off by discharging the capacitor.

[0005] A totem-pole driver, formed in silicon (as shown in the schematic in Figure 1), features complementary PNP and NPN transistors. The collector of the NPN transistor (the high-side component) is connected to a high-voltage DC rail, while the collector of the PNP transistor (the low-side component) is connected to a low-voltage DC rail. In this article, the terms "high-side" and "low-side" generally refer to different sections of the driver circuitry. The high-side section is connected to the high-voltage positive DC rail and is responsible for driving the power device during the on-state. The low-side section is connected to ground (or a low-potential DC rail) and is responsible for driving the power device during the off-state. The emitters of the two transistors can be connected together and connected to the gate of the power device through a resistor. This structure also allows for optimal gate clamping to a voltage equal to VDD + VBE, where VBE is the base-emitter voltage of the NPN transistor. This feature is particularly beneficial for certain gate-sensitive GaN power devices (those with a limit on the voltage that can be applied to the gate). The dV / dt slope during the on- and off-states is often adjusted by introducing an additional gate resistor. Alternatively, the emitters of the two transistors can be connected to the gate through different resistance paths so that their respective dV / dt slopes can be adjusted independently during the on-off process. Ideally, NPN and PNP transistors operate in saturation so that the voltage drop between their collector and emitter terminals is minimal. However, bipolar transistors generally require a relatively high base current to operate in saturation (to minimize the voltage drop between their collector and emitter terminals). In addition, PNP transistors are particularly prone to slow speeds and are limited by the relatively large voltage drop in saturation for a given chip area. In addition, a bypass capacitor is provided between VDD and ground. This capacitor charges to VDD and provides gate current when the power device is on.

[0006] In an alternative solution, two NPN transistors are used, wherein the PNP transistor is replaced by an NPN transistor, and an inverter is further connected to the base of the NPN transistor.

[0007] A double-stage CMOS inverter structure is also known in the prior art, wherein the second-stage inverter is composed of a plurality of parallel-connected inverter chips ( FIG. 2 ).

[0008] The second-stage inverter (202, 203, 204) (with its output connected to the gate of the power device) can be replaced by a single large-area (high-current) inverter that can provide the same current as the parallel structure described above. The second-stage inverter can include: a low-side n-channel MOSFET device responsible for shutting off the discharge path of the power device input capacitor, and a p-channel MOSFET device for opening the charging path of the power device input capacitor. The lower the on-resistance of both the n-channel and p-channel MOSFETs, the faster the gate charge and discharge opening and closing speeds.

[0009] In an attractive architecture, the driver and power device are monolithically integrated, reducing the number of components and lowering parasitic effects (parasitic inductance, parasitic capacitance, and parasitic resistance) between the driver and the power device. This architecture is particularly suitable for power integrated circuits that need to operate at high frequencies. Due to their inherent low parasitic capacitance, GaN power devices can actually operate at higher frequencies than equivalent silicon devices, so monolithic integration can meet their needs. In addition, this integration approach can also reduce parasitic effects (such as parasitic inductance) between the power device and the driver, thereby helping to reduce the effects of dV / dt and dI / dt.

[0010] However, integrating a complete driver within GaN has certain drawbacks. NPN or PNP transistors are not yet available in GaN technology, and the development of p-channel unipolar transistors is still in its infancy. These p-channel transistors, operating via a two-dimensional hole gas (2DHG), have poor performance due to their extremely low hole mobility.

[0011] Furthermore, since GaN technology lacks CMOS architecture (due to the absence of p-channel devices), the power consumption of drivers monolithically integrated in GaN (especially in standby mode) cannot be ignored. Furthermore, integrating the complete driver and power devices on the same chip can lead to thermal coupling between the two, further degrading driver performance.

[0012] In view of the above problems, architectural improvements are needed.

[0013] The following documents may be considered as prior art:

[0014] [1] F. Udrea et al., “A dual-function smart IC eGaN™ platform for sensing and protection that improves both ease of use and gate reliability,” 2022 34th IEEE International Conference on Power Semiconductor Devices and Integrated Circuits (ISPSD Conference), pp. 41–44, doi:10.1109 / ISPSD49238.2022.9813659.

[0015] [2] L. Efthymiou, M. Arnold, G. Longobardi, and F. Udria, “A new depletion-mode p-type GaN island HEMT and its use in a monolithically integrated startup circuit,” ESSDERC 2022 - 52nd IEEE European Solid-State Device Research Conference (ESSDERC Conference), 2022, pp. 396–399, doi:10.1109 / ESSDERC55479.2022.9947100;

[0016] [3]US11081578;

[0017] [4]US11404565. Summary of the Invention

[0018] In general, an object of the present invention is to provide an improved architecture between a power device and a driver to solve the above-mentioned problems.

[0019] According to a first aspect of the present invention, a power integrated circuit is provided, comprising: a heterojunction gallium nitride (GaN) chip, the GaN chip comprising at least one GaN layer and at least one aluminum gallium nitride (AlGaN) layer, wherein the GaN chip comprises at least one main power device, the main power device comprising a source terminal, a drain terminal, a gate terminal, and a two-dimensional electron gas (2DEG), the 2DEG being formed at the interface between the AlGaN layer and the GaN layer and being located between the source terminal and the drain terminal, the gate terminal being configured to modulate at least a portion of the 2DEG when a charge is applied to the gate terminal; and a driver comprising at least one low-side component and at least one high-side component, wherein the low-side component comprises a terminal connected to a low DC voltage rail and at least one other terminal connected to the gate terminal of the main power device, and the high-side component comprises at least one terminal connected to a high DC voltage rail and at least one other terminal connected to the gate of the main power device. The at least one low-side component of the driver is configured to discharge the input capacitance of the main power device during shutdown of the main power device and is monolithically integrated with the GaN chip. The at least one high-side component of the driver is used to charge the input capacitance of the main power device and is formed in a semiconductor region of a non-GaN material.

[0020] Optionally, the at least one other terminal of the high-side component connected to the main power device gate is directly connected to the main power device gate.

[0021] Optionally, the at least one other terminal of the high-side component connected to the gate of the main power device is indirectly connected to the gate of the main power device via a diode and / or a resistor.

[0022] Preferably, the main power device and / or the low-side component of the driver is a high electron mobility transistor (HEMT), and the output power and blocking voltage of the main power device are greater than the output power and blocking voltage of the low-side component of the driver.

[0023] Optionally, the low-side component of the main power device and / or the driver comprises a plurality of 2DEG channels arranged in parallel between the source terminal and the drain terminal of the main power device.

[0024] Optionally, the low-side component of the driver includes one of a HEMT, a MOSFET, or a MISFET, which can be used as a Miller clamp with its drain terminal connected to the gate terminal of the main power device and its source connected to the source of the main power device. The low-side component can be located near the main power device or within the main power device structure. Preferably, the low-side component of the driver is a HEMT and can use similar layers as the main power device to facilitate manufacturing.

[0025] Optionally, the at least one low-side component of the driver comprises a normally-on or normally-off transistor, or a parallel combination of normally-on and normally-off transistors.

[0026] Optionally, the low-side component of the driver is configured to provide an increased resistance when the low-side component is in an off-state and a decreased resistance when the low-side component is in an on-state.

[0027] Optionally, the low-side component of the driver includes a HEMT, the HEMT including a plurality of p+GaN islands arranged perpendicular to the direction of current flow between the source terminal and the drain terminal of the HEMT, and each p+GaN island is connected to the gate terminal of the HEMT. Here, "p+GaN" refers to a gallium nitride layer that is highly doped with an acceptor-type dopant (such as magnesium). For example, at least 1e19 cm -3 The concentration of can be regarded as a suitable high doping level.

[0028] Optionally, the GaN chip includes one or more other 2DEG low-power transistors connected to the main power device or low-side components of the driver.

[0029] Optionally, the at least one high-side component is configured as a hole conducting component.

[0030] Optionally, the at least one high-side component is disposed in a first semiconductor material, the at least one low-side component is disposed in a second semiconductor material, and the first semiconductor material and the second semiconductor material are different semiconductor materials.

[0031] Optionally, the at least one high-side component and the at least one low-side component are used as CMOS cells.

[0032] Optionally, another low-side component of the driver is arranged in parallel with the at least one low-side component of the driver and is arranged in a semiconductor region of a non-GaN material (the first semiconductor).

[0033] Alternatively, the other low-side component of the driver comprises an n-channel MOSFET, an n-channel JFET, a PNP bipolar transistor, or an NPN transistor whose base is additionally driven by an inverter.

[0034] According to another embodiment of the present disclosure, a power integrated circuit (power IC) is provided, comprising: a gallium nitride chip (GaN chip) based on a heterojunction structure, the GaN chip comprising at least one gallium nitride (GaN) layer and at least one aluminum gallium nitride (AlGaN) layer. The GaN chip contains at least one main power device, the main power device comprising a source terminal, a drain terminal, a gate terminal, and a two-dimensional electron gas (2DEG), the 2DEG being formed at the interface between the AlGaN layer and the GaN layer and located between the source terminal and the drain terminal, wherein at least a portion of the 2DEG layer is modulated by a charge applied to the gate terminal. Furthermore, a driver is included, the driver comprising at least one low-side component and at least one high-side component, wherein the low-side component comprises a terminal connected to a low DC voltage rail (such as ground) and at least one other terminal connected to the gate of the main power device, and the high-side component comprises at least one terminal connected to a high DC voltage rail (such as VDD) and at least one other terminal connected directly to the gate of the main power device or indirectly to the gate terminal of the main power device via a diode and / or resistor. The at least one low-side component of the driver is responsible for discharging the input capacitance of the main power device during shutdown and is monolithically integrated with the GaN chip. The at least one high-side component of the driver is responsible for charging the input capacitance of the main power device and is contained in a semiconductor region based on a material other than GaN.

[0035] The main power device may be a HEMT (high electron mobility transistor) and may have a two-dimensional electron gas (2DEG) at the heterojunction interface between the AlGaN layer and the GaN layer and between the source terminal and the drain terminal. The main power device may be a normally-off device or a normally-on device. The main power device may have a p-type GaN gate (for example, made of magnesium) for modulating the 2DEG channel in the region between the source terminal and the drain terminal. An ohmic metal or a Schottky metal may be provided on the p-type gate to form a gate terminal. Alternatively, the main power device may have an insulating gate or a Schottky gate. The main power device may include a plurality of finger structures or units to expand the current capacity.

[0036] The main power device can have multiple 2DEG channels formed between subsequent GaN and AlGaN layers. These multiple 2DEG layers help reduce the on-resistance between the source and drain terminals when the device is in the on state. This multi-channel HEMT can have a tri-gate or FinFET structure for the control channels, or it can be based on a CASCODE structure.

[0037] The at least one low-side component of the driver can be a HEMT device with a 2DEG and operates in a manner similar to a Miller clamp. The drain terminal of the HEMT device is connected to the gate terminal of the GaN power device, and its source can be connected to the source of the main power device. The at least one low-side component (Miller clamp) is integrated into the GaN chip and can be arranged side by side with the main power device, or located near it or even inside it ( Figure 4 ). The on-state current and blocking voltage capability of the at least one low-side component (low-side HEMT) are less than the on-state current and blocking voltage capability of the power device. As used herein, the term "blocking voltage" refers to a voltage that can be applied between the drain and source terminals of a component without causing it to conduct, either due to a breakdown mechanism or due to a significant increase in leakage current. The term also refers to breakdown voltage or avalanche voltage. This voltage is the maximum voltage that can be applied to a component, beyond which it will begin to conduct and allow current to pass, even when the device is biased in the off mode of operation. In some cases, the breakdown voltage may refer to the voltage at which the device fails open (that is, the device is unable to continue conducting current even when subsequently biased in the on mode of operation).

[0038] Alternatively, the at least one low-side component of the driver may be an n-channel MOSFET or MISFET employing a conventional insulated gate and surface channel and monolithically integrated into the GaN chip.

[0039] The low-side component of the driver can be a normally-off or normally-on device, or a parallel combination of a normally-on and normally-off device. The low-side component of the driver can be a low-side HEMT, which is manufactured using the same process steps and similar layers as the main power device, thereby minimizing the complexity of the process flow. The voltage and power of this low-side HEMT can be lower than those of the main GaN power device, and its size can be much smaller than the main power device. The low-side HEMT (the low-side component of the driver) can be self-isolated from the main power device. Alternatively, the main power device and the low-side HEMT can be located at two different locations in the active area, with isolation between them.

[0040] When the main power device is formed using multiple 2DEG channels, the low-side component (low-side HEMT) preferably also uses multiple channels with a similar gate architecture as the main power device. The low-side component of the gate driver (Miller clamp) can have a single 2DEG channel, while the multi-power device can have multiple 2DEG channels.

[0041] The low-side HEMT device may be based on or adopt the p+ island design as described in US11081578 and US11404565 and in F. Udria et al. [1] and L. Iversmuir et al. [2].

[0042] The driver may include other components and logic modules. For example, the driver may include a first-stage inverter and a second-stage inverter connected in series, wherein the second-stage inverter may include the at least one low-side component and the at least one high-side component. The first-stage inverter may be driven by a PWM signal from a controller, and the second-stage inverter may have one or more output terminals connected directly or indirectly (via a resistor and / or a diode) to the gate terminal of the main power device. The driver may also include one or more bypass capacitors, diodes (such as Schottky or Zener diodes) for clamping and protection purposes, or multiple DC rails for biasing.

[0043] The GaN chip can further monolithically integrate another low-side component of the first-stage inverter in the form of another low-power HEMT ( Figure 5 The drain and source of another low-power HEMT may be connected to the gate and source of the at least one low-side component of the second-stage inverter in the driver, respectively. Compared to the low-power component of the driver, the other low-power HEMT may have lower power and lower blocking voltage capability. The other low-power HEMT may be part of the first-stage inverter of the driver and may be connected to the PWM signal.

[0044] The first-stage inverter may further include another high-side p-channel device (performing hole conduction). The other high-side p-channel device may have lower power than the high-side p-channel device of the second-stage inverter.

[0045] Alternatively, the other low-side components of the first-stage inverter may be contained in other semiconductor regions based on materials other than GaN.

[0046] Furthermore, any logic components or low-power components (part of a driver or controller, or part of a sensing and protection circuit) formed in an n-channel (i.e., conducting electrons) or functioning as low-side devices can be further monolithically integrated within the GaN chip. These components are in the form of low-power HEMTs, leveraging the high electron mobility advantages of the 2DEG channel and the performance advantages of HEMTs, including low on-resistance and low parasitic capacitance. Alternatively, in addition to the at least one low-side component (Miller clamp) of the driver, the low-side components can be incorporated into other semiconductor regions based on materials other than GaN for matching purposes, to meet the requirements of local integration within CMOS circuits, or to meet the requirements of using bipolar transistors such as low-power n-channel components.

[0047] Furthermore, at least one high-side component and any other components having p-channel devices (conducting holes rather than electrons) or any components employing NPN or PNP transistors may be included in other semiconductor regions based on materials other than GaN.

[0048] Figure 6 Shown are an NPN transistor on the high side of the driver (contained within a semiconductor region based on materials other than GaN) and a low-power HEMT on the low side of the driver, monolithically integrated with the main power devices. In this figure, the first-stage inverter is shown as an n-channel and p-channel MOSFET implemented in a silicon chip using a CMOS structure.

[0049] Optionally, another low-side component (of the second stage) may be arranged in parallel with the at least one low-side component (Miller clamp) and in another semiconductor region based on a material other than GaN. This component may be, for example, an n-channel MOSFET, an n-channel JFET, a PNP transistor ( Figure 7a ) or an NPN transistor with an additional inverter at the base ( Figure 7b ). The purpose of this other low-side component of the driver is to assist in the discharge of the input capacitor during the shutdown process and thereby provide a parallel path for the transient current during the shutdown process of the main power device. For example, when a PNP transistor is added, the parallel combination of the PNP transistor based on other semiconductor regions of materials other than GaN and the low-side component of the driver contained in the GaN chip (Miller clamp) can achieve higher stability at higher temperatures. On the one hand, bipolar devices such as HEMTs formed in GaN are known to have a significant increase in on-resistance at high temperatures due to the reduction of channel mobility (2DEG mobility) at high temperatures. On the other hand, the base-emitter junction voltage will decrease at high temperatures, and the carrier injection phenomenon is aggravated at high temperatures. Therefore, the parallel combination of the low-side GaN HEMT and the low-side PNP transistor formed in other semiconductor materials can achieve more stable operation in terms of temperature. This effect can also be achieved when the PNP transistor is replaced with an NPN transistor with an additional inverter at the base. An advantage of using another low-side component in the driver may be that high dV / dt currents can be absorbed more efficiently, thereby increasing dV / dt robustness.

[0050] Other semiconductor regions based on materials other than GaN can be part of the accompanying silicon chip. Optionally (and preferably), the silicon chip can be placed adjacent to the GaN chip, preferably within the same package or module. The silicon and GaN chips can be arranged laterally to facilitate bonding between the dies. In this way, the two chips (GaN and silicon) can be integrated in a hybrid manner within the same package or module.

[0051] The advantage of using a companion silicon chip is that the at least one high-side component of the driver can be made of a p-channel MOSFET or an NPN bipolar transistor. Such devices can be manufactured using mature silicon processes (such as the 0.35μm node, the 0.18μm node, and the 0.13μm node) and achieve good performance. In contrast, such transistors (i.e., p-channel transistors or bipolar transistors) made with gallium nitride either do not exist or have very low performance. The companion silicon chip can be manufactured using, for example, a CMOS process, a bipolar process, a CMOS-bipolar process, a bipolar-CMOS-DMOS (BCD) process, or a high-voltage CMOS process.

[0052] Furthermore, p-channel high-side components (such as MOSFETs) formed in silicon and n-channel low-side components (HEMTs) formed in GaN can together form a highly efficient CMOS-type cell that achieves low power consumption (almost zero in steady state and relatively small power consumption in transient state) and optimizes area consumption.

[0053] Furthermore, n-channel low-side components (HEMTs) can be located in GaN very close to the main power device to reduce unwanted parasitic effects (particularly parasitic inductance) between their drain terminal and the main power device's gate. This helps improve robustness to dV / dt and dI / dt signals during turn-on and turn-off. Given the high mobility (>1600 cm² / (Vs)) and low parasitic capacitance of HEMTs, these devices have the potential to offer higher performance or a smaller footprint than equivalent n-channel transistors integrated in silicon. As mentioned above, it is crucial for these devices to be located close to the power device to quickly discharge the input capacitance during turn-off and minimize gate signal oscillation. In this context, the terms "near" or "close" mean "close to" the main power device. In this sense, the low-side components can be located very close to or within the main power device.

[0054] When the main power device is on or conducting during active reverse conduction, the low-side component (HEMT) in GaN can be in a conducting state in high resistance mode (kilo-ohm range). When the main power device is off, or when it is in the off state or reverse conduction, the low-side component can be in a fully conducting state in low resistance mode (ohm range).

[0055] Other semiconductor regions based on materials other than GaN may be part of the substrate and physically located below (or near below) the GaN and AlGaN layers ( Figure 8This allows for high integration and an extremely compact solution. Contact to the substrate can be achieved by etching through the upper GaN layers. Transistors in the substrate can be fabricated using common transistor fabrication techniques, such as etching through the GaN layers followed by implantation, oxidation, or oxide deposition.

[0056] The substrate can be made of silicon or silicon carbide (SiC). Although silicon carbide costs more than silicon, it has a higher breakdown field strength and is more compatible with the GaN / AlGaN layer above it. In addition, when using a SiC substrate, it allows the growth of thinner GaN layers. However, the channel mobility of a p-channel transistor formed in silicon is higher than that of an equivalent p-channel transistor formed in silicon carbide.

[0057] In another implementation of the present disclosure ( Figure 9 ), the power integrated circuit includes: a half-bridge circuit, the half-bridge circuit including a low-side main power device provided in a GaN chip and a high-side main power device provided in the GaN chip or another GaN chip; a driver, the driver including a first pair and a second pair, each pair including at least one low-side component and at least one high-side component, wherein the first pair is used to charge and discharge the input capacitance of the low-side main power device during the on-off process of the low-side main power device, and the second pair is used to charge and discharge the input capacitance of the high-side main power device during the on-off process of the low-side main power device. The driver also includes a level converter that converts the low-voltage control of the first pair to the high-voltage control of the second pair.

[0058] Each of the at least one low-side components of the driver is formed in a GaN chip or in another GaN chip. Finally, each of the at least one high-side components of the driver is contained in another semiconductor region based on a material other than GaN.

[0059] As mentioned above, other semiconductor regions based on materials other than GaN may be part of a companion silicon chip, or may be part of a silicon substrate or a silicon carbide substrate.

[0060] Likewise, the level converter may be part of a matching silicon chip (or may be part of a silicon substrate or a silicon carbide substrate), or some of its components may be provided in a silicon chip, while other components may be provided in a GaN chip or another GaN chip.

[0061] An isolation zone with optical, capacitive, and inductive (magnetic) components can be set up between the logic signal (PWM) from the controller and the input driver. For example, isolation can be achieved through an optocoupler with an LED and a photodiode.

[0062] A half-bridge consisting of two main power devices can be integrated into a single GaN chip. This approach is preferred for reducing component count, complexity, and cost. However, integrating low-side high-voltage devices with high-side high-voltage devices presents significant challenges due to voltage crosstalk and isolation. For this reason, the two main power devices can be placed in separate chips with different substrates.

[0063] Each main power device can have a driver low-side component based on a 2DEG and operating in a similar manner to a Miller clamp. The driver's high-side components (such as p-channel MOSFETs or bipolar transistors) can be located in other semiconductor regions based on materials other than GaN. The high-side components can use different DC rail voltages (and be level-shifted relative to each other).

[0064] In another implementation of the present disclosure ( Figure 11 ), provides a power integrated circuit, comprising: a plurality of GaN chips, each GaN chip having a main power device and a low-side component of a driver (Miller clamp), wherein all the main power devices are connected in parallel to increase the output current and / or reduce the on-resistance; and a single supporting silicon chip, the supporting silicon chip having at least one high-side component of the driver, wherein the at least one high-side component of the driver is directly connected to the drain terminals of all the low-side components of the driver (or indirectly connected via a resistor and / or a diode) and is connected to the gate terminal of the main power device.

[0065] In this implementation, a single companion chip is provided for multiple GaN chips arranged in parallel, rather than a companion silicon chip for each GaN chip. This approach has the advantage of reducing the BOM and improving assembly and cost efficiency.

[0066] The above-mentioned supporting silicon chip may further include any of the following circuit modules:

[0067] -Level converter (converts signals from high-side power devices)

[0068] -Logic circuits (inverters, gates)

[0069] -PWM controller

[0070] - Voltage regulators (regulate various voltage rails)

[0071] - Startup circuit (provides DC voltage from the high voltage rail)

[0072] - Bandgap reference (provides a reference voltage with high temperature stability)

[0073] - Current sensing, current amplification, or transconductance circuitry (provides current sensing functionality, facilitates current sensing functionality, or amplifies the signal from a current sensing device)

[0074] - Temperature sensing (e.g., via a VPTAT circuit)

[0075] -Overcurrent and overtemperature protection circuit

[0076] - Memory (e.g. for calibration purposes)

[0077] - Undervoltage lockout circuit

[0078] -Slew rate control circuit

[0079] -Electrostatic discharge protection devices

[0080] The GaN chip may further include a current sensing device or a high-voltage current sensing switch for facilitating current sensing.

[0081] In this disclosure, unless otherwise specified, a heterojunction transistor may be any known heterojunction-based transistor, such as a p-type gate HEMT transistor, a Schottky gate transistor, or an insulated gate transistor such as a metal-insulator semiconductor field-effect transistor (MISFET). A diode may be a Schottky diode, a Zener diode, a PN diode, or a diode formed by connecting the gate terminal of a transistor to any other terminal. A GaN chip may be a heterojunction chip or a chip containing a heterojunction power device, and may be referred to as a heterojunction intelligent power device, a heterojunction intelligent chip, a heterojunction power integrated circuit, or a heterojunction integrated circuit.

[0082] A single GaN chip or multiple GaN chips within a power IC and their accompanying silicon chips can be contained in a single package or module. BRIEF DESCRIPTION OF THE DRAWINGS

[0083] The above and other aspects are described below, wherein:

[0084] FIG1 is a schematic illustration of a known totem pole type driver;

[0085] FIG2 is a schematic diagram illustrating a known bipolar CMOS inverter type driver;

[0086] Figure 3 A schematic diagram illustrating the gate driver and main power device of the present disclosure;

[0087] Figure 4 for Figure 3 A schematic cross-sectional illustration of an embodiment of a component formed in GaN is shown;

[0088] Figure 5 is a schematic diagram illustrating another embodiment of a gate driver and a main power device of the present disclosure, wherein the gate driver is partially formed in silicon and partially formed in GaN;

[0089] Figure 6 is a schematic diagram illustrating another embodiment of a gate driver and a main power device of the present disclosure, wherein the gate driver is partially formed in silicon and partially formed in GaN;

[0090] Figure 7a is a schematic diagram illustrating another embodiment of a gate driver and a main power device of the present disclosure, wherein the gate driver is partially formed in silicon and partially formed in GaN;

[0091] Figure 7b is a schematic diagram illustrating another embodiment of a gate driver and a main power device of the present disclosure, wherein the gate driver is partially formed in silicon and partially formed in GaN;

[0092] Figure 8 A schematic cross-sectional view illustrating an embodiment of components in GaN and silicon formed within the same wafer according to the present disclosure;

[0093] Figure 9 is a schematic diagram illustrating another embodiment of the present disclosure, wherein each gate driver and main power transistor combination can be used in a half-bridge structure;

[0094] Figure 10 For Figure 3 An illustrative block diagram of a supporting silicon chip for use with the GaN chip disclosed herein;

[0095] Figure 11 An illustration of multiple GaN chips of the present disclosure connected in parallel with a companion silicon chip. DETAILED DESCRIPTION

[0096] Figure 1 is a schematic diagram of a totem-pole driver in the prior art. The illustrated totem-pole driver includes complementary PNP and NPN transistors. The collector of NPN transistor Q1 (serving as the high-side component) is connected to the high-voltage DC rail VDD, while the collector of PNP transistor Q2 (serving as the low-side component) is connected to the low-voltage DC rail. In the embodiment shown in Figure 1, the collector of the PNP transistor is connected to the source terminal of power device Q3. The emitters of the two transistors can be connected together and optionally connected to the gate of the power device via a resistor (not shown).

[0097] Figure 2 is a schematic diagram of a known bipolar CMOS inverter driver in the prior art. The driver includes a first-stage CMOS inverter. In the illustrated embodiment, the second-stage inverter includes three parallel inverters. However, more or fewer parallel inverters may be used. The output of the second stage may optionally be connected to the gate of a power device via a resistor (not shown).

[0098] Figure 3Schematic diagram of the gate driver and main power device, wherein the gate driver is partially formed in silicon and partially formed in GaN. In this embodiment, the main power device Q4 is formed in GaN. Figure 3 In the illustrated embodiment, the gate driver portion formed in silicon is the CMOS inverter INV1 and the high-side device Q6, where the high-side device is a p-channel MOSFET. The gate driver portion formed in GaN is the low-side device Q5, where the low-side device in this embodiment is a GaN HEMT.

[0099] Figure 4 for Figure 3 Schematic diagram of a cross section of an embodiment of components formed in GaN is shown. The cross section shows the substrate and the epitaxial stack including a silicon substrate 404, a transition layer 403, a GaN layer 402 and an AlGaN layer 401. Two devices are formed on this material, one is the main power HEMT 40 and the other is the low-side device of the gate driver 41. Both devices are three-terminal devices including a drain contact, a source contact and a gate contact. Both devices shown in the figure include a p-type GaN gate. As shown in the figure, the drift region length (i.e., the spacing between the drain contact and the gate contact) of the main power HEMT 40 is larger than that of the gate driver low-side device 41, and therefore the rated voltage is higher. As shown in the figure Figure 3 As shown, the electrical connections between the gate driver device and the main power HEMT can be made by metal traces.

[0100] Figure 5 Schematic diagram of another embodiment of a gate driver and a main power device, wherein the gate driver is partially formed in silicon and partially formed in GaN. Similar to the previous embodiment, in this embodiment, the main power HEMT Q9 and at least one gate driver low-side device Q10 are formed in GaN. However, in this embodiment, another low-side device Q11 is also formed in GaN, wherein the other low-side device can also be a GaN HEMT. Figure 5 In the embodiment shown, all gate driver high-side devices (Q7 and Q8) are formed in silicon and may be p-channel MOSFETs.

[0101] Figure 6 FIG1 is a schematic diagram of another embodiment of a gate driver and a main power device, wherein the gate driver is partially formed in silicon and partially formed in GaN. In this embodiment, the main power device Q15 is formed in GaN. Figure 6In the illustrated embodiment, the gate driver portion formed in silicon is a CMOS inverter (Q13, Q14) and a high-side device Q12, wherein the high-side device is an NPN transistor. In this embodiment, the NPN transistor is driven by an input signal from the gate driver. The input signal to the gate driver can be a signal from a controller, such as a pulse signal such as a PWM signal. The gate driver portion formed in GaN is a low-side device Q16, wherein in this embodiment, the low-side device is a GaN HEMT. The gate signal of the GaN HEMT, which serves as the low-side device, is the output signal of the CMOS inverter.

[0102] Figure 7a Schematic diagram of another embodiment of a gate driver and a main power device Q15, wherein the gate driver is partially formed in silicon and partially formed in GaN. In this embodiment, the gate driver formed in silicon includes a totem pole driver (Q19, Q20A) as shown in Figure 1, and further includes a CMOS inverter (Q17, Q18). The output end of the totem pole driver (Q19, Q20A) can be optionally connected to the gate of the power device Q15 through a resistor (not shown). The output of the CMOS inverter (Q17, Q18) formed in silicon is used to drive the low-side GaN device Q16. In this embodiment, the low side of the totem pole driver is set in parallel with the at least one low-side GaN component Q16, and its function is to assist the input capacitor to discharge during the shutdown process, thereby providing a parallel path for the transient current during the shutdown process of the main power device Q15. This advantage is achieved while retaining the advantage of reducing unwanted parasitic effects (particularly parasitic inductance) between the drain terminal of the n-channel low-side component Q16 (HEMT) in GaN and the main power device Q15 by placing it very close to the main power device Q15 (i.e., on chip).

[0103] Figure 7b FIG. 1 is a schematic diagram of another embodiment of a gate driver and a main power device Q15 , wherein the gate driver is partially formed in silicon and partially formed in GaN. Figure 7b and Figure 7a The embodiment shown is similar except that, in this embodiment, the PNP transistor Q20A is replaced by an inverter INV2 and an NPN transistor Q20B.

[0104] Figure 8A schematic cross-section of an embodiment of components formed in GaN and silicon on the same wafer (i.e., monolithic integration where the driver and GaN devices are in thermal equilibrium) is shown. The cross-section shows the substrate and the epitaxial stack comprising a silicon substrate 404, a transition layer 403, a GaN layer 402, and an AlGaN layer 401. Two devices are formed on this material: a main power HEMT 40 and a low-side device for a gate driver 41. Both devices are three-terminal devices comprising a drain contact, a source contact, and a gate contact. Both devices shown include a p-type GaN gate. The cross-section further includes a driver high-side component 42 formed on the silicon substrate 404 by extending to the substrate using conventional techniques. In this embodiment, the high-side component comprises a p-channel MOS transistor.

[0105] Figure 9 This is a schematic diagram of another embodiment, in which the gate driver and main power transistor combination described in the above embodiment can be used in a half-bridge structure. There are two pairs of gate driver-associated devices. Each pair includes a low-side device and a high-side device. The reason for setting two pairs of devices is that the number of power devices in the half-bridge structure is two. The main power device Q24 can be used as a half-bridge low-side device, and the main power device Q23 can be used as a half-bridge high-side device. The gate driver of the half-bridge low-side device can receive a PWM signal (or other pulse signal) from the low-side controller. The PWM signal can be flipped as shown. In Figure 9 In the embodiment shown, the gate drivers for the low-side devices of the half-bridge include a first pair of devices Q22 and Q26. The gate drivers for the high-side devices can also receive signals from the low-side controller, but the signals need to be level-shifted using a level shifter. Figure 9 In the illustrated embodiment, the gate drivers for the half-bridge high-side devices include a second pair of devices Q21 and Q25 .

[0106] The above level converter can also be Figure 9 A portion of the illustrated companion silicon chip, or some of its components, may be placed in a silicon chip, while the remaining components may be placed in a GaN chip (not shown).

[0107] Figure 10 For Figure 3 An example block diagram of a companion silicon chip for the GaN chip. In addition to the high-side components of gate driver 1001, given the greater maturity of silicon technology compared to GaN technology, particularly with regard to the availability of p-channel devices, the companion silicon chip can also be used to include a range of control and protection circuits to improve speed, power consumption, design flexibility, and yield. These control and protection circuits include, but are not limited to, current sensing circuitry, a bandgap reference circuitry, overcurrent protection circuitry, undervoltage lockout (UVLO) circuitry, slew rate control circuitry, overtemperature detection and protection circuitry, voltage regulators, level shifters, electrostatic discharge protection circuitry, logic circuitry, startup circuitry, and / or any other control and protection circuitry.

[0108] Figure 11 Another aspect of the present invention is shown, in which multiple GaN chips (GaN chip 1, GaN chip 2, ..., GaN chip N) are connected in parallel with a matching silicon chip. Each GaN chip includes the main power device and the associated low-side components of the driver, while the high-side components of the driver are located in the silicon chip. In addition, the silicon chip also includes Figure 10 A similar series of control and protection circuits.

[0109] Those skilled in the art will understand that, in the foregoing description and the appended claims, terms describing positions such as "top," "upper," "overlying," "lower," and "side" are used in conjunction with standard cross-sectional views of the device and conceptual illustrations such as the accompanying drawings. Such terms are intended for descriptive purposes and are not intended to be limiting. Therefore, when describing the device, such terms should be understood in the context of the orientation shown in the accompanying drawings.

[0110] Although the present disclosure has been described through the above preferred embodiments, it should be understood that such embodiments are for illustrative purposes only and the claims are not limited to such embodiments. Those skilled in the art may obtain modifications and alternatives based on the present disclosure, but such alternatives are deemed to fall within the scope of the claims. Each feature disclosed or shown in this specification may be incorporated into the present disclosure as a standalone feature or in combination with any other feature disclosed or shown herein in any appropriate combination.

[0111] Those skilled in the art can come up with a variety of other effective alternatives. It should be understood that the present disclosure is not limited to the above embodiments, but covers all modifications that fall within the spirit and scope of the present disclosure.

[0112] For example, the term "low power" as used herein generally refers to a controller output power that is insufficient on its own to drive the gate. In contrast, "high power" refers to a driver output power that is sufficient to drive the gate.

Claims

1. A power integrated circuit, characterized in that: include: A gallium nitride chip with a heterojunction structure, comprising at least one gallium nitride layer and at least one aluminum gallium nitride layer, wherein the gallium nitride chip includes at least one main power device, the main power device including a source terminal, a drain terminal, a gate terminal, and a two-dimensional electron gas, wherein the two-dimensional electron gas is formed at the interface between the aluminum gallium nitride layer and the gallium nitride layer and is located between the source terminal and the drain terminal, wherein the gate terminal is used to modulate at least a portion of the two-dimensional electron gas when a charge is applied to the gate terminal; and A driver comprising at least one low-side component and at least one high-side component, wherein the low-side component comprises a terminal connected to a low DC voltage rail and at least one further terminal connected to the gate terminal of the main power device, wherein the high-side component comprises at least one terminal connected to a high DC voltage rail and at least one further terminal connected to the gate of the main power device, The at least one low-side component of the driver is used to discharge the input capacitance of the main power device during the shutdown process of the main power device, and is monolithically integrated with the gallium nitride chip. The at least one high-side component of the driver is used to charge the input capacitor of the main power device and is formed in a semiconductor region of a non-gallium nitride material.

2. The power integrated circuit according to claim 1, wherein: The at least one other terminal of the high-side component connected to the gate of the main power device is indirectly connected to the gate of the main power device via a diode and / or a resistor.

3. The power integrated circuit according to claim 1 or 2, characterized in that: The main power device and / or the low-side component of the driver is a high electron mobility transistor, wherein the output power and blocking voltage of the main power device are greater than the output power and blocking voltage of the low-side component of the driver.

4. The power integrated circuit according to any one of the preceding claims, characterized in that: The low-side component of the main power device and / or the driver includes a plurality of two-dimensional electron gas channels arranged in parallel between the source terminal and the drain terminal of the main power device.

5. The power integrated circuit according to any one of the preceding claims, characterized in that: The low-side component of the driver includes one of a HEMT, a MOSFET, or a MISFET capable of functioning as a Miller clamp with a drain terminal connected to the gate terminal and a source connected to the source of the main power device, and The low-side component can be disposed near the main power device or inside the structure of the main power device.

6. The power integrated circuit according to any one of the preceding claims, characterized in that: The at least one low-side component of the driver includes a normally-on transistor or a normally-off transistor, or a parallel combination of a normally-on transistor and a normally-off transistor.

7. The power integrated circuit according to claim 4, wherein: The low-side component of the driver is configured to provide an increased high resistance when the low-side component of the driver is in an off-state and a decreased resistance when the low-side component of the driver is in an on-state.

8. The power integrated circuit according to claim 5, wherein: The low-side component of the driver includes the high electron mobility transistor, wherein the high electron mobility transistor includes a plurality of p+ gallium nitride islands arranged along a direction perpendicular to the direction of current flow between the source terminal and the drain terminal of the high electron mobility transistor, wherein each of the p+ gallium nitride islands is connected to the gate terminal of the high electron mobility transistor.

9. The power integrated circuit according to any one of the preceding claims, characterized in that: The gallium nitride chip includes one or more other two-dimensional electron gas low-power transistors connected to the main power device or the low-side component of the driver.

10. The power integrated circuit according to any one of the preceding claims, characterized in that: The at least one high-side component of the driver is configured as: a hole-conducting component; and / or a p-channel metal oxide semiconductor field effect transistor; and / or a bipolar NPN transistor.

11. The power integrated circuit according to any one of the preceding claims, characterized in that: The at least one high-side component of the driver is disposed in a first semiconductor material, and the at least one low-side component of the driver is disposed in a second semiconductor material, wherein the first semiconductor material and the second semiconductor material are different semiconductor materials.

12. The power integrated circuit according to claim 11, wherein: The at least one high-side component of the driver and the at least one low-side component of the driver function as complementary metal oxide semiconductor cells.

13. The power integrated circuit according to any one of the preceding claims, characterized in that: Another low-side component of the driver is arranged in parallel with the at least one low-side component of the driver and is disposed in the semiconductor region of the non-gallium nitride material.

14. The power integrated circuit according to claim 13, wherein: The other low-side component of the driver includes an n-channel metal oxide semiconductor field effect transistor, an n-channel junction field effect transistor, a PNP bipolar transistor or an NPN transistor, wherein a base terminal of the NPN transistor is additionally provided with an inverter.

15. A power integrated circuit, characterized in that: include: At least one heterojunction gallium nitride chip, comprising at least one gallium nitride layer and at least one aluminum gallium nitride layer, wherein the gallium nitride chip includes at least one main power device, the main power device including a source terminal, a drain terminal, a gate terminal, and a two-dimensional electron gas, wherein the two-dimensional electron gas is formed at the interface between the aluminum gallium nitride layer and the gallium nitride layer and is located between the source terminal and the drain terminal, wherein the gate terminal is configured to modulate at least a portion of the two-dimensional electron gas when a charge is applied to the gate terminal; a half-bridge circuit comprising a low-side main power device formed in the at least one gallium nitride chip and a high-side main power device formed in the at least one gallium nitride chip or in another gallium nitride chip; and A driver comprising a first pair and a second pair, wherein each pair comprises at least one low-side component and at least one high-side component, wherein the first pair is used to charge and discharge the input capacitance of the low-side main power device during the on-off process of the low-side main power device, wherein the second pair is used to charge and discharge the input capacitance of the high-side main power device during the on-off process of the low-side main power device, The driver further includes a level converter for converting the low voltage control of the first pair to the high voltage control of the second pair. Each of the at least one low-side component of the driver is formed in the gallium nitride chip or in the further gallium nitride chip, Each of the at least one high-side component of the driver is formed in a semiconductor region of a non-gallium nitride material.

16. A power integrated circuit, characterized in that: include: A plurality of heterojunction gallium nitride chips, wherein each gallium nitride chip includes at least one gallium nitride layer and at least one aluminum gallium nitride layer, wherein each of the gallium nitride chips includes at least one main power device, wherein the main power device includes a source terminal, a drain terminal, a gate terminal, and a two-dimensional electron gas, wherein the two-dimensional electron gas is formed at the interface between the aluminum gallium nitride layer and the gallium nitride layer and is located between the source terminal and the drain terminal, wherein the gate terminal is used to modulate at least a portion of the two-dimensional electron gas when a charge is applied to the gate terminal. Each of the gallium nitride chips includes a low-side component of a driver, The main power devices of the plurality of gallium nitride chips are connected in parallel; and A single companion silicon chip includes at least one high-side component of the driver, wherein the at least one high-side component of the driver is connected to the drain terminals of the low-side components of the main power devices of the plurality of gallium nitride chips and further connected to the gate terminals of the main power devices of the plurality of gallium nitride chips.

17. The power integrated circuit according to claim 16, wherein: The non-GaN semiconductor region includes a supporting silicon chip for one of complementary metal oxide semiconductor (CMOS) operation, high voltage complementary metal oxide semiconductor (HVCMOS) operation, bipolar complementary metal oxide semiconductor (BCMOS) operation, bipolar complementary metal oxide semiconductor (BCM) operation, and double diffused metal oxide semiconductor (DDMOS) operation.

18. The power integrated circuit according to claim 16 or 17, characterized in that: The single supporting silicon chip includes one or more of the following: Level converter; Logic circuits; Voltage stabilizer; Starter circuit; Bandgap reference; Current sensing, current amplification or transconductance circuits; Temperature sensing; Overcurrent and overtemperature protection circuits; Memory; Undervoltage lockout circuit; Slew rate control circuit; Electrostatic discharge protection device; as well as Pulse Width Modulation Controller.

19. The power integrated circuit according to any one of claims 1 to 14, characterized in that: The gallium nitride chip includes one or more current sensing devices or high-voltage current sensing switches for current sensing.

20. The power integrated circuit according to any one of claims 1 to 14 and claim 19, characterized in that: The semiconductor region of non-gallium nitride material is formed on a semiconductor substrate and is located below or near the heterojunction interface of the gallium nitride chip, wherein the substrate comprises silicon or silicon carbide material.

Images