Silicon-based micro-lens array anti-lateral-erosion ICP etching method and silicon-based micro-lens array anti-lateral-erosion ICP etching system

Abstract

The invention discloses an anti-lateral-erosion ICP etching method and system for a silicon-based micro-lens array, and relates to the technical field of micro-nano optical device manufacturing. The anti-lateral-erosion ICP etching method for the silicon-based micro-lens array comprises the following steps: performing dual-mode mask compensation based on the depth-to-width ratio of an etching vector height and a target bottom diameter and the size of a depth-to-width ratio threshold value; calculating a mask design bottom diameter based on linear compensation when the depth-to-width ratio is smaller than or equal to a depth-to-width ratio threshold value; calculating a mask design bottom diameter based on index correction when the depth-to-width ratio is greater than a depth-to-width ratio threshold value; adjusting a corresponding gas ratio based on the depth-to-width ratio at the current moment so as to reduce lateral erosion abrupt change; the control unit synchronously controls the pulse bias and the temperature of the silicon wafer stage so as to optimize thermal management in the etching process; the control unit adjusts a pulse bias parameter to minimize heat input; and the control unit controls the temperature of the silicon wafer stage based on the temperature control module to reduce thermal deformation of the photoresist. Through dual-mode mask compensation of a depth-to-width ratio threshold value, the design bottom diameter of the mask is accurately adjusted, and the influence of lateral erosion is reduced.

Description

Technical Field

[0001] The present application relates to the technical field of micro-nano optical device manufacturing, and in particular to a method and system for resisting side-etching ICP etching of a silicon-based microlens array. Background Art

[0002] Conventional ICP (Inductively Coupled Plasma) etching ( In the mixed gas), the neutral particle bombardment causes lateral etching of the sidewall of the photoresist mask, and the bottom diameter shrinkage rate of the 100μm feature size is large.

[0003] Pattern density sensitivity: When the pattern density increases from 20% to 80%, the etch depth uniformity decreases.

[0004] Thermally induced mask deformation: Local high temperature in the chamber causes thermal reflow of the photoresist, increasing the amount of mask edge collapse.

[0005] Among the existing technical solutions:

[0006] CN113611592A:Adopt Improve anisotropy, but the surface roughness Ra>10nm, not suitable for optical devices.

[0007] US20220301784A1: Using a hard mask It reduces side etching, but adds three photolithography steps, which increases costs. Summary of the Invention

[0008] To solve the above problems, the present application provides a silicon-based microlens array anti-side erosion ICP etching method, which uses dual-mode mask compensation of aspect ratio threshold to accurately adjust the mask design bottom diameter and reduce the impact of side erosion; correspondingly, a silicon-based microlens array anti-side erosion ICP etching system is proposed to implement silicon-based microlens array anti-side erosion ICP etching methods in different situations.

[0009] The first technical solution adopted in this application is to provide a method for ICP etching of a silicon-based microlens array to resist side etching, comprising the following steps: Dual-mode mask compensation is performed based on the aspect ratio of the etching sag and the target bottom diameter and the aspect ratio threshold; when the aspect ratio is less than or equal to the aspect ratio threshold, the mask design bottom diameter is calculated based on linear compensation; when the aspect ratio is greater than the aspect ratio threshold, the mask design bottom diameter is calculated based on exponential correction; Adjust the corresponding gas ratio based on the current aspect ratio to reduce the sudden change of side erosion; The control unit synchronously controls the pulse bias and the wafer stage temperature to optimize thermal management during the etching process; the control unit adjusts the pulse bias power, duty cycle, and frequency to minimize heat input; and the control unit controls the wafer stage temperature based on the temperature control module to reduce thermal deformation of the photoresist.

[0010] In an optional embodiment, the linear compensation calculation of the mask design bottom diameter is implemented based on the following formula: ; in, Design the bottom diameter for the mask, is the target bottom diameter, is the etching height.

[0011] In an optional embodiment, the index correction calculation of the mask design base diameter is implemented based on the following formula: ; in, is the bottom diameter of the mask design, and AR is the aspect ratio.

[0012] In an optional embodiment, an aspect ratio range threshold is set. If the aspect ratio at the current moment is greater than or equal to the aspect ratio threshold - the aspect ratio range threshold, and less than or equal to the aspect ratio threshold + the aspect ratio range threshold, the mask design bottom diameter is calculated using a linear compensation and an exponentially corrected weighted average.

[0013] In an optional embodiment, adjusting the corresponding gas ratio based on the current aspect ratio includes four stages: The first stage: the initial gas ratio is ; Stage 2: When the aspect ratio is greater than 0.1, switch to ; Stage 3: Switch to when the aspect ratio is greater than 0.3 ; Stage 4: The aspect ratio is greater than 0.3 and lasts for 5 minutes. .

[0014] In an optional embodiment, the plasma density of the pulse bias is > , the source power range is 800-1000W.

[0015] In an optional embodiment, the temperature control module controls the temperature of the wafer stage based on a porous electrostatic chuck in conjunction with a He gas microchannel.

[0016] In an optional embodiment, the control unit monitors the plasma state in real time through optical emission spectroscopy, and dynamically adjusts the pulse bias power, duty cycle, and frequency based on the plasma state.

[0017] The second technical solution adopted in this application is to provide a silicon-based microlens array anti-side erosion ICP etching system, which can be applied to the silicon-based microlens array anti-side erosion ICP etching method as described in any of the above items, including: a mask compensation design module, wherein the mask compensation design module selects a linear compensation or an exponential correction algorithm based on an aspect ratio threshold; A control unit, wherein the control unit adjusts the gas ratio based on the gas gradient control module; the control unit adjusts the pulse bias parameters based on the pulse bias generator; and the control unit controls the temperature of the wafer stage based on the temperature control module; A real-time monitoring module monitors the plasma state based on an optical emission spectrometer and feeds back the status to a control unit.

[0018] In an optional embodiment, the gas gradient control module includes an etching depth real-time monitoring unit and a three-channel mass flow controller, wherein the etching depth real-time monitoring unit is used to obtain the real-time etching depth and output a signal to the three-channel mass flow controller; the three-channel mass flow controller controls 、 and Gas flow rate.

[0019] Due to the adoption of the above technical solution, the present application has at least one of the following beneficial effects compared with the prior art:

[0020] 1. Through dual-mode mask compensation of aspect ratio threshold, the bottom diameter of the mask design is accurately adjusted to reduce the impact of side erosion.

[0021] 2. Multi-level gas gradient control combined with multi-source online monitoring closed-loop control system makes the etching rate more uniform and stable.

[0022] 3. A pulsed bias and temperature synergistic control mechanism is introduced to precisely control the wafer stage temperature based on a backside cooling structure. This effectively reduces thermal deformation of the photoresist caused by high temperatures.

[0023] 4. By precisely controlling the plasma density, source power, and pulse bias parameters, not only the etching quality and efficiency are improved, but also the roughness of the silicon surface is greatly optimized. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without inventive efforts. Among them: Figure 1A schematic diagram of a process for an ICP etching method for resisting side erosion of a silicon-based microlens array provided in one embodiment of the present application; Figure 2 A schematic diagram of an aspect ratio correction curve provided in one embodiment of the present application; Figure 3 A schematic diagram of a gas control timing sequence provided in one embodiment of the present application; Figure 4 A schematic diagram of the framework of a silicon-based microlens array anti-side erosion ICP etching system provided in one embodiment of the present application; Figure 5 for Figure 4 A schematic diagram of the framework of an embodiment of a gas gradient control module. DETAILED DESCRIPTION

[0025] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. It will be understood that the specific embodiments described herein are only used to explain the present application, rather than to limit the present application. It should also be noted that, for ease of description, only some, rather than all, structures related to the present application are shown in the drawings. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0026] The terms "first," "second," and the like in this application are used to distinguish between different objects, not to describe a particular order. Furthermore, the terms "including," "having," and any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or elements is not limited to the listed steps or elements, but may optionally include steps or elements not listed, or may optionally include other steps or elements inherent to the process, method, product, or apparatus.

[0027] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0028] Existing ICP etching process uses When etching silicon-based microlenses using mixed gases, random bombardment of plasma neutral particles causes lateral etching of the photoresist mask sidewalls. This can lead to shrinkage of feature dimensions. In view of this, the present application provides an ICP etching method for silicon-based microlens arrays to resist side etching. By using dual-mode mask compensation based on aspect ratio threshold, the mask design bottom diameter is precisely adjusted to reduce the impact of side etching. Figure 1 As shown, Figure 1 A schematic flow chart of a method for ICP etching of a silicon-based microlens array to resist side erosion provided in one embodiment of the present application includes the following steps:

[0029] S1: Dual-mode mask compensation is performed based on the aspect ratio of the etching sag and the target bottom diameter and the aspect ratio threshold; when the aspect ratio is less than or equal to the aspect ratio threshold, the mask design bottom diameter is calculated based on linear compensation; when the aspect ratio is greater than the aspect ratio threshold, the mask design bottom diameter is calculated based on exponential correction; the aspect ratio is the ratio of the etching sag to the target bottom diameter; Figure 2 As shown, Figure 2 A schematic diagram of an aspect ratio correction curve is provided for one embodiment of the present application. In this embodiment, the aspect ratio threshold is 0.3. It should be noted that in other embodiments, the aspect ratio threshold may be selected separately without any limitation.

[0030] When the aspect ratio is less than or equal to 0.3, the mask design base diameter is calculated based on linear compensation. The linear compensation calculation of the mask design base diameter is based on the following formula: ; in, Design the bottom diameter for the mask, is the target bottom diameter, is the etching height, is the linear proportional coefficient, is the exponent of the power term.

[0031] When the aspect ratio is greater than 0.3, the mask design base diameter is calculated based on the exponential correction. The exponential correction calculation of the mask design base diameter is based on the following formula: ; in, is the bottom diameter of the mask design, AR is the aspect ratio, , is the exponential proportional coefficient, is the decay constant.

[0032] To obtain a complete linear compensation calculation formula and exponential correction calculation, curve fitting is required. For example, in this embodiment, multiple sets of etching experiments are performed and multiple regression fitting is performed to determine the compensation parameters. The experimental data are shown in Table 1: .

[0033] The detailed steps of multivariate fitting are common knowledge to those skilled in the art and will not be repeated here. The compensation parameters obtained based on the above experimental data are as follows: α=0.27, β=1.25, γ=1.18, δ=4.8.

[0034] That is, the linear compensation calculation formula is as follows: .

[0035] The index correction calculation formula is as follows: .

[0036] The following describes the physical mechanism of why different compensation formulas are selected based on different aspect ratios. When the aspect ratio is ≤0.3, the vertical incidence of ions dominates, and the side erosion amount is in a power law relationship with the aspect ratio. ; When the aspect ratio is greater than 0.3, the side wall shadow effect is significant, and the ion incident angle is , the side corrosion shows an exponential saturation characteristic.

[0037] In another embodiment, an aspect ratio range threshold is further provided. If the aspect ratio at the current moment is greater than or equal to the aspect ratio threshold - the aspect ratio range threshold, and less than or equal to the aspect ratio threshold + the aspect ratio range threshold, the mask design bottom diameter is calculated using a linear compensation and an exponentially corrected weighted average. In this embodiment, the aspect ratio range threshold is 0.02. In other embodiments, the aspect ratio range threshold may be selected separately without any limitation.

[0038] The following describes in detail how different compensation formulas are selected based on different aspect ratios in this embodiment: When the aspect ratio is less than 0.28, the mask design bottom diameter is calculated based on the linear compensation calculation formula; When the aspect ratio is 0.28≤≤0.32, the mask design base diameter is calculated based on the weighted average of linear compensation and exponential correction. The specific calculation formula is as follows: ; in, Design the bottom diameter for the mask, is a linear scale, is the linear compensation calculation result, is an exponential ratio, This is the result of exponential compensation calculation.

[0039] In this embodiment: , , AR is the aspect ratio.

[0040] When the aspect ratio is greater than 0.32, the mask design bottom diameter is calculated based on the exponential correction calculation formula.

[0041] By setting the aspect ratio threshold and its range, and using the weighted average of linear compensation and exponential correction in the critical area to calculate the mask design bottom diameter, the most suitable compensation scheme can be found regardless of low or high aspect ratio, thereby improving the adaptability and flexibility of the entire process.

[0042] The two compensation mechanisms can dynamically adjust the mask design bottom diameter according to the specific etching conditions, ensuring high etching accuracy and consistency even in complex manufacturing processes; this not only reduces errors caused by side etching, but also improves product yield.

[0043] S2: Based on the current aspect ratio, adjust the corresponding gas ratio to reduce the side erosion mutation; Figure 3 As shown, Figure 3 A schematic diagram of a gas control timing sequence provided in an embodiment of the present application; in this embodiment, adjusting the corresponding gas ratio based on the current aspect ratio includes four stages:

[0044] The first stage: the initial gas ratio is The first stage is suitable for the initial stage of etching, when the depth-to-width ratio is small, and the main purpose is to begin to accurately form the basic outline of the microlens structure.

[0045] Stage 2: When the aspect ratio is greater than 0.1, switch to ; As the etching depth increases, adjusting the gas ratio helps maintain the verticality of the sidewall and reduce side erosion.

[0046] Stage 3: Switch to when the aspect ratio is greater than 0.3 Maintaining the stability and consistency of high aspect ratio structures is crucial, which can effectively inhibit side etching and ensure uniformity during the etching process.

[0047] Stage 4: The aspect ratio is greater than 0.3 and lasts for 5 minutes. ; Meet the special needs of long-term high aspect ratio conditions and ensure high-quality etching results even under extreme conditions.

[0048] By adjusting the gas ratio in stages, the side etching phenomenon can be more effectively controlled under different aspect ratios, especially for high aspect ratio structures, which significantly reduces the lateral erosion of the side walls and improves the etching accuracy; the appropriate gas ratio not only helps to accelerate the etching process, but also improves the quality of the etched surface, reduces the roughness, and makes the optical performance of the final product even better.

[0049] S3: The control unit synchronously controls the pulse bias and wafer stage temperature to optimize thermal management during the etching process. The control unit adjusts the pulse bias power, duty cycle, and frequency to minimize heat input. In this embodiment, the peak power density of the pulsed polarization power is approximately 2.5 W / cm², the frequency is 10 kHz, and the duty cycle is adjustable between 20% and 30%. The control unit controls the wafer stage temperature based on the temperature control module to ensure a stable wafer stage temperature throughout the etching process, thereby reducing thermal deformation of the photoresist caused by temperature changes.

[0050] By precisely adjusting the parameters of the pulse bias, the heat input can be effectively controlled, local overheating can be avoided, and material damage or quality degradation caused by high temperature can be reduced. The ability to dynamically adjust the pulse bias and temperature allows the process to flexibly respond to different etching requirements, enhancing the processing capabilities of various complex structures and materials, and improving production efficiency and product yield.

[0051] Pulse bias plasma density> , maintain plasma density> It helps to improve the etching rate and anisotropy, ensuring the formation of fine structures; high-density plasma can remove materials more efficiently while reducing the impact on surrounding areas.

[0052] Source power ranges from 800-1000W; power levels can be adjusted to optimize etch rate and uniformity based on specific process requirements.

[0053] The temperature control module controls the temperature of the wafer stage based on a porous electrostatic chuck and He gas microchannels. A porous electrostatic chuck is installed as the base of the wafer stage. The chuck has multiple tiny holes that allow He gas to flow to achieve a cooling effect. A He gas microchannel network is set up inside the electrostatic chuck to ensure that the He gas can be evenly distributed and flow under the entire chuck surface, thereby effectively removing heat.

[0054] The integrated temperature sensor and control system monitors the temperature of the wafer stage in real time and adjusts the He gas flow or the working status of the electrostatic chuck as needed to maintain the set temperature range (e.g., -10°C to +10°C).

[0055] The control unit monitors the plasma state in real time through optical emission spectroscopy and dynamically adjusts the pulse bias power, duty cycle, and frequency based on the plasma state. The initial settings for the pulse bias power range are 800-1000W, the frequency is 10kHz, and the duty cycle is 20%-30%. For example, when the F / Cl intensity ratio is greater than 1.2, the pulse duty cycle is automatically increased to 30%, which helps minimize heat input and reduce the impact on the photoresist.

[0056] By monitoring the F / Cl intensity ratio in real time, the plasma state and its impact on the material can be accurately determined. Dynamic adjustment of pulse bias parameters effectively controls heat input, avoiding localized overheating and minimizing material damage or quality degradation caused by high temperatures.

[0057] In summary, the ICP etching method for silicon-based microlens arrays to resist side etch includes the following steps: dual-mode mask compensation based on the aspect ratio of the etching sag and target base diameter relative to the aspect ratio threshold; linear compensation calculation of the mask design base diameter when the aspect ratio is less than or equal to the aspect ratio threshold; exponential correction calculation of the mask design base diameter when the aspect ratio is greater than the aspect ratio threshold; adjustment of the corresponding gas ratio based on the current aspect ratio to reduce sudden side etch; a control unit synchronously controlling the pulse bias and wafer stage temperature to optimize thermal management during the etching process; adjustment of the pulse bias power, duty cycle, and frequency to minimize heat input; and control of the wafer stage temperature using a temperature control module to reduce thermal deformation of the photoresist. Through dual-mode mask compensation based on the aspect ratio threshold, the mask design base diameter is precisely adjusted to reduce the impact of side etch.

[0058] The present application also provides a silicon-based microlens array anti-side erosion ICP etching system, which can be applied to the silicon-based microlens array anti-side erosion ICP etching method of any of the above embodiments; Figure 4 As shown, Figure 4 A schematic diagram of a framework of a silicon-based microlens array anti-side erosion ICP etching system provided in one embodiment of the present application includes: Mask compensation design module, which selects linear compensation or exponential correction algorithm based on aspect ratio threshold; The control unit adjusts the gas ratio based on the gas gradient control module; the control unit adjusts the pulse bias parameters based on the pulse bias generator; and the control unit controls the temperature of the silicon wafer stage based on the temperature control module; The real-time monitoring module monitors the plasma state based on an optical emission spectrometer and feeds back to the control unit.

[0059] like Figure 5 As shown, Figure 5 for Figure 4 A schematic diagram of a framework of an embodiment of a gas gradient control module, comprising an etching depth real-time monitoring unit and a three-channel mass flow controller, wherein the etching depth real-time monitoring unit is used to obtain the real-time etching depth and output a signal to the three-channel mass flow controller; the three-channel mass flow controller controls 、 and Gas flow rate.

[0060] In the several embodiments provided in this application, it should be understood that the disclosed methods and devices can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the modules or units is merely a logical functional division. In actual implementation, other division methods may be used, such as combining or integrating multiple units or components into another system, or ignoring or not implementing certain features.

[0061] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of this embodiment.

[0062] In addition, each functional unit in each embodiment of the present application may be integrated into a processing unit, each unit may exist physically separately, or two or more units may be integrated into a single unit. The above-mentioned integrated units may be implemented in the form of hardware or software functional units.

[0063] The above description is only an implementation method of the present application and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the description and drawings of this application, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A method for ICP etching of silicon-based microlens arrays to resist side etching, characterized in that: The steps include: Dual-mode mask compensation is performed based on the aspect ratio of the etching sag and the target bottom diameter and the aspect ratio threshold; when the aspect ratio is less than or equal to the aspect ratio threshold, the mask design bottom diameter is calculated based on linear compensation; When the aspect ratio is greater than the aspect ratio threshold, calculating the mask design bottom diameter based on the exponential correction; Adjust the corresponding gas ratio based on the current aspect ratio to reduce the sudden change of side erosion; The control unit synchronously controls the pulse bias and the wafer stage temperature to optimize thermal management during the etching process; the control unit adjusts the pulse bias power, duty cycle, and frequency to minimize heat input; and the control unit controls the wafer stage temperature based on the temperature control module to reduce thermal deformation of the photoresist.

2. The method for ICP etching of silicon-based microlens array to resist side etching according to claim 1, characterized in that: The linear compensation calculation of the mask design bottom diameter is implemented based on the following formula: ； in, Design the bottom diameter for the mask, is the target bottom diameter, is the etching height.

3. The method for ICP etching of silicon-based microlens array to resist side etching according to claim 2, characterized in that: The index correction calculation of the mask design bottom diameter is based on the following formula: ； in, is the bottom diameter of the mask design, and AR is the aspect ratio.

4. The method for ICP etching of silicon-based microlens array to resist side etching according to claim 3, characterized in that: An aspect ratio range threshold is set. If the aspect ratio at the current moment is greater than or equal to the aspect ratio threshold - the aspect ratio range threshold, and less than or equal to the aspect ratio threshold + the aspect ratio range threshold, the mask design base diameter is calculated using a weighted average of linear compensation and exponential correction.

5. The ICP etching method for resisting side erosion of a silicon-based microlens array according to claim 1, characterized in that: The gas ratio corresponding to the current aspect ratio adjustment includes four stages: The first stage: the initial gas ratio is ; Stage 2: When the aspect ratio is greater than 0.1, switch to ; Stage 3: Switch to when the aspect ratio is greater than 0.3 ; Stage 4: The aspect ratio is greater than 0.3 and lasts for 5 minutes. .

6. The ICP etching method for resisting side erosion of a silicon-based microlens array according to claim 1, characterized in that: The plasma density of the pulse bias> , the source power range is 800-1000W.

7. The ICP etching method for resisting side erosion of a silicon-based microlens array according to claim 1, characterized in that: The temperature control module controls the temperature of the silicon wafer stage based on a porous electrostatic chuck and a He gas microchannel.

8. The ICP etching method for resisting side erosion of a silicon-based microlens array according to claim 1, characterized in that: The control unit monitors the plasma state in real time through optical emission spectroscopy and dynamically adjusts the pulse bias power, duty cycle and frequency based on the plasma state.

9. A silicon-based microlens array anti-side erosion ICP etching system, applicable to the silicon-based microlens array anti-side erosion ICP etching method according to any one of claims 1 to 8, characterized in that: include: a mask compensation design module, wherein the mask compensation design module selects a linear compensation or an exponential correction algorithm based on an aspect ratio threshold; A control unit, which adjusts the gas ratio based on the gas gradient control module; The control unit adjusts the pulse bias parameters based on the pulse bias generator; the control unit controls the temperature of the wafer stage based on the temperature control module; A real-time monitoring module monitors the plasma state based on an optical emission spectrometer and feeds back the status to a control unit.

10. The silicon-based microlens array anti-side erosion ICP etching system according to claim 9, characterized in that: The gas gradient control module includes an etching depth real-time monitoring unit and a three-channel mass flow controller, wherein the etching depth real-time monitoring unit is used to obtain the real-time etching depth and output a signal to the three-channel mass flow controller; the three-channel mass flow controller 、 and Gas flow rate.

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