Planar optical waveguide type laser beam combiner chip for encoder

Abstract

The invention discloses a planar optical waveguide type laser beam combiner chip for an encoder, and relates to the technical field of optoelectronic devices and integrated optics. The beam combining efficiency is gt; the wavelength compatibility covers the visible light band to the near-infrared band; the chip size is lt; 5 * 5mm < 2 > and can be directly packaged in an encoder probe; the device supports on-line wavelength tuning, adapts to encoders with different precision levels (the resolution is 1-1nm), and solves the problems of volume, efficiency and stability of laser beam combination in the encoders.

Description

Technical Field

[0001] The present invention relates to the technical field of optoelectronic devices and integrated optics, and in particular to a planar optical waveguide laser beam combiner chip for an encoder. Background Art

[0002] A laser beam combiner is a device that combines multiple laser beams into a single high-power beam. It has a wide range of applications, including scientific research, industrial processing, and medical surgery. Laser beam combiners operate on two main principles: spectral beam combining and spatial beam combining. Spectral beam combining achieves power superposition by adjusting the wavelengths of the lasers to achieve spectral overlap, while spatial beam combining achieves power superposition by focusing multiple laser beams onto a single point using an optical system.

[0003] Traditional laser beam combiners (such as prisms and fiber couplers) are bulky and difficult to integrate, making them difficult to meet the needs of miniaturized encoders. Existing integrated optical waveguide combiners have problems such as high insertion loss and poor multi-wavelength compatibility, which leads to a decrease in the signal-to-noise ratio of the encoder signal. The process is complex and costly. For example, silicon photonics-based combiners require deep ultraviolet lithography and have a low yield. To this end, we propose a planar optical waveguide laser beam combiner chip for encoders. Summary of the Invention

[0004] The purpose of the present invention is to solve the problems mentioned in the above background technology. The present invention provides a planar optical waveguide laser combiner chip for an encoder.

[0005] In order to achieve the above-mentioned purpose, the present invention specifically adopts the following technical solutions:

[0006] A planar optical waveguide laser beam combiner chip for an encoder, comprising: a chip,

[0007] The chip includes:

[0008] Input / output waveguide array: adopts asymmetric tapered waveguide design, with input end width of 5μm and output end width of 2μm;

[0009] Multimode interference combining area: the optimized length is Where W is the waveguide width and λ is the laser wavelength;

[0010] Anti-reflection layer: SiO2 / Ta2O5 multilayer film (refractive index gradient 1.45 to 2.1) is plated on the output end to suppress echo reflection to below -50dB.

[0011] Furthermore, the size of the chip is <5×5mm 2 .

[0012] Furthermore, the chip adopts a double-layer structure of waveguide material SiO2 / SiON, wherein the upper cladding SiO2 is 3 μm thick, the core SiON is 1.2 μm thick, and the refractive index difference Δ=1.5%, which is compatible with CMOS technology.

[0013] Furthermore, the core layer refractive index of the waveguide material is 1.52, and the cladding layer refractive index is 1.46.

[0014] Furthermore, the chip manufacturing process includes the following steps:

[0015] A1. Photolithography, forming waveguide patterns through photolithography;

[0016] A2, Reactive Ion Etching: A high-frequency power supply ionizes the gas to generate ions and free radicals. The electric field accelerates the ions to form a high-speed beam. The ion beam reacts physically or chemically with the material surface to remove the target substance.

[0017] A3, PECVD cladding deposition, on a 4-inch silicon substrate, a 3-μm-thick SiO2 lower cladding layer was deposited by PECVD, and a 1.2-μm-thick SiON core layer was deposited by reactive sputtering;

[0018] A4. Electrode integration: After depositing the upper cladding layer, Cr / Au thermal tuning electrodes are deposited by electron beam evaporation.

[0019] Furthermore, the waveguide pattern in the photolithography has a line width of 2-5 μm and a side wall roughness of <10 nm.

[0020] Furthermore, the thermal tuning electrode in the electrode integration adopts a serpentine layout, has a width of 50 μm, a resistance value of 10 Ω, and a tuning sensitivity of 0.1 nm / mV.

[0021] The beneficial effects of the present invention are as follows:

[0022] The beam combining efficiency of the present invention is greater than 95%, and the wavelength compatibility covers the visible light to near infrared band; the chip size is less than 5×5mm 2 , can be directly encapsulated inside the encoder probe; supports online wavelength tuning, adapts to encoders of different accuracy levels (resolution 1μm~1nm), and solves the volume, efficiency and stability problems of laser beam combining in the encoder. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a schematic diagram of the three-dimensional structure of the chip in the present invention;

[0024] Figure 2 is a schematic diagram of the waveguide cross-section and mode field distribution simulation results in the present invention;

[0025] Figure 3 It is a manufacturing process flow chart of the present invention;

[0026] Figure 4 It is a three-dimensional schematic diagram of the measured insertion loss (<0.5dB) and wavelength tuning range (±15nm) curve of the present invention. DETAILED DESCRIPTION

[0027] To make the objectives, technical solutions and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0028] See also Figure 1 - Figure 4 The present invention provides a planar optical waveguide laser beam combiner chip for an encoder, comprising: a chip,

[0029] The chips include:

[0030] Input / output waveguide array: adopts asymmetric tapered waveguide design, with the input waveguide (N channels) width gradually changing from 5μm to 2μm, reducing mode field mismatch loss;

[0031] Multimode interference combining area: the optimized length is Where W is the waveguide width and λ is the laser wavelength; it supports TE / TM dual-polarization mode combining.

[0032] By jointly optimizing the tapered waveguide and the multimode interference combining area, a combining efficiency of over 95% is achieved, with a measured wavelength range of 630-850nm.

[0033] Anti-reflection layer: SiO2 / Ta2O5 multilayer film (refractive index gradient 1.45 to 2.1) is plated on the output end to suppress echo reflection to below -50dB.

[0034] The integrated tunable grating (period Λ = 310nm) adjusts the output wavelength through the thermode to adapt to different encoder resolution requirements. The built-in tunable grating supports dynamic wavelength matching and adapts to the encoder's multiple working modes.

[0035] In this embodiment, preferably, the chip size is less than 5×5 mm 2 ; Can be directly packaged inside the encoder probe.

[0036] In this embodiment, preferably, the chip adopts a double-layer structure of waveguide material SiO2 / SiON, wherein the upper cladding SiO2 is 3 μm thick, the core SiON is 1.2 μm thick, the refractive index difference Δ=1.5%, and it is compatible with CMOS process; the SiON material system is used to reduce the transmission loss to below 0.1 dB / cm, and is compatible with wafer-level batch manufacturing.

[0037] In this embodiment, preferably, the refractive index of the core layer of the waveguide material is 1.52, and the refractive index of the cladding layer is 1.46.

[0038] The beam combining efficiency is >95%, and the wavelength compatibility covers the visible light to near-infrared band; it supports online wavelength tuning and is compatible with encoders of different precision levels (resolution 1μm to 1nm).

[0039] In this embodiment, preferably, the chip manufacturing process includes the following steps:

[0040] A1. Photolithography, forming waveguide patterns through photolithography;

[0041] A2, Reactive Ion Etching: A high-frequency power supply ionizes the gas to generate ions and free radicals. The electric field accelerates the ions to form a high-speed beam. The ion beam reacts physically or chemically with the material surface to remove the target substance.

[0042] A3, PECVD cladding deposition, on a 4-inch silicon substrate, a 3-μm-thick SiO2 lower cladding layer was deposited by PECVD, and a 1.2-μm-thick SiON core layer was deposited by reactive sputtering;

[0043] A4. Electrode integration: After depositing the upper cladding layer, Cr / Au thermal tuning electrodes are deposited by electron beam evaporation.

[0044] Test Verification

[0045] The three-wavelength laser inputs (650nm / 785nm / 850nm) were used, and the beam combining efficiencies measured using an integrating sphere power meter were 96.2%, 94.7%, and 93.1%, respectively.

[0046] Applying a 0-5V voltage to the thermode, the output wavelength linearly drifts Δλ=0.1nm / mV, meeting the encoder dynamic calibration requirements.

[0047] In this embodiment, preferably, the line width of the waveguide pattern in the photolithography is 2-5 μm, and the side wall roughness is less than 10 nm.

[0048] In this embodiment, preferably, the thermal tuning electrode in the electrode integration adopts a serpentine layout, has a width of 50 μm, a resistance value of 10 Ω, and a tuning sensitivity of 0.1 nm / mV.

[0049] The working principle and use process of the present invention:

[0050] Chip size <5×5mm 2 ; Can be directly packaged inside the encoder probe.

[0051] The chip uses a double-layer SiO2 / SiON waveguide material structure, in which the upper cladding SiO2 is 3μm thick and the core SiON is 1.2μm thick, with a refractive index difference of Δ=1.5%, which is compatible with CMOS technology. The use of the SiON material system reduces transmission loss to below 0.1dB / cm and is compatible with wafer-level batch manufacturing.

[0052] The core refractive index of the waveguide material is 1.52, and the cladding refractive index is 1.46.

[0053] The beam combining efficiency is >95%, and the wavelength compatibility covers the visible light to near-infrared band; it supports online wavelength tuning and is compatible with encoders of different precision levels (resolution 1μm to 1nm).

[0054] Input / output waveguide array: adopts asymmetric tapered waveguide design, with the input waveguide (N channels) width gradually changing from 5μm to 2μm, reducing mode field mismatch loss;

[0055] Multimode interference combining area: the optimized length is Where W is the waveguide width and λ is the laser wavelength; it supports TE / TM dual-polarization mode combining.

[0056] By jointly optimizing the tapered waveguide and the multimode interference combining area, a combining efficiency of over 95% is achieved, with a measured wavelength range of 630-850nm.

[0057] Anti-reflection layer: SiO2 / Ta2O5 multilayer film (refractive index gradient 1.45 to 2.1) is plated on the output end to suppress echo reflection to below -50dB.

[0058] The integrated tunable grating (period Λ = 310nm) adjusts the output wavelength through the thermode to adapt to different encoder resolution requirements. The built-in tunable grating supports dynamic wavelength matching and adapts to the encoder's multiple working modes.

[0059] The chip manufacturing process includes the following steps:

[0060] A1. Photolithography: Waveguide patterns are formed through photolithography; the waveguide pattern line width is 2-5μm, and the sidewall roughness is less than 10nm. A2. Reactive Ion Etching: A high-frequency power source ionizes the gas to generate ions and free radicals. The electric field accelerates the ions to form a high-speed beam, which physically or chemically interacts with the material surface to remove the target substance.

[0061] A3, PECVD cladding deposition, on a 4-inch silicon substrate, a 3-μm-thick SiO2 lower cladding layer was deposited by PECVD, and a 1.2-μm-thick SiON core layer was deposited by reactive sputtering;

[0062] A4. Electrode integration: After depositing the upper cladding layer, Cr / Au thermal tuning electrodes are deposited by electron beam evaporation. The thermal tuning electrodes in the electrode integration adopt a serpentine layout with a width of 50μm, a resistance of 10Ω, and a tuning sensitivity of 0.1nm / mV.

[0063] Test Verification

[0064] The three-wavelength laser inputs (650nm / 785nm / 850nm) were used, and the beam combining efficiencies measured using an integrating sphere power meter were 96.2%, 94.7%, and 93.1%, respectively.

[0065] Applying a 0-5V voltage to the thermode, the output wavelength linearly drifts Δλ=0.1nm / mV, meeting the encoder dynamic calibration requirements.

[0066] The above description of the disclosed embodiments is intended to enable one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not limited to the embodiments shown herein but is intended to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A planar optical waveguide laser beam combiner chip for an encoder, characterized in that: include: A chip, comprising: Input / output waveguide array: adopts asymmetric tapered waveguide design, with input end width of 5μm and output end width of 2μm; Multimode interference combining area: the optimized length is Where W is the waveguide width and λ is the laser wavelength; Anti-reflection layer: SiO2 / Ta2O5 multilayer film (refractive index gradient 1.45 to 2.1) is plated on the output end to suppress echo reflection to below -50dB.

2. The planar optical waveguide laser beam combiner chip for an encoder according to claim 1, characterized in that: The size of the chip is <5×5mm 2 .

3. The planar optical waveguide laser beam combiner chip for an encoder according to claim 1, characterized in that: The chip adopts a double-layer structure of waveguide material SiO2 / SiON, wherein the upper cladding SiO2 is 3 μm thick, the core SiON is 1.2 μm thick, and the refractive index difference Δ=1.5%, which is compatible with CMOS technology.

4. The planar optical waveguide laser beam combiner chip for an encoder according to claim 1, characterized in that: The core layer refractive index of the waveguide material is 1.52, and the cladding layer refractive index is 1.

46.

5. The planar optical waveguide laser beam combiner chip for an encoder according to claim 1, characterized in that: The chip manufacturing process includes the following steps: A1. Photolithography, forming waveguide patterns through photolithography; A2, Reactive Ion Etching: A high-frequency power supply ionizes the gas to generate ions and free radicals. The electric field accelerates the ions to form a high-speed beam. The ion beam reacts physically or chemically with the material surface to remove the target substance. A3, PECVD cladding deposition, on a 4-inch silicon substrate, a 3-μm-thick SiO2 lower cladding layer was deposited by PECVD, and a 1.2-μm-thick SiON core layer was deposited by reactive sputtering; A4. Electrode integration: After depositing the upper cladding layer, Cr / Au thermal tuning electrodes are deposited by electron beam evaporation.

6. The planar optical waveguide laser beam combiner chip for an encoder according to claim 5, characterized in that: The waveguide pattern in the photolithography has a line width of 2-5 μm and a side wall roughness of <10 nm.

7. The planar optical waveguide laser beam combiner chip for an encoder according to claim 5, characterized in that: The thermal tuning electrode in the electrode integration adopts a serpentine layout, has a width of 50 μm, a resistance value of 10 Ω, and a tuning sensitivity of 0.1 nm / mV.

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