Construction method of OPC model, method for obtaining mask pattern, and related device

Abstract

The application belongs to the technical field of semiconductors, and provides an OP C model construction method, a mask layout acquisition method and related equipment. The OP C model construction method of the application classifies wafer patterns according to imaging contrast, filters out wafer patterns whose imaging contrast does not meet preset requirements, and uses CDSEM images of the wafer patterns and test layout for overlay, so that the feature size of the wafer pattern consistent with the alignment mark position of the test layout is accurately and quickly obtained as a calibration feature size. The calibration feature size obtained by this method is more accurate relative to the original feature size, and is used for constructing an OP C model, so that the accuracy of the OP C model can be improved.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology and relates to a method for constructing an optical proximity correction (OPC) model, a method for acquiring a mask pattern, and related equipment. Background Art

[0002] With the continuous development of the integrated circuit industry, demands for chip performance are increasing, driving continuous improvements in chip manufacturing processes, decreasing linewidths, and increasing chip structure complexity. As linewidths continue to decrease, from micron- to nanometer-scale dimensions, optical diffraction behavior during the photolithography process intensifies, leading to a widening discrepancy between the layout and the wafer pattern formed after the layout is developed. Therefore, optical proximity effect correction based on OPC models has gained widespread application at process nodes below 90nm. The OPC model construction method primarily involves collecting the critical dimensions (CD) of the wafer pattern formed after developing a test layout, establishing an initial OPC model, and then using the test layout as input. The initial OPC model is then simulated under a specified process using rigorous physical optics and chemical photoresist simulations. The model parameters are calibrated based on the difference between the feature dimensions of the simulated pattern and the actual feature dimensions of the collected wafer pattern. When the feature dimensions of the simulated pattern match those of the actual wafer pattern, the OPC model for that process is successfully established. Among them, the characteristic dimensions of wafer patterns are collected mainly through a critical dimension scanning electron microscope (CDSEM).

[0003] CDSEM mainly determines the boundary of the wafer pattern based on the grayscale of the image, and then obtains the size of the line width. According to the measurement mode of CDSEM, the contour of the periodic two-dimensional (2D) pattern after exposure and development is usually measured in Max (maximum) or Min (minimum) measurement mode, that is, the maximum or minimum position of the actual measured contour line width. However, due to the low Normalized Image Log-Slope (NILS) of the 2D pattern and poor imaging contrast, the measurement position when measuring the characteristic size of the wafer pattern does not correspond to the alignment mark (gauge) position on the test layout. For example, Figure 1 The measurement position in (a) is lower than the gauge position. Figure 1The middle (b) measurement position is lower than the gauge position, so that the feature size of the collected wafer pattern is inaccurate, which reduces the accuracy of the constructed OPC model, affects the prediction accuracy of the OPC model on the 2D pattern, and finally affects the product yield.

[0004] Currently, the industry calibrates the OPC model by threshold, but in actual operation, the threshold still needs human judgment of the specification (spec), so that the effect is only from the first-order human judgment to the high-order human judgment, and the problem of low accuracy of the OPC model cannot be fundamentally solved. SUMMARY

[0005] In order to solve the problem of low accuracy of the OPC model in the prior art, the application provides a method for constructing an OPC model, a method for obtaining a mask pattern, and related equipment.

[0006] The application is implemented by the following technical solutions:

[0007] In a first aspect, the application provides a method for constructing an OPC model, comprising:

[0008] Obtaining CDSEM images and original feature sizes corresponding to a plurality of wafer patterns, respectively; the wafer pattern is a pattern formed on a wafer after testing a mask pattern; the original feature size refers to a feature size measured by a CDSEM;

[0009] Selecting wafer patterns with imaging contrast not meeting a preset requirement from all wafer patterns as calibration wafer patterns, and the remaining wafer patterns as non-calibration wafer patterns, and the CDSEM image corresponding to the calibration wafer pattern as a CDSEM image to be processed;

[0010] Superimposing the CDSEM image to be processed and the test mask pattern to obtain a feature size of the CDSEM image to be processed at a position corresponding to the alignment mark position of the test mask pattern as a calibration feature size of the calibration wafer pattern;

[0011] Constructing an initial OPC model, calibrating the model parameters of the initial OPC model according to the calibration feature size of the calibration wafer pattern and the original feature size of the non-calibration wafer pattern, and obtaining an OPC model.

[0012] Preferably, the calibration wafer pattern is selected from all wafer patterns with imaging contrast not meeting a preset requirement, and specifically:

[0013] Calculate the NILS of all wafer patterns and select wafer patterns with NILS less than the preset NILS standard value as the wafer patterns to be calibrated.

[0014] Furthermore, the NILS of all wafer patterns is calculated by taking the test pattern and the light source information used in the lithography as input, performing optical simulation using an optical simulation model, and obtaining the NILS of each wafer pattern.

[0015] Preferably, the CDSEM image to be processed is superimposed on the test layout to obtain the characteristic size of the CDSEM image to be processed at a position corresponding to the alignment mark position of the test layout, specifically:

[0016] Extract the contour of the CDSEM image to be processed;

[0017] Overlaying the outline of the CDSEM image to be processed with the test pattern;

[0018] Extracting the alignment mark positions of the test layout, and matching the alignment mark positions to corresponding positions of the outline of the CDSEM image to be processed;

[0019] The characteristic size of the contour of the CDSEM image to be processed at the corresponding position is extracted.

[0020] Furthermore, the outline of the CDSEM image to be processed is superimposed on the test pattern, specifically:

[0021] S1, identifies the one-dimensional and two-dimensional regions of the test layout;

[0022] S2, overlaying the outline of the CDSEM image to be processed with the test pattern according to the one-dimensional region and the two-dimensional region;

[0023] S3, obtaining edge placement errors of the one-dimensional region and the two-dimensional region after overlay;

[0024] S4, calculating the evaluation function based on the edge placement error. If the evaluation function is less than the preset function value, the overlay is completed, otherwise return to S2.

[0025] Preferably, the model parameters of the initial OPC model are calibrated according to the calibration feature size of the wafer pattern to be calibrated and the original feature size of the non-calibrated wafer pattern to obtain the OPC model, specifically:

[0026] The test layout is simulated using an initial OPC model to obtain multiple simulated patterns and feature sizes of the simulated patterns that correspond one-to-one to the wafer patterns. Based on the differences between the feature sizes of the simulated patterns and the calibrated feature sizes of the wafer patterns to be calibrated and the original feature sizes of the non-calibrated wafer patterns, the model parameters of the OPC model are calibrated until the preset convergence conditions are met to obtain the OPC model.

[0027] In a second aspect, the present invention provides an OPC model construction system, comprising:

[0028] A data acquisition module is used to obtain CDSEM images and original feature sizes corresponding to a plurality of wafer patterns; the wafer patterns are patterns formed on the wafer after photolithography of the test pattern; the original feature sizes refer to the feature sizes measured by CDSEM;

[0029] A screening module is used to screen out wafer patterns whose imaging contrast does not meet the preset requirements from all wafer patterns, and use them as wafer patterns to be calibrated. The remaining wafer patterns are non-calibrated wafer patterns, and the CDSEM images corresponding to the wafer patterns to be calibrated are used as CDSEM images to be processed.

[0030] A size calibration module is used to overlay the CDSEM image to be processed with the test layout to obtain the feature size of the CDSEM image to be processed at a position corresponding to the alignment mark position of the test layout as the calibration feature size of the wafer pattern to be calibrated;

[0031] The OPC model building module is used to build an initial OPC model, and calibrate the model parameters of the initial OPC model according to the calibration feature size of the wafer pattern to be calibrated and the original feature size of the non-calibrated wafer pattern to obtain the OPC model.

[0032] In a third aspect, the present invention provides a computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the OPC model construction method as described above when executing the computer program.

[0033] In a fourth aspect, the present invention provides a computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the steps of the method for constructing an OPC model as described above.

[0034] In a fifth aspect, the present invention provides a method for obtaining a mask pattern, comprising:

[0035] Get the map;

[0036] Performing optical proximity effect correction on the layout using an OPC model to obtain a mask pattern;

[0037] The OPC model is constructed using the OPC model construction method described above.

[0038] Compared with the prior art, the present invention has the following beneficial effects:

[0039] The method for constructing an OPC model of the present invention screens and classifies wafer graphics according to imaging contrast, and screens out wafer graphics whose imaging contrast does not meet preset requirements. Since the imaging contrast of these screened wafer graphics does not meet the preset requirements, the accuracy of the original feature size obtained by directly measuring them using CDSEM is low; if the original feature size of these wafer graphics is directly used to construct the OPC model, the accuracy of the OPC model will be reduced. Therefore, the present invention does not use the original feature size of these wafer graphics to construct the OPC model, but instead uses the CDSEM images of these wafer graphics to overlay with the test layout, accurately and quickly obtaining the feature size of the wafer graphics that is consistent with the alignment mark position of the test layout, as the calibration feature size. The calibration feature size obtained by this method is more accurate than the original feature size, and is used to construct the OPC model, which can improve the accuracy of the OPC model. For wafer graphics whose imaging contrast meets the preset requirements, the original feature size obtained by directly measuring them using CDSEM is more accurate and can be directly used to construct the OPC model. The method of the present invention is fully automated and has no risks caused by human intervention. The constructed OPC model greatly improves the prediction ability of 2D graphics and reduces labor costs and time costs while improving accuracy.

[0040] Furthermore, the present invention selects NILS as an indicator for evaluating imaging contrast because NILS can be obtained by calculation and is an absolute value after normalization, making it relatively easy to preset the NILS standard value. Other indicators that can reflect imaging contrast are not easy to calculate through formulas, and it is not easy to preset the NILS standard value.

[0041] Furthermore, the present invention uses an optical simulation model to obtain accurate NILS of wafer patterns, which is more efficient and has a higher accuracy of the obtained NILS.

[0042] Furthermore, when the present invention overlays the outline of the CDSEM image to be processed with the test layout, an evaluation function is calculated based on the edge placement error, and the degree of overlay between the outline of the CDSEM image to be processed and the test layout is evaluated by the evaluation function. According to the decreasing tendency of the evaluation function, the degree of overlay can be improved, thereby ensuring that a more accurate feature size can be obtained subsequently, avoiding the problem of manual adjustment.

[0043] The OPC model constructed by the method of the present invention is used to correct the optical proximity effect of the layout, and the correction accuracy is higher, so that the obtained mask pattern is more accurate. It is used in the manufacture of masks and semiconductors, which can reduce the expenditure cost of masks, promote research and development progress, and improve product yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0045] Figure 1 Schematic diagram of direct measurement of feature size using critical dimension electron microscopy;

[0046] Figure 2 A flow chart for obtaining the calibration feature size of a wafer pattern to be calibrated according to the present invention;

[0047] Figure 3 A schematic diagram of obtaining the calibration feature size of a wafer pattern to be calibrated according to the present invention;

[0048] Figure 4 Schematic diagram of overlaying the outline of the CDSEM image to be processed with the test pattern of the present invention;

[0049] Figure 5 CDSEM images and NILS data of a portion of the wafer pattern in the concave pattern in Example 1 of the present invention;

[0050] Figure 6 CDSEM images and NILS data of a portion of the wafer pattern in the convex pattern of Example 1 of the present invention;

[0051] Figure 7 The error data between the characteristic size of the simulated pattern obtained by simulating the OPC model constructed by the present invention in Example 2 and the characteristic size of the corresponding wafer pattern;

[0052] Figure 8 This is the error data between the characteristic size of the simulated pattern obtained by simulating the OPC model calibrated by the threshold method in Example 2 and the characteristic size of the corresponding wafer pattern. DETAILED DESCRIPTION

[0053] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0054] It should be noted that the process equipment or devices not specifically specified in the following embodiments are all conventional equipment or devices in the art.

[0055] It should be noted that the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products, or apparatuses. Furthermore, unless otherwise specified, the numbering of each method step is merely a convenient tool for identifying each method step, and is not intended to limit the order of arrangement of each method step or to define the scope of the invention. Changes or adjustments to their relative relationships, without substantially changing the technical content, should also be considered within the scope of the invention.

[0056] The method for constructing the OPC model of the present invention comprises:

[0057] Obtaining CDSEM images and original feature sizes corresponding to a plurality of wafer patterns, respectively; the wafer patterns are patterns formed on the wafer after photolithography of the test pattern; the original feature sizes refer to the feature sizes measured by CDSEM;

[0058] Screening out wafer patterns whose imaging contrast does not meet preset requirements from all wafer patterns as wafer patterns to be calibrated, and the remaining wafer patterns as non-calibrated wafer patterns. The CDSEM images corresponding to the wafer patterns to be calibrated are used as CDSEM images to be processed;

[0059] Overlaying the CDSEM image to be processed with the test pattern to obtain the characteristic dimensions of the CDSEM image to be processed at positions corresponding to the alignment mark positions of the test pattern as the calibration characteristic dimensions of the wafer pattern to be calibrated;

[0060] An initial OPC model is constructed, and model parameters of the initial OPC model are calibrated according to the calibration feature size of the wafer pattern to be calibrated and the original feature size of the non-calibrated wafer pattern to obtain the OPC model.

[0061] In the above-mentioned OPC model construction method of the present invention, the wafer pattern is obtained by a conventional photolithography process. The specific method can be: spin-coating photoresist on the wafer, curing to form a photoresist layer, exposing and developing with the assistance of a mask, thereby forming a developed pattern on the photoresist layer, i.e., the wafer pattern; wherein the pattern on the mask is a test pattern.

[0062] In the OPC model construction method described in the present invention, the CDSEM images and original feature sizes corresponding to multiple wafer patterns can be obtained by the following method: the wafer pattern is scanned using a critical dimension electron microscope to obtain a CDSEM image of the wafer pattern. While scanning the wafer pattern using a critical dimension electron microscope, the feature size of the wafer pattern can also be measured and obtained as the original feature size of the wafer pattern.

[0063] The original feature size is directly measured by a critical dimension electron microscope. Since the critical dimension electron microscope has a relatively low accuracy in measuring the feature size of wafer graphics with poor imaging contrast, if the original feature size of the wafer graphics with poor imaging contrast is directly used to construct the OPC model, the accuracy of the OPC model will be relatively low. If these wafer graphics with poor imaging contrast are directly discarded and only the original feature size of the wafer graphics with good imaging contrast is used to construct the OPC model, the constructed OPC model will be only suitable for correcting the layout with good imaging contrast. When used to correct the layout with poor imaging contrast, the accuracy is even lower. Therefore, the wafer graphics with poor imaging contrast cannot be directly discarded. The present invention abandons the original feature size of the wafer graphics with poor imaging contrast, and adopts the method of the present invention to regain the feature size of the wafer graphics with poor imaging contrast as the calibration feature size for the construction of the OPC model, thereby improving the accuracy of the OPC model. The wafer graphics with poor imaging contrast described in the present invention refer to wafer graphics whose imaging contrast does not meet the preset requirements.

[0064] In order to re-obtain the characteristic size of the wafer pattern whose imaging contrast does not meet the preset requirement, first, it is necessary to screen out the wafer pattern whose imaging contrast does not meet the preset requirement from all wafer patterns.

[0065] As a preferred embodiment of the present invention, the present invention uses the Normalized Image Log-Slope (NILS) as an indicator for judging imaging contrast to screen wafer patterns. The method is: calculating the NILS of all wafer patterns, screening out wafer patterns whose NILS is less than a preset NILS standard value, and obtaining wafer patterns whose imaging contrast does not meet the preset requirements as wafer patterns to be calibrated. The remaining wafer patterns are non-calibrated wafer patterns.

[0066] In a specific embodiment of the present invention, the NILS of the wafer pattern is calculated by the following method: using the test pattern and the light source information used in the lithography as input, optical simulation is performed using an optical simulation model to obtain the NILS of each wafer pattern.

[0067] In the specific implementation of the present invention, the same test layout contains multiple patterns, which are developed through a photolithography process to form corresponding wafer patterns on different wafers. Therefore, by inputting the test layout and the light source information used in the photolithography into an optical simulation model for optical simulation, the NILS of multiple wafer patterns can be obtained simultaneously.

[0068] The optical simulation model used by the NILS for calculating wafer graphics of the present invention can be constructed using relevant optical simulation software such as S-LITHO, and the construction method can adopt conventional technology.

[0069] The present invention can measure the line width roughness (LWR) of wafer patterns by CDSEM, and preset the NILS standard value according to the LWR.

[0070] The CDSEM images corresponding to the wafer patterns to be calibrated are used as the CDSEM images to be processed, and the processed CDSEM images are processed to obtain the characteristic dimensions of the wafer patterns to be calibrated, which are used as the calibration characteristic dimensions of the wafer patterns to be calibrated for the construction of the OPC model. The CDSEM images corresponding to the non-calibrated wafer patterns do not require special processing, and the original characteristic dimensions of the non-calibrated wafer patterns can be directly applied to the construction of the OPC model.

[0071] refer to Figure 2 and Figure 3 As a preferred embodiment of the present invention, the CDSEM image to be processed is superimposed on the test layout to obtain the characteristic size of the CDSEM image to be processed at a position corresponding to the alignment mark position of the test layout, and the specific method is:

[0072] Extract the contour of the CDSEM image to be processed;

[0073] Overlaying the outline of the CDSEM image to be processed with the test pattern;

[0074] Extracting alignment mark positions of the test layout;

[0075] Matching the alignment mark position to the corresponding position of the outline of the CDSEM image to be processed;

[0076] The characteristic size of the outline of the CDSEM image to be processed at the corresponding position is extracted as the calibration characteristic size of the wafer pattern to be calibrated.

[0077] Specifically, the present invention can extract the contour of the CDSEM image to be processed by using existing conventional technologies, for example, using the contour extraction tool of Mentor Graphics (Mentor) to extract the image contour. There is no particular limitation on this, as long as the image contour can be extracted.

[0078] In the present invention, the outline of the CDSEM image to be processed is superimposed on the test pattern, and the specific method is as follows:

[0079] S1, identifies the one-dimensional and two-dimensional regions of the test layout;

[0080] S2, superimposing the outline of the CDSEM image to be processed with the test pattern according to the one-dimensional region and the two-dimensional region;

[0081] S3, obtaining the edge placement error (EPE) of the one-dimensional region and the two-dimensional region after overlay;

[0082] S4, calculating a cost function according to the edge placement error. If the cost function is less than a preset function value, the overlay is completed; otherwise, the process returns to S2.

[0083] As a specific embodiment of the present invention, the method for identifying one-dimensional areas and two-dimensional areas is specifically as follows: obtaining the length L of a certain area on the test layout; if L>2×fragment, the area is considered to belong to a one-dimensional area; if the area is at the endpoint of the graphic and the endpoint length is less than 1.5×fragment, the area is considered to belong to a two-dimensional area; wherein fragment represents the minimum resolvable feature size of the exposure system, and the exposure system refers to the exposure system used when forming the wafer graphic through a photolithography process.

[0084] like Figure 4 As shown, taking a rectangular pattern on a test layout as an example, the rectangular pattern includes two opposing one-dimensional regions and two opposing two-dimensional regions, the two two-dimensional regions being referred to as the first two-dimensional region and the second two-dimensional region. The rectangular pattern is divided into multiple segments along its length (e.g., each 5 nm is a segment), and the two one-dimensional regions in each segment are referred to as the first one-dimensional region and the second one-dimensional region. The calculation formula for the evaluation function is as follows:

[0085]

[0086] in, n Indicates the number of segments the rectangular figure is divided into along the length direction. p represents the weight coefficient of the one-dimensional region, qWeight coefficients representing a two-dimensional region, EPE1Da represents an edge placement error of a first one-dimensional region, EPE1Da' represents an edge placement error of a second one-dimensional region, EPE2Da represents an edge placement error of a first two-dimensional region, and EPE2Da' represents an edge placement error of a second two-dimensional region.

[0087] The evaluation function is used to evaluate the overlay degree of the profile of the CDSEM image to be processed and the test layout, and the overlay degree can be improved according to the minimality of the evaluation function, so that more accurate feature sizes can be obtained in the subsequent process, and the problem of manual adjustment can be avoided.

[0088] In the present application, the edge placement errors of the one-dimensional region and the two-dimensional region after overlay can be obtained by using conventional techniques.

[0089] In the present application, the alignment mark position of the test layout is extracted, the alignment mark position is matched to the corresponding position of the profile of the CDSEM image to be processed, and the feature size of the profile of the CDSEM image to be processed at the corresponding position is extracted, which can be realized by using conventional techniques.

[0090] After obtaining the calibration feature size of the wafer pattern to be calibrated, the model parameters of the initial OPC model can be calibrated according to the calibration feature size of the wafer pattern to be calibrated and the original feature size of the non-calibration wafer pattern, so as to obtain the final OPC model.

[0091] Specifically, the initial OPC model can be constructed by using conventional techniques, and then the test layout is simulated by using the initial OPC model to obtain a plurality of simulation patterns corresponding to the wafer patterns one by one and the feature sizes of the simulation patterns. The model parameters of the OPC model are calibrated according to the differences between the feature sizes of the simulation patterns and the calibration feature size of the wafer pattern to be calibrated and the original feature size of the non-calibration wafer pattern, until the preset convergence condition is met, and the final OPC model is obtained. The specific implementation of this process can refer to conventional techniques, and the present application will not be described here.

[0092] It should be noted that the test layout can be simulated to obtain a plurality of simulation patterns, each simulation pattern corresponding to a different wafer pattern, which can be a wafer pattern to be calibrated or a non-calibration wafer pattern. Therefore, the feature size of each simulation pattern is compared with the feature size of the corresponding wafer pattern, and the model parameters of the OPC model are calibrated according to the difference between the two.

[0093] The present application also provides a method for obtaining a mask layout, comprising:

[0094] Obtaining a layout;

[0095] Performing optical proximity effect correction on the layout using an OPC model to obtain a mask pattern;

[0096] The OPC model is constructed using the OPC model construction method described above.

[0097] The mask pattern obtained according to the above method can be used to manufacture a mask, which can then be used to fabricate semiconductor devices. Because the OPC model constructed by the present invention more accurately corrects the optical proximity effect of the layout, the resulting mask pattern is more accurate, and the mask produced based on this method has higher precision. Therefore, the wafer pattern produced using this mask is closer to the layout, and the product yield is higher.

[0098] Example 1

[0099] This embodiment provides a method for constructing an OPC model. In this embodiment, a wafer pattern is obtained through a photolithography process. The specific process is as follows: photoresist is spin-coated on the wafer, solidified to form a photoresist layer, and exposed and developed with the assistance of a mask, thereby forming a developed pattern on the photoresist layer, namely the wafer pattern; wherein the pattern on the mask is a test pattern. Scanning the wafer pattern using a critical dimension electron microscope can obtain CDSEM images corresponding to each wafer pattern. At the same time, the original feature size and LWR of each wafer pattern can be measured. Using the test pattern and the light source information used in the photolithography as input, an optical simulation model is used to perform optical simulation to obtain the NILS of each wafer pattern.

[0100] In this embodiment, wafer patterns are divided into two categories: concave patterns and convex patterns. Six wafer patterns with poor imaging contrast are selected from all concave patterns based on LWR and numbered as wafer pattern 1, wafer pattern 2, wafer pattern 3, wafer pattern 4, wafer pattern 5, and wafer pattern 6. The CDSEM images and NILS images corresponding to these wafer patterns are shown in Figure 2. Figure 5 As shown, the NILS of wafer pattern 1, wafer pattern 2, wafer pattern 3, wafer pattern 4, wafer pattern 5 and wafer pattern 6 are 1.44, 1.59, 1.64, 1.72, 1.79 and 1.80 respectively. Based on this, the NILS standard value corresponding to the preset concave pattern is 1.79.

[0101] Therefore, among all concave patterns, the wafer patterns with NILS less than 1.79 are wafer patterns that do not meet the imaging contrast requirements and are used as wafer patterns to be calibrated, and the CDSEM images corresponding to these wafer patterns are CDSEM images to be processed; the wafer patterns with NILS greater than or equal to 1.79 are wafer patterns whose imaging contrast meets the preset requirements and are used as non-calibrated wafer patterns.

[0102] According to LWR, five wafer patterns with poor imaging contrast were selected from all convex patterns and numbered as wafer pattern 7, wafer pattern 8, wafer pattern 9, wafer pattern 10 and wafer pattern 11. The CDSEM images and NILS images corresponding to these wafer patterns are shown in Figure 1. Figure 6 As shown, the NILS of wafer pattern 7, wafer pattern 8, wafer pattern 9, wafer pattern 10 and wafer pattern 11 are 0.76, 0.86, 0.88, 1.03 and 1.06 respectively. Based on this, the NILS standard value corresponding to the preset convex pattern is 1.03.

[0103] Therefore, among all convex patterns, wafer patterns with NILS less than 1.03 are wafer patterns that do not meet the imaging contrast requirements and are used as wafer patterns to be calibrated, and the CDSEM images corresponding to these wafer patterns are CDSEM images to be processed; wafer patterns with NILS greater than or equal to 1.03 are wafer patterns whose imaging contrast meets the preset requirements and are used as non-calibrated wafer patterns.

[0104] Extract the outline of the CDSEM image to be processed; overlay the outline of the CDSEM image to be processed with a test layout; extract the alignment mark position of the test layout, and match the alignment mark position to the corresponding position of the outline of the CDSEM image to be processed; extract the characteristic size of the outline of the CDSEM image to be processed at the corresponding position as the calibration characteristic size of the wafer pattern to be calibrated.

[0105] An initial OPC model is constructed, and then the test layout is simulated using the initial OPC model to obtain multiple simulated patterns and feature sizes of the simulated patterns that correspond one-to-one to the wafer patterns. According to the difference between the feature size of each simulated pattern and the calibrated feature size of the wafer pattern to be calibrated and the original feature size of the non-calibrated wafer pattern, the model parameters of the OPC model are calibrated until the preset convergence conditions are met to obtain the final OPC model.

[0106] Example 2

[0107] This example verifies the accuracy of the OPC model constructed in Example 1. The OPC model constructed in Example 1 is used to simulate a test layout corresponding to the active layer (AA layer) of a semiconductor device, obtaining multiple simulated patterns corresponding one-to-one to wafer patterns and the characteristic dimensions (Model CD) of the simulated patterns.

[0108] The test pattern corresponding to the AA layer was used to develop multiple wafer patterns on the wafer. Taking 10 wafer patterns (2D-1, 2D-2, 2D-3, 2D-4, 2D-5, 2D-6, 2D-7, 2D-8, 2D-9 and 2D-10) as examples, the characteristic dimensions (Wafer CD) of the 10 wafer patterns were measured by critical dimension electron microscopy. The standard deviation (Root Mean Square, RMS) of the characteristic dimensions of these 10 wafer patterns and the characteristic dimensions of the simulated patterns was calculated to be 1.6, and the fit error range was (-3, 2.8), which is within the allowable error range (spec-3, spec+3), as shown in Table 1 and Figure 7 shown.

[0109] Using the same method as above, the RMS of the metal layer of the semiconductor device is obtained to be 1.8, with an error range of (-3, 3.2).

[0110] Using the threshold-calibrated OPC model as a control, the same method as above was used to obtain an RMS of 3.2 for the AA layer with an error range of (-5, 6); the RMS of the Metal layer was 3.2 with an error range of (-6, 6), which could not be controlled within the allowable error range (spec-3, spec+3), as shown in Table 1 and Figure 8 shown.

[0111] Table 1 RMS and error range obtained by different methods

[0112]

[0113] The above results show that compared to the industry's threshold-based OPC model calibration method, the OPC model constructed by the present invention improves the fit of the AA layer from 3.2 to 1.6, a 50% improvement; and the fit of the Metal layer from 3.0 to 1.8, a 40% improvement. This demonstrates that the OPC model constructed by the present invention has higher prediction accuracy for 2D graphics. The present method can effectively improve the accuracy of OPC correction for asymmetric graphics, reduce mask costs, advance R&D progress, and improve product yield.

[0114] The following is an embodiment of the device of the present invention, which can be used to implement the embodiment of the method for constructing the OPC model of the present invention. For details not disclosed in the embodiment of the device, please refer to the embodiment of the method for constructing the OPC model of the present invention.

[0115] In one embodiment of the present invention, a system for constructing an OPC model is provided, comprising:

[0116] A data acquisition module is used to obtain CDSEM images and original feature sizes corresponding to a plurality of wafer patterns; the wafer patterns are patterns formed on the wafer after photolithography of the test pattern; the original feature sizes refer to the feature sizes measured by CDSEM;

[0117] A screening module is used to screen out wafer patterns whose imaging contrast does not meet the preset requirements from all wafer patterns, and use them as wafer patterns to be calibrated. The remaining wafer patterns are non-calibrated wafer patterns, and the CDSEM images corresponding to the wafer patterns to be calibrated are used as CDSEM images to be processed.

[0118] A size calibration module is used to overlay the CDSEM image to be processed with the test layout to obtain the characteristic size of the CDSEM image to be processed at a position corresponding to the alignment mark position of the test layout as the calibration characteristic size of the wafer pattern to be calibrated;

[0119] The OPC model building module is used to build an initial OPC model, and calibrate the model parameters of the initial OPC model according to the calibration feature size of the wafer pattern to be calibrated and the original feature size of the non-calibrated wafer pattern to obtain the OPC model.

[0120] The data acquisition module is a reading module that can directly read CDSEM images and original feature sizes corresponding to multiple wafer patterns from an external device that stores CDSEM images and original feature sizes.

[0121] In another embodiment of the present invention, a computer device is provided, comprising a processor and a memory, wherein the memory is used to store a computer program, the computer program including program instructions, and the processor is used to execute the program instructions stored in the computer storage medium. The processor may be a central processing unit (CPU), or may be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. It is the computing core and control core of the terminal, and is suitable for implementing one or more instructions, specifically suitable for loading and executing one or more instructions in the computer storage medium to implement the corresponding method flow or corresponding function. The processor described in the embodiment of the present invention can be used for the operation of the OPC model construction method.

[0122] In another embodiment of the present invention, a storage medium is provided, specifically a computer-readable storage medium (Memory). The computer-readable storage medium is a memory device in a computer device, used to store programs and data. It is understood that the computer-readable storage medium herein may include both built-in storage media in the computer device and, of course, extended storage media supported by the computer device. The computer-readable storage medium provides storage space, which stores the terminal's operating system. Furthermore, the storage space also stores one or more instructions suitable for being loaded and executed by a processor. These instructions may be one or more computer programs (including program code). It should be noted that the computer-readable storage medium herein may be random access memory (RAM) or non-volatile memory, such as at least one disk drive. The processor may load and execute the one or more instructions stored in the computer-readable storage medium to implement the corresponding steps of the OPC model construction method described in the above-mentioned embodiment.

[0123] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, systems, or computer program products. Thus, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, optical storage, etc.) containing computer-usable program code.

[0124] The present invention is described with reference to flowcharts and / or block diagrams of methods, systems (devices), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowcharts and / or block diagrams, as well as combinations of processes and / or blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowcharts and / or block diagrams. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0125] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0126] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0127] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to the above embodiments, ordinary technicians in the field should understand that the specific implementation methods of the present invention can still be modified or replaced by equivalents. Any modification or equivalent replacement that does not depart from the spirit and scope of the present invention should be covered by the scope of protection of the claims of the present invention.

Claims

1. The method for constructing an OPC model is characterized in that: include: Obtaining CDSEM images and original feature sizes corresponding to a plurality of wafer patterns, respectively; the wafer patterns are patterns formed on the wafer after photolithography of the test pattern; the original feature sizes refer to the feature sizes measured by CDSEM; Screening out wafer patterns whose imaging contrast does not meet preset requirements from all wafer patterns as wafer patterns to be calibrated, and the remaining wafer patterns as non-calibrated wafer patterns. The CDSEM images corresponding to the wafer patterns to be calibrated are used as CDSEM images to be processed; Overlaying the CDSEM image to be processed with the test pattern to obtain the characteristic dimensions of the CDSEM image to be processed at positions corresponding to the alignment mark positions of the test pattern as the calibration characteristic dimensions of the wafer pattern to be calibrated; An initial OPC model is constructed, and model parameters of the initial OPC model are calibrated according to the calibration feature size of the wafer pattern to be calibrated and the original feature size of the non-calibrated wafer pattern to obtain the OPC model.

2. The method for constructing an OPC model according to claim 1, wherein: The wafer patterns whose imaging contrast does not meet the preset requirements are screened out from all wafer patterns as the wafer patterns to be calibrated, specifically: Calculate the NILS of all wafer patterns and select wafer patterns with NILS less than the preset NILS standard value as the wafer patterns to be calibrated.

3. The method for constructing an OPC model according to claim 2, wherein: The NILS of all wafer patterns is calculated by taking the test pattern and the light source information used in the lithography as input, performing optical simulation using an optical simulation model, and obtaining the NILS of each wafer pattern.

4. The method for constructing an OPC model according to claim 1, wherein: The CDSEM image to be processed is superimposed on the test layout to obtain the characteristic size of the CDSEM image to be processed at a position corresponding to the alignment mark position of the test layout, specifically: Extract the contour of the CDSEM image to be processed; Overlaying the outline of the CDSEM image to be processed with the test pattern; Extracting the alignment mark positions of the test layout, and matching the alignment mark positions to corresponding positions of the outline of the CDSEM image to be processed; The characteristic size of the contour of the CDSEM image to be processed at the corresponding position is extracted.

5. The method for constructing an OPC model according to claim 4, wherein: The outline of the CDSEM image to be processed is superimposed on the test pattern, specifically: S1, identifies the one-dimensional and two-dimensional regions of the test layout; S2, overlaying the outline of the CDSEM image to be processed with the test pattern according to the one-dimensional region and the two-dimensional region; S3, obtaining edge placement errors of the one-dimensional region and the two-dimensional region after overlay; S4, calculating the evaluation function based on the edge placement error. If the evaluation function is less than the preset function value, the overlay is completed, otherwise return to S2.

6. The method for constructing an OPC model according to claim 1, wherein: The OPC model is obtained by calibrating the model parameters of the initial OPC model according to the calibration feature size of the wafer pattern to be calibrated and the original feature size of the non-calibrated wafer pattern, specifically: The test layout is simulated using an initial OPC model to obtain multiple simulated patterns and feature sizes of the simulated patterns that correspond one-to-one to the wafer patterns. Based on the differences between the feature sizes of the simulated patterns and the calibrated feature sizes of the wafer patterns to be calibrated and the original feature sizes of the non-calibrated wafer patterns, the model parameters of the OPC model are calibrated until the preset convergence conditions are met to obtain the OPC model.

7. The OPC model construction system is characterized by: include: A data acquisition module is used to obtain CDSEM images and original feature sizes corresponding to a plurality of wafer patterns; the wafer patterns are patterns formed on the wafer after photolithography of the test pattern; the original feature sizes refer to the feature sizes measured by CDSEM; A screening module is used to screen out wafer patterns whose imaging contrast does not meet the preset requirements from all wafer patterns, and use them as wafer patterns to be calibrated. The remaining wafer patterns are non-calibrated wafer patterns, and the CDSEM images corresponding to the wafer patterns to be calibrated are used as CDSEM images to be processed. A size calibration module is used to overlay the CDSEM image to be processed with the test layout to obtain the feature size of the CDSEM image to be processed at a position corresponding to the alignment mark position of the test layout as the calibration feature size of the wafer pattern to be calibrated; The OPC model building module is used to build an initial OPC model, and calibrate the model parameters of the initial OPC model according to the calibration feature size of the wafer pattern to be calibrated and the original feature size of the non-calibrated wafer pattern to obtain the OPC model.

8. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the method for constructing an OPC model according to any one of claims 1 to 6 are implemented.

9. A computer-readable storage medium storing a computer program, wherein: When the computer program is executed by a processor, the steps of the method for constructing an OPC model according to any one of claims 1 to 6 are implemented.

10. A method for obtaining a mask pattern, characterized in that: include: Get the map; Performing optical proximity effect correction on the layout using an OPC model to obtain a mask pattern; Wherein, the OPC model is constructed by using the OPC model construction method described in any one of claims 1 to 6.

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